Commit Graph

562 Commits

Author SHA1 Message Date
Florent Kermarrec 31b404c42f mng_rkx7: Add SPI Flash support. 2021-09-30 11:29:56 +02:00
Florent Kermarrec df7fe5687e Add initial MNT Reform Kintex-7 module (RKX7) support with Clk, UART and DDR3.
Compiles but untested on hardware.
2021-09-30 11:06:39 +02:00
enjoy-digital dfa572083a
Merge pull request #273 from ozbenh/wukong-v2
Wukong board improvements
2021-09-28 13:22:42 +02:00
Alessandro Comodi 228245075a boards: added datacenter DDR4 RDIMM tester board
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-09-27 10:15:55 +02:00
Benjamin Herrenschmidt 4a52996106 Wukong board improvements
This adds support for v2 of the board via a --board-version argument
and a way to select the FPGA speed grade via a --speed-grade argument.

Note that the speed grade now defaults to -1. QMTech confirmed that
V1 of the board were made in two batches, one with -1 and one with -2,
while V2 of the board is all -1. So -1 is the safer default.

This also fixes the inversion of j10 and j11 and a typo in the pin
definition of jp3

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2021-09-24 12:13:56 +10:00
enjoy-digital f18b10d1ed
Merge pull request #249 from Quiddle11/atlys
Initial Digilent Atlys support
2021-09-23 10:21:49 +02:00
Florent Kermarrec 921c300b50 digilent_atlys: Simplify/Remove entropy...
Build tested with ./digilent_atlys.py --with-ethernet --build.
2021-09-23 10:17:54 +02:00
alainlou 1333f89ed6 rz_easyfpga: adjust SDRAM clk phase
- also add 1:2 rate
2021-09-22 00:26:28 -04:00
Alain Lou 610e82d774
Add initial RZ-EasyFPGA support! (#270) 2021-09-21 09:55:22 +02:00
Florent Kermarrec d5eea94289 sispeed_tang_nano_4k: Avoid IOStandard constraints on HyperRAM (Not present in example designs). 2021-09-20 11:46:10 +02:00
Florent Kermarrec 5190c9c869 sipeed_tang_nano_4k: Initial Video Out support.
With colorbars for now, need to free up BRAMS for Video Terminal (or finish HyperRAM support).
2021-09-20 09:32:20 +02:00
Florent Kermarrec 376a836583 sipeed_tang_nano: Add SPI Flash, Enable CPU and use new external SPI Flash support from OpenFPGALoader.
./sipeed_tang_nano_4k.py --cpu-type=vexriscv --cpu-variant=lite --build --flash

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2021 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Sep 17 2021 15:54:08
 BIOS CRC passed (6cc6de6d)

 Migen git sha1: a5bc262
 LiteX git sha1: 46cd9c5a

--=============== SoC ==================--
CPU:		VexRiscv_Lite @ 27MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		64KiB
SRAM:		8KiB
FLASH:		4096KiB

--========== Initialization ============--

Initializing W25Q32 SPI Flash @0x80000000...
SPI Flash clk configured to 13 MHz
Memspeed at 0x80000000 (Sequential, 4.0KiB)...
   Read speed: 1.3MiB/s
Memspeed at 0x80000000 (Random, 4.0KiB)...
   Read speed: 521.9KiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex>
2021-09-17 15:57:55 +02:00
Florent Kermarrec 28571308bc sispeed_tang_nano: Add simple UART loopback test... (Not working...) 2021-09-16 19:34:48 +02:00
Florent Kermarrec 5955a35372 Add initial Sipeed Tang Nano support (Clk/Leds/Buttons). 2021-09-16 19:22:30 +02:00
Florent Kermarrec c0aed8a727 litex_m2_baseboard: Add Video Terminal support. 2021-09-16 18:54:50 +02:00
Florent Kermarrec 32a9256f3b litex_m2_baseboard: Add SDCard support. 2021-09-16 18:17:34 +02:00
Florent Kermarrec 0854a5d234 litex_m2_baseboard: Add Ethernet/Etherbone support. 2021-09-16 18:02:55 +02:00
Florent Kermarrec 8d2f75ca6d litex_m2_baseboard: Add PMODs connectors. 2021-09-16 17:48:53 +02:00
Florent Kermarrec 3ad0eb6992 Add initial LiteX M2 Baseboard support with Clk/Serial/Buttons. 2021-09-16 17:44:50 +02:00
enjoy-digital 26943959b5
Merge pull request #268 from trabucayre/runber_support
Add runber support
2021-09-15 08:32:05 +02:00
Gwenhael Goavec-Merou 7ccae3332d Add runber support 2021-09-15 06:50:57 +02:00
Gwenhael Goavec-Merou fed36afaba platforms/sipeed_tang_nano_4k: fix period computation 2021-09-15 06:46:29 +02:00
Nathaniel R. Lewis b8373a361d alchitry_mojo: new board 2021-09-10 02:40:31 -07:00
enjoy-digital d4613562a8
Merge pull request #265 from trabucayre/tangNano4K_connector
platforms/sipeed_tang_nano_4k: add P6 and P7 connectors
2021-09-09 11:43:05 +02:00
enjoy-digital cacb76450f
Merge pull request #264 from teknoman117/alchitry-au
Add Alchitry Au as new board
2021-09-09 11:42:37 +02:00
Gwenhael Goavec-Merou 945e48ea83 platforms/sipeed_tang_nano_4k: add P6 and P7 connectors 2021-09-09 11:35:14 +02:00
Florent Kermarrec 8d91489756 tang_nano_4k: Add more IOs. 2021-09-09 11:23:20 +02:00
Nathaniel R. Lewis 9bbdb87130 alchitry_au: new board 2021-09-09 00:03:19 -07:00
Florent Kermarrec 88534c6689 tang_nano_4k: Fix typo in sipeed. 2021-09-08 23:02:39 +02:00
Florent Kermarrec ce52c8c5ed beaglewire: Fix typo in qwertyembedded. 2021-09-08 21:29:29 +02:00
Florent Kermarrec ecebe7e267 Add initial SiSpeed Tang Nano 4K support (Led blink only for now...).
./sispeed_tang_nano_4k.py --build --load

Build with Gowin EDA.
Load with OpenFPGALoader.
2021-09-08 19:36:46 +02:00
Florent Kermarrec fddca1cd40 gsd_butterstick: Add SDCard (SPI & SD modes) support. 2021-09-02 14:06:09 +02:00
Florent Kermarrec 596f430326 gsd_butterstick: Add SPI Flash support. 2021-09-02 11:28:21 +02:00
Florent Kermarrec 1bbbf5b3e7 gsd_butterstick: Add SYZYGY0/1 IOs to connectors. 2021-09-02 10:26:18 +02:00
Florent Kermarrec 55ea71bd01 gsd_butterstick: Add initial DDR3 support.
Validated with:
./gsd_butterstick.py --uart-name=crossover --with-etherbone --csr-csv=csr.csv --build --load
litex_server --udp
litex_term bridge


        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2021 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Sep  1 2021 19:09:52
 BIOS CRC passed (3d349845)

 Migen git sha1: 27dbf03
 LiteX git sha1: 315fbe18

--=============== SoC ==================--
CPU:		VexRiscv @ 75MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		128KiB
SRAM:		8KiB
L2:		8KiB
SDRAM:		524288KiB 16-bit @ 300MT/s (CL-6 CWL-5)

--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Read leveling:
  m0, b00: |01110000| delays: 02+-01
  m0, b01: |00000000| delays: -
  m0, b02: |00000000| delays: -
  m0, b03: |00000000| delays: -
  best: m0, b00 delays: 02+-01
  m1, b00: |01110000| delays: 02+-01
  m1, b01: |00000000| delays: -
  m1, b02: |00000000| delays: -
  m1, b03: |00000000| delays: -
  best: m1, b00 delays: 02+-01
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
  Write: 0x40000000-0x40200000 2.0MiB
   Read: 0x40000000-0x40200000 2.0MiB
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
  Write speed: 13.6MiB/s
   Read speed: 15.6MiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex>
2021-09-01 19:21:16 +02:00
Florent Kermarrec 1f25a98476 butterstick: Add Ethernet/Etherbone support (UART crossover working over Etherbone). 2021-09-01 18:03:13 +02:00
Florent Kermarrec 1f149ece6b Add intial ButterStick support (with just Clk, Buttons and Leds). 2021-09-01 17:33:54 +02:00
enjoy-digital 4731c500fb
Merge pull request #258 from danc86/clnexevn-device-arg
lattice_crosslink_nx_evn: allow specifying the FPGA device
2021-09-01 10:22:42 +02:00
Florent Kermarrec ce254208ff beaglewire: Review/Cleanup for consistency with other targets.
- Now uses regular UART.
- Build tested with: ./quertyembedded_beaglewire.py --cpu-type=serv --build
- Can still be build with Crossover UART with --uart-name=crossover+bridge.
2021-09-01 10:18:11 +02:00
Florent Kermarrec 35df77258a beaglewire: Rename to quertyembedded_beaglewire. 2021-09-01 09:36:09 +02:00
enjoy-digital 1e1f6a476d
Merge pull request #254 from ombhilare999/master
beaglewire platform and target added
2021-09-01 09:33:07 +02:00
Florent Kermarrec 4a18951651 tul_pynq_z2: Fix copyrights, remove PS7 part for now. 2021-09-01 08:50:56 +02:00
enjoy-digital 54c777a49c
Merge pull request #252 from developandplay/PYNQ-Z2
WIP: Initial PYNQ Z2 support
2021-09-01 08:46:44 +02:00
enjoy-digital 6a08a7973c
Merge pull request #251 from niw/fix_orangecrab_feather_spi_pad_name
FIX: OrangeCrab Feather SPI pad name
2021-08-31 18:59:09 +02:00
Dhiru Kholia 781d83bab6 Add support for EBAZ4205 'Development' Board
Usage:

```
./ebaz4205.py --cpu-type=vexriscv --build --load
```

```
$ pwd
litex-boards/litex_boards/targets
```

Tip: Use `GTKTerm` to connect to /dev/ttyUSB0 (usually) and interact
with the LiteX BIOS.

References:

- https://github.com/fusesoc/blinky#ebaz4205-development-board
- https://github.com/olofk/serv/#ebaz4205-development-board
- https://github.com/xjtuecho/EBAZ4205#ebaz4205
- https://github.com/nmigen/nmigen-boards/pull/180 (merged)
- https://github.com/olofk/corescore/pull/33
- The existing 'Zybo Z7' example

Note: The `PS7` stuff remains untested via LiteX for now.
2021-08-31 18:54:49 +02:00
Yoshimasa Niwa fc78c96444 FIX: OrangeCrab Feather SPI pad name
**Problems**

`SPIMaster` pad names are `clk`, `cs_n`, `mosi`, and `miso`.
However, `feather_spi` is using `sck` instead of `clk`, therefore
it is not able to use as-is for `SPIMaster`, for example,
with `add_spi` on Linux On LiteX VexRiscv.

**Solution**

In fact, `spisdcard` and other SPI related pad names are
using `clk`, only `feather_spi` is using `sck`.
Therefore, rename `sck` to `clk`.
2021-08-29 17:59:45 -07:00
Dan Callaghan cc9e39286a lattice_crosslink_nx_evn: allow specifying the FPGA device
This board is documented as having the LIFCL-40-9BG400C part, but some
versions of the board exist which were fitted with LIFCL-40-8BG400CES,
an engineering sample part. The distinction is important because the
engineering sample requires a different device ID to be embedded in the
bitstream. If you try to build a bitstream for LIFCL-40-9BG400C and load
it onto LIFCL-40-8BG400CES the configuration fails (indicated by the red
"INITN" LED on this board).

Accept --device to allow the user to specify which FPGA part their board
has.
2021-08-17 18:30:03 +10:00
ombhilare999 db9c98b28a beaglewire platform and target added 2021-08-16 20:14:45 +05:30
Martin Troiber 22e823d756 Initial PYNQ Z2 support 2021-08-13 16:23:39 +02:00
MV b81309401e Initial Digilent Atlys support 2021-08-06 13:24:19 +02:00
Sergiu Mosanu 99ff82c75a xilinx_alveo_u280: Add more IOs and enable HBM2. 2021-07-28 18:11:49 +02:00
Florent Kermarrec 3e8b6677e9 platforms: Make sure all platforms have a default Clk. (To be able to run simple target). 2021-07-28 12:03:06 +02:00
Florent Kermarrec 2df3f9e664 pr243/platforms: Consistency with other platforms. 2021-07-27 14:55:19 +02:00
Florent Kermarrec 3fb73b3603 platforms/digilent_nexys4ddr: Fix INTERNAL_VREF voltage (0.900v instead of 0.750v). 2021-07-27 12:29:42 +02:00
Florent Kermarrec 2becaaabfc pr243: Minor platform cleanups. 2021-07-27 12:28:04 +02:00
Florent Kermarrec 2418df9f2b pr243: Add @tweakoz copyrights. 2021-07-27 12:21:23 +02:00
enjoy-digital 369d2cf49d
Merge pull request #243 from tweakoz/master
add FPGA Boards (Digilent CMOD A7, Digilent Nexys 4, Micronova Mercury2)
2021-07-27 12:17:04 +02:00
enjoy-digital 4d20cfe5cd
Merge pull request #245 from racerxdl/feat/MuselabIceSugarPro
muselab_icesugar_pro: initial support
2021-07-23 14:34:57 +02:00
Lucas Teske 5852dbb88f
muselab_icesugar_pro: initial support 2021-07-22 11:26:27 -03:00
Florent Kermarrec a3f479837c digilent_arty: Allow exposing raw PMOD IOs (for tests with MicroPython). 2021-07-21 13:50:12 +02:00
Florent Kermarrec 8c8e163eee trenz_tec0117: Add SDCard (SPI and SD mode), move SPI Flash to 0x00000000 and use default l2_cache_min_data_width. 2021-07-20 17:25:51 +02:00
Michael Mayers 75cadf845f add FPGA Boards
1.  Digilent CMOD A7
      https://reference.digilentinc.com/programmable-logic/cmod-a7/start

2. Digilent Nexys 4
      https://reference.digilentinc.com/programmable-logic/nexys-4/start

3. MicroNova Mercury 2
      https://www.micro-nova.com/mercury-2
2021-07-17 22:03:17 -06:00
Florent Kermarrec a74b6e83f7 trenz_tec0117: Add clock constraints. 2021-07-15 11:07:05 +02:00
Florent Kermarrec 8c1e6c6a02 decklink_quad_hdmi_recorder: Remove WIP (SoC + DDR3 now working) and add build/use instructions. 2021-07-02 15:54:57 +02:00
Florent Kermarrec 548f77c79c decklink_quad_hdmi_recorder: Add INTERNAL_VREF constraint on DRAM banks. 2021-07-02 14:32:14 +02:00
Florent Kermarrec 1b65bad4c2 decklink_quad_hdmi: Add Clk IOs, use clk200 as primary clk and add JTAGBone. 2021-07-01 20:00:35 +02:00
Florent Kermarrec 18b2758e4e decklink_quad_hdmi_recorder: Add other DDR3 SDRAM modules building but untested. 2021-06-30 11:50:42 +02:00
Florent Kermarrec e65308ee13 decklink_quad_hdmi_recorder: Add DDR3 SDRAM (only first module), building but untested. 2021-06-30 09:40:08 +02:00
Florent Kermarrec 84cb5d797d decklink_intensity_pro_4k: Add WIP. 2021-06-30 09:06:00 +02:00
Sylvain Munaut 7cb155fb9c icebreaker: Minor fix to usb (add PMOD2 position and fix typo)
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2021-06-27 16:00:09 +02:00
Florent Kermarrec 591377cf95 decklink: Pinout fixes on itensity_pro_4k and quad_hdm_recorder. 2021-06-25 11:19:05 +02:00
Florent Kermarrec ebfb4fad57 Add initial Decklink Intensity Pro 4K support (with documented PCIe / Untested). 2021-06-24 19:55:40 +02:00
Florent Kermarrec 5f8560bf69 Add initial Decklink Quad HDMI Recorder support (with documented PCIe/HDMI In).
LitePCIe Gen3 X4 enumerating correctly.
2021-06-24 19:48:31 +02:00
Sylvain Munaut 2ebcb4a726 platforms: Add new 1bitsquared_icebreaker_bitsy platform
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2021-06-21 16:17:54 +02:00
Sylvain Munaut 4c758dc0e3 platforms/1bitsquared_icebreaker: Fix wrong URL in header
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2021-06-21 16:16:47 +02:00
Sylvain Munaut 675616493c platform/1bitsquare_icebreaker: Add possible USB pinouts
The pin outs come from LUNA :
https://github.com/greatscottgadgets/luna/blob/main/luna/gateware/platform/icebreaker.py#L94

and are some commonly used ones from other projects / pmods.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2021-06-20 22:25:49 +02:00
Florent Kermarrec caac75c7db trenz_max1000: Review/Cleanup. 2021-06-16 18:04:55 +02:00
Antti Lukats 8ef138eaa0 added MAX1000 board 2021-06-16 17:55:06 +02:00
Florent Kermarrec fa045e6fa4 enclustra_mercury_kx2: Comment user_led2/3 (Conflicting with DRAM pins). 2021-06-16 11:54:52 +02:00
David Sawatzke fe7b3968e4 Fix colorlight 5a 75b v6.1 flash pins
As with the other versions, the clk pin can't be directly driven
2021-06-06 02:59:48 +02:00
enjoy-digital 588b430a0c
Merge pull request #217 from hansfbaier/master
QMTech EP4CE15: Add daughterboard support, small DECA addition
2021-05-25 10:15:26 +02:00
Florent Kermarrec 1c4825e7c4 basys3: Review/Simplify and fix build. 2021-05-25 08:44:26 +02:00
enjoy-digital 25867c4dcb
Merge pull request #218 from helium729/master
Add digilent basys3 board support
2021-05-23 19:46:58 +02:00
Jakub Cabal dd5a4bdc92 CYC1000: Add initial support of CYC1000 board 2021-05-22 21:17:27 +02:00
helium729 ce5b2a74a1 add digilent basys3 support 2021-05-17 16:39:16 +08:00
Hans Baier f01e0c02c9 qmtech ep4ce15: Add daughterboard support, add spiflash 2021-05-15 13:16:43 +07:00
enjoy-digital c010b9a335
Merge pull request #215 from hansfbaier/qmtech-xc7a35t
Qmtech xc7a35t
2021-05-10 08:31:08 +02:00
Hans Baier ddaab5317e qmtech_xc7a35 set symbiflow_device, needed when using symbiflow 2021-05-08 18:01:01 +07:00
Hans Baier f2b51b0233 icesugar: map the usb port 2021-05-08 07:34:10 +07:00
Florent Kermarrec e99272cb07 muselab_icesugar: Modify comments a bit. 2021-05-07 08:57:34 +02:00
enjoy-digital 5ae130661f
Merge pull request #213 from hansfbaier/icesugar
muselab_icesugar: first basic version which boots
2021-05-07 08:50:50 +02:00
enjoy-digital 2c2a9db3cc
Merge pull request #212 from hansfbaier/qmtech-xc7a35t
add QMTECH XC7A35T core board + daughter board
2021-05-07 08:32:16 +02:00
enjoy-digital 9e86c094c9
Merge pull request #211 from Acathla-fr/master
Lattice iCE40 UltraPlus Breakout board (iCE40UP5K-B-EVN) added
2021-05-07 08:30:01 +02:00
Hans Baier c2e0f6026e muselab_icesugar: first basic version that boots 2021-05-07 11:50:28 +07:00
Florent Kermarrec 3bb84b0071 Add initial Blackmagic Decklink Mini 4K support (with UART, DDR3, PCIe, Video Out).
Mini Monitor 4K and Mini Recorder 4K are almost the same hardware with just changes on
the Video In/Out. For now tests have been done on the Mini Monitor 4K, but the aim  is
support both boards in the same platform/target in the future, thus the mini_4k naming.

These boards could be used as affordable Artix7 dev boards for LiteX, to run Linux with
LiteX (512MB of RAM + a Video Framebuffer) or to create custom systems like a fast software
defined signal generator/recorder directly from a PC over PCIe, custom HDMI/SDI video
cards, etc... lots of possibilities :)
2021-05-06 09:47:01 +02:00
Hans Baier eec1078736 add QMTECH XC7A35T core board + daughter board 2021-05-06 05:50:48 +07:00
Fabien 213d100860 Lattice iCE40 UltraPlus Breakout board (iCE40UP5K-B-EVN) added 2021-05-04 12:19:21 +02:00
Florent Kermarrec 7d651a9a17 siglent_sds1104xe: Switch to VideoVGAPHY and adjust timings. 2021-04-29 10:41:19 +02:00
Florent Kermarrec f7ee3fa454 sds1104xe: Framebuffer fixes. 2021-04-27 19:32:03 +02:00
Florent Kermarrec 228a9650d4 sqrl_acorn: Add flashing/reload support when used with PCIe, fix JTAG flash. 2021-04-21 17:00:40 +02:00
Florent Kermarrec 443b954c0c platforms/xilinx_kcu105: Add Pmod0/1 connectors. 2021-04-19 15:11:43 +02:00
Shinken Sanada d2eabd112d Add E-Elements Ego1 initial board support. 2021-04-12 08:20:46 +02:00
Shinken Sanada cd3d4c826e Add Trenz te0725 initial board support. 2021-04-12 08:16:45 +02:00
Sergiu Mosanu 5519c931f8 xilinx_alveo_u280: Fix DDR4 (tested with 8 modules on C0 and C1). 2021-04-12 08:07:16 +02:00
enjoy-digital d830ef8393
Merge pull request #200 from rdolbeau/wukong_ethfix_fb
Qmtech Wukong: updates
2021-04-11 14:44:25 +02:00
Vegard Storheil Eriksen bad8821c2d platforms/ecpix5: Add ULPI signals. 2021-04-11 11:12:56 +02:00
Romain Dolbeau d5318dcb03 Qmtech Wukong: updates
fix ethernet clock (it's a GMII), add FB support over the HDMI connector (hdmi clock set from the resolution)
2021-04-10 16:26:25 +02:00
Florent Kermarrec 03accabc25 lpddr4_test_board: Add antmicro vendor prefix. 2021-03-31 09:48:23 +02:00
Jędrzej Boczar a834985e00 Add target for LPDDR4 Test Board 2021-03-30 14:50:02 +02:00
Florent Kermarrec a48def1352 rhsresearchllc_litefury: Remove since already supported by ./acorn.py --variant=cle-101. 2021-03-26 23:54:56 +01:00
Florent Kermarrec 4329a69128 sqrl_acorn_cle_215: Rename to sqrl_acorn and add support for all variants (CLE-101, 215 and 215+). 2021-03-26 23:52:36 +01:00
Florent Kermarrec 52ded1c9aa terasic_deca: Fix default_clk_name. 2021-03-26 22:43:40 +01:00
Florent Kermarrec b54eed0859 terasic_sockit: Review/Cleanup for consistency with other boards. 2021-03-26 22:39:19 +01:00
Florent Kermarrec 53a767c85c terasic_deca: Review/Cleanup for consistency with other boards. 2021-03-26 22:12:13 +01:00
Hans Baier 8c0ddd140b terasic_deca: fix cable name, ulpi, names, add gpio_serial 2021-03-26 10:46:37 +07:00
Florent Kermarrec 333fb362ca Move import Compat directly to litex_boards.__init__.py and simplify. 2021-03-25 16:47:47 +01:00
Florent Kermarrec 062b899e29 platforms/targets: Add mode Vendor prefixes. 2021-03-25 16:19:11 +01:00
Florent Kermarrec 5253a3c43e test/ci: Fix/Update. 2021-03-25 14:21:13 +01:00
Florent Kermarrec 8a3cacae32 boards: Add Vendor prefix to platforms/targets name when useful and when multiple boards from the same vendor. (With Retro-Compat on the imports). 2021-03-25 14:11:17 +01:00
Kaz Kojima cb4e00c3f2 colorlight_i5: Integrate Video Terminal and Video Framebuffer with new VideoECP5HDMIPHY. 2021-03-20 07:56:59 +09:00
Gabriel Somlo 7a1fe7a6bc nexys4ddr: add pmod connectors, and optional sdcard on pmodd 2021-03-19 12:33:11 -04:00
enjoy-digital 6d32c76aa2
Merge pull request #188 from hansfbaier/848-deca-video-bloat
fix #848: allow ram initialization in bitstream to enable block ram
2021-03-19 11:11:05 +01:00
Florent Kermarrec ddd46205aa ulx3s: Integrate Video Terminal and Video Framebuffer with new VideoECP5HDMIPHY. 2021-03-18 15:06:35 +01:00
Florent Kermarrec 4330769add minispartan6: Integrate Video Terminal and Video Framebuffer with new VideoS6HDMIPHY. 2021-03-18 14:10:42 +01:00
Hans Baier b7d86df01d fix #848: allow ram initialization in bitstream to enable block ram inference for ROM/RAM with initial value 2021-03-18 08:41:19 +07:00
Hans Baier 8b69ee57a6 arrow_sockit: get video terminal working on VGA 2021-03-16 12:31:41 +07:00
Florent Kermarrec 0e2d9a571e alveo_u280: Fix copyrights (avoid too much cascading on Platforms/Targets) and generate reset on idelay clock domain (similarly to recent change on others Ultrascale+ boards). 2021-03-10 11:23:27 +01:00
enjoy-digital f4ea3fb0d9
Merge pull request #168 from hplp/alveo_u280
Alveo U280 board
2021-03-10 11:16:32 +01:00
enjoy-digital 7c6876df42
Merge pull request #186 from gatecat/mipi_pins_x
crosslink_nx_vip: Remove constraints for hard MIPI pins
2021-03-10 11:13:49 +01:00
Florent Kermarrec 47faaf20d5 deca: Integrate Video Terminal (untested, resource issue). 2021-03-09 15:02:30 +01:00
gatecat 496cae54ff crosslink_nx_vip: Remove constraint for MIPI pins
Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-08 14:26:40 +00:00
gatecat 547157c9ca crosslink_nx_vip: Fix cam_reset IO configuration
Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-05 11:26:56 +00:00
gatecat 542001dddf crosslink_nx_vip: Split camera MCLK to its own resource
Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-05 11:18:37 +00:00
Florent Kermarrec 51a0bbfa65 platforms/targets: Harmonize VGA pins and use new Video Terminal on all targets with VGA support. 2021-03-03 18:05:24 +01:00
Florent Kermarrec 3af8ec0c8d targets/nexys4ddr: Replace VGA terminal with new LiteX's VideoTerminal. 2021-03-03 17:10:22 +01:00
Florent Kermarrec 7e3b8ab3b5 icebreaker: Add optional DVI Video Terminal with new LiteX's VideoOut core.
Tested with: ./icebreaker.py --cpu-type=serv --with-video-terminal --build --flash

https://twitter.com/enjoy_digital/status/1365324823447171074
2021-03-03 16:21:04 +01:00
enjoy-digital aa5c4f9e5a
Merge branch 'master' into arty-numato-sdcard-pmod 2021-02-25 09:37:34 +01:00
Hans Baier 6f558a5d65 Add board support for Terasic/Arrow DECA board 2021-02-25 12:25:43 +07:00
Joel Stanley 2b49082696 platforms/arty: Add numato sd card pmod
It has a different layout.

Thanks to David for documenting the pinout in this issue:
https://github.com/enjoy-digital/litex/issues/817

 Expansion Pin 	SD 	SPI SD 	Artix 	Arty-A7 	PMOD PIN 	PMOD Index
 2 		DATA_2 	  	D4 	JD1 		1 		0
 4 		CMD 	MOSI 	D3 	JD2 		2 		1
 6 		DATA_0 	MISO 	F4 	JD3 		3 		2
   		CD 	  	F3 	JD4 		4 		3
 1 		DATA_3 	CS_N 	E2 	JD7 		7 		4
 3 		CLK 	CLK 	D2 	JD8 		8 		5
 5 		DATA_1 	  	H2 	JD9 		9 		6
   	  		  	G2 	JD10

Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-02-24 14:59:50 +10:30
enjoy-digital 5b28c619d5
Merge pull request #178 from yetifrisstlama/vc707_clk
fix vc707 default_clk_period
2021-02-23 12:17:45 +01:00
Florent Kermarrec a90c0bc8f9 platforms/sds1104xe: Integrate changes from https://github.com/360nosc0pe/scope. 2021-02-22 13:45:48 +01:00
Michael Betz 09c3bd616b Merge branch 'master' into vc707_clk 2021-02-19 22:49:46 -08:00
Michael Betz c32e790421 vc707: fix default clock frequency 2021-02-19 22:47:18 -08:00
enjoy-digital 1fcd96971d
Merge pull request #172 from hansfbaier/master
sockit: Add an option to plug in an UART via the GPIO daughter board, make connector pin numbers one-based
2021-02-16 22:44:52 +01:00
Florent Kermarrec 975150ca68 platforms/sds1104xe: fix ddram IOStandard (SSTL15, thanks @tmbinc) and add INTERNAL_VREF on ddram banks. 2021-02-16 17:32:41 +01:00
Florent Kermarrec 9baa9d5d83 platform/de10nano: fix programmer (thanks @Godtec, see https://github.com/enjoy-digital/litex/pull/811). 2021-02-12 15:23:17 +01:00
Hans Baier 9a94e835c3 sockit: Add an option to plug in an UART via the GPIO daughter board 2021-02-10 14:52:19 +07:00
Michael Betz 7442c2dada vc707.py: clk156 add missing constraint 2021-02-08 19:04:01 -08:00
Florent Kermarrec fef9dd036a platforms/de0nano: directly use JP1 connector for serial pins. 2021-02-08 09:52:26 +01:00
enjoy-digital ea58ef94a7
Merge pull request #170 from hansfbaier/master
arrow_sockit: add support for MiSTer XS SDRAM modules
2021-02-04 16:44:58 +01:00
Jan Kowalewski cdff5e3ca3 nexys_video: enable symbiflow toolchain
Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
2021-02-03 14:52:54 +01:00
Hans Baier c64e13f687 arrow_sockit: add support for MiSTer XS SDRAM modules 2021-02-03 09:37:03 +07:00
Sergiu Mosanu a1d830566a added ddr4_sdram_c1 constraints 2021-02-01 12:22:41 -05:00
Florent Kermarrec 7c48af9b50 tec0117: get SDRAM working and increase sys_clk_freq to 25MHz.
./tec0117.py --build --load

Still some FIXMEs but validate use of the embedded SDRAM with LiteDRAM/LiteX:

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2020 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Feb  1 2021 13:09:35
 BIOS CRC passed (5abceb2e)

 Migen git sha1: 40b1092
 LiteX git sha1: f324f953

--=============== SoC ==================--
CPU:		VexRiscv_Lite @ 25MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		24KiB
SRAM:		4KiB
L2:		0KiB
SDRAM:		8192KiB 16-bit @ 25MT/s (CL-2 CWL-2)

--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2MiB)...
  Write: 0x40000000-0x40200000 2MiB
   Read: 0x40000000-0x40200000 2MiB
Memtest OK
Memspeed at 0x40000000 (2MiB)...
  Write speed: 5MiB/s
   Read speed: 6MiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex> mem_list

Available memory regions:
ROM       0x00000000 0x6000
SRAM      0x01000000 0x1000
SPIFLASH  0x80000000 0x1000000
MAIN_RAM  0x40000000 0x800000
CSR       0x82000000 0x10000

litex> mem_test 0x40000000 0x800000

Memtest at 0x40000000 (8MiB)...
  Write: 0x40000000-0x40800000 8MiB
   Read: 0x40000000-0x40800000 8MiB
Memtest OK

litex>
2021-02-01 13:32:01 +01:00
Florent Kermarrec 6cce07d9db tec0117: add spiflash4x pins, rework flash function to flash both bitstream/bios. 2021-02-01 13:31:44 +01:00
Florent Kermarrec 0831b33285 tec0117: fix copyrights. 2021-02-01 13:31:39 +01:00
Hans Baier 5e4b29c0b5 sockit: Fix cable name, default to jtag_atlantic 2021-02-01 11:48:06 +07:00
enjoy-digital 601c297c8f
Merge pull request #164 from rdolbeau/ztex213
Support file for the ZTEX USB-FPGA Module 2.13
2021-01-30 21:43:07 +01:00
Guillaume REMBERT 31df53ef0a Add flash to SPI flash support for board ECPIX5 (needs update to openfpgaloader.py from litex to work) 2021-01-30 13:19:08 +01:00
Romain Dolbeau 027e57b851 Support file for the ZTEX USB-FPGA Module 2.13 2021-01-30 05:19:18 -05:00
Florent Kermarrec abccd12058 tec0117: add initial SDRAM support for the embedded SDRAM of the SIP.
Still a WIP but able to do the P&R with modifications on LiteX to generate
the IO_PORT constraints but not the IO_LOC for the SDRAM pins.
2021-01-29 22:28:40 +01:00
Vadzim Dambrouski 345feddce9 ECPIX-5: ddram: Add missing address pin.
Fixes #161
2021-01-29 16:03:43 +03:00
Florent Kermarrec 7525b8772f platforms/fpc_iii: avoid dummy pin on ethernet.rst_n.
rst_n is optional in LiteEth's PHYs.
2021-01-29 09:33:33 +01:00
Florent Kermarrec 19767e1a2a platforms/fpc_iii: avoid using dummy pin on odt.
Now possible with 2f5784432d.
2021-01-29 09:30:54 +01:00
Florent Kermarrec 6c6d8a1393 platforms/fpc_iii: review/cleanup to increase similarities with others platforms and ease maintenance. 2021-01-29 08:41:10 +01:00
Sergiu Mosanu 1916677dc9 use VREF constraint for DDR4 C0 2021-01-28 19:58:38 -05:00
Gary Wong 4e5bb1bf1e Add FPC-III board support.
FPC-III is the Free Permutable Computer; details on the board are
available from:

    https://repo.or.cz/fpc-iii.git
2021-01-28 09:51:42 -07:00
Florent Kermarrec aa20fca1f1 ecpix5: reorder rgb_leds to have ld7:0, ld8:1, ld5:2, ld6:3. 2021-01-28 14:25:16 +01:00
enjoy-digital 691bfd8b70
Merge pull request #159 from euryecetelecom/master
Add ECPIX5 board components and pinouts (sata/spiflash/PMOD) + review openocd IDs
2021-01-28 14:01:01 +01:00
Alessandro Comodi bd716d956f netv2: add device variant to allow 100T as well
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-01-28 13:19:53 +01:00
Guillaume REMBERT 9beba7209d Add ECPIX5 components and pinouts (pmod/sata/spiflash) + review IDs from ECPIX5 openocd configuration 2021-01-28 12:00:28 +01:00
Sergiu Mosanu 84656a9c2e re-compare and adjust to u250 2021-01-26 23:03:09 -05:00
Kaz Kojima c3fa0eac8b Add colorlight i5 board support 2021-01-27 11:44:59 +09:00
Florent Kermarrec 537f494cbb arrow_sockit: review/harmonize with others boards. 2021-01-25 09:14:46 +01:00
Florent Kermarrec 4adc1b14c4 platforms/de0nano: use separator for connectors. 2021-01-25 08:58:12 +01:00
enjoy-digital bbaa2fdc98
Merge pull request #149 from hansfbaier/master
Add board support for Terasic/Arrow SocKit, Add connectors to de0-nano
2021-01-25 08:55:48 +01:00
enjoy-digital 45f538b1d3
Merge pull request #155 from blakesmith/add_spi_flash
ULX3S: Make spiflash optionally accessible from the SoC, and bootable
2021-01-24 21:22:35 +01:00
enjoy-digital 8132f9f65b
Merge pull request #154 from euryecetelecom/master
Fix SDCard issue when no SDCard inserted in ECPIX5 board.
2021-01-24 21:14:58 +01:00
Blake Smith cae51c0c24 ULX3S: Make spiflash optionally accessible from the SoC, and bootable 2021-01-23 14:44:26 -06:00
Hans Baier aa771e9ff4 de0-nano: add connectors 2021-01-23 20:18:15 +07:00
Hans Baier c9f0745d54 sockit: add board definitions for Terasic SocKit 2021-01-23 20:17:38 +07:00
Guillaume REMBERT b386ee5059 Fix SDCard issue when no SDCard inserted in ECPIX5 board. Now enable to detect SDCard presence.
https://github.com/litex-hub/linux-on-litex-vexriscv/issues/171
2021-01-20 18:02:13 +01:00
Vadim Kaushan a678672fc9
ecpix5: add option to select ECP5 device 2021-01-19 01:22:52 +03:00
Sergiu Mosanu 7a738245af fix bitstream problem 2021-01-14 21:53:25 -05:00
Sergiu Mosanu 5a73eb0b6d initiate target and platform for alveo_u280 board 2021-01-14 18:35:43 -05:00
enjoy-digital a6e867c691
Merge pull request #144 from gsomlo/gls-genesys2-sdcard
genesys2: LiteSDCard support
2021-01-07 08:12:24 +01:00
Gabriel Somlo 4eb0026a69 genesys2: add "rst" and "cd" signals to (spi-)sdcard records
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2021-01-04 13:10:13 -05:00
Geert Uytterhoeven 4a95b94dbf platforms/ecp5: Fix slewrate configuration
When building linux-on-litex-vexriscv for OrangeCrab:

    Warning: IOBUF 'spisdcard_clk' attribute 'SLEW' is not recognised (on line 207)
    Warning: IOBUF 'spisdcard_mosi' attribute 'SLEW' is not recognised (on line 210)
    Warning: IOBUF 'spisdcard_cs_n' attribute 'SLEW' is not recognised (on line 214)
    Warning: IOBUF 'spisdcard_miso' attribute 'SLEW' is not recognised (on line 218)

Platforms using litex.build.lattice.LatticePlatform seem to support only
"SLEWRATE", not "SLEW".  Fix the few offenders in the LogicBone and
OrangeCrab platform definitions.

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2021-01-04 17:08:51 +01:00
Florent Kermarrec 93779ecb95 platforms/colorlight_5a_75b: revert toolchain args.
Useful to do tests with Diamiond.
2020-12-29 14:22:42 +01:00
enjoy-digital f2985f1e71
Merge pull request #141 from la6m/Colorlight_v8.0
add colorlight v8.0 PCB
2020-12-29 14:20:29 +01:00
Florent Kermarrec b67b18caad qmtech_wukong: review/cleanup platform. 2020-12-29 14:10:49 +01:00
la6m 3e6b934961 add colorlight v8.0 PCB 2020-12-29 13:52:13 +01:00
Shinken Sanada 4b721eded7 add QmTech Wukong board support. 2020-12-29 13:20:42 +01:00
Florent Kermarrec 9beaf25822 nexys4ddr: fix eth/int_n pin (B8) and use 4-bit on vga.blue. 2020-12-24 10:15:29 +01:00
Sahaj Sarup 2a04c5c74e nexys4ddr: add support for litexvideo VGA Terminal
This commit adds VGA support for the Nexys A7/ Nexys 4 DDR.

The VGA is however limited to RGB443 instead of the full 12bit RGB444.
This is because IO D8 which is MSB for Blue, is also used for ETH int_n.
This makes the final output have a yellow tint.
2020-12-23 02:24:18 +05:30
Florent Kermarrec ec4ccc9fa5 platforms/xcu1525: fix ddram 1/2/3 pinout.
DDR4 now validated successfully with LiteDRAM on the 4 channels.
2020-12-11 13:58:26 +01:00
Robert Winkler 18337cdf25 targets/arty: sync with litex repository
Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
2020-12-07 17:32:40 +01:00
Alessandro Comodi f66860c201 zybo_z7: fix clock pin constraint
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-12-07 16:46:20 +01:00
Gwenhael Goavec-Merou 8d1095224f add support for redpitaya14/16 2020-11-26 06:54:11 +01:00
David Shah 11fa5c34ac nexus: Allow selection of toolchain
Signed-off-by: David Shah <dave@ds0.me>
2020-11-25 09:45:25 +00:00