4330769add
minispartan6: Integrate Video Terminal and Video Framebuffer with new VideoS6HDMIPHY.
2021-03-18 14:10:42 +01:00
b7d86df01d
fix #848 : allow ram initialization in bitstream to enable block ram inference for ROM/RAM with initial value
2021-03-18 08:41:19 +07:00
8b69ee57a6
arrow_sockit: get video terminal working on VGA
2021-03-16 12:31:41 +07:00
0e2d9a571e
alveo_u280: Fix copyrights (avoid too much cascading on Platforms/Targets) and generate reset on idelay clock domain (similarly to recent change on others Ultrascale+ boards).
2021-03-10 11:23:27 +01:00
f4ea3fb0d9
Merge pull request #168 from hplp/alveo_u280
...
Alveo U280 board
2021-03-10 11:16:32 +01:00
7c6876df42
Merge pull request #186 from gatecat/mipi_pins_x
...
crosslink_nx_vip: Remove constraints for hard MIPI pins
2021-03-10 11:13:49 +01:00
47faaf20d5
deca: Integrate Video Terminal (untested, resource issue).
2021-03-09 15:02:30 +01:00
496cae54ff
crosslink_nx_vip: Remove constraint for MIPI pins
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-08 14:26:40 +00:00
547157c9ca
crosslink_nx_vip: Fix cam_reset IO configuration
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-05 11:26:56 +00:00
542001dddf
crosslink_nx_vip: Split camera MCLK to its own resource
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-05 11:18:37 +00:00
51a0bbfa65
platforms/targets: Harmonize VGA pins and use new Video Terminal on all targets with VGA support.
2021-03-03 18:05:24 +01:00
3af8ec0c8d
targets/nexys4ddr: Replace VGA terminal with new LiteX's VideoTerminal.
2021-03-03 17:10:22 +01:00
7e3b8ab3b5
icebreaker: Add optional DVI Video Terminal with new LiteX's VideoOut core.
...
Tested with: ./icebreaker.py --cpu-type=serv --with-video-terminal --build --flash
https://twitter.com/enjoy_digital/status/1365324823447171074
2021-03-03 16:21:04 +01:00
aa5c4f9e5a
Merge branch 'master' into arty-numato-sdcard-pmod
2021-02-25 09:37:34 +01:00
6f558a5d65
Add board support for Terasic/Arrow DECA board
2021-02-25 12:25:43 +07:00
2b49082696
platforms/arty: Add numato sd card pmod
...
It has a different layout.
Thanks to David for documenting the pinout in this issue:
https://github.com/enjoy-digital/litex/issues/817
Expansion Pin SD SPI SD Artix Arty-A7 PMOD PIN PMOD Index
2 DATA_2 D4 JD1 1 0
4 CMD MOSI D3 JD2 2 1
6 DATA_0 MISO F4 JD3 3 2
CD F3 JD4 4 3
1 DATA_3 CS_N E2 JD7 7 4
3 CLK CLK D2 JD8 8 5
5 DATA_1 H2 JD9 9 6
G2 JD10
Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-02-24 14:59:50 +10:30
5b28c619d5
Merge pull request #178 from yetifrisstlama/vc707_clk
...
fix vc707 default_clk_period
2021-02-23 12:17:45 +01:00
a90c0bc8f9
platforms/sds1104xe: Integrate changes from https://github.com/360nosc0pe/scope .
2021-02-22 13:45:48 +01:00
09c3bd616b
Merge branch 'master' into vc707_clk
2021-02-19 22:49:46 -08:00
c32e790421
vc707: fix default clock frequency
2021-02-19 22:47:18 -08:00
1fcd96971d
Merge pull request #172 from hansfbaier/master
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sockit: Add an option to plug in an UART via the GPIO daughter board, make connector pin numbers one-based
2021-02-16 22:44:52 +01:00
975150ca68
platforms/sds1104xe: fix ddram IOStandard (SSTL15, thanks @tmbinc) and add INTERNAL_VREF on ddram banks.
2021-02-16 17:32:41 +01:00
9baa9d5d83
platform/de10nano: fix programmer (thanks @Godtec, see https://github.com/enjoy-digital/litex/pull/811 ).
2021-02-12 15:23:17 +01:00
9a94e835c3
sockit: Add an option to plug in an UART via the GPIO daughter board
2021-02-10 14:52:19 +07:00
7442c2dada
vc707.py: clk156 add missing constraint
2021-02-08 19:04:01 -08:00
fef9dd036a
platforms/de0nano: directly use JP1 connector for serial pins.
2021-02-08 09:52:26 +01:00
ea58ef94a7
Merge pull request #170 from hansfbaier/master
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arrow_sockit: add support for MiSTer XS SDRAM modules
2021-02-04 16:44:58 +01:00
cdff5e3ca3
nexys_video: enable symbiflow toolchain
...
Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
2021-02-03 14:52:54 +01:00
c64e13f687
arrow_sockit: add support for MiSTer XS SDRAM modules
2021-02-03 09:37:03 +07:00
a1d830566a
added ddr4_sdram_c1 constraints
2021-02-01 12:22:41 -05:00
7c48af9b50
tec0117: get SDRAM working and increase sys_clk_freq to 25MHz.
...
./tec0117.py --build --load
Still some FIXMEs but validate use of the embedded SDRAM with LiteDRAM/LiteX:
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2020 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Feb 1 2021 13:09:35
BIOS CRC passed (5abceb2e)
Migen git sha1: 40b1092
LiteX git sha1: f324f953
--=============== SoC ==================--
CPU: VexRiscv_Lite @ 25MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 24KiB
SRAM: 4KiB
L2: 0KiB
SDRAM: 8192KiB 16-bit @ 25MT/s (CL-2 CWL-2)
--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2MiB)...
Write: 0x40000000-0x40200000 2MiB
Read: 0x40000000-0x40200000 2MiB
Memtest OK
Memspeed at 0x40000000 (2MiB)...
Write speed: 5MiB/s
Read speed: 6MiB/s
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex> mem_list
Available memory regions:
ROM 0x00000000 0x6000
SRAM 0x01000000 0x1000
SPIFLASH 0x80000000 0x1000000
MAIN_RAM 0x40000000 0x800000
CSR 0x82000000 0x10000
litex> mem_test 0x40000000 0x800000
Memtest at 0x40000000 (8MiB)...
Write: 0x40000000-0x40800000 8MiB
Read: 0x40000000-0x40800000 8MiB
Memtest OK
litex>
2021-02-01 13:32:01 +01:00
6cce07d9db
tec0117: add spiflash4x pins, rework flash function to flash both bitstream/bios.
2021-02-01 13:31:44 +01:00
0831b33285
tec0117: fix copyrights.
2021-02-01 13:31:39 +01:00
5e4b29c0b5
sockit: Fix cable name, default to jtag_atlantic
2021-02-01 11:48:06 +07:00
601c297c8f
Merge pull request #164 from rdolbeau/ztex213
...
Support file for the ZTEX USB-FPGA Module 2.13
2021-01-30 21:43:07 +01:00
31df53ef0a
Add flash to SPI flash support for board ECPIX5 (needs update to openfpgaloader.py from litex to work)
2021-01-30 13:19:08 +01:00
027e57b851
Support file for the ZTEX USB-FPGA Module 2.13
2021-01-30 05:19:18 -05:00
abccd12058
tec0117: add initial SDRAM support for the embedded SDRAM of the SIP.
...
Still a WIP but able to do the P&R with modifications on LiteX to generate
the IO_PORT constraints but not the IO_LOC for the SDRAM pins.
2021-01-29 22:28:40 +01:00
345feddce9
ECPIX-5: ddram: Add missing address pin.
...
Fixes #161
2021-01-29 16:03:43 +03:00
7525b8772f
platforms/fpc_iii: avoid dummy pin on ethernet.rst_n.
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rst_n is optional in LiteEth's PHYs.
2021-01-29 09:33:33 +01:00
19767e1a2a
platforms/fpc_iii: avoid using dummy pin on odt.
...
Now possible with 2f5784432d
2021-01-29 09:30:54 +01:00
6c6d8a1393
platforms/fpc_iii: review/cleanup to increase similarities with others platforms and ease maintenance.
2021-01-29 08:41:10 +01:00
1916677dc9
use VREF constraint for DDR4 C0
2021-01-28 19:58:38 -05:00
4e5bb1bf1e
Add FPC-III board support.
...
FPC-III is the Free Permutable Computer; details on the board are
available from:
https://repo.or.cz/fpc-iii.git
2021-01-28 09:51:42 -07:00
aa20fca1f1
ecpix5: reorder rgb_leds to have ld7:0, ld8:1, ld5:2, ld6:3.
2021-01-28 14:25:16 +01:00
691bfd8b70
Merge pull request #159 from euryecetelecom/master
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Add ECPIX5 board components and pinouts (sata/spiflash/PMOD) + review openocd IDs
2021-01-28 14:01:01 +01:00
bd716d956f
netv2: add device variant to allow 100T as well
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-01-28 13:19:53 +01:00
9beba7209d
Add ECPIX5 components and pinouts (pmod/sata/spiflash) + review IDs from ECPIX5 openocd configuration
2021-01-28 12:00:28 +01:00
84656a9c2e
re-compare and adjust to u250
2021-01-26 23:03:09 -05:00
c3fa0eac8b
Add colorlight i5 board support
2021-01-27 11:44:59 +09:00
537f494cbb
arrow_sockit: review/harmonize with others boards.
2021-01-25 09:14:46 +01:00
4adc1b14c4
platforms/de0nano: use separator for connectors.
2021-01-25 08:58:12 +01:00
bbaa2fdc98
Merge pull request #149 from hansfbaier/master
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Add board support for Terasic/Arrow SocKit, Add connectors to de0-nano
2021-01-25 08:55:48 +01:00
45f538b1d3
Merge pull request #155 from blakesmith/add_spi_flash
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ULX3S: Make spiflash optionally accessible from the SoC, and bootable
2021-01-24 21:22:35 +01:00
8132f9f65b
Merge pull request #154 from euryecetelecom/master
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Fix SDCard issue when no SDCard inserted in ECPIX5 board.
2021-01-24 21:14:58 +01:00
cae51c0c24
ULX3S: Make spiflash optionally accessible from the SoC, and bootable
2021-01-23 14:44:26 -06:00
aa771e9ff4
de0-nano: add connectors
2021-01-23 20:18:15 +07:00
c9f0745d54
sockit: add board definitions for Terasic SocKit
2021-01-23 20:17:38 +07:00
b386ee5059
Fix SDCard issue when no SDCard inserted in ECPIX5 board. Now enable to detect SDCard presence.
...
https://github.com/litex-hub/linux-on-litex-vexriscv/issues/171
2021-01-20 18:02:13 +01:00
a678672fc9
ecpix5: add option to select ECP5 device
2021-01-19 01:22:52 +03:00
7a738245af
fix bitstream problem
2021-01-14 21:53:25 -05:00
5a73eb0b6d
initiate target and platform for alveo_u280 board
2021-01-14 18:35:43 -05:00
a6e867c691
Merge pull request #144 from gsomlo/gls-genesys2-sdcard
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genesys2: LiteSDCard support
2021-01-07 08:12:24 +01:00
4eb0026a69
genesys2: add "rst" and "cd" signals to (spi-)sdcard records
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2021-01-04 13:10:13 -05:00
4a95b94dbf
platforms/ecp5: Fix slewrate configuration
...
When building linux-on-litex-vexriscv for OrangeCrab:
Warning: IOBUF 'spisdcard_clk' attribute 'SLEW' is not recognised (on line 207)
Warning: IOBUF 'spisdcard_mosi' attribute 'SLEW' is not recognised (on line 210)
Warning: IOBUF 'spisdcard_cs_n' attribute 'SLEW' is not recognised (on line 214)
Warning: IOBUF 'spisdcard_miso' attribute 'SLEW' is not recognised (on line 218)
Platforms using litex.build.lattice.LatticePlatform seem to support only
"SLEWRATE", not "SLEW". Fix the few offenders in the LogicBone and
OrangeCrab platform definitions.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2021-01-04 17:08:51 +01:00
93779ecb95
platforms/colorlight_5a_75b: revert toolchain args.
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Useful to do tests with Diamiond.
2020-12-29 14:22:42 +01:00
f2985f1e71
Merge pull request #141 from la6m/Colorlight_v8.0
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add colorlight v8.0 PCB
2020-12-29 14:20:29 +01:00
b67b18caad
qmtech_wukong: review/cleanup platform.
2020-12-29 14:10:49 +01:00
3e6b934961
add colorlight v8.0 PCB
2020-12-29 13:52:13 +01:00
4b721eded7
add QmTech Wukong board support.
2020-12-29 13:20:42 +01:00
9beaf25822
nexys4ddr: fix eth/int_n pin (B8) and use 4-bit on vga.blue.
2020-12-24 10:15:29 +01:00
2a04c5c74e
nexys4ddr: add support for litexvideo VGA Terminal
...
This commit adds VGA support for the Nexys A7/ Nexys 4 DDR.
The VGA is however limited to RGB443 instead of the full 12bit RGB444.
This is because IO D8 which is MSB for Blue, is also used for ETH int_n.
This makes the final output have a yellow tint.
2020-12-23 02:24:18 +05:30
ec4ccc9fa5
platforms/xcu1525: fix ddram 1/2/3 pinout.
...
DDR4 now validated successfully with LiteDRAM on the 4 channels.
2020-12-11 13:58:26 +01:00
18337cdf25
targets/arty: sync with litex repository
...
Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
2020-12-07 17:32:40 +01:00
f66860c201
zybo_z7: fix clock pin constraint
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-12-07 16:46:20 +01:00
8d1095224f
add support for redpitaya14/16
2020-11-26 06:54:11 +01:00
11fa5c34ac
nexus: Allow selection of toolchain
...
Signed-off-by: David Shah <dave@ds0.me>
2020-11-25 09:45:25 +00:00
389b623fe2
targets/litefury: new target
...
LiteFury is an Artix-7 development board in the M.2 form factor
for PCIe accelerator development. It's similar to the Aller but
with an xc7a100t rather than an xc7a200t and no TPM module.
https://rhsresearch.com/collections/rhs-public/products/litefury
2020-11-19 21:52:14 -08:00
27f60b2e93
add initial Siglent SDS1104X-E support (Ethernet & DDR3 validated).
...
Pinout from https://github.com/360nosc0pe project.
2020-11-13 12:20:15 +01:00
843e724e3d
targets/pcie: simplify using new LiteX's add_pcie method and enable it on all devices supported by LitePCIe.
2020-11-12 16:39:42 +01:00
9f11bfb0d1
qmtech_ep4ce15: convert name to lowercase, minor cleanup and add to test_targets.
2020-11-12 14:33:45 +01:00
31eb74dc2d
Merge pull request #122 from baselsayeh/master
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add Qmtech EP4CE15 coreboard support
2020-11-12 14:27:49 +01:00
46e8a957fe
platforms/zybo_z7: fix default_clk typo.
2020-11-12 14:26:36 +01:00
ac075f18c7
platforms/crosslink_nx_evn/vip: add default_clk.
2020-11-12 14:26:17 +01:00
0fc67ddfdb
update copyright
2020-11-12 15:25:39 +02:00
a4d05522d4
platforms/ice40/ecp5: add toolchain parameter with default to trellis (ECP5) or icestorm (iCE40).
...
Required to simplify simple.py target and use trellis/icestorm as default toolchain.
2020-11-12 13:33:30 +01:00
1b1ed5ebf1
add Qmtech EP4CE15 coreboard support
2020-11-12 01:56:36 +02:00
97b64d16a6
Lattice NX PLL Support
2020-11-08 20:34:46 -06:00
1f52fbaca6
xcu1525: fix last ddram channel numbering.
2020-11-06 10:48:26 +01:00
2da4eabffe
platforms/icebreaker: fix refactoring typo.
2020-11-04 09:30:01 +01:00
c093d0d0fc
platforms: cleanup pass to uniformize comments/separators/orders.
2020-11-03 10:48:57 +01:00
d1c9cc7553
Add LFE5U-12F device for ULX3S
2020-11-01 23:45:32 +00:00
d626861e95
platforms/acorn_cle_215: add serial_io (on P2).
2020-10-29 12:10:12 +01:00
51934567fe
Merge pull request #118 from daveshah1/lifcl-vip
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Add CrossLink-NX VIP board platform and target
2020-10-22 11:03:47 +02:00
a38c1e7062
mist: add copyrights.
2020-10-22 10:48:58 +02:00
20720693c4
crosslink_nx_vip: Add HyperRAM support
...
Signed-off-by: David Shah <dave@ds0.me>
2020-10-22 09:15:40 +01:00
b278d8bccc
Add CrossLink-NX VIP board platform and target
2020-10-22 09:15:35 +01:00
4541c39e94
Initial support for the MIST board ( https://github.com/mist-devel/mist-board/wiki )
2020-10-17 12:28:22 +02:00
982cfd5ad5
platforms/xcu1525: fix ddram constraints, add clk300 constraints for all channels.
2020-10-13 11:50:36 +02:00
ddf7038c78
ulx3s: add 1.7 and 2.0 revisions support.
2020-10-12 13:23:26 +02:00
3b11e60fb1
Update ULX3S SD pins for revision 2.0
2020-10-11 14:17:48 +11:00
55da8b867a
platforms/zedboard: minor cleanups to uniformize with other platforms.
2020-10-07 11:25:20 +02:00
e225cbd28f
add zedboard platform to CI
2020-10-06 11:35:03 -07:00
8ee20a3f30
clean up imports
2020-10-06 11:24:34 -07:00
865c2bd98c
zedboard platform: clean up
...
* remove unused code
* remove oled integration code
* openocd = default programmer
2020-10-06 11:00:36 -07:00
12aed44577
add zedboard platform
2020-10-06 00:28:54 -07:00
79ef091a06
Merge pull request #110 from pepijndevos/gowin
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Add initial support for Trenz TEC0117 board
2020-10-05 19:50:09 +02:00
2ee32f2a15
Merge pull request #109 from geertu/orangecrab-Fix-r0.1-user_led-mapping
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orangecrab: Fix r0.1 user_led mapping
2020-10-02 09:40:41 +02:00
062fbd6c63
Merge pull request #108 from daveshah1/dave/nx-evn-doc
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crosslink_nx_evn: Improve documentation on UART jumpers
2020-10-02 09:40:04 +02:00
81e4f1f158
add initial support for Trenz TEC0117 board
2020-09-30 14:01:36 +02:00
b2e34f5faf
orangecrab: Fix r0.1 user_led mapping
...
On r0.1, all three user_leds are mapped to the same pin.
Fix this by mapping them to the pins connected to the individual
channels of the RGB LED, to match the comments, the schematics, and the
spirit of r0.2.
Untested on real hardware (I have r0.2 only).
Fixes: c94cbae0c0
2020-09-25 10:33:21 +02:00
c6610b4a3f
platforms/xcu1525: update ddram1/2/3 pinout.
...
Using https://github.com/d953i/Custom_Part_Data_Files/blob/master/Boards/Xilinx_BCU1525/BCU1525_DIMMx.xdc
2020-09-20 21:07:00 +02:00
e5a144e9cd
platforms/xcu1525: update ddram0 pinout.
...
Using https://github.com/d953i/Custom_Part_Data_Files/blob/master/Boards/Xilinx_BCU1525/BCU1525_DIMM0.xdc .
2020-09-19 23:28:34 +02:00
8ffb86c0dc
platforms/fk33/xcu1525: define pcie_x2/x4/x8/x16.
2020-09-19 22:37:05 +02:00
8a9fd02768
crosslink_nx_evn: Improve documentation on UART jumpers
...
Signed-off-by: David Shah <dave@ds0.me>
2020-09-05 09:58:28 +01:00
76ac4a69a8
rename forest_kitten_33 platform/target to fk33.
2020-09-04 20:05:18 +02:00
979fee7517
forest_kitten_33: add pcie.
2020-09-04 20:02:43 +02:00
ad48728160
xcu1525: update headers (were still using old format).
2020-09-04 19:59:09 +02:00
ad4c483c32
Merge pull request #106 from daveshah1/dave/alveo_u250_pcie
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alveo_u250: Add PCIe x4 support
2020-09-04 19:22:48 +02:00
a68c00e48e
Merge pull request #104 from DerFetzer/colorlight_5a_75e_v6_0
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Add support for 5A-75E V6.0 board
2020-09-04 19:21:02 +02:00
ae6a052e57
alveo_u250: Add PCIe x4 support
...
Based on the implementation in xcu1525
Signed-off-by: David Shah <dave@ds0.me>
2020-09-04 14:20:04 +01:00
2eda9d0252
xcu1525: add DDR4 IOs for C1/C2/C3 and fix compilation (untested).
2020-09-04 11:34:33 +02:00
7b6b71d4e3
xcu1525: add initial DDR4 support in C0 (untested).
2020-09-03 19:48:23 +02:00
51e881d1ff
add minimal xcu1525 support (VCU1525 or BCU1525 boards).
2020-09-03 19:06:43 +02:00
cc78574297
targets/colorlight_5a_75x: fix rx_data pin order for Ethernet PHY 0
2020-09-02 22:04:23 +02:00
8b1fee0e66
Add support for 5A-75E V6.0 board
2020-09-01 17:02:17 +02:00
beccecf59f
orangecrab: reduce DDR3 power consumption/heat and get back USB PLL to CRGSDRAM.
...
- disable DQ termination.
- disable RTT_NOM.
- drive VCCIO/GND pads.
Reduce current from 0.25A to 0.12A with: ./orangecrab.py --uart-name=usb_acm --sys-clk-freq=48e6.
Still working at 96MHz, 0.17A with: ./orangecrab.py --uart-name=usb_acm --sys-clk-freq=96e6.
See https://github.com/enjoy-digital/litedram/issues/216 .
2020-08-28 20:01:54 +02:00
63b65e278c
crosslink_nx_evn: update copyrights.
2020-08-24 22:33:58 +02:00
795e34aafd
add initial Crosslink-NX support.
2020-08-24 16:47:38 +02:00
70594a5305
ulx3s: simplify sdram constraints and increase phase to 180 for sdram_rate=1:2.
2020-08-24 09:05:58 +02:00
1781be166a
general: add SPDX License identifier to header and specify files are part of LiteX-Boards.
2020-08-23 15:00:17 +02:00
83d8b8d1b4
platforms/acorn_cle_215: integrated sdcard ios as extension.
2020-08-22 22:11:51 +02:00
f328909578
Moved platform call inside of BaseSoC init for compatibility with linux-on-litex-vexriscv support. Added optional spi-sdcard support over P2 header.
2020-08-09 16:27:41 -04:00
d2cd6d4c0e
arty: Change USB-uart and I2S Pmod configuration
...
This makes it compatible with the Arty A7 expansion board by Antmicro
(https://github.com/antmicro/arty-expansion-board ).
2020-08-05 11:54:25 +02:00
eba70377b7
add optional OLED peripheral to ULX3S target
2020-08-04 11:07:30 +02:00
929e55d7e6
platforms/trellisboard: add SDCard PMOD pins.
2020-07-29 09:07:55 +02:00
5fd3e8dbcd
ecpix5: add SDCard.
...
Validated with Linux-on-LiteX-VexRiscv.
2020-07-28 17:45:49 +02:00
760b8ff93a
arty: improve xy_pmod_io genericity (allow selecting the PMOD) and enable SDCard.
2020-07-24 16:29:35 +02:00
9730c6f722
platforms/de10nano: use additional sdram constraints required for HalfRate.
2020-07-24 12:27:36 +02:00
7399d13cef
paltforms/de10nano/sdram: enable fast input/output on dq.
2020-07-24 11:27:25 +02:00
b4b1ab8621
paltforms/de10nano: simplify IO constraints (for consistency with others platforms).
2020-07-24 09:03:35 +02:00
89c5bf43cf
Merge pull request #92 from rob-ng15/master
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Enable use of HalfRateGENSDRPHY on de10nano
2020-07-24 08:49:09 +02:00
1e1589a514
zybo_z7: demonstrate use of PS7 (with --cpu-type=zynq7000).
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This uses a pre-generated .xci hosted on github, still need to figure out where the best location for it.
2020-07-23 17:45:21 +02:00
cf9839307f
Add Misc
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Add Misc("") arguments to various inputs/outputs for stability. Allows de10nano to use HalfRateGENSDRPHY for sdram
2020-07-23 14:40:04 +01:00
8a3b453e2f
add Zybo Z7 minimal platform/targets: no PS7 support and USB-UART PMOD on JB.
2020-07-23 15:26:22 +02:00
e723bef49a
platforms/arty: add usb_uart_pmod_io (USB-UART PMOD on JA) to ease debug with a second UART (for UARTbone/LiteScope).
...
Also use pmod connector names in i2s_pmod and sdcard_pmod.
2020-07-22 14:41:09 +02:00
19d0b95867
platforms/targets: keep in sync with litex.
2020-07-22 08:53:49 +02:00
0ee4b215b9
trellisboard/ulx3s: fix sdcard slewrate.
2020-07-21 15:23:08 +02:00
7efa1c37a1
platforms/arty: add missing pullups on sdcard.
2020-07-21 15:22:39 +02:00
2ce24df76d
platforms/genesys2: add internal_vref to 0.750v on bank 34 (DDR3).
2020-07-18 22:18:41 +02:00
135c387155
platforms/ulx3s: add assertion for supported devices.
2020-07-17 12:04:06 +02:00
851378f0a9
platforms/trellisboard: move ddram_vtt_en.
2020-07-17 12:03:37 +02:00
44ad902aad
platforms/kc705.py: LPC DP0_M2C/C2M diff pair
2020-07-13 10:26:17 -07:00
a461f5ac59
orangecrab: add usb, rst_n signals for r0.1
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- fix standard io extensions
- Use newly assigned code for orangecrab 1209:5af0
2020-07-09 19:56:32 +09:30
f3d02d8fca
Merge pull request #87 from antmicro/arty_i2s
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arty: Add configuration of I2S pins
2020-07-07 17:22:10 +02:00
df54b93db3
arty: Add configuration of I2S pins
2020-07-07 15:25:10 +02:00
40fbbbbebc
platforms/orangecrab: add sdcard pins on r0_2.
2020-07-06 17:48:48 +02:00
49973990f3
Merge pull request #85 from oskirby/logicbone
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Add Logicbone ECP5 board
2020-06-29 16:24:15 +02:00
76a32ba8ec
Add Logicbone ECP5 board
...
The Logicbone is an Open Source development board for the Lattice ECP5
being developed at https://github.com/oskirby/logicbone
2020-06-27 03:32:47 -07:00
782c856619
platforms/genesys2: add usb_fifo.
2020-06-23 18:02:53 +02:00
936ba5b279
platforms/genesys2: add openocd specific configuration (channel 1 used for JTAG).
2020-06-23 11:55:50 +02:00
55ed9fbf02
platforms/kcu105: add sdcard/spisdcard.
2020-06-23 11:44:40 +02:00
eee00ebd0a
platforms/genesys2: add sdcard/spisdcard.
2020-06-23 11:44:26 +02:00
6568c8a3ae
platforms/netv2: add spisdcard.
2020-06-23 11:44:10 +02:00
7de7c4be5c
platforms/kc705: rename mmc to sdcard and make it similar to other boards.
2020-06-23 10:56:31 +02:00
0ecb8609b3
platform/arty: also update spisdcard.
2020-06-16 20:15:12 +02:00
7a8b0b743d
platforms/pano_logic_g2: -x.
2020-06-16 19:53:46 +02:00
f70655d1ac
Change sdcard Pmod from JB to JD
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-06-15 12:01:46 +02:00
04f6d4463a
versa_ecp5: simplify device (LFE5UM5G or LFE5UM) and adapt integrated_rom_size only for Microwatt.
2020-06-13 11:17:05 +02:00
90092164c8
Add device option for ECP5 Versa board
...
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
2020-06-12 18:39:43 -05:00
9b45ec0f35
de10lite: simplify vga terminal.
2020-06-11 19:59:32 +02:00
85cac7abc0
de10nano/Mister: review/simplify.
2020-06-11 19:54:55 +02:00
c94cbae0c0
orangecrab: add user_led (RGB leds), DFUProg and --load support.
2020-06-11 19:21:40 +02:00
9aea2272eb
Merge pull request #80 from rob-ng15/master
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Use 128mb sdram, uart via i/o port on i/o board and vga terminal via i/o board
2020-06-11 18:16:18 +02:00
ad1693a1ad
Merge pull request #82 from Disasm/colorlight-5a-75e
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Add Colorlight 5A-75E V7.1 board
2020-06-10 23:09:26 +02:00
b312c65eb9
Merge pull request #81 from Disasm/fix-5a-75b
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Update J4 pin 5 on Colorlight 5A-75B V7.0
2020-06-10 23:07:33 +02:00
b6df166f5a
platforms/arty: add spisdcard to _sdcard_pmod_io.
2020-06-10 17:38:16 +02:00
00c8e40d02
platforms/ulx3s: add sdcard pins.
2020-06-10 17:37:50 +02:00
1acdb962a5
Add 5A-75E V7.1 board
2020-06-10 03:07:20 +03:00
939f05fea4
Update J4 pin 5 on Colorlight 5A-75B V7.0
2020-06-10 02:49:18 +03:00
e52d6aca5f
Use 128mb sdram, uart via i/o port on i/o board and vga terminal via i/o board
2020-06-08 11:05:36 +01:00
0b11aba8a1
platforms/nexys_video: add spisdcard pins.
2020-05-29 19:37:04 +02:00
33fe308ef0
Merge pull request #78 from antmicro/jboc/spd-read
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ZCU104: add I2C
2020-05-27 14:56:31 +02:00
e5578a1ae8
zcu104/platform: change I2C number to 0
2020-05-27 14:31:22 +02:00
ac1f1cd6a7
zcu104: add I2C
2020-05-27 12:47:43 +02:00
2f3817cba9
pano_logic_g2: add ethernet (build but not functional yet) and use user_btn_n as sys_rst.
2020-05-27 10:13:12 +02:00
f19bc36813
pano_logic_g2: add revision support (b and c, c as default) and add OpenOCD programmer.
...
Tested with:
./pano_logic_g2.py --uart-name=jtag_uart --build --load
./litex_jtag_uart.py --config=openocd_xc6_ft232.cfg
lxterm /dev/pts/X
2020-05-27 08:58:40 +02:00
0648c04158
Updated comment, added link to clocking documentation.
2020-05-25 14:48:24 -07:00
1ab46562bd
Take Ethernet PHY out of reset so default clock is 125 Mhz (and baud rate is 115,200)
2020-05-25 10:11:03 -07:00
9b572ece0e
forest_kitten_33: add minimal target and use es1.
...
Tested with:
./forest_kitten_33.py --uart-name=jtag_uart --build --load
litex/tools/litex_jtag_uart.py
lxterm /dev/pts/X
2020-05-25 12:26:52 +02:00
0d549a8c89
platforms: add forest_kitten_33 initial platform suppport.
2020-05-24 11:22:02 +02:00
12b54a7a7f
platforms/alveo_u250: add clk300 clock constraints.
2020-05-24 11:18:30 +02:00
46f78b5002
nexys_video: add usb_fifo pins.
2020-05-22 14:28:55 +02:00
445338e2e7
platforms/nexys_video: add specific openocd cfg (use channel 1).
2020-05-22 14:12:45 +02:00
76551dec4c
platforms/nexys_video: add sdcard pins, move clk/rst to top.
2020-05-20 13:05:18 +02:00
83457b8791
platforms/arty: add _sdcard_pmod_io.
2020-05-20 12:09:43 +02:00
587caf7584
paltforms/marblemini: add break_off_pmod.
2020-05-19 15:42:53 +02:00
c2cd863658
platforms/ecp5_evn: rename spiflash1x to spiflash, rewrite hardware/configuration description and remove make_spiflash.
...
The Platform file should not contain import code related to cores, this has to be done in the target.
2020-05-19 15:29:25 +02:00
3f0f12011b
Merge pull request #70 from ilya-epifanov/ecp5-evn-spi1x-and-flash-params
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ECP5-EVN SpiFlash parameters
2020-05-19 15:16:25 +02:00
b9ee3a797a
alveo_u250: re-organize the auto-generated IOs, add build/load parameters.
2020-05-16 11:47:14 +02:00
6757c4e298
Merge pull request #71 from daveshah1/alveo_u250
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[WIP] Add Alveo U250 platform and target
2020-05-13 09:10:22 +02:00
4faa91c7f2
platforms/marblemini: review/cleanup.
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- add copyrights.
- add link to documentation.
- reindent code.
- rename some IOs (for consistency with the others platforms).
- add pullup on clk20_vcxo_en.
- set clk20_vcxo as default clock.
- remove ununnecessary eth constraints. (we are using IO primitives).
- move PMODS to connectors (for consistency with others platforms).
2020-05-09 10:16:42 +02:00
4ffdcb5ea9
Merge pull request #75 from jersey99/marblemini
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Marblemini [https://github.com/berkeleylab/marble-mini/ ]
2020-05-09 09:39:40 +02:00
e4ccfcfad1
platforms/marblemini.py: Cleanup. Add openocd for programming marblemini
2020-05-08 17:20:14 -07:00
6f22f082ff
targets: add LedChaser on platforms with user_leds.
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Default to Chaser mode and similar user interface than GPIOOut.
2020-05-08 22:16:13 +02:00
a7d6de78ae
Merge branch 'master' into marblemini
2020-05-07 12:19:47 -07:00
99c04358bf
platforms/pano_logic_g2: simplify/cleanup.
2020-05-07 16:35:34 +02:00
6b5492a707
pano_logic_g2: add copyrights.
2020-05-07 15:24:03 +02:00
6ddd859309
add pano_logic_g2 from litex-buildenv.
2020-05-07 15:22:22 +02:00
d34c3baf15
prog: use different openocd config files for FT232/FT2232.
2020-05-06 16:14:51 +02:00
e500d90bcc
platforms/ecpix5: set pullups on rx_data to advertise as RGMII mode.
2020-05-06 16:00:46 +02:00
59e8c2cd30
acorn_cle_215: add .bin generation and --flash argument, working on hardware :).
2020-05-06 12:27:07 +02:00
a049fa6856
add Acorn CLE 215+ platform/target.
2020-05-06 07:53:55 +02:00
b58b9b9e6a
platforms: fix CI.
2020-05-05 16:01:43 +02:00
19eb5708de
platforms: make sure all traditional platforms have a create_programmer method.
2020-05-05 13:34:57 +02:00
1f88a9d5ec
platforms: make sure clocks inputs are constraints on all platforms.
...
Also use new loose lookup_request to simplify constraints.
2020-05-05 11:45:41 +02:00
86648ec7d8
platforms/vcu118: rename ddram_second_channel to ddram:1.
2020-05-05 09:54:11 +02:00
e1820c7831
platforms/ac701: indent HPC.
2020-05-05 09:49:59 +02:00
2129b67779
platforms: make sure all plarforms have separators.
2020-05-05 09:47:55 +02:00
ea0eda9f75
platforms: make sure all Xilinx/Altera platforms have a create_programmer method, use OpenOCD on Spartan6 and 7-Series.
2020-05-05 09:42:34 +02:00
088cceca8b
Add Alveo U250 platform and target
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Signed-off-by: David Shah <dave@ds0.me>
2020-04-29 12:31:16 +01:00
0ba8045789
Added spiflash1x pins, a method to create an SpiFlash instance and a note on a second UART channel of FT2232H
2020-04-28 21:56:33 +02:00
865b01ec75
ecpix5: add ethernet.
2020-04-22 20:21:59 +02:00
6fe4c4ea62
ecpix5: add DDR3 (working)
2020-04-22 17:03:22 +02:00
efb13bc118
add mininal ECPIX-5 board support (Clk/Rst/Leds/UART), BIOS working.
2020-04-22 16:31:07 +02:00
4ad6042e07
platforms/de0nano: swap serial tx/rx to ease use of cheap FT232 based cables.
2020-04-18 11:36:18 +02:00
389e8aa13a
Addition of USB ACM for ECP5
2020-04-14 13:53:46 +01:00
52c9648176
arty_s7: fix copyrights, rename to arty_s7, various minor changes to make it similar to others targets.
2020-04-13 15:20:36 +02:00
bbb1ded9f8
Added Arty S7 board
...
As the pin-out is totally different from the A7 board I did put this
in a separate class and not as a variant of the Arty board.
Used migen Arty S7 board file and Digilent xdc file as reference.
2020-04-12 21:48:25 +02:00
4d7135f167
platforms/versa_ecp5: remove LatticeProgrammer (no longer used since we can now use OpenOCD).
2020-04-09 23:06:57 +02:00
2cf3c3e845
platforms: cosmetic cleanups.
2020-04-09 23:05:13 +02:00
df5de8816d
platforms/ulx3s: cleanup, fix user_leds, add PULLMODE/DRIVE constraints on SDRAM.
2020-04-09 18:53:06 +02:00
467b14a0ad
colorlight_5a_75b: minor comment changes.
2020-04-09 08:14:17 +02:00
4fc9df8414
colorlight_5a_75b/v6.1: Add eth_clock & serial pins
2020-04-09 05:06:08 +02:00
4ddde31429
colorlight_5a_75b/v6.1: Fix bank activate pin
2020-04-09 05:05:29 +02:00
9b3f16af1e
Merge pull request #62 from ilya-epifanov/ecp5-evn-button1-and-spi-flash-ios
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ECP5-EVN board: Added BUTTON_1 and SPI flash pins to IOs
2020-04-08 09:00:12 +02:00
a7fbe0a724
colorlight_5a_75b: add SoC with regular UART (on J19).
2020-04-03 10:28:53 +02:00
9ae8a0cc11
colorlight_5a_75b/v7.0: add spiflash pins.
2020-03-31 16:18:12 +02:00
a43072ac40
ECP5-EVN board: Added BUTTON_1 and SPI flash pins to IOs
2020-03-28 13:08:46 +01:00
ccfc021c1a
Merge pull request #61 from ilya-epifanov/ecp5-evn-programming
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programming the ECP5-EVN flash through the OpenOCD JTAG-SPI proxy
2020-03-28 12:59:19 +01:00
8afc9a5b03
programming the ECP5-EVN flash through the OpenOCD JTAG-SPI proxy
2020-03-28 11:27:34 +01:00
89dd00d3a2
platforms/aller: rename pcie to pcie_x4 (for consistency with others platforms).
2020-03-27 13:01:36 +01:00
d2edf54ab3
zcu104: add fully working SO-DIMM config
2020-03-26 16:37:11 +01:00
6e6b6dac55
platforms/orangecrab: add spisdcard pins.
2020-03-25 10:21:57 +01:00
87fd4dc059
platforms/minispartan6: add spisdcard pins.
2020-03-25 09:53:04 +01:00
92f793f9c5
platforms: remove versa_ecp3 (ECP3 no longer supported).
2020-03-24 19:58:12 +01:00
eb35ec92ba
orangecrab: combine revisions in target
2020-03-23 09:20:01 +10:30
159360da2c
orangecrab: Add r0.2 support
2020-03-22 21:04:07 +10:30
88d3f1d63e
orangecrab: r0.1 OrangeCrab fixes
2020-03-22 20:14:29 +10:30
33bf1d3ee2
Merge pull request #58 from gsomlo/gls-trellisboard-spisdcard
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Move trellisboard target to SoCCore, add SPI-mode SDCard support
2020-03-20 19:07:00 +01:00
Florent Kermarrec
Hans Baier
gatecat
Joel Stanley
Michael Betz
Jan Kowalewski
Sergiu Mosanu
Guillaume REMBERT
Romain Dolbeau
Vadzim Dambrouski
Gary Wong
Alessandro Comodi
Kaz Kojima
Blake Smith
Vadim Kaushan
Gabriel Somlo
Geert Uytterhoeven
la6m
Shinken Sanada
Sahaj Sarup
Robert Winkler
Gwenhael Goavec-Merou
David Shah
Nathaniel R. Lewis
Basel Sayeh
davidcorrigan714
Kevin Mehall
YanekJ
Bryan Jacobs
Pepijn de Vos
DerFetzer
Piense
connorwk
Pawel Sagan
rob-ng15
Vamsi K Vytla
Greg Davill
Owen Kirby
Kamil Rakoczy
Raptor Engineering Development Team
Jędrzej Boczar
Skip Hansen
Vamsi K Vytla
Ilya Epifanov
Dave Marples
Staf Verhaegen
David Sawatzke
Piotr Binkowski