1b1ed5ebf1
add Qmtech EP4CE15 coreboard support
2020-11-12 01:56:36 +02:00
5fbb176c2a
targets/crosslink_nx: update NXLRAM import.
2020-11-09 11:05:18 +01:00
afe44e2bd6
targets/crosslink_nx_evn: update NXPLL import.
2020-11-09 10:25:30 +01:00
39d979a9d3
targets/Ultrascale: add missing AsyncResetSynchronizer import.
2020-11-09 10:25:05 +01:00
97b64d16a6
Lattice NX PLL Support
2020-11-08 20:34:46 -06:00
2b17dc1b89
target: add rst signal to CRG to allow full reset of the SoC on reboot command.
2020-11-04 11:13:42 +01:00
aa6b9cab4a
targets/crosslink_nx_vip: +x.
2020-11-04 09:30:57 +01:00
ce14775dfb
targets/tec0117: move SerialFlashManager import to flash function.
2020-11-04 09:30:31 +01:00
c093d0d0fc
platforms: cleanup pass to uniformize comments/separators/orders.
2020-11-03 10:48:57 +01:00
8d26c241cd
kc705: revert sys_clk_freq to 125MHz.
2020-11-02 19:51:48 +01:00
babf638c2b
targets/nexys_video: add SATA support.
2020-11-02 19:43:25 +01:00
e950a4a588
targets/kc705: update sata pads.
2020-10-30 17:12:59 +01:00
a410e447e1
targets/kc705/sata: enable write support.
2020-10-30 14:51:40 +01:00
f9252fdd45
targets/kc705: simplify SATA using LiteX's add_sata integration method.
2020-10-29 10:16:40 +01:00
7da8628fba
targets/kc705: switch SATA to gen2.
2020-10-28 19:09:30 +01:00
931f6667ac
targets/kc705: add initial SATA support.
2020-10-26 15:15:24 +01:00
51934567fe
Merge pull request #118 from daveshah1/lifcl-vip
...
Add CrossLink-NX VIP board platform and target
2020-10-22 11:03:47 +02:00
a38c1e7062
mist: add copyrights.
2020-10-22 10:48:58 +02:00
20720693c4
crosslink_nx_vip: Add HyperRAM support
...
Signed-off-by: David Shah <dave@ds0.me>
2020-10-22 09:15:40 +01:00
b278d8bccc
Add CrossLink-NX VIP board platform and target
2020-10-22 09:15:35 +01:00
4541c39e94
Initial support for the MIST board ( https://github.com/mist-devel/mist-board/wiki )
2020-10-17 12:28:22 +02:00
814e7630e4
targets/xilinx: use generic name for idelay clk (avoid clk200, clk400, etc...) since we somtimes want to change it.
2020-10-13 12:10:29 +02:00
06137452d2
targets/xcu1525: use ddram_channel to select clk300.
2020-10-13 11:57:00 +02:00
c3ea04b6e9
targets/s7/us: update sdram (manual cmd_latency no longer needed).
2020-10-12 18:46:21 +02:00
ddf7038c78
ulx3s: add 1.7 and 2.0 revisions support.
2020-10-12 13:23:26 +02:00
5e67853a21
versa_ecp5: Add --eth-phy to select ethernet phy
...
This also simplifies the logic a bit.
2020-10-09 23:56:16 +02:00
477734ff06
versa_ecp5: Add etherbone support
...
Etherbone can be enabled with --with-etherbone
2020-10-09 00:53:08 +02:00
fff20f7532
targets/fomu: base it on iCEBreaker target + USB-ACM.
...
This uniformizes Fomu target with others, provide a simple example of LiteX SoC
on Fomu and will ease maintenance.
2020-10-06 11:39:30 +02:00
79ef091a06
Merge pull request #110 from pepijndevos/gowin
...
Add initial support for Trenz TEC0117 board
2020-10-05 19:50:09 +02:00
062fbd6c63
Merge pull request #108 from daveshah1/dave/nx-evn-doc
...
crosslink_nx_evn: Improve documentation on UART jumpers
2020-10-02 09:40:04 +02:00
18e5def9f2
don't verify erase, very slow
2020-10-01 08:41:16 +02:00
81e4f1f158
add initial support for Trenz TEC0117 board
2020-09-30 14:01:36 +02:00
de09b10726
targets/xcu1525: add ddram-channel selection and rewrite DRC workaround comment.
2020-09-24 18:19:49 +02:00
cc53206aff
targets/kcu105: create specific cd_eth for ethphy.
2020-09-24 10:25:55 +02:00
5b7288cfee
targets/kcu105: add Etherbone support.
2020-09-24 09:55:11 +02:00
77ba49f2bb
targets/pcie: update timing_constraints (now provided by the .xci).
2020-09-24 09:50:55 +02:00
e4cdbe0f7a
targets/ac701: reduce ddram pads to the first 4 modules.
2020-09-05 11:46:07 +02:00
8a9fd02768
crosslink_nx_evn: Improve documentation on UART jumpers
...
Signed-off-by: David Shah <dave@ds0.me>
2020-09-05 09:58:28 +01:00
76ac4a69a8
rename forest_kitten_33 platform/target to fk33.
2020-09-04 20:05:18 +02:00
979fee7517
forest_kitten_33: add pcie.
2020-09-04 20:02:43 +02:00
ad48728160
xcu1525: update headers (were still using old format).
2020-09-04 19:59:09 +02:00
ad4c483c32
Merge pull request #106 from daveshah1/dave/alveo_u250_pcie
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alveo_u250: Add PCIe x4 support
2020-09-04 19:22:48 +02:00
a68c00e48e
Merge pull request #104 from DerFetzer/colorlight_5a_75e_v6_0
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Add support for 5A-75E V6.0 board
2020-09-04 19:21:02 +02:00
ae6a052e57
alveo_u250: Add PCIe x4 support
...
Based on the implementation in xcu1525
Signed-off-by: David Shah <dave@ds0.me>
2020-09-04 14:20:04 +01:00
2eda9d0252
xcu1525: add DDR4 IOs for C1/C2/C3 and fix compilation (untested).
2020-09-04 11:34:33 +02:00
7b6b71d4e3
xcu1525: add initial DDR4 support in C0 (untested).
2020-09-03 19:48:23 +02:00
5a62a07b45
xcu1525: add initial PCIe support (untested).
2020-09-03 19:26:02 +02:00
51e881d1ff
add minimal xcu1525 support (VCU1525 or BCU1525 boards).
2020-09-03 19:06:43 +02:00
8bd736bd77
targets/colorlight_5a_75x: make Ethernet PHY selectable, cast sys_clk_freq to int for Wishbone
2020-09-02 22:08:45 +02:00
24b853c2db
targets/colorlight_5a_75x: force use of internal oscillator when using Ethernet with 5A-75E V6.0
2020-09-01 17:07:52 +02:00
8b1fee0e66
Add support for 5A-75E V6.0 board
2020-09-01 17:02:17 +02:00
9b6ed6bdf1
targets/orangecrab: add fallback to bootloader when usr_btn is pressed for 1 second.
2020-09-01 16:22:32 +02:00
b9ac72cf78
targets: simplify clocking on iCE40/ECP5 targets (AsyncResetSynchronizer now integrated in PLL).
2020-09-01 13:38:32 +02:00
9e2d301745
targets/icebreaker: simplify, update PLL/API and BIOS execution from SPI Flash.
2020-09-01 12:58:13 +02:00
beccecf59f
orangecrab: reduce DDR3 power consumption/heat and get back USB PLL to CRGSDRAM.
...
- disable DQ termination.
- disable RTT_NOM.
- drive VCCIO/GND pads.
Reduce current from 0.25A to 0.12A with: ./orangecrab.py --uart-name=usb_acm --sys-clk-freq=48e6.
Still working at 96MHz, 0.17A with: ./orangecrab.py --uart-name=usb_acm --sys-clk-freq=96e6.
See https://github.com/enjoy-digital/litedram/issues/216 .
2020-08-28 20:01:54 +02:00
63b65e278c
crosslink_nx_evn: update copyrights.
2020-08-24 22:33:58 +02:00
153326fa26
targets/icebreaker: update flash.
2020-08-24 17:19:15 +02:00
795e34aafd
add initial Crosslink-NX support.
2020-08-24 16:47:38 +02:00
84c19a6cdf
targets/de0nano: set sys2x_ps phase to 180° for sdram_rate=1:2.
2020-08-24 09:28:51 +02:00
70594a5305
ulx3s: simplify sdram constraints and increase phase to 180 for sdram_rate=1:2.
2020-08-24 09:05:58 +02:00
1781be166a
general: add SPDX License identifier to header and specify files are part of LiteX-Boards.
2020-08-23 15:00:17 +02:00
f328909578
Moved platform call inside of BaseSoC init for compatibility with linux-on-litex-vexriscv support. Added optional spi-sdcard support over P2 header.
2020-08-09 16:27:41 -04:00
45bb329b56
targets/colorlight_5a_75x: enable HalfRate SDRAM PHY.
2020-08-07 19:26:12 +02:00
b6a1ad5a9c
targets/orangecrab: add simple CRG when built without DDR3.
2020-08-07 18:10:03 +02:00
869ceadacb
targets: use platform.request_all on LedChaser.
2020-08-06 20:04:03 +02:00
ee28d7b5ec
targets/ulx3s/add_oled: simplify.
2020-08-04 12:31:15 +02:00
eba70377b7
add optional OLED peripheral to ULX3S target
2020-08-04 11:07:30 +02:00
5fd3e8dbcd
ecpix5: add SDCard.
...
Validated with Linux-on-LiteX-VexRiscv.
2020-07-28 17:45:49 +02:00
94ccf1dd3e
targets/trellisboard: simplify clocking when no DDR3, remove firmware_ram (was here for debug).
2020-07-27 16:31:46 +02:00
eb8a484032
targets/de10nano: fix typo.
2020-07-26 12:01:11 +02:00
2cef54a909
targets/colorlight_5a_75x: avoid sys_clk_freq of 125MHz with etherbone (no longer required).
...
This allows creating SoCs with CPU, SDRAM and Etherbone enabled all together.
2020-07-26 11:58:42 +02:00
760b8ff93a
arty: improve xy_pmod_io genericity (allow selecting the PMOD) and enable SDCard.
2020-07-24 16:29:35 +02:00
04fc98f834
de0nano/ulx3s: add sdram HalfRate support (untested).
2020-07-24 16:12:46 +02:00
d0ca1befa6
targets/de10nano/minispartan6: simplify HalfRate support, rename argument to sdram_rate.
2020-07-24 16:11:57 +02:00
89c5bf43cf
Merge pull request #92 from rob-ng15/master
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Enable use of HalfRateGENSDRPHY on de10nano
2020-07-24 08:49:09 +02:00
1e1589a514
zybo_z7: demonstrate use of PS7 (with --cpu-type=zynq7000).
...
This uses a pre-generated .xci hosted on github, still need to figure out where the best location for it.
2020-07-23 17:45:21 +02:00
7cda143250
Allow use of HalfRateGENSDRPHY
2020-07-23 14:41:35 +01:00
8a3b453e2f
add Zybo Z7 minimal platform/targets: no PS7 support and USB-UART PMOD on JB.
2020-07-23 15:26:22 +02:00
19d0b95867
platforms/targets: keep in sync with litex.
2020-07-22 08:53:49 +02:00
02f53e6326
targets/minispartan6: add support for HalfRateGENSDRPHY
2020-07-14 11:01:09 +02:00
d9595a317e
targets/orangecrab: use user_btn as rst_n.
2020-07-06 17:49:05 +02:00
7b1bf9d74a
targets: remove sdcard specific clock domain (now generated by the PHY).
2020-07-03 20:09:30 +02:00
31e6997e70
sdcard: rename cd_sdcard to cd_sd to avoid unnecessary clock domain.
2020-07-01 12:58:48 +02:00
fe3ea805bc
targets/pcie: make pcie optional (--with-pcie) and avoid forcing uart to crossover.
2020-06-30 18:44:00 +02:00
7a48a61605
targets: add indentifier on all targets.
2020-06-30 18:11:04 +02:00
fc22e28fe9
targets: replace PCIeSoC with BaseSoC.
2020-06-30 17:41:57 +02:00
d28a0c4258
targets/pcie: remove DNA/XADC/ICAP that were only on PCIe targets.
...
DNA/XADC/ICAP are demonstrated in LitePCIe repository and should probably be added with
a add_xy method.
2020-06-30 17:37:24 +02:00
e91a5d6b82
targets/pcie: remove soft reset.
2020-06-30 17:28:13 +02:00
1356ebb416
targets/ecp5: update clocking on boards with DDR3 to use reset from ddrphy.init and use primary clock for Power on reset.
2020-06-29 16:42:53 +02:00
49973990f3
Merge pull request #85 from oskirby/logicbone
...
Add Logicbone ECP5 board
2020-06-29 16:24:15 +02:00
76a32ba8ec
Add Logicbone ECP5 board
...
The Logicbone is an Open Source development board for the Lattice ECP5
being developed at https://github.com/oskirby/logicbone
2020-06-27 03:32:47 -07:00
efe33c9764
targets/arty: add fixed sdcard clock and remove sys2x (use NETWORKING interface_type on DDR3).
2020-06-25 11:21:24 +02:00
6753a92296
targets: add fixed sdcard clock on boards with SDCard support.
2020-06-25 11:20:38 +02:00
04f6d4463a
versa_ecp5: simplify device (LFE5UM5G or LFE5UM) and adapt integrated_rom_size only for Microwatt.
2020-06-13 11:17:05 +02:00
90092164c8
Add device option for ECP5 Versa board
...
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
2020-06-12 18:39:43 -05:00
b1be5dcc23
Fix FTBFS from undersized BIOS ROM region with Microwatt
...
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
2020-06-12 18:39:43 -05:00
9b45ec0f35
de10lite: simplify vga terminal.
2020-06-11 19:59:32 +02:00
85cac7abc0
de10nano/Mister: review/simplify.
2020-06-11 19:54:55 +02:00
64372d7876
targets/orangecrab: add spi-sdcard and workaround for ValentyUSB.
2020-06-11 19:21:44 +02:00
c94cbae0c0
orangecrab: add user_led (RGB leds), DFUProg and --load support.
2020-06-11 19:21:40 +02:00
9aea2272eb
Merge pull request #80 from rob-ng15/master
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Use 128mb sdram, uart via i/o port on i/o board and vga terminal via i/o board
2020-06-11 18:16:18 +02:00
45bd50b000
targets: rename colorlight_5a_75b to colorlight_5a_75x (since we are now also supporting the 75e).
2020-06-10 23:14:37 +02:00
ad1693a1ad
Merge pull request #82 from Disasm/colorlight-5a-75e
...
Add Colorlight 5A-75E V7.1 board
2020-06-10 23:09:26 +02:00
94861bbb9a
targets/orangecrab: uncomment MT41K512M16.
2020-06-10 19:30:07 +02:00
0c590abf12
Update colorlight_5a_75b target: add 5A-75E board support
2020-06-10 03:20:32 +03:00
485c242f24
Use 128mb sdram, uart via i/o port on i/o board and vga terminal via i/o board
2020-06-08 11:05:58 +01:00
f9a8edb973
targets/trellisboard: add initial LiteSDCard support
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-06-03 13:41:57 -04:00
d87a11a9cb
targets/pcie: use generate_litepcie_software on all targets with PCIe.
2020-06-03 08:30:54 +02:00
9f83b6e3cf
targets/acorn_cle_215: use new generate_litepcie_software functions and add --driver argument to generate driver.
2020-06-03 08:20:43 +02:00
091ec846a1
targets/acorn_cle_215: automatically copy software from litepcie and generate headers in kernel directory.
2020-06-02 20:09:45 +02:00
06edf48897
targets: rename gateware-toolchain parameter to toolchain.
2020-06-02 13:45:05 +02:00
76df4e39c8
targets: simplify Ethernet/Etherbone integration on targets with both.
2020-05-29 19:20:27 +02:00
2e1a816d1f
pano_logic_g2: switch to LiteEthPHY and simplify Ethernet/Etherbone.
2020-05-29 10:41:35 +02:00
33fe308ef0
Merge pull request #78 from antmicro/jboc/spd-read
...
ZCU104: add I2C
2020-05-27 14:56:31 +02:00
e5578a1ae8
zcu104/platform: change I2C number to 0
2020-05-27 14:31:22 +02:00
ac1f1cd6a7
zcu104: add I2C
2020-05-27 12:47:43 +02:00
71f220a24d
colorlight_5a_75b: remove unnecessary parenthesis.
2020-05-27 10:13:44 +02:00
2f3817cba9
pano_logic_g2: add ethernet (build but not functional yet) and use user_btn_n as sys_rst.
2020-05-27 10:13:12 +02:00
f19bc36813
pano_logic_g2: add revision support (b and c, c as default) and add OpenOCD programmer.
...
Tested with:
./pano_logic_g2.py --uart-name=jtag_uart --build --load
./litex_jtag_uart.py --config=openocd_xc6_ft232.cfg
lxterm /dev/pts/X
2020-05-27 08:58:40 +02:00
22f18f618e
pano_logic_g2: move gmii_rst_n to _CRG.
2020-05-26 08:36:06 +02:00
1ab46562bd
Take Ethernet PHY out of reset so default clock is 125 Mhz (and baud rate is 115,200)
2020-05-25 10:11:03 -07:00
9b572ece0e
forest_kitten_33: add minimal target and use es1.
...
Tested with:
./forest_kitten_33.py --uart-name=jtag_uart --build --load
litex/tools/litex_jtag_uart.py
lxterm /dev/pts/X
2020-05-25 12:26:52 +02:00
435913f7d8
platforms/nexys4ddr: add option to build with spi-mode sdcard support
2020-05-24 19:09:25 -04:00
5aeb7d85e6
targets/acorn_cle_215: fix typo in description.
2020-05-21 10:18:06 +02:00
eeba64d7b2
targets: use soc.build_name in load/flash bitstream.
2020-05-21 09:12:29 +02:00
8158d94ae7
targets/c10lprefkit: switch to litehyperbus.
2020-05-19 15:48:19 +02:00
b9ee3a797a
alveo_u250: re-organize the auto-generated IOs, add build/load parameters.
2020-05-16 11:47:14 +02:00
c0b7afc739
targets/alveo_u250: +x.
2020-05-16 11:13:01 +02:00
482d7a6b95
targets/pcie: use 128-bit datapath and 8 max_pending_requests on pcie_x4 configurations.
2020-05-14 15:34:00 +02:00
2bb7fce5e3
targets/acorn_cle_215: add minimal instructions to reproduce the results.
2020-05-13 17:55:52 +02:00
6757c4e298
Merge pull request #71 from daveshah1/alveo_u250
...
[WIP] Add Alveo U250 platform and target
2020-05-13 09:10:22 +02:00
c7404e356f
targets/acorn_cle_215: switch to MT41K512M16 (Acorn has a 1GB DDR3 vs 512MB on NiteFury).
2020-05-09 16:39:17 +02:00
d05b10fd76
target/camlink_4k: add missing import.
2020-05-09 12:27:07 +02:00
6f22f082ff
targets: add LedChaser on platforms with user_leds.
...
Default to Chaser mode and similar user interface than GPIOOut.
2020-05-08 22:16:13 +02:00
b9a0f2363c
Merge pull request #74 from tommythorn/master
...
targets/orangecrab.py: propagate command arguments
2020-05-08 07:28:05 +02:00
19b12fd984
targets/panol_logic_g2: replace with a minimal target.
2020-05-07 16:36:04 +02:00
6b5492a707
pano_logic_g2: add copyrights.
2020-05-07 15:24:03 +02:00
6ddd859309
add pano_logic_g2 from litex-buildenv.
2020-05-07 15:22:22 +02:00
27c242b2ca
targets/pcie: switch to PCIe X4 on all boards that support it.
2020-05-07 12:18:39 +02:00
f9939532b6
targets/pcie: update LitePCIe constraints.
2020-05-07 12:15:52 +02:00
6335717eca
targets/orangecrab.py: propagate command arguments
...
The parsed args are stripped off by soc_core_argdict() (called from
soc_sdram_argdict() so we have to pass them explicitly (or pass the
original "args", but this mimics the rest of the code in the repo).
This fixes #72
2020-05-06 18:24:11 -07:00
59e8c2cd30
acorn_cle_215: add .bin generation and --flash argument, working on hardware :).
2020-05-06 12:27:07 +02:00
a049fa6856
add Acorn CLE 215+ platform/target.
2020-05-06 07:53:55 +02:00
da61aabc5b
targets: remove USDDRPHY_DEBUG and set cmd_latency to on all Kintex7/Ultrascale targets.
2020-05-05 16:32:10 +02:00
2d9543b65e
targets: add build/load parameters on all targets.
2020-05-05 15:11:47 +02:00
84468c2a63
targets/CRG: platforms are now automatically constraining the input clocks.
2020-05-05 11:51:57 +02:00
1f88a9d5ec
platforms: make sure clocks inputs are constraints on all platforms.
...
Also use new loose lookup_request to simplify constraints.
2020-05-05 11:45:41 +02:00
78b5727774
targets: rename usb_cdc to usb_acm.
...
As discussed recently on Discord.
2020-04-30 21:48:10 +02:00
088cceca8b
Add Alveo U250 platform and target
...
Signed-off-by: David Shah <dave@ds0.me>
2020-04-29 12:31:16 +01:00
2213d73b89
targets/kcu105: use cmd_latency=1.
2020-04-25 12:13:49 +02:00
a8a42c55c9
targets/kc705: manual DDRPHY_CMD_DELAY adjustment no longer needed.
2020-04-25 11:08:05 +02:00
865b01ec75
ecpix5: add ethernet.
2020-04-22 20:21:59 +02:00
6fe4c4ea62
ecpix5: add DDR3 (working)
2020-04-22 17:03:22 +02:00
efb13bc118
add mininal ECPIX-5 board support (Clk/Rst/Leds/UART), BIOS working.
2020-04-22 16:31:07 +02:00
4154bdf034
targets/PCIe: add PCIe software reset.
2020-04-20 12:30:09 +02:00
4185a019f5
targets: manual define of the SDRAM PHY is no longer needed.
2020-04-16 11:25:59 +02:00
cb95962850
targets/ulx3s and colorlight_5a_75b: cleanup USB ACM addition and only keep USB ACM changes.
...
- remove update in loading/flashing: we need to thinks how to integrate this.
- remove specific README: documentation is moved to the files, link to more complete project can
be added if maintained externally, as done for the iCEBreaker for example.
- revert default freq on ULX3S to 50MHz and instantiate a second PLL as done on the colorlight.
2020-04-14 16:14:18 +02:00
f79a010a29
Addition of flash for colorlight board
2020-04-14 14:37:56 +01:00
389e8aa13a
Addition of USB ACM for ECP5
2020-04-14 13:53:46 +01:00
a12faae0fb
targets/colorlight_5a_75b: increase sys_ps phase (fixes memtest).
2020-04-14 11:24:16 +02:00
52c9648176
arty_s7: fix copyrights, rename to arty_s7, various minor changes to make it similar to others targets.
2020-04-13 15:20:36 +02:00
bbb1ded9f8
Added Arty S7 board
...
As the pin-out is totally different from the A7 board I did put this
in a separate class and not as a variant of the Arty board.
Used migen Arty S7 board file and Digilent xdc file as reference.
2020-04-12 21:48:25 +02:00
188d4a45d6
targets: use DDROutput on sdram_clock and similar configuration for all SDRAM targets.
2020-04-10 14:43:04 +02:00
ca197af2be
targets/simple: use CRG from litex.build.
2020-04-10 10:26:19 +02:00
b8a648d499
litex.build: update from migen.genlib.io litex.build.io.
2020-04-10 09:23:33 +02:00
467b14a0ad
colorlight_5a_75b: minor comment changes.
2020-04-09 08:14:17 +02:00
15a27d40fa
targets/colorlight_5a_75b: Change baudrate to work on v6.1
...
There seems to be some capacitance on KEY+, so the usual 115200 don't work
2020-04-09 05:08:23 +02:00
db67dff0ea
targets/de10lite: use Max10PLL, remove 50MHz limitation.
2020-04-08 08:55:30 +02:00
8ccab03358
targets/c10lprefkit: use Cyclone10LPPLL, remove 50MHz limitation.
2020-04-08 08:34:59 +02:00
4cdc121327
targets/de10nano: use CycloneVPLL, remove 50MHz limitation.
2020-04-08 08:11:04 +02:00
2d8a4ef9ec
targets/de1_soc: use CycloneVPLL, remove 50MHz limitation.
2020-04-08 08:07:37 +02:00
cec4cbb6dc
targets/de2_115: use CycloneIVPLL, remove 50MHz limitation.
2020-04-08 08:03:41 +02:00
1fac6077fb
targets/de0nano: use CycloneIVPLL, remove 50MHz limitation.
2020-04-07 17:01:58 +02:00
5f629c203b
targets/vcu118: fix clk500 typo.
2020-04-07 13:53:22 +02:00
a7fbe0a724
colorlight_5a_75b: add SoC with regular UART (on J19).
2020-04-03 10:28:53 +02:00
19e5366ad1
targets/colorlight_5a_75b: update sys/sys_ps phases.
2020-03-31 18:18:45 +02:00
d2edf54ab3
zcu104: add fully working SO-DIMM config
2020-03-26 16:37:11 +01:00
3b91e96c42
targets/add_constant: avoid specifying value when value is None (=default)
2020-03-26 09:47:22 +01:00
555bf6c4dc
targets/Ultrascale(+): enable USDDRPHY_DEBUG.
2020-03-26 09:17:09 +01:00
4053c02d7e
targets/orangecrab: add USB PLL for USB CDC with ValentyUSB.
2020-03-25 19:38:36 +01:00
85f38876c2
targets: update PCIe on Numato targets.
...
Should be compatible with software from: https://github.com/enjoy-digital/netv2 .
2020-03-25 11:53:52 +01:00
24033e331c
targets: update SDRAM to use new GENSDRPHY and new ECP5PLL phase support.
2020-03-24 19:59:42 +01:00
eb35ec92ba
orangecrab: combine revisions in target
2020-03-23 09:20:01 +10:30
159360da2c
orangecrab: Add r0.2 support
2020-03-22 21:04:07 +10:30
bf3c9dc9bf
orangecrab: Add sdram selection option
2020-03-22 20:41:12 +10:30
88d3f1d63e
orangecrab: r0.1 OrangeCrab fixes
2020-03-22 20:14:29 +10:30
78224b1e56
targets/colorlight_5a_75b: add SDRAM.
2020-03-21 22:11:47 +01:00
a95a4eed3f
targets/colorlight_5a_75b: switch to add_ethernet/add_etherbone methods.
2020-03-21 21:50:05 +01:00
7bba5caab0
targets/c10prefkit: remove keep attributes (no longer needed, added automatically).
2020-03-21 21:44:44 +01:00
6c31933e89
targets: switch to add_etherbone method.
2020-03-21 21:40:45 +01:00
159386e3d3
targets: always use sys_clk_freq on SDRAM modules.
2020-03-21 20:00:56 +01:00
3fb3ba18e8
targets: switch to add_ethernet method instead of EthernetSoC.
2020-03-21 18:29:52 +01:00
83e6fb29f8
targets: switch to SoCCore/add_sdram instead of SoCSDRAM.
2020-03-21 12:43:39 +01:00
33bf1d3ee2
Merge pull request #58 from gsomlo/gls-trellisboard-spisdcard
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Move trellisboard target to SoCCore, add SPI-mode SDCard support
2020-03-20 19:07:00 +01:00
fb1cab857a
targets/arty: use new ISERDESE2 MEMORY mode.
2020-03-20 18:59:17 +01:00
f021c1de5f
targets/trellisboard: add '--with-spi-sdcard' build option
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Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-20 07:14:13 -04:00
69a78c8c66
targets/trellisboard: switch to SoCCore, use add_ethernet() method
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Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-19 18:09:37 -04:00
6ab13a0661
de10nano/MiSTer: rename SPI SD CARD pins to spisdcard and remove SPI SD Card integration from target.
2020-03-19 11:09:48 +01:00
bc6ef0bc48
Allow access to secondary sd card via hardware spi bitbanging
2020-03-18 12:13:37 +00:00
a99d258411
targets/icebreaker: use simplified version closer to the others targets.
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Add description of the board, link to the crowdsupply campaign and to the more complete example.
2020-03-13 09:43:43 +01:00
74a5ffb9ef
targets/Ultrascale+: use 500MHz IDELAYCTRL reference clock.
...
The minimum is 300MHz on Ultrascale+ vs 200MHz on Ultrascale.
2020-03-10 16:58:30 +01:00
e2a66090ee
targets/Ultrascale(+): simplify CRG using USIDELAYCTRL.
2020-03-10 16:55:22 +01:00
cf58550bba
targets/Ultrascale+: use USPDDRPHY.
2020-03-10 16:06:48 +01:00
90de99eb46
platforms/mercury_xu5: fix sdram timing issues
2020-03-10 15:03:31 +01:00
f4ae21a7a2
zcu104: fix copyrights.
2020-03-09 09:24:06 +01:00
5031c11d57
mercury_xu5: add missing copyrights.
2020-03-09 09:23:08 +01:00
dc1371108d
Merge pull request #52 from antmicro/jboc/mercury-xu5
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add Enclustra Mercury XU5 board
2020-03-09 09:11:15 +01:00
2b1b9684de
targets/icebreaker: simplify CRG, just use a 12MHz sys_clk and por_clk for reset.
2020-03-07 18:25:26 +01:00
9416ddd84a
targets/icebreaker: simplify arguments and make it closer to others targets.
2020-03-07 18:13:02 +01:00
992f7066fa
targets/icebreaker: simplify leds.
2020-03-07 18:12:59 +01:00
682316214c
targets/icebreaker: use specific method to set Yosys/Nextpnr settings. Rename argument to nextpnr-xxyy.
2020-03-07 18:12:52 +01:00
f777d4b08c
targets/icebreaker: +x
2020-03-05 23:11:35 +01:00
6f517ad1d6
targets/ecp5: make sure all BaseSoC/EthernetSoc default to trellis.
2020-03-05 10:57:59 +01:00
d002059e0b
add Enclustra Mercury XU5 board
2020-03-05 10:52:32 +01:00
745c99ba14
icebreaker: Updated to build on newer litex. Disabled bios building.
2020-03-05 00:12:18 -08:00
3ac9d927a9
targets: icebreaker: Minor style fixes.
2020-03-05 00:12:18 -08:00
738967176c
targets: icebreaker: set the boot address to point to SPI flash
...
Signed-off-by: Sean Cross <sean@xobs.io>
2020-03-05 00:12:18 -08:00
093e4913c4
targets: icebreaker: hack to get boot working
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Signed-off-by: Sean Cross <sean@xobs.io>
2020-03-05 00:12:18 -08:00
77b780eb4b
targets: icebreaker: switch to single SPI
...
The Icebreaker doesn't have the QE/ bit set in config, so default to
using single SPI.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-03-05 00:12:18 -08:00
e6dcdc31ed
targets: icebreaker: fix cpu and add spi flash
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Signed-off-by: Sean Cross <sean@xobs.io>
2020-03-05 00:12:18 -08:00
0185095782
targets: icebreaker: fix argument parsing for cpu
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Signed-off-by: Sean Cross <sean@xobs.io>
2020-03-05 00:12:18 -08:00
f0dd31f6c8
target: targets: add crg and begin getting it working
...
Signed-off-by: Sean Cross <sean@xobs.io>
2020-03-05 00:12:18 -08:00
ce9b67e2ee
Added icebreaker platform and target.
...
Target is heavily based on Fomu.
2020-03-05 00:12:18 -08:00
be5ed35871
targets: default to trellis toolchain on all ECP5 targets (now able to build all supported targets).
2020-02-28 09:46:54 +01:00
b44885d222
vc707: fix copyrights (Michael Betz is the initial author)
2020-02-28 08:39:52 +01:00
b89af28a05
targets/kc705: use DDRPHY_CMD_DELAY to center write leveling.
2020-02-27 12:58:52 +01:00
d8de4fbdfb
platforms/targets: keep in sync with LiteX
2020-02-27 11:06:53 +01:00
d87b8b3c66
zcu104: add separate ddram_32/64 definitions and use ddram_32 for now.
...
Ease switching between ddram_32 and ddram_64.
2020-02-27 10:05:17 +01:00
8ecfb13f3c
zcu104: add copyrights
2020-02-27 09:57:26 +01:00
608541d5b8
add ZCU104 board
2020-02-26 13:53:21 +01:00
4a84e9b08a
targets/colorlight_5a_75b: add instruction to build/load and use bitstream with wishbone-tool
2020-02-25 12:47:08 +01:00
f279fe9d33
vc707: cleanup platform/targets, remove Ethernet support (no Ethernet pads defined)
2020-02-25 10:35:18 +01:00
3581df5af6
vc707: cleanup platform/targets, remove Ethernet support (SGMII is not currently supported)
2020-02-25 09:41:53 +01:00
88a1f80db1
vc707/vcu118: use proper copyrights
2020-02-25 09:03:52 +01:00
373e74f435
add new board files for VC707 and VCU118, only specified limited ports for VCU118, including clock, reset and DDR4
2020-02-24 14:20:47 -05:00
f72e7bd314
Merge pull request #41 from lromor/fix-wrong-import
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Changed wrong imports for fomu board.
2020-02-12 18:48:13 +07:00
ec30cc05c3
Changed wrong imports for fomu board.
2020-02-12 12:40:07 +01:00
c94360c2e0
targets: avoid direct use of mem_decoder.
2020-02-11 21:59:42 +01:00
4edf196911
targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC)
2020-02-11 17:45:35 +01:00
8211aca2e8
Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
...
We initially wanted to provide different level of support for the platforms/targets, mainly
to avoid too much maintenance and let each contributor update its contributed platforms and
targets, but it's easier to update all platforms/targets all-together when LiteX evolves or
changes (and that's what has been done on litex-boards since the creation of the repository).
So let just simplify things and avoid this differentiation.
2020-02-03 09:36:30 +01:00
Basel Sayeh
Florent Kermarrec
davidcorrigan714
David Shah
YanekJ
Konrad Beckmann
Pepijn de Vos
DerFetzer
Piense
connorwk
rob-ng15
Jędrzej Boczar
Owen Kirby
Raptor Engineering Development Team
Vadim Kaushan
Gabriel Somlo
Skip Hansen
Tommy Thorn
Dave Marples
Staf Verhaegen
David Sawatzke
Piotr Binkowski
Greg Davill
Piotr Esden-Tempski
Sean Cross
Fei Gao
Leonardo Romor