Charles Papon
066ddc23e6
Add regression concurrent os executions flag to avoid running debug plugin tests
2019-06-11 00:22:38 +02:00
Charles Papon
21c8933bbb
Fix DYNAMIC_TARGET prediction correction in BranchPlugin
2019-06-11 00:12:29 +02:00
Charles Papon
5b53440d27
DYNAMIC_TARGET prediction datapath/control path are now splited
2019-06-10 22:20:32 +02:00
Charles Papon
0e95154869
individual regression : more env control
2019-06-10 21:01:41 +02:00
Charles Papon
bd46dd88aa
Fix RVC fetcher pc branches
2019-06-10 20:48:04 +02:00
Charles Papon
24e1e3018c
Fix exception handeling
2019-06-09 23:40:37 +02:00
Charles Papon
5243e46ffb
Fix BranchPlugin when SRC can have hazard in execute stage
2019-06-09 20:15:36 +02:00
Charles Papon
af0755d8cf
rework flush with flushNext and flushIt
...
static branch prediction jump do not depend on stage fireing anymore
2019-06-09 15:44:05 +02:00
Charles Papon
357681a5c6
csrPlugin add pipelinedInterrupt, set by default
2019-06-08 22:22:16 +02:00
Charles Papon
0df4ec45ad
Merge remote-tracking branch 'origin/master' into dev
...
# Conflicts:
# build.sbt
2019-06-05 00:35:41 +02:00
Charles Papon
56f7c27d18
Fix WFI. Not sensitive anymore to global interrupt enables, delegation and privilege
2019-06-05 00:32:38 +02:00
Charles Papon
38a464a829
DataCache now allocate ways randomly
2019-05-25 00:28:30 +02:00
Charles Papon
4a40184b35
Add cache Bandwidth counter, previous commit was about random instruction cache way allocation
2019-05-25 00:22:27 +02:00
Charles Papon
94606d38e2
Add cache bandwidth counter
2019-05-25 00:21:48 +02:00
Charles Papon
206c7ca638
Fix Bmb datacache bridge
2019-05-24 00:22:58 +02:00
Charles Papon
f6f94ad7c1
Fix InstructionCache Bmb bridge
2019-05-22 19:03:26 +02:00
Charles Papon
9b49638654
Allow CsrPlugin config access
2019-05-22 17:27:47 +02:00
Charles Papon
8abc06c8f2
Add Bmb support for i$/d$
2019-05-22 17:04:36 +02:00
Charles Papon
49b4b61a1a
Update Bmb bridges
2019-05-20 14:14:42 +02:00
Charles Papon
0301ced000
Fix dBusSimplePlugin to bmb bridge
2019-05-16 19:49:13 +02:00
Charles Papon
3753f64429
Fix Bmb compilation
2019-05-13 23:44:20 +02:00
Dolu1990
abb7bd99ab
Merge pull request #75 from SpinalHDL/dev
...
Merge dev (SpinalHDL 1.3.4)
2019-05-10 17:28:09 +02:00
Charles Papon
db307075cf
Merge branch 'AHB' into dev
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# Conflicts:
# src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
# src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
2019-05-07 17:21:52 +02:00
Charles Papon
01db217ab9
Add supervisor support in the ExternalInterruptArrayPlugin
2019-05-06 16:23:43 +02:00
Charles Papon
d27fa4766d
DBusCachedPlugin add earlyWaysHits in regressions
2019-05-06 00:05:40 +02:00
Charles Papon
d12decde80
Remove test which had issues with the testbench ref checks because of getting passed delayed
2019-05-05 22:46:46 +02:00
Charles Papon
5f18705358
Add DBusCachedPlugin.relaxedMemoryTranslationRegister option
2019-05-05 21:19:48 +02:00
Charles Papon
c738246610
Remove the legacy pipelining from Axi4 cacheless bridges
2019-05-01 12:03:01 +02:00
Sean Cross
d1e215e312
caches: work without writeBack stage
...
In the case of an MMU miss, the data caches will create a retry branch port.
These currently implicitly go into the memory/writeBack stage, however
not all CPUs have this stage.
Place the retry branch port into the correct stage.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-04-26 18:02:43 +08:00
Sean Cross
b2f387ccac
MmuPlugin: fix generation without writeBack stage
...
If there is no writeBack stage, the elaboration step would hit a
NullPointerException when trying to insert into the writeBack stage.
Instead, pull from the most recent stage, which is where MMU access
should reside.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-04-26 18:01:35 +08:00
Charles Papon
d64589cc48
Add configs without memory/writeback stages in regressions
...
Add rfReadInExecute configs in regressions
Fix ShiftPluginLight and DBusSimplePlugin for configs with rfReadInExecute stage configs
2019-04-25 17:36:13 +02:00
Charles Papon
74e5cc49f9
Add the linux config into the synthesis bench
2019-04-24 12:32:37 +02:00
Charles Papon
a331f35724
Icestorm flow now use nextpnr
2019-04-24 12:32:24 +02:00
Charles Papon
b654d824ad
remove DebugPlugin from linux.scala, and set static branch prediction
2019-04-23 21:55:54 +02:00
Charles Papon
266bdccc2e
update Riscv software model lrsc implementation
2019-04-23 21:55:54 +02:00
Charles Papon
4078f84e8f
Dhrystone regression now also run coremark
2019-04-23 21:55:54 +02:00
Charles Papon
c6dbaa52f6
Longer linux regression timeout for very slow configs
2019-04-21 22:16:42 +02:00
Charles Papon
14efe6ffda
Riscv software model now implement interrupt priority accordingly to 496c59d064 (diff-a38d447c5232bd448697af4c6c8adb1a)
changes
2019-04-21 20:01:39 +02:00
Charles Papon
d7ca153c8b
remove interrupt assertion
2019-04-21 19:45:24 +02:00
Charles Papon
0e10c460c3
Update Zephyr tests, the mem_pool_threadsafe one was bugy by the past, and now it is just too long
2019-04-21 17:58:42 +02:00
Charles Papon
4cbb93cfc8
Look like zephyr mem_pool_threadsafe is a broken test
2019-04-21 17:48:08 +02:00
Dolu1990
1c86bf7514
Increase liveness trigger to allow large instruction cache flush
2019-04-21 15:25:39 +02:00
Charles Papon
963805ad48
Bring freertos back in tests
...
Better travis test range
2019-04-21 12:50:28 +02:00
Charles Papon
edde3e3011
Add zephyr tests
2019-04-21 02:56:44 +02:00
Charles Papon
3b0f2e9551
better travis timings
...
travis job naming
reduce verilator cache size
Fix dcache test timeout
travis cleaning
travis wip
verilator wip
fix java 10 compilation
Travis wip
travis rework
2019-04-20 14:56:56 +02:00
Charles Papon
b49076ecab
add missing coremark patch
2019-04-19 19:41:05 +02:00
Charles Papon
728a5ff20f
Fix coremark binaries (no csr)
2019-04-19 18:28:46 +02:00
Charles Papon
e47b76fa67
#60 Added automated linux regression in travis
...
Fix DBusCached plugin access sharing for the MMU deadlock when exception is in the decode stage
Fix IBusSimplePlugin issues with used with non regular configs + MMU
Bring back the LinuxGen config into a light one
2019-04-19 17:35:48 +02:00
Charles Papon
2810ff05b0
Fix emulator instruction emulation trap redirection to supervisor.
...
Impact only AMO less configs
2019-04-19 02:31:39 +02:00
Charles Papon
b79b02152b
#60 Fix SFENCE_VMA deadlock
2019-04-18 18:33:06 +02:00
Dolu1990
d2b324e32b
Add jtag and vhdl option
2019-04-15 11:01:51 +02:00
Charles Papon
6f04c02cd2
TestInduvidualFeatures now use the linux config + MMU
2019-04-14 23:06:04 +02:00
Charles Papon
8c7407967e
Fix non RVC fetcher exception PC capture
2019-04-14 23:04:30 +02:00
Charles Papon
61d25e931e
#60 Add sim error message on RVC instruction without RVC capabilities
2019-04-13 10:44:06 +02:00
Charles Papon
5d1ec604b2
Make regression sim great again
2019-04-13 10:41:15 +02:00
Charles Papon
9ac1d3d59e
riscv software model without RVC now trap on RVC instruction before pcWrite + 2
2019-04-13 10:40:53 +02:00
Charles Papon
3301a1b364
Add CsrPlugin.userGen option which now remove privilegeReg when not set
2019-04-12 16:37:34 +02:00
Charles Papon
d5723968da
Merge remote-tracking branch 'origin/master' into linux
...
# Conflicts:
# src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
# src/test/cpp/regression/main.cpp
2019-04-12 16:26:08 +02:00
Charles Papon
8421328ee1
restore freertos tests
2019-04-12 16:09:20 +02:00
Charles Papon
13b774b535
#69 Relax address calculation of decode branch predictor by adding KEEP synthesis attribut
2019-04-12 15:56:22 +02:00
Charles Papon
41ff87f83b
Remove jalr from decode branch prediction missaligned inibition
2019-04-12 15:27:10 +02:00
Charles Papon
63cd5f42af
Fix #69 discoverd fmax issue with decode stage branch predictions
2019-04-12 15:24:33 +02:00
Charles Papon
b329ee85ad
#60 Fix missing ecallGen flag
2019-04-11 15:30:54 +02:00
Charles Papon
ece1e73547
Default linux config is now without RVC
...
Remove all linux usless CSR from the config
Remove verilator instruction fetch check
2019-04-11 01:18:15 +02:00
Charles Papon
caa37a8028
Reduce machine mode emulator CSR requirements and emulate more CSR (in the case they aren't supporter in hardware)
2019-04-10 19:04:52 +02:00
Charles Papon
6b22594961
Flush MMU line with exception on context switching instead than on cmd fire
2019-04-10 15:42:39 +02:00
Charles Papon
926b74a203
shorter coremark
2019-04-10 15:41:58 +02:00
Charles Papon
189cadfbb3
Add coremark
2019-04-10 15:41:38 +02:00
Charles Papon
d7f6c18c0a
Fix DebugPlugin -> force machine mode, force uncached memory load
2019-04-10 00:35:15 +02:00
Charles Papon
9b6b65b8b4
Fix icache test when dynamic target branch prediction is enabled
2019-04-09 19:37:18 +02:00
Charles Papon
a6dc530441
Added lrsc/amo tests
2019-04-09 19:27:42 +02:00
Charles Papon
fd42e7701e
Add hardware AMO, require AMO=yes in sim and withAmo=true in linux.scala
2019-04-09 01:22:32 +02:00
Charles Papon
21cb8615fd
Clean and fix things to get all the non-linux configs and machine only configs working
2019-04-08 16:06:05 +02:00
Charles Papon
32921491b8
#60 Fix instruction cache refill
2019-04-08 14:24:37 +02:00
Charles Papon
fd15a938c5
#60 Fix machine mode emulator atomic emulation. Do not write regfile if the page was set as read only.
2019-04-08 13:20:56 +02:00
Charles Papon
c2595273ec
Add a busy flag from MMU ports
...
iBus/dBus now halt on MMU busy, which avoid looping forever on page fault
2019-04-08 11:38:40 +02:00
Charles Papon
f89ee0d422
#60 Fix MMU holding invalid tlb, while linux is assuming it isn't doing so.
2019-04-07 15:44:25 +02:00
Tom Verbeure
4fd36454d7
Complain about wrong earlyBranch settings.
2019-04-06 12:58:19 -07:00
Tom Verbeure
39a4aa5e26
GenMicroNoCsr: no memory stage, no write-back stage
2019-04-06 12:38:54 -07:00
Charles Papon
6df3e57843
workaround Verilator comparaison linting
2019-04-06 02:00:47 +02:00
Charles Papon
21b4ae8f2f
update todo, nothing todo ? everything done ?
2019-04-06 01:42:01 +02:00
Charles Papon
e7f3dd5553
Rework CsrPlugin exception delegation
2019-04-05 23:40:39 +02:00
Charles Papon
ddf0f06834
Add more delegation tests
...
Reduce dcache test duration
2019-04-05 22:56:12 +02:00
Charles Papon
acaa931e11
Rework CsrPlugin interrupt delegation
2019-04-05 22:55:42 +02:00
Charles Papon
9e72971ff0
Move user mode page fault checkes from iBus/dBus plugin into the MmuPlugin
...
SUM was in fact already supported
2019-04-05 21:34:44 +02:00
Charles Papon
82c894932a
update todolist
2019-04-05 20:04:28 +02:00
Charles Papon
aeb418a99e
Add dcache tests
2019-04-05 20:03:22 +02:00
Charles Papon
5a6665e57f
Fix DataCache flush on the last line
2019-04-05 20:02:57 +02:00
Charles Papon
8459d423b8
add icache flush test
2019-04-05 18:11:33 +02:00
Charles Papon
60a41bfc75
rework i$ flush
2019-04-05 18:11:10 +02:00
Charles Papon
f5d4e745c7
Look like precise fence.i isn't required in practice
2019-04-05 18:08:25 +02:00
Charles Papon
446e9625af
Centralised all todo in linux.scala
...
Sorted out fence fence.i instruction in iBus/dBus plugins.
Fixed MMU permitions while in used mode and bypassing the MMU
2019-04-05 12:17:29 +02:00
Charles Papon
888e1c0b8a
Fix RVC instruction cache xtval allignement
2019-04-05 01:08:57 +02:00
Charles Papon
8e6010fd71
Got the debug plugin working with the linux config (had to disable CSR ebreak)
2019-04-05 00:25:27 +02:00
Charles Papon
4f0a02594c
Change LR/SC to reserve the whole memory
...
Fix MPP access from other plugins
Got all the common configuration to compile and pass regression excepted the debugger one
First synthesis results
2019-04-04 20:34:35 +02:00
Charles Papon
f8b438d9dc
cleaning
2019-04-04 12:59:08 +02:00
Charles Papon
de1c9c6fea
Removing D$ reports
2019-04-03 14:47:00 +02:00
Charles Papon
3f7a859e07
Got multiway I$ D$ running linux fine.
2019-04-03 14:33:35 +02:00
Charles Papon
922c18ee49
Add data cache flush feature
2019-04-03 15:56:58 +02:00
Charles Papon
066f562c5e
Got the MMU refilling itself with datacache cached memory access instead of io accesses
2019-04-03 14:32:21 +02:00
Charles Papon
8be40e637b
#60 Got the new data cache design passing all tests and running linux
2019-04-02 23:44:53 +02:00
Charles Papon
fd4da77084
#60 Got the new instruction cache design passing the standard regressions
2019-04-02 00:26:53 +02:00
Charles Papon
bc0af02c97
#60 Got instruction cache running linux :D
2019-04-01 11:59:04 +02:00
Charles Papon
1dff9aff8a
#60 Fix interrupt causing fetch privilege issues
2019-04-01 10:47:54 +02:00
Charles Papon
e74a5a71eb
Better simulation console integration
2019-04-01 10:31:55 +02:00
Charles Papon
369a3d0f5f
#60 Sync everything, added much comment on the top of Linux.scala to help reproduce
2019-03-31 23:43:56 +02:00
Charles Papon
c7314cc606
Got buildroot login, userspace, commands working
...
Moved location of DTB, initrd. Will move again
Added getChar SBI in emulator
Added an QEMU mode in the emulator config.h, work with qemu riscv32 virt
2019-03-31 15:17:45 +02:00
Dolu1990
de500ad8f9
Add qemu command
2019-03-30 18:29:17 +01:00
Dolu1990
9383445e0b
Add a qemu option (wip)
2019-03-30 18:26:44 +01:00
Charles Papon
1a36f2689d
#60 Fix software model. Forgot physical address for on RVC instruction
2019-03-30 11:24:29 +01:00
Charles Papon
29980016f3
#60 Fix instruction fetch exception PC by forcing LSB to be zero
2019-03-30 10:10:25 +01:00
Dolu1990
9fff419346
Better fix
2019-03-29 09:18:44 +01:00
Dolu1990
391cff69d3
#60 should fix the first instruction fetch privilege after interrupt
2019-03-29 09:02:44 +01:00
Dolu1990
0c48729611
Sync impact less changes (asfar i know)
2019-03-29 08:43:15 +01:00
Dolu1990
ad27007c3c
DBusSimplePlugin AHB bridge add hazard checking, pass tests
2019-03-28 11:41:49 +01:00
Dolu1990
53c05c31c7
IBusSimplePlugin AHB bridge fix, pass tests
2019-03-28 10:12:42 +01:00
Dolu1990
b0522cb491
Add AhbLite3 simulation config
2019-03-28 08:32:12 +01:00
Dolu1990
9ac4998478
Fix emulator nested exception redirection privilege
2019-03-28 00:38:38 +01:00
Dolu1990
ac06111163
Fix MMU MPRV, Fix emulator nested exception
2019-03-27 22:58:30 +01:00
Dolu1990
0bed511a6c
Fix cacheless LR/SC xtval, did some SRC/ADD_SUB/ALU redesign
2019-03-27 18:58:02 +01:00
Dolu1990
43c3922a3d
Add prerequired stuff
2019-03-27 10:55:20 +01:00
Dolu1990
f113946e66
Added a neutral LINUX_SOC for sim purposes
2019-03-27 10:53:41 +01:00
Dolu1990
b69c474fa2
#60 user space reached
...
/sbin/init: error while loading shared libraries: libm.so.6: cannot stat shared object: Error 38
2019-03-27 00:26:51 +01:00
Dolu1990
7a9f7c4fb9
Untested cacheless buses to AHB bridges
2019-03-26 16:30:53 +01:00
Dolu1990
94fc2c3ecf
Fix some models missmatch
...
Add more SBI
Add hardware LR/SC support in dbus cacheless
2019-03-26 01:25:18 +01:00
Dolu1990
1c3fd5c38b
Fix mprv and add it into the softare model
2019-03-25 12:03:32 +01:00
Dolu1990
1ec11dc03d
Fix mprv
2019-03-25 11:47:56 +01:00
Dolu1990
c34f5413a3
Add MMU MPRIV for easier machinemode emulation #60
2019-03-25 10:30:13 +01:00
Dolu1990
9d55283b3b
Machine mode emulator
2019-03-25 02:00:19 +01:00
Dolu1990
e28702eb40
Add PlicCost test
2019-03-24 12:17:39 +01:00
Dolu1990
6c0608f0dd
#60
...
Add LitexSoC workspace / linux loading.
Need to emulate peripherals and adapte the kernel now.
Probably also need some machine mode emulation
Software time !
2019-03-24 10:52:56 +01:00
Tom Verbeure
ea62fd0e16
Same thing for DBusSimpleBus.
2019-03-23 23:36:13 +00:00
Tom Verbeure
95c3e436dc
Make toPipelinedMemoryBus() just like the other busses
2019-03-23 22:32:48 +00:00
Dolu1990
0656a49332
Make xtval more compliant
2019-03-23 20:12:36 +01:00
Dolu1990
7159237104
Fix csrrs/csrrc for xip registers
2019-03-23 18:11:26 +01:00
Dolu1990
505bff6f45
CSR Plugin now implement interruptions as specified in the spec
2019-03-23 12:56:04 +01:00
Dolu1990
3652ede130
Add mdeleg tests
2019-03-23 11:41:10 +01:00
Dolu1990
9139b4d269
Restore all tests
2019-03-22 18:03:35 +01:00
Dolu1990
597336b491
MMU sum/mxr tested and ok, all seem finen
2019-03-22 17:11:55 +01:00
Dolu1990
f7b793b7bf
Add SSTATUS.SUM/MXR feature, need testing
2019-03-22 15:49:36 +01:00
Dolu1990
e4cdc2397a
MMU pass all test, need to and SUM and MXR and it's all ok
2019-03-22 14:52:49 +01:00
Dolu1990
2b458fc642
Added MMU superpage support, pass MMU tests
2019-03-22 12:23:47 +01:00
Dolu1990
af2acbd46e
Got the new MMU design to pass simple tests #60
2019-03-22 01:10:17 +01:00
Dolu1990
ea56481ead
Add supervisor CSR in the riscv golden model
2019-03-20 23:26:08 +01:00
Dolu1990
7cbe399f1f
Fix some supervisor CSR access
2019-03-20 23:25:52 +01:00
Dolu1990
6f2e5a0eb7
goldenmodel Implement some of the supervisor CSR
2019-03-20 20:28:04 +01:00
Dolu1990
39b2803914
Fix some CsrPlugin flags issues
2019-03-20 20:27:47 +01:00
Dolu1990
6c2fe934fd
Bring changes and fixies from @kgugala @daveshah1. Thanks guys !
2019-03-20 16:27:35 +01:00
Dolu1990
130a69eeae
Pass regressions machinemode with CSR config including Supervisor
2019-03-20 14:14:59 +01:00
Dolu1990
d205f88fb8
riscv golden model and RTL pass all current regressions
...
add RVC into the linux config
2019-03-20 12:17:43 +01:00