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Author SHA1 Message Date
Dolu1990
cc423cbe49 Litex cluster add DMA sel feature 2020-07-21 19:42:27 +02:00
Dolu1990
15bda15bc9 Litex cluster can now set cache layout 2020-07-21 19:35:56 +02:00
Dolu1990
9f62f37538 improve LitexCluster area for single core configuration 2020-07-21 15:45:02 +02:00
Dolu1990
da666ade49 Add VexRiscvLitexSmpClusterCmdGen 2020-07-21 15:07:32 +02:00
Dolu1990
fe5401f835 BmbGenerators refractoring (bus -> ctrl) 2020-07-16 13:04:25 +02:00
Dolu1990
da73317912 Cleanup BmbGenerators 2020-07-15 20:51:46 +02:00
Dolu1990
5f0aec7570 BmbInterconnectGenerator refractoring 2020-07-15 17:03:05 +02:00
Dolu1990
d0a572de98 Add openroad config 2020-07-08 01:37:10 +02:00
Dolu1990
32f778613f DBusCachedPlugin now support asyncTagMemory 2020-07-08 01:36:58 +02:00
Dolu1990
60ee7e2b4c Better VexRiscvSmpCluster config 2020-07-08 01:36:40 +02:00
Dolu1990
51070d0e69 Fix MmuPlugin when used in multi stage config 2020-07-05 13:17:39 +02:00
Dolu1990
06584518da Remove CsrPlugin redoInterface combinatorial depedency from execut_isStuck 2020-07-05 13:17:07 +02:00
Dolu1990
a404078117 Few fixes 2020-07-05 13:16:39 +02:00
Dolu1990
c51e25f8c4 Litex SoC add coherent DMA master 2020-07-05 13:15:44 +02:00
Dolu1990
32539dfe6d Got VexRiscvSmpLitexCluster refractoring to work 2020-06-30 22:29:33 +02:00
Dolu1990
0da94ac66f Bring back smp cluster parameters 2020-06-29 15:49:01 +02:00
Dolu1990
062509deee Update Bmb brides and comment out SmpCluster for now 2020-06-29 11:44:10 +02:00
Dolu1990
c12f9a378d Fix inv regression 2020-06-20 13:18:46 +02:00
Dolu1990
f0f2cf61da D$ inv/ack are now fragment, which ease serialisation of wider invalidations 2020-06-19 15:57:56 +02:00
Dolu1990
c18bc12cb2 Fix DebugPlugin.fromBmb 2020-06-19 15:57:21 +02:00
Dolu1990
490c1f6b02 cleanup of old todo 2020-06-19 15:56:45 +02:00
Dolu1990
b0cd88c462 SmpCluster now with proper jtag and plic 2020-06-12 16:18:41 +02:00
Dolu1990
cb5597818d Fix d$ generation crash 2020-06-07 11:29:07 +02:00
Dolu1990
1f9fce6388 Fix d$ uncached writes exception handeling 2020-06-06 22:12:37 +02:00
Dolu1990
760d2f74d0 Update litex cluster to implement utime 2020-06-05 13:31:24 +02:00
Dolu1990
d6455817e7 smp cluster now have 2w*4KB of d$ , no more rdtime emulation 2020-06-05 10:43:03 +02:00
Dolu1990
71760ea372 CsrPlugin now support utime csr to avoid emulation 2020-06-05 10:43:03 +02:00
Dolu1990
3dafe8708b Cfu update 2020-06-05 10:43:03 +02:00
Dolu1990
0668046407 More smp cluster profiling 2020-06-05 10:40:51 +02:00
Dolu1990
97c2dc270c Fix typo 2020-06-04 10:11:30 +02:00
Dolu1990
89c13bedbd Fix litex smp cluster sim 2020-06-03 16:31:54 +02:00
Dolu1990
73f88e47cb Fix BmbToLitexDram coherency 2020-06-03 16:31:54 +02:00
Dolu1990
db50f04653 Add litexMpCluster 2020-06-03 16:31:54 +02:00
Dolu1990
08189ee907 DebugPlugin now support Bmb 2020-06-02 19:13:55 +02:00
Dolu1990
2942d0652a fix Briey verilator 2020-06-01 11:18:25 +02:00
Dolu1990
5e5c730959 Add LitexSmpDevCluster with per cpu dedicated litedram ports 2020-05-29 10:56:55 +02:00
Dolu1990
bc4a2c3747 Fix SmpCluster jtag 2020-05-27 14:19:37 +02:00
Dolu1990
18cce053a3 Improve SingleInstructionLimiterPlugin to also include fetch stages 2020-05-27 14:19:17 +02:00
Dolu1990
a64fd9cf3b Add CsrPlugin external hartid 
d$ rsp/sync now decrement pendings by signal amount
 2020-05-20 13:49:10 +02:00
Tom Verbeure
b901651ab5 Add default value of NONE to uinstret CSR. 2020-05-19 14:48:35 -07:00
Tom Verbeure
c74b03b4de Add uinstret support. 2020-05-19 13:40:46 -07:00
Dolu1990
cf60989ae1 Litex smp cluster now blackboxify d$ data ram 2020-05-14 00:05:54 +02:00
Dolu1990
42fef8bbcd Smp cluster now use i$ reduceBankWidth 2020-05-12 23:59:38 +02:00
Dolu1990
685c914227 Add i$ reduceBankWidth to take advantage of multi way by remaping the data location to reduce on chip ram data width 2020-05-12 23:59:38 +02:00
Dolu1990
0471c7ad76 Fix machineCsr test 2020-05-12 23:55:47 +02:00
Dolu1990
cb44a474fc more smp cluster profiling 2020-05-12 13:25:55 +02:00
Dolu1990
63511b19a2 smp cluster add more profiling 2020-05-11 10:35:24 +02:00
Charles Papon
b592b0bff8 Add regression TRACE_SPORADIC, LINUX_SOC_SMP 
regression golden model now properly sync dut exceptions
 2020-05-09 17:00:13 +02:00
Dolu1990
0a159f06b2 update smp config 2020-05-07 22:50:36 +02:00
Dolu1990
0e76cf9ac8 i$ now support multi cycle MMU 2020-05-07 22:50:25 +02:00
Dolu1990
41ee8fd226 MmuPlugin now support multiple stages, D$ can now take advantage of that 2020-05-07 13:37:53 +02:00
Dolu1990
8e025aeeaa more litex smp cluster pipelining 2020-05-07 13:18:11 +02:00
Dolu1990
fc0f3a2020 cleanup mmu interface 2020-05-06 18:05:20 +02:00
Dolu1990
6323caf265 MMU now allow $ to match tag against tlb pyhsical values directly 
D$ retiming
D$ directTlbHit feature added for better timings
 2020-05-06 17:09:46 +02:00
Dolu1990
ed4a89e4af more pipelineing in Litex SMP cluster interconnect 2020-05-06 17:06:45 +02:00
Dolu1990
8043feebd5 More VexRiscv smp cluster probes 2020-05-06 17:06:17 +02:00
Dolu1990
09724e907b play around with CSR synthesis impact on design size 2020-05-05 00:32:59 +02:00
Dolu1990
c16f2ed787 Add probes in SmpCluster sim 2020-05-04 12:54:28 +02:00
Dolu1990
b0f7f37ac8 D$ now support memDataWidth > 32 2020-05-04 12:54:16 +02:00
Dolu1990
93b386e16e litex smp cluster now use OO decoder 2020-05-02 23:44:58 +02:00
Dolu1990
f0745eb0d9 update SMP line size to 64 bytes 2020-05-02 23:44:27 +02:00
Dolu1990
09ac23b78f Fix SMP fence lock when 4 stages CPU 2020-05-01 12:45:16 +02:00
Dolu1990
f5f30615ba Got litex SMP cluster to work on FPGA 2020-05-01 11:14:52 +02:00
Dolu1990
dc0da9662a Update SMP fence (final) 2020-05-01 11:14:11 +02:00
Dolu1990
7c50fa6d55 SmpCluster now use i$ line of 64 bytes 2020-04-29 14:03:00 +02:00
Dolu1990
9e9d28bfa6 d$ now implement consistancy hazard by using writeback redo 2020-04-29 14:02:41 +02:00
Dolu1990
86e0cbc1f3 I$ with memDataWidth > cpuDataWidth now mux memWords into cpuWords before the decode stage by default. Add twoCycleRamInnerMux option to move that to the decode stage 2020-04-29 13:59:43 +02:00
Dolu1990
7b80e1fc30 Set SMP workspace to use i$ memDataWidth of 128 bits 2020-04-28 22:11:41 +02:00
Dolu1990
eee9927baf IBusCachedPlugin now support memory data width multiple of 32 2020-04-28 22:10:56 +02:00
Dolu1990
03a0445775 Fix SMP for configuration without writeback stage. 
Include SMP core into the single core tests regressions
 2020-04-28 15:50:20 +02:00
Dolu1990
4a49b23636 Fix regression 2020-04-28 14:38:27 +02:00
Dolu1990
3ba509931c Add VexRiscvSmpLitexCluster with the required pipelining to get proper FMax 2020-04-27 17:38:06 +02:00
Dolu1990
5fd0b220cd CsrPlugin add openSbi config 2020-04-27 17:37:30 +02:00
Dolu1990
0c59dd9ed3 SMP fence now ensure ordering for all kinds of memory transfers 2020-04-27 17:37:15 +02:00
Dolu1990
3fb123a64a fix withStall 2020-04-21 21:20:54 +02:00
Dolu1990
3885e52bb7 Merge remote-tracking branch 'origin/dev' into smp 2020-04-21 17:21:48 +02:00
Dolu1990
056bf63866 Add more consistancy tests 2020-04-21 16:03:03 +02:00
Dolu1990
b389878d23 Add smp consistency check, fix VexRiscv invalidation read during write hazard logic 2020-04-21 12:18:10 +02:00
Dolu1990
0e55caacab deduplicae VexRiscv wishbone 2020-04-21 10:33:51 +02:00
Dolu1990
b383b4b98b Add commented usage of fromXilinxBscane2 2020-04-20 12:13:12 +02:00
Dolu1990
8e8b64feaa Got full linux / buildroot to boot in 4 cpu config 2020-04-19 19:49:26 +02:00
Dolu1990
a1b6353d6b workaround AMO LR/SC consistancy issue, but that need a proper fix 2020-04-19 19:48:57 +02:00
Dolu1990
ad2d2e411a Add tap less debug plugin bridges 2020-04-19 17:56:33 +02:00
Dolu1990
af128ec9eb revert to 4 cpu 2020-04-18 01:27:35 +02:00
Dolu1990
4a49e6d91f initialize the clint in sim 2020-04-18 01:26:31 +02:00
Dolu1990
befecc7ed6 cleaning 2020-04-18 00:51:57 +02:00
Dolu1990
8c0e534c6b Add openSBI test, seem to work fine 2020-04-18 00:51:47 +02:00
Dolu1990
d5a52caab8 fix smp test barrier 2020-04-16 17:27:27 +02:00
Dolu1990
d88d04dbc4 More SMP tests (barrier via AMO and LRSC) 2020-04-16 15:23:25 +02:00
Dolu1990
fd52f9ba50 Add smp.bin 2020-04-16 02:22:18 +02:00
Dolu1990
73c21177e5 Add VexRiscvSmpCluster, seem to work on simple case 2020-04-16 01:30:03 +02:00
Dolu1990
b9ceabf128 few fixes 2020-04-16 01:29:13 +02:00
Dolu1990
46207abbc4 dataCache now implement invalidation sync 2020-04-16 01:28:38 +02:00
Dolu1990
a00605b10c fix Briey verilator 2020-04-13 13:01:12 +02:00
Dolu1990
467a2bc488 refactor DBus invalidation, and add invalidation enable 2020-04-11 19:06:22 +02:00
Dolu1990
abbfaf6bcf regression : restore normal invalidation setup 2020-04-10 18:58:03 +02:00
Dolu1990
4a9b8c1f72 improve invalidation read during write hazard logic 2020-04-10 14:44:28 +02:00
Dolu1990
0ad0f5ed3f Add d$ invalidation tests 
fix d$ invalidation, linux OK
 2020-04-10 14:28:16 +02:00
Dolu1990
f71f360e32 Add SMP synthesis 2020-04-10 14:27:39 +02:00
Dolu1990
296cb44bc4 Add hardware AMO support using LR/SC exclusive 2020-04-09 20:12:37 +02:00
Dolu1990
1d0e180e1d Add GenTwoStage config and UltraScale synthesis 2020-04-09 20:11:56 +02:00
Dolu1990
861df664cf clean some AMO stuff 2020-04-08 18:48:01 +02:00
Dolu1990
6922f80a87 DataCache now implement fence operations 2020-04-08 18:12:13 +02:00
Dolu1990
9e1817a280 fix DataCache for config without invalidation 2020-04-07 20:05:24 +02:00
Dolu1990
0c8ea4a368 DataCache add invalidation feature 2020-04-07 19:18:20 +02:00
Dolu1990
1ef099e308 Merge branch 'dev' into smp 2020-04-07 12:29:58 +02:00
Dolu1990
f20eb4d541 Merge pull request #115 from antmicro/fix_emulator 
emulator: Use external hw/common.h from LiteX
 2020-04-07 12:29:40 +02:00
Dolu1990
ddc59bc404 Fix DebugPlugin step by step 2020-04-07 12:27:52 +02:00
Dolu1990
5aa0b86d96 Fix DebugPlugin step by step 2020-04-07 12:13:40 +02:00
Dolu1990
a52b833727 fix weird regression testbench memory bug 2020-04-06 21:42:44 +02:00
Dolu1990
a107e45116 fix non smp regression 2020-04-06 06:43:28 +02:00
Dolu1990
ca72a421be LrSc align software model to the hardware. Linux OK 2020-04-05 21:45:45 +02:00
Dolu1990
2eec18de65 LrSc SMP, linux crash in userspace 2020-04-05 16:28:46 +02:00
Dolu1990
f2ef8e95ab Implement external LrSc 2020-04-05 11:38:57 +02:00
Dolu1990
ff074459ad Fix LrSc for configs without mmu 2020-04-04 22:54:35 +02:00
Dolu1990
c9bbf0d12a update LrSc reservation logic to match the spec 2020-04-04 21:21:35 +02:00
Dolu1990
2dac7dae32 Fix BranchPlugin.jumpInterface priority to avoid conflicts with other instructions on DYNAMIC_TARGET missprediction 2020-03-28 14:36:06 +01:00
Dolu1990
b3215e8beb Make things generated in a deterministic order 2020-03-24 13:11:07 +01:00
Dolu1990
97258c214a
Merge pull request #115 from antmicro/fix_emulator 
emulator: Use external hw/common.h from LiteX
 2020-03-18 12:02:27 +01:00
Dolu1990
defe3c5558 DataCache relax flush timings 2020-03-08 12:35:24 +01:00
Dolu1990
97db4f02a0 Merge branch 'rework_fetch' into dev 2020-03-07 18:22:46 +01:00
Dolu1990
44005ebf31 update Synthesis results 2020-03-07 18:22:01 +01:00
Charles Papon
58af94269e add CsrPlugin.csrOhDecoder 2020-03-05 00:13:04 +01:00
Charles Papon
505d0b700a MulDivPlugin now give names to div stages 2020-03-04 19:58:54 +01:00
Dolu1990
0a212c91fd update synthesisBench paths 2020-03-04 18:13:56 +01:00
Dolu1990
ff5cfc0dde Fix DebugPlugin step 2020-03-03 18:27:53 +01:00
Dolu1990
12463e40a4 improve debugPlugin step logic 2020-03-03 15:59:30 +01:00
Dolu1990
ef5398ce21 Fix #117 DataCache mem blackboxing 2020-03-02 14:24:27 +01:00
Dolu1990
54581f6d9e Fix #117 DataCache mem blackboxing 2020-03-02 14:23:59 +01:00
Dolu1990
78d4660282 Merge branch 'dev' into rework_fetch 
# Conflicts:
#	src/test/scala/vexriscv/TestIndividualFeatures.scala
 2020-03-01 22:58:25 +01:00
Dolu1990
ea5464ea26 TestIndividualFeatures is now multithreaded 2020-03-01 21:40:53 +01:00
Dolu1990
559260020b Improve testing infrastructure with more options and better readme 
https://github.com/litex-hub/linux-on-litex-vexriscv/issues/112
 2020-03-01 13:02:08 +01:00
Charles Papon
25d880f6c7 Fix synthesis bench 2020-02-28 18:20:08 +01:00
Charles Papon
c94d8f1c6c Fetcher and IBusSimplePlugin flush reworked 2020-02-28 17:23:44 +01:00
Charles Papon
492310e6fa DBusCachedPlugin fix noWriteBack redo priority 2020-02-28 17:21:59 +01:00
Charles Papon
76d063f20a Fix MulPlugin keep attribute 2020-02-24 22:43:08 +01:00
Mateusz Holenko
f88b259eba emulator: Use external hw/common.h from LiteX 
Remove code copied from `hw/common.h` and use
the header from the LiteX repository provided
using `LITEX_BASE` environment variable.

Content of `common.h` is now evolving (new functions
are added, some are removed) and syncing it
between repos would be cumbersome.
 2020-02-24 14:27:45 +01:00
Charles Papon
485b4a5838 Improve maxPerf configs 2020-02-23 23:52:43 +01:00
Charles Papon
fad09e805f Add Fetcher.predictionBuffer option to pipeline BRANCH_TARGET, higher FMax, about 1 ns critical path gain on Arty7 => 5 ns 2020-02-23 23:18:27 +01:00
Charles Papon
67d2071a32 typo 2020-02-23 23:17:02 +01:00
Charles Papon
c8016e90a4 MulPlugin now add KEEP attribute on RS1 and RS2 to force Vivado to not retime it with the DSP 2020-02-23 20:25:31 +01:00
Charles Papon
01e5112680 Fetcher RVC ensure redo keep PC(1) 
Fix BranchTarget RVC inibition
 2020-02-23 10:44:44 +01:00
Charles Papon
5ea0b57d1b Fix BRANCH_TARGET with RVC patch 2020-02-22 11:53:47 +01:00
Charles Papon
41008551c1 CsrPlugin redo interface do not need next pc calculation 2020-02-21 20:01:35 +01:00
Charles Papon
4ad1215873 Fix iBusSimplePlugin MMU integration 2020-02-21 13:28:42 +01:00
Charles Papon
befc54a444 No more Fetcher flush() API as it can now be done via the decoder.flushNext 2020-02-21 13:28:29 +01:00
Charles Papon
32fade50e5 Fix fetcher decompressor when driving decode stage 2020-02-21 02:03:29 +01:00
Charles Papon
59508d5b57 Fix target branch prediction for RVC, all default configs pass dhrystone 2020-02-20 02:27:57 +01:00
Charles Papon
a684d5e4d1 Rework/clean decompressor logic 2020-02-19 01:20:52 +01:00
Charles Papon
a7440426fd Fix FetchPlugin redo gen condition 
Fix injectorFailure reset
 2020-02-18 01:00:11 +01:00
Charles Papon
f63c4db469 Fix CsrPlugin pipeline liberator 2020-02-18 00:59:39 +01:00
Charles Papon
53a29e35e9 fix deleg external interrupt propagation time failure 2020-02-17 23:27:17 +01:00
Charles Papon
e0cd9a6e06 clean iBusRsp redo 2020-02-17 22:45:34 +01:00
Charles Papon
0e0a568743 Apply DYNAMIC_TARGET correction all the time 2020-02-17 21:43:02 +01:00
Charles Papon
e23295f06e Fix Fetcher pcValid pipeline 2020-02-17 19:29:41 +01:00
Charles Papon
9e75e2cb58 IBusFetcher disable pcRegReusedForSecondStage when using fetch prediction. 
Fix some fetch flush
DYNAMIC_PREDICTION start to work again
 2020-02-17 14:36:08 +01:00
Charles Papon
8be50b8e3d IBusFetcher now support proper iBusRsp.redo/flush 2020-02-17 12:50:12 +01:00
Charles Papon
ebfa9e6577 Merge branch 'dev' into rework_fetch 2020-02-16 18:52:31 +01:00
Charles Papon
29f85a7ae2 Remove INSTRUCTION_READY 
Add proper Fetcher.ibusRsp.flush
prediction are disabled yet
much is broken for sure, WIP
 2020-02-16 18:44:10 +01:00
Charles Papon
3d34d754a9 Remove usages of implicit string to B/U/S 2020-02-15 10:11:00 +01:00
Charles Papon
5b8febb977 Revert "Revert "Merge branch 'master' into dev"" 
This reverts commit c01c256757.

Fix dBusCachedPlugin relaxedMemoryTranslationRegister when mmu translation is done in the execute stage
 2020-01-29 22:37:09 +01:00
Charles Papon
c01c256757 Revert "Merge branch 'master' into dev" 
This reverts commit b5374433a5, reversing
changes made to f01da9c73b.
 2020-01-29 15:20:13 +01:00
Charles Papon
b5374433a5 Merge branch 'master' into dev 2020-01-29 12:50:41 +01:00
sebastien-riou
badc38d645 Merge remote-tracking branch 'origin/master' into arty 2020-01-17 00:54:19 +01:00
sebastien-riou
1fb1e358bb fix makefile clean target 2020-01-17 00:49:35 +01:00
sebastien-riou
97b2838d18 Murax on Digilent Arty A7-35 2020-01-16 21:58:55 +01:00
sebastien-riou
de9f704de2 better pin names in scala, bootloader without magic word 2020-01-13 21:58:08 +01:00
Charles Papon
f01da9c73b CsrPlugin add printCsr 2020-01-13 20:44:55 +01:00
sebastien-riou
b866dcb07f XIP on Murax improvements 2020-01-12 16:08:14 +01:00
Charles Papon
4c7025b964 Fix xtval when no exception and read_only 2020-01-06 20:07:23 +01:00
Charles Papon
2a06907902 fix compilation 2019-12-24 01:09:55 +01:00
Charles Papon
3b494e97cd Moved KeepAttribute to spinal.lib 2019-12-24 00:43:36 +01:00
Charles Papon
052c8dd602 Fix inWfi naming, fix regressions 2019-12-20 00:21:55 +01:00
Charles Papon
0702f97806 CsrPlugin add wfiOutput 2019-12-19 22:55:17 +01:00
Charles Papon
e25dfb4fbf CsrPlugin now make SATP write rescheduling the next instruction 2019-12-09 22:23:07 +01:00
Charles Papon
744b040c70 Sync CFU progress 2019-11-29 11:50:00 +01:00
Charles Papon
7ae218704e CsrPlugin now implement a IWake interface 
DebugPlugin now wake the CPU if a halt is asked to flush the pipeline
 2019-11-19 18:36:53 +01:00
Charles Papon
6d0d70364c Add BranchPlugin.decodeBranchSrc2 for branch target configs 2019-11-08 14:01:53 +01:00
Charles Papon
4fe7fa56c7 GenCustomInterrupt demo now enabled vectored interrupt 2019-11-07 19:55:26 +01:00
Charles Papon
bb405e705b Add UserInterruptPlugin 2019-11-07 19:52:45 +01:00
Charles Papon
8839f8a8e9 Fix DBus AXI bridges from writePending counter deadlock 2019-11-03 16:45:24 +01:00
Charles Papon
2bf6a536c9 Fix DBus AXI bridges from writePending counter deadlock 2019-11-03 16:44:09 +01:00
Charles Papon
bd2787b562 RegFilePlugin project X0 against boot glitches if no x0Init but zeroBoot 2019-11-01 16:24:07 +01:00
Charles Papon
bb9261773b Fix MulDiveIterative plugin when RSx have hazard in the execute stage 2019-10-23 00:02:08 +02:00
Charles Papon
67028cdb48 Add Mul16Plugin to regression tests 
Fix missing MulSimplePlugin in regressions tests
 2019-10-21 12:53:53 +02:00
Charles Papon
8091a872f3 Fix muldiv plugin for CPU configs without memory/writeback stages 2019-10-21 12:53:03 +02:00
Richard Petri
2d56c6738c Multiplication Plugin using 16-bit DSPs 2019-10-20 22:24:19 +02:00
Charles Papon
b4c75d4898 Merge remote-tracking branch 'origin/dev' into dev 2019-10-11 00:25:37 +02:00
Charles Papon
a2b49ae000 Fix CFU arbitration, add CFU decoder, CFU now redirect custom-0 with func3 2019-10-11 00:25:22 +02:00
Charles Papon
310c325eaa IBusCached add Keep attribut on the line loader to avoid Artix7 block ram merge, but do not seem to have effect 2019-10-11 00:24:21 +02:00
Charles Papon
711eed1e77 MulPlugin add withInputBuffer feature and now use RSx instead of SRCx 2019-10-11 00:23:29 +02:00
Charles Papon
3fc0a74102 Add Keep attribut on dBusCached relaxedMemoryTranslationRegister feature 2019-10-11 00:22:44 +02:00
Charles Papon
51d22d4a8c Merge remote-tracking branch 'origin/cfu' into dev 2019-10-10 15:00:43 +02:00
Charles Papon
5df56bea79 Allow getDrivingReg to properly see i$ decode.input(INSTRUCTION) register 
(used to inject instruction from the debug plugin)
 2019-10-03 00:20:33 +02:00
Charles Papon
49944643d2 Add regression for data cache without writeback stage, seem to pass tests, including linux ones 2019-09-23 15:20:51 +02:00
Charles Papon
bf82829e9e Data cache can now be used without writeback stage 2019-09-23 15:20:20 +02:00
Charles Papon
ace963b542 Hazard on memory stage do not need to know if that's bypassable if the memory stage is the last one 2019-09-21 14:13:28 +02:00
Charles Papon
e1795e59d5 Enable RF bypass on MUL DIV with pipeline wihout writeback/memory stages 2019-09-21 13:00:54 +02:00
Charles Papon
e8236dfebe Add MulSimplePlugin regressions 2019-09-21 12:49:46 +02:00
Sean Cross
b8b053e706 muldiviterative: fix build for short pipelines 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-09-20 08:36:01 +08:00
Sean Cross
fdc95debef dbuscached: fix build for short pipelines 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-09-20 08:35:49 +08:00
Sean Cross
0b79c637b6 mulsimpleplugin: fix build for short pipelines 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-09-20 08:35:23 +08:00
Charles Papon
6ed41f7361 Improve CSR FMax 2019-09-16 13:53:55 +02:00
Charles Papon
d94cee13f0 Add dummy decoding, exception code/tval 
Add Cpu generation code
Add support for always ready rsp
 2019-09-05 19:06:28 +02:00
Charles Papon
5ac443b745 Manage cases where a rsp buffer is required 2019-09-05 10:41:45 +02:00
Dolu1990
6951f5b8e6 CfuPlugin addition 2019-09-05 10:41:45 +02:00
Mateusz Holenko
86f5af5ca9 Fix handling LiteX uart and timer. 2019-09-05 10:41:45 +02:00
Mateusz Holenko
8813e071bc Add litex target 
Use configuration from the `csr.h` file
generated dynamically when building a LiteX platform.
 2019-09-05 10:41:45 +02:00
Mateusz Holenko
64a2815544 Create makefile targets 
Allow to change build target without modifiying the sources.
In order to keep compatibilty `sim` target is built by default.
 2019-09-05 10:41:45 +02:00
Mateusz Holenko
e76435c6c6 Allow to set custom DTB/OS_CALL addresses 
Setting those from command line during compilation allows
to create a custom setup without the need of modifying the
sources.
 2019-09-05 10:41:45 +02:00
Mateusz Holenko
c8280a9a88 Allow to set custom RAM base address for emulator 
This is needed when loading the emulator to RAM
with an offset.
 2019-09-05 10:41:45 +02:00
Charles Papon
b65ef189eb sync with SpinalHDL SDRAM changes 2019-08-29 16:03:20 +02:00
Mateusz Holenko
5085877eed Fix handling LiteX uart and timer. 2019-07-24 16:09:21 +02:00
Mateusz Holenko
6a2584b840 Add litex target 
Use configuration from the `csr.h` file
generated dynamically when building a LiteX platform.
 2019-07-11 15:56:48 +02:00
Mateusz Holenko
39c3f408e5 Create makefile targets 
Allow to change build target without modifiying the sources.
In order to keep compatibilty `sim` target is built by default.
 2019-07-11 15:50:15 +02:00
Mateusz Holenko
423355ecbf Allow to set custom DTB/OS_CALL addresses 
Setting those from command line during compilation allows
to create a custom setup without the need of modifying the
sources.
 2019-07-11 14:09:06 +02:00
Mateusz Holenko
28a11976da Allow to set custom RAM base address for emulator 
This is needed when loading the emulator to RAM
with an offset.
 2019-07-11 14:06:24 +02:00
Charles Papon
a2569e76c0 Update sdram ctrl package 2019-07-08 11:23:48 +02:00
Charles Papon
624c641af5 xip refractoring 2019-06-28 10:23:39 +02:00
Charles Papon
1257b056dc Revert "test only dynamic_target for intensive test" 
This reverts commit 635ef51f82.
 2019-06-16 18:24:59 +02:00
Charles Papon
635ef51f82 test only dynamic_target for intensive test 2019-06-16 17:43:07 +02:00
Charles Papon
9656604848 rework dynamic_target failure correction 2019-06-16 17:42:39 +02:00
Charles Papon
60c9c094a7 Merge remote-tracking branch 'origin/rework_jump_flush' into dev 2019-06-15 18:09:38 +02:00
Charles Papon
a3a0c402bc Remove broken freertos test and add zephyr instead 2019-06-15 10:46:10 +02:00
Charles Papon
617f4742cd Fix dynamic branch prediction correction on misspredicted fetch which are done on a 32 bits instruction crossing two words in configs which have at least 2 cycle latency fetch 2019-06-14 08:13:22 +02:00
Charles Papon
d603de1bfe Fix recent changes 2019-06-13 16:55:24 +02:00
Charles Papon
c8ab99cd0b Cleaning and remove BlockQ regression 2019-06-12 00:00:38 +02:00
Charles Papon
21ec368927 Fix DYNAMIC_TARGET by fixing decode PC updates 2019-06-11 19:56:33 +02:00
Charles Papon
afbf0ea777 Fix regression makefile 2019-06-11 01:05:49 +02:00
Charles Papon
066ddc23e6 Add regression concurrent os executions flag to avoid running debug plugin tests 2019-06-11 00:22:38 +02:00
Charles Papon
21c8933bbb Fix DYNAMIC_TARGET prediction correction in BranchPlugin 2019-06-11 00:12:29 +02:00
Charles Papon
5b53440d27 DYNAMIC_TARGET prediction datapath/control path are now splited 2019-06-10 22:20:32 +02:00
Charles Papon
0e95154869 individual regression : more env control 2019-06-10 21:01:41 +02:00
Charles Papon
bd46dd88aa Fix RVC fetcher pc branches 2019-06-10 20:48:04 +02:00
Charles Papon
24e1e3018c Fix exception handeling 2019-06-09 23:40:37 +02:00
Charles Papon
5243e46ffb Fix BranchPlugin when SRC can have hazard in execute stage 2019-06-09 20:15:36 +02:00
Charles Papon
af0755d8cf rework flush with flushNext and flushIt 
static branch prediction jump do not depend on stage fireing anymore
 2019-06-09 15:44:05 +02:00
Charles Papon
357681a5c6 csrPlugin add pipelinedInterrupt, set by default 2019-06-08 22:22:16 +02:00
Charles Papon
0df4ec45ad Merge remote-tracking branch 'origin/master' into dev 
# Conflicts:
#	build.sbt
 2019-06-05 00:35:41 +02:00
Charles Papon
56f7c27d18 Fix WFI. Not sensitive anymore to global interrupt enables, delegation and privilege 2019-06-05 00:32:38 +02:00
Charles Papon
38a464a829 DataCache now allocate ways randomly 2019-05-25 00:28:30 +02:00
Charles Papon
4a40184b35 Add cache Bandwidth counter, previous commit was about random instruction cache way allocation 2019-05-25 00:22:27 +02:00
Charles Papon
94606d38e2 Add cache bandwidth counter 2019-05-25 00:21:48 +02:00
Charles Papon
206c7ca638 Fix Bmb datacache bridge 2019-05-24 00:22:58 +02:00
Charles Papon
f6f94ad7c1 Fix InstructionCache Bmb bridge 2019-05-22 19:03:26 +02:00
Charles Papon
9b49638654 Allow CsrPlugin config access 2019-05-22 17:27:47 +02:00
Charles Papon
8abc06c8f2 Add Bmb support for i$/d$ 2019-05-22 17:04:36 +02:00
Charles Papon
49b4b61a1a Update Bmb bridges 2019-05-20 14:14:42 +02:00
Charles Papon
0301ced000 Fix dBusSimplePlugin to bmb bridge 2019-05-16 19:49:13 +02:00
Charles Papon
3753f64429 Fix Bmb compilation 2019-05-13 23:44:20 +02:00