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2722 commits

Author SHA1 Message Date
Gabriel Somlo
df3428be07 liblitesdcard/sdcard: (temporarily) slow down SDCARD_CLK_FREQ to 25MHz 
Rocket's DMA slave interface (and/or internal routing) currently
appears unable to route DMA writes from LiteSDCard at frequencies
above 25MHz (as tested on nexys4ddr, with Rocket, at 75MHz main
system clock frequency).

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-08-03 16:14:11 -04:00
Gabriel Somlo
2d9dc8f939 cores/cpu/rocket: expose slave port for DMA 
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-08-03 16:14:11 -04:00
Gabriel Somlo
d8161e5a86 integration/soc: make DMA slave region cover (at least) the lower 4GB 
Assuming we currently support a 32-bit (4GB) physical address space,
ensure that the dma_bus slave covers the entire range, covering any
possible layout of the LiteX SoC memory map (e.g., rocket has MMIO
in a wide range of registers located below 2GB, and DRAM starting at
the 2GB mark, needing DMA accesses to be routed appropriately for the
entire 4GB physical address range).

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-08-03 16:14:11 -04:00
Gabriel Somlo
70eae5cbf9 interconnect/wishbone: increase WB address width to 31 
This is needed to support memory regions up to 4GB in size (currently
limited to 2GB, or 0x8000_0000).

FIXME: CI complains about assertions re. axi_lite.address_width in
       relationship to len(wishbone.adr) and wishbone_adr_shift, which
       seems to be a problem on the 32bit (vexriscv?) CPU used for CI,
       but seems to work fine on Rocket.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>

foo
 2020-08-03 16:11:26 -04:00
Gabriel Somlo
b8c9da81ea soc/interconnect/axi: add Wishbone2AXI converter 2020-08-03 12:50:00 -04:00
Florent Kermarrec
2ec4604c41 cores/gpio: add support for Record on GPIOOut, GPIOIn and GPIOInOut. 2020-08-03 18:47:17 +02:00
Jędrzej Boczar
c1ae7e596c build/sim: allow for arbitrary clocks generation using clockers 2020-08-03 17:06:38 +02:00
Jędrzej Boczar
38054874ac build/sim: use a real timebase in the simulation 2020-08-03 15:21:24 +02:00
enjoy-digital
5e53e5d73a
Merge pull request #615 from pepijndevos/openfpgaloader 
Add openFPGALoader programmer
 2020-08-03 14:01:50 +02:00
Pepijn de Vos
79ca4d9640 remove debugging 2020-08-01 11:07:04 +02:00
Pepijn de Vos
f6e20700d4 add openFPGAloader programmer 2020-08-01 11:05:09 +02:00
Florent Kermarrec
eab0726cc8 cpu/vexriscv/core: use variant name as human_name. 
Allow it to be shown in the BIOS and help support.
 2020-07-31 08:59:53 +02:00
Florent Kermarrec
e0a763e534 cpu/vexriscv/system.h: provide empty flush_cpu_i/dcache functions for variants with no i/d cache. 2020-07-31 08:58:30 +02:00
Florent Kermarrec
3ff1bcaf05 cpu/zynq7000: set csr map to 0x00000000. 2020-07-30 21:37:25 +02:00
enjoy-digital
c0253e3f77
Merge pull request #611 from antmicro/jboc/axi-lite 
soc/interconnect/axi: add AXILite -> AXI converter
 2020-07-30 14:22:21 +02:00
Florent Kermarrec
cc8440549f tools/litex_server/read_merger: review/simplify a bit. 2020-07-30 13:58:40 +02:00
enjoy-digital
4f382ccf55
Merge pull request #605 from cklarhorst/feature-uart-read-merger 
Merge sequential reads for the UART litex_server backend
 2020-07-30 13:56:48 +02:00
Jędrzej Boczar
e78d950a31 soc/interconnect/axi: add AXILite -> AXI converter 2020-07-30 13:50:34 +02:00
Florent Kermarrec
a942e358b9 cpu/blackparrot: minor cleanups, add sim variant (since use different flist). 2020-07-30 12:10:32 +02:00
Dolu1990
023ab15ec1 soc/cores/cpu/vexriscv_smp enable dynamic litedram datawidth 2020-07-29 12:40:16 +02:00
Dolu1990
e5cd5d5466 Merge branch 'master' into vexriscv_smp 2020-07-29 11:14:09 +02:00
Florent Kermarrec
1938ce363d integration/soc/add_sdram: allow the CPU to add the direct memory buses when adding the sdram. 
This is useful for CPUs elaborated at buildtime to use sdram's native data width on the CPU memory ports.
 2020-07-29 11:10:05 +02:00
Florent Kermarrec
6576416b8e cores/cpu/rocket: add use_memory_bus parameter to easily disable direct memory bus for testing. 
Useful for current tests with LiteSDCard using DMA and that requires the DMA to be connnected to
the DMA bus of Rocket when the direct memory bus is used.
 2020-07-29 09:35:15 +02:00
Dolu1990
789a70e7c8 Merge branch 'master' into vexriscv_smp 2020-07-28 19:11:54 +02:00
Dolu1990
d284dfbea9 soc/cores/cpu/vexriscv_smp config update 2020-07-28 19:07:02 +02:00
Florent Kermarrec
fe38e12b21 cpu/vexriscv_smp: move litedram import, remove os.path import. 2020-07-28 18:10:32 +02:00
Dolu1990
aa57c7a25e soc/cores/cpu/vexriscv_smp integration 2020-07-28 16:20:16 +02:00
Florent Kermarrec
f87513ab92 liblitesdcard/sdcard: increase SDCARD_CLK_FREQ to 50MHz. 2020-07-28 14:36:49 +02:00
Florent Kermarrec
9518ccf453 integration/soc/etherbone: expose ethcore (useful to combine udp/etherbone). 2020-07-27 19:57:29 +02:00
Florent Kermarrec
9e07623b61 integration/soc: fix dma_bus typo. 2020-07-27 11:06:09 +02:00
Christian Klarhorst
2034c563b0 Merge sequential reads for the UART litex_server backend 
The UART backend writes [read identifier, num_reads, addr] for
every read request.
Etherbone packets are able to include multiple read requests.
Therefore, it is beneficial to merge sequential read requests to reduce writes
(and possible latency overhead).

Benchmark:
A typical litescope fetch script with the following
signals [ddrphy.dfi,cpu.ibus.cyc,cpu.ibus.stb] results in 1 read for the
data_valid register and 24 sequential reads for the scope data per timestamp.
Fetching data for a capture length of 512 over a 921600 baud UART (arty board)
took:
205s (current master branch)
 18s (with this merge function)

The proposed merger only merges read requests from one etherbone packet
at a time and doesn't change the read order.
 2020-07-26 13:19:32 +02:00
Florent Kermarrec
1fdffdfd6b targets: keep in sync with litex-boards. 2020-07-24 16:34:17 +02:00
enjoy-digital
8a0684b15e
Merge pull request #604 from antmicro/jboc/axi-lite 
Improve AXI Lite data width converters
 2020-07-24 14:54:11 +02:00
Jędrzej Boczar
879e6ffe73 soc/interconnect/axi: add basic AXI Lite up-converter 2020-07-24 13:47:18 +02:00
Sean Cross
dd366467ed litex: add sphinx_extra_config to generate_docs() 
This allows us to append additional strings to the sphinx `conf.py`.

Signed-off-by: Sean Cross <sean@xobs.io>
 2020-07-24 16:01:54 +08:00
Jędrzej Boczar
32160e615f soc/interconnect/axi: separate AXI Lite converter channels 2020-07-24 09:25:57 +02:00
Florent Kermarrec
041c7527ce core/cpu: integrate Zynq as a classical CPU (Zynq7000), deprecate SoCZynq. 
This is the logical continuation of the recent change to avoid specific SoC classes.
A Zynq FPGA can be used with or without the PS7. When used without the PS7, a softcore CPU
can be used as with others FPGAs. When using the PS7, the softcore is replaced with the PS7
and connected to the SoC through one of the AXI GP interface.

An example is available on litex-boards.
 2020-07-23 17:40:46 +02:00
Florent Kermarrec
8bdf6941a3 liblitesdcard/sdcard: use max divider of 256 (128 was not enough for the initial 400Khz clock frequency). 2020-07-22 23:15:36 +02:00
enjoy-digital
99e88dfc0b
Merge pull request #600 from antmicro/jboc/axi-lite 
Implement AXI Lite interconnect
 2020-07-22 23:03:07 +02:00
Florent Kermarrec
d38048baac soc: add initial DMA bus support (optionally provided by CPU(s) for cache coherency). 
When provided, the modules doing DMA shall connect the DMA to the dma_bus to allow the CPU(s) to manage cache coherency
and avoid the manual cache flushes.

This has been tested with VexRiscv SMP and LiteSDCard doing DMA while loading Linux binaries.
 2020-07-22 18:44:37 +02:00
Jędrzej Boczar
367eb12240 soc/integration: use AXILiteSRAM when using bus_standard="axi-lite" 2020-07-22 17:16:33 +02:00
Jędrzej Boczar
706bc25dc1 soc/integration: add bus standard parser arguments 2020-07-22 17:16:33 +02:00
Jędrzej Boczar
32d9e212c5 soc/interconnect/axi: improve Timeout module and test it with shared interconnect 2020-07-22 17:16:33 +02:00
Jędrzej Boczar
2cab7fbf0f test/axi: add shared AXI Lite interconnect tests 2020-07-22 17:16:33 +02:00
Jędrzej Boczar
3a08b21d44 soc/interconnect/axi: implement AXI Lite decoder 2020-07-22 17:16:33 +02:00
Jędrzej Boczar
214cfdcaeb soc/interconnect/axi: lock AXILiteArbiter until all requests have been responded to 2020-07-22 17:16:33 +02:00
Jędrzej Boczar
a8a583d6b4 socinterconnect/axi: interconnect shared sketch 2020-07-22 17:16:26 +02:00
Jędrzej Boczar
f47ccdae99 soc/interconnect/axi: point-to-point interconnect and timeout module with tests 2020-07-22 17:16:12 +02:00
Jędrzej Boczar
b4c1120e3d soc/integration: choose interconnect based on bus standard 2020-07-22 17:16:07 +02:00
Jędrzej Boczar
69d8dd788d soc/integration: add axi-lite standard to SoCBusHandler 2020-07-22 17:13:28 +02:00
enjoy-digital
2361abb12d
Merge pull request #599 from antmicro/gen-mmcm-pr 
litex-gen: add mmcm core
 2020-07-22 14:52:26 +02:00
Piotr Binkowski
66c5f37133 litex-gen: add mmcm core 2020-07-22 12:34:32 +02:00
Florent Kermarrec
6b72f52c5d boards: keep in sync with litex-boards. 2020-07-22 08:50:38 +02:00
Florent Kermarrec
1f27b7405e soc/integration/add_sdcard: add direct connection to VexRiscv's dmabus for testing. 2020-07-21 19:54:42 +02:00
Florent Kermarrec
408d1a9f5d cpu/vexriscv/system.h: update flush_cpu_dcache. 2020-07-21 19:43:00 +02:00
Florent Kermarrec
47ce15b431 interconnect/wishbone: add minimal UpConverter. 2020-07-21 19:35:14 +02:00
enjoy-digital
9fc488bdf6
Merge pull request #597 from antmicro/jboc/litex-buildenv-add-adapter-fix 
Fix Vivado crash when using 1:1 wishbone.Converter
 2020-07-20 23:11:01 +02:00
enjoy-digital
b92519502a
Merge pull request #595 from betrusted-io/master 
wire up missing register bits.
 2020-07-20 22:47:16 +02:00
Ilia Sergachev
8656ea9b67 interconnect/csr_bus: fix paged access warning 2020-07-20 18:23:09 +02:00
Jędrzej Boczar
07bc589c41 fix/Vivado: don't instantiate wishbone.Converter in add_adapter when not needed 
Fixes an issue with Vivado which crashes with SIGSEGV when building litex-buildenv at:
cc003bef3a
and litex bumped to 4a18b828bc,
with options:
    CPU=mor1kx; CPU_VARIANT=linux; PLATFORM=arty; FIRMWARE=linux; TARGET=net
The only difference in Verilog is that we avoid creating new Interface and doing
`new_interface.connect(interface)`, so this shouldn't make any difference, but
this somehow generates the error in Vivado (tested on v2018.3 and v2019.2).
 2020-07-20 15:26:21 +02:00
Florent Kermarrec
4a18b828bc software/liblitesdcard/spisdcard: remove optimization on receive_block (not working on all configs) and increase max clk_freq to 20MHz. 2020-07-20 13:48:49 +02:00
Florent Kermarrec
100aa5a4ca soc/cores/spi/SPIMaster: rewrite/simplify. 
- Make sure MOSI is latched on start, MISO is stable during Xfer (last value).
- Allow clk_divider down to 2.
- improve test errors reporting with hex() on AssertEqual.
 2020-07-20 10:44:18 +02:00
bunnie
53a567daef wire up missing register bits. 
Not sure how they went missing...but just noticed them.
 2020-07-19 03:00:25 +08:00
Florent Kermarrec
63c19ff45f liblitesdcard/spisdcard: update comments. 2020-07-17 15:39:39 +02:00
Florent Kermarrec
1f34f6ef00 soc/cores/spi: make sure done and miso are synchronous. 2020-07-17 15:38:52 +02:00
Florent Kermarrec
754f140a9d spisdcard: revert to 8-bit SPI, optimize spisdcardreceive_block and reduce clk to 12.5MHz for now. 2020-07-17 11:58:26 +02:00
Florent Kermarrec
8143f1a08b soc/cores/spi: make sure miso is stable during xfer. 2020-07-17 11:56:27 +02:00
Florent Kermarrec
ac35e158c1 bios/boot: add bootargs support on netboot/sdcardboot to optionally specify r1/r2/r3/addr. 
For example:
{
	"Image":  "0x40000000",
	"bootargs": {
		"r1":  "0x12345678",
	}
}

will copy Image to 0x40000000 and set r1 to 0x12345678.

By default, r1,r2,r3 are set to 0 and addr is the address if the last loaded image, so:

{
	"Image":         "0x40000000",
	"rootfs.cpio":   "0x40800000",
	"rv32.dtb":      "0x41000000",
	"emulator.bin":  "0x41100000",
}

is equivalent to:

{
	"Image":         "0x40000000",
	"rootfs.cpio":   "0x40800000",
	"rv32.dtb":      "0x41000000",
	"emulator.bin":  "0x41100000",
	"bootargs": {
		"r1":   "0x00000000",
		"r2":   "0x00000000",
		"r3":   "0x00000000",
		"addr": "0x00000000",
	}
}
 2020-07-16 18:12:11 +02:00
enjoy-digital
ee4b1d81a7
Merge pull request #594 from antmicro/jboc/axi-lite 
Add AXILiteDownConverter
 2020-07-16 17:56:33 +02:00
Jędrzej Boczar
229da572ff soc/interconnect/axi: propagate response errors in AXILiteDownConverter 2020-07-16 17:16:35 +02:00
Jędrzej Boczar
93bcc94b53 soc/interconnect/axi: implement AXILite down-converter 2020-07-16 17:02:49 +02:00
enjoy-digital
21c48eed76
Merge pull request #593 from antmicro/jboc/axi-lite 
Add AXILite components: AXILiteSRAM and AXILite2CSR
 2020-07-16 11:56:57 +02:00
Jędrzej Boczar
0be607dad9 soc/integration: revert bus argument for add_ram/add_rom 2020-07-16 10:26:12 +02:00
Jędrzej Boczar
2700ec3ce5 soc/integration: use AXILiteConverter (dummy implementation) in add_adapter() 2020-07-15 15:59:16 +02:00
Jędrzej Boczar
f3072d4984 soc/interconnect/axi: add connect methods for convenience 2020-07-15 15:48:40 +02:00
Jędrzej Boczar
78a631f392 test/axi: add AXILite2CSR and AXILiteSRAM tests 2020-07-15 12:40:39 +02:00
Jędrzej Boczar
a5be2cd257 soc/interconnect/axi: improve SRAM/CSR access speed 2020-07-15 11:44:14 +02:00
Alessandro Comodi
3f7568de09 symbiflow: changed toolchain command names in Makefile 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-07-15 11:31:06 +02:00
Jędrzej Boczar
d8a242d86f soc/interconnect: add AXILite SRAM 2020-07-15 10:58:34 +02:00
Jędrzej Boczar
b692b2a3f1 soc/interconnect: add AXILite2CSR bridge 2020-07-15 10:36:34 +02:00
Jędrzej Boczar
35149c4e80 soc/integration: update add_adapter to convert between AXILite/Wishbone 2020-07-14 16:31:46 +02:00
Florent Kermarrec
6671eb6218 build/lattice/trellis: set default spimode to None (--spimode not passed to ecppack) as default instead of fast-read. 
Using fast-read as default prevent loading the .bit via JTAG (see #589).
 2020-07-13 11:55:03 +02:00
Florent Kermarrec
ae3c78f6d1 build/lattice/trellis: fix spimode typo. 2020-07-11 21:30:19 +02:00
Owen Kirby
0aec5b0f8c trellis: Add option to select SPI mode. 
This allows a significant speedup when booting large bitstreams on ECP5
boards that support dual or quad SPI operation.
 2020-07-11 11:48:10 -07:00
enjoy-digital
e76464167b
Merge pull request #587 from antmicro/mor1x_ror_instruction 
mor1kx: Do not generate the ror instruction
 2020-07-10 11:21:13 +02:00
Florent Kermarrec
468db3cf08 integration/soc/sdcard: add mode parameter to enable read only, write only or read+write modes. 2020-07-10 11:18:22 +02:00
Mateusz Holenko
b8d900862c mor1kx: Do not generate the ror instruction 
The mor1kx core does not support `l.ror` instruction
by default, but gcc/clang flags allowed the
compiler to generate it.
 2020-07-10 11:07:12 +02:00
Florent Kermarrec
b7e4507686 core/cpu/CPUNone: set endianness to little. 2020-07-10 10:42:00 +02:00
Filipe Laíns
235e8cf62b
cpu: add a few missing GCC toolchains 
This names are used by Arch Linux for eg.

Signed-off-by: Filipe Laíns <lains@archlinux.org>
 2020-07-09 15:58:33 +01:00
Florent Kermarrec
5ebdfd9307 liblitesdcard/sdcard: clamp divider value. 2020-07-09 13:09:36 +02:00
enjoy-digital
23085cffea
Merge pull request #584 from ozbenh/memtest 
Memtest/memspeed improvements
 2020-07-09 12:54:42 +02:00
Florent Kermarrec
5c332e4b58 cores/dma: add stream.last support on WishboneDMAReader. 2020-07-09 12:18:09 +02:00
Benjamin Herrenschmidt
83d24d087d memspeed: Write a fixed value 
Otherwise we have at least an extra addition in the loop
which squews the result compared to the read loop.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 2020-07-08 17:13:37 +10:00
Florent Kermarrec
146ead4c4c buid/io/InferedSDRIO/InferedSDRTristate: avoid unnecessary clk_domain/limitation. 
Just create a local clk_domain from clk signal.
 2020-07-08 08:33:52 +02:00
Florent Kermarrec
b54b3b3362 interconnect/avalon: minor cleanup, remove max on SyncFIFO depth. 2020-07-08 07:53:42 +02:00
Benjamin Herrenschmidt
c0b948d4f9 memtest: Fix memspeed access size 
The move to libbase reverted the type of the pointer
from long to int.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 2020-07-08 13:21:45 +10:00
Benjamin Herrenschmidt
798b3d7ba4 memtest: Fix integer size/type printf errors 
In a couple of places, memtest uses %x to print a pointer which
is illegal (and could be problematic on 64-bit). Use %p instead.

Additionally, use %ld when printing longs

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 2020-07-08 13:17:48 +10:00
Florent Kermarrec
8af4e05c7f software/litesdcard: use new clocking and use slow clock during initialization. 2020-07-07 19:59:50 +02:00
Florent Kermarrec
52f36b1257 integration/soc/sdcard: cleanup emulator integration, fix sim. 2020-07-07 15:05:07 +02:00
Florent Kermarrec
7602977c16 integration/soc: move pads.rst control to PHY. 2020-07-07 14:58:06 +02:00
Florent Kermarrec
51f2e6ce64 build/io/InferedSDRTristate: pass clock domain to SDROutput/SDRInput. 2020-07-07 12:11:47 +02:00
Florent Kermarrec
23dfefb9be software/liblitesdcard: improve sdcard_init and handle errors. 2020-07-07 11:03:26 +02:00
Florent Kermarrec
8d76509032 litesdcard: use new Block2Mem/Mem2Block DMAs. 2020-07-07 09:24:08 +02:00
Florent Kermarrec
eeea30eada litex/gen: remove io that has been replaced with litex/build/io (and should have been removed). 2020-07-07 08:14:42 +02:00
Gabriel Somlo
6fdb36b84a liblitesdcard/sdcard: adjust card-ready timeout 
Testing on nexys4ddr and rocket, approximately 12 iterations of the
timeout loop (using `busy_wait(1)`) are needed to receive a "ready"
response from the SDcard, assuming a "warm" reset where the card has
already been previously initialized.

If the SDcard is ejected and re-inserted, or if the board is "cold-reset"
(e.g., reprogrammed via openocd vs. a simple push of the reset button),
it takes approximately 450 iterations before the SDCard responds with a
"ready" message.

In either case, a timeout of 10 is insufficient. This patch increases
the busy-wait to 10, and the timeout loop counter to 128, which should
cover most cases.

Additionally, make a few minor cosmetic improvements.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-07-06 17:38:07 -04:00
Florent Kermarrec
e473c6f29e liblitesdcard/sdcard: add timeout when waiting card to be ready. 2020-07-06 20:07:20 +02:00
Florent Kermarrec
31d4d7c22c liblitesdcard/sdcard: use new SDClocker enable CSR. 2020-07-06 18:59:28 +02:00
Florent Kermarrec
f0a97791a9 interconnect/csr_bus: move/rewrite paged access warning. 
Was incorrectly triggered with csr_data_width=32.
 2020-07-06 12:26:24 +02:00
Florent Kermarrec
9e46195299 interconnect/csr_bus: remove 64-bit CSR bus alignment support (no longer supported in SoCs). 2020-07-06 09:51:32 +02:00
Gabriel Somlo
c52731d1f1 liblitesdcard/sdcard: return error code outside '#ifdef SDCARD_DEBUG' 2020-07-04 15:24:05 -04:00
Gabriel Somlo
499d291daa liblitesdcard/sdcard: cosmetic: fix indentation, eliminate redundant counter 2020-07-04 15:22:28 -04:00
Florent Kermarrec
2bfa372b7c targets: remove sdcard clock domain (now generated in the PHY). 2020-07-03 20:11:05 +02:00
Florent Kermarrec
31a9273c6d litesdcard: use new clocker. 2020-07-03 20:06:42 +02:00
Florent Kermarrec
ee8da87e41 liblitesdcard/sdcard: use new register names and new software initalization register. 2020-07-03 19:30:06 +02:00
Florent Kermarrec
e6b94b1663 interconnect/stream: allow empty description/payload on Endpoint. 2020-07-03 19:29:05 +02:00
Florent Kermarrec
2f6b27da23 litelitesdcard/sdcard: remove wait workaround and replace remove SDCARD_MULTIPLE_BLOCK_SUPPORT define (replace it with SDCARD_CMD23_SUPPORT). 2020-07-03 18:48:43 +02:00
Florent Kermarrec
94821cb73c litesdcard: update integration. 2020-07-03 14:57:40 +02:00
Florent Kermarrec
2c53f9b2ff interconnect/stream: add ClockDomainCrossing wrapper around AsyncFIFO. 2020-07-03 14:39:31 +02:00
Florent Kermarrec
23a95bea1d integration/soc/etherbone: always run ethcore in eth_tx clock domain and remove clock_domain parameter. 
This avoid issues when sys_clk_freq < eth_tx clock like sys_clk_freq < 125MHz with 1Gbps link.
 2020-07-02 11:38:54 +02:00
Pawel Sagan
16a0aebcad i2s: Fix the incorrect TX fifo almost empty offset 2020-07-01 13:32:53 +02:00
Florent Kermarrec
8f204e7797 sdcard: rename cd_sdcard to cd_sd to avoid unnecessary clock domain. 2020-07-01 12:50:24 +02:00
Florent Kermarrec
42bfb90f14 liblitesdcard/sdcard: add SDCARD_MULTIPLE_BLOCK_SUPPORT define. 2020-07-01 12:40:23 +02:00
Florent Kermarrec
e492e96bf7 integration/soc/add_sdcard: update SDEmulator. 2020-07-01 12:39:56 +02:00
Florent Kermarrec
996e9a9180 tools/litex_sim: cleanup cpu endianness. 2020-07-01 09:47:10 +02:00
enjoy-digital
1c631ceeee
Merge pull request #580 from Dolu1990/patch-2 
Improve verilator compilation speed
 2020-07-01 08:37:03 +02:00
Florent Kermarrec
949a8e73c2 boards/platforms/versa_ecp5: fix mising update. 2020-07-01 08:35:54 +02:00
Florent Kermarrec
c0dba18d59 tools/litex_crossover_uart: add host argument to connect to a remote server. 
example: litex_server over PCIe running on a remote machine and create virtual uart on our local machine.
 2020-06-30 19:19:00 +02:00
Florent Kermarrec
6fe4994f66 targets: add identifier on all targets and update Versa ECP5. 2020-06-30 18:32:11 +02:00
Florent Kermarrec
5713c21017 tools/remote/comm_pcie: use ctypes.c_uint32 to do 32-bit accesses and avoid double writes/reads. 2020-06-30 14:12:35 +02:00
Florent Kermarrec
68297fce9e tools/litex_crossover_uart: add base_address argument (required when wishbone translation). 2020-06-30 14:11:27 +02:00
Dolu1990
b455a81678
Improve verilator compilation speed 
by asking verilator to split the C++ model into multiple files.
 2020-06-30 10:38:26 +02:00
Florent Kermarrec
54598ed2f8 software/bios/Makefile: fix #578 merge. (get back #579). 2020-06-29 17:01:36 +02:00
Florent Kermarrec
7beffba187 software/libbase/memtest: fix bus errors reporting. 2020-06-29 16:46:03 +02:00
sadullah
caf520c854 clean Makefile 2020-06-28 21:23:56 -04:00
sadullah
9256a4db6d minor change in BP top module 2020-06-28 13:10:24 -04:00
sadullah
7c83a1b858 syn with master blackparrot, upgrade BP to IMA 2020-06-28 13:07:59 -04:00
enjoy-digital
dae23f2a82
Merge pull request #576 from betrusted-io/deprecate_slave 
Deprecate slave terminology
 2020-06-27 09:35:04 +02:00
Florent Kermarrec
1e605fb23d liblitesdcard/sdcard: update with litesdcard. 2020-06-26 20:10:10 +02:00
Florent Kermarrec
34e9d12ef2 interconnect/axi/AXIStreamInterface: add tuser support. 2020-06-26 08:36:16 +02:00
Florent Kermarrec
4094a6ec3a liblitesdcard/sdcard: increase busy_wait and use common timeout. 2020-06-25 20:07:39 +02:00
Florent Kermarrec
e8f84c96a7 liblitesdcard/sdcard: decode cid only when SDCARD_DEBUG is set. 2020-06-25 13:48:49 +02:00
Florent Kermarrec
c07703124f liblitesdcard/sdcard_read: enable multiple block read. 
>10MB/s read speed with a 25MHz clock.
 2020-06-25 13:46:39 +02:00
Florent Kermarrec
8c572d2b3e targets: add fixed sdcard clock on boards with SDCard support. 2020-06-25 11:13:24 +02:00
Florent Kermarrec
c466900322 software/bios/litesdcard: remove sdcard_set_clk. 2020-06-25 11:12:40 +02:00
Florent Kermarrec
dfa3768d0e integration/soc/add_sdcard: remove sdclk. 2020-06-25 11:12:17 +02:00
bunnie
0b4c5059f2 Deprecate slave terminology 
http://oshwa.org/a-resolution-to-redefine-spi-signal-names
 2020-06-25 17:12:12 +08:00
Florent Kermarrec
9a27465d1d cores/clock/S6DCM: add expose_drp. 
From LiteSDCard SDClockerS6.
 2020-06-25 10:11:42 +02:00
Florent Kermarrec
d8aa9a42e4 software/bios/boot: improve printfs. 2020-06-25 09:58:08 +02:00
Florent Kermarrec
55e0193701 software/libase/memtest: improve printfs and add progress bar on data test. 2020-06-25 09:57:29 +02:00
Florent Kermarrec
497413664e libbase/progress: reduce to 40 HASHES_PER_LINE. 2020-06-25 09:56:13 +02:00
Florent Kermarrec
52d7f59af5 software/liblitedram: remove DDRPHY_CMD_DELAY support (no longer useful). 2020-06-25 09:01:33 +02:00
Florent Kermarrec
07f145fdaf software/liblitedram/sdram: remove SRAM hack. 
We now have memtest bios functions to test memories and testing SRAM while used by the BIOS is probably not a good idea.
 2020-06-25 08:58:01 +02:00
Florent Kermarrec
e2f9a82529 software/libbase/memtest: reorder functions. 2020-06-25 08:47:57 +02:00
Jędrzej Boczar
3b084b284a bios: move memtest from liblitedram to libbase 2020-06-24 14:53:18 +02:00
Florent Kermarrec
3a5aec6933 software/liblitesdcard: simplify, switch to DMAs, remove clocking/test functions. 2020-06-24 12:25:37 +02:00
Florent Kermarrec
fd4765e159 integration/soc: replace SDDataReader/SDDataWriter with DMAs. 2020-06-24 12:23:35 +02:00
Florent Kermarrec
bc64e35480 soc/cores: add simple DMA with WishboneDMAReader/WishboneDMAWriter. 2020-06-24 12:22:44 +02:00
Florent Kermarrec
d7cc7d2ac6 platforms/genesys2: add usb_fifo. 2020-06-23 18:01:51 +02:00
Florent Kermarrec
309eda4246 litex_term: keep and reduce inter-frame delay to 1e-5. 
Removing it completely would require revisiting the gateware/firmware code of the
UART. Since this is use for test purpose only and already allow > 600KB/s upload
speed, keeping it is acceptable.
 2020-06-23 17:20:12 +02:00
Florent Kermarrec
64589cfd2b soc/cores/uart/FT245: only use Asynchronous FIFO (Synchronous FIFO requires a software configuration). 2020-06-23 16:53:17 +02:00
Florent Kermarrec
0780b629a9 soc/cores/usb_fifo: cleanup and reduce fifo_depth (provide similar throughput when used as UART). 2020-06-23 16:51:24 +02:00
Florent Kermarrec
d59cec5acc software: use a single crt0 (deprecate crt0-ctr/crt0-xip) and avoid unnecessary defines. 
Since https://github.com/enjoy-digital/litex/issues/566, crt0-ctr and crt0-xip are now similiar
so we can get back to a single crt0 and remove the defines that were generated to distinguish
the different cases.

Since LiteX/MiSoC have diverged and are no longer compatible, we also no longer need to generate
the LiteX flag.
 2020-06-23 12:41:48 +02:00
Florent Kermarrec
384646c6be platforms/genesys2: use openocd_genesys2.cfg. 2020-06-23 11:58:36 +02:00
Florent Kermarrec
e92efc1ac5 platforms/kcu105: add sdcard/spisdcard. 2020-06-23 11:54:33 +02:00
Florent Kermarrec
35b04658a6 genesys2: add sdcard/spisdcard. 2020-06-23 11:54:16 +02:00
Florent Kermarrec
d53a51c550 platforms/netv2: add spisdcard. 2020-06-23 11:54:05 +02:00
Florent Kermarrec
c895586461 platforms/k705: rename mmc to sdcard and make it similar to other boards. 2020-06-23 10:57:43 +02:00
Florent Kermarrec
02908c51b3 cpu/lm32: fix config include paths. 
Was broken since the switch to python data modules.
 2020-06-23 09:47:04 +02:00
Florent Kermarrec
b1fe3140d7 bios/main: enable sdcardboot in boot_sequence with litesdcard. 2020-06-22 21:57:00 +02:00
Florent Kermarrec
847a5fcff4 software/liblitesdcard/sdcard: boot with FatFs working (hacky). 
Tested with Linux-on-LiteX-Vexriscv on Trellisboard with 10MHz clock.
 2020-06-22 21:33:17 +02:00
Florent Kermarrec
5b2f9c244d cores/cpu/microwatt: revert setup stack and fix missing subi %r1,%r1,0x100 (thanks ozbenh). 
Tested with powerpc64le-buildroot-linux-gnu-gcc.br_real (Buildroot 2020.02-00011-g7ea8a52) 8.4.0.
 2020-06-22 17:09:55 +02:00
Florent Kermarrec
0c0689f444 wishbone/DownConverter: fix read datapath when access is skipped because sel = 0. 
We also need to shift dat_r when acess is skipped.
 2020-06-22 13:37:14 +02:00
Florent Kermarrec
84617b585b cores/cpu/microwatt: temporary revert crt0.S/setup stack. 
lxsim --cpu-type=microwatt --cpu-variant=standard+ghdl no longer working otherwise.
 2020-06-22 11:36:19 +02:00
Benjamin Herrenschmidt
28ea4b3f4c software/microwatt: Fix copying data to RAM and clearing BSS 
This also makes us use the "small" memory model to avoid having to
use more complex constructs and adds the TOC to the linker script

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 2020-06-21 19:35:04 +10:00
Florent Kermarrec
13e0852af4 tools/litex_server: set socket option flags separately (required for Mac OS X). 2020-06-20 22:20:29 +02:00
Florent Kermarrec
efa41fd6bb litex_sim: simplify a bit ethernet+etherbone. 2020-06-20 09:15:56 +02:00
Florent Kermarrec
b0b37b4cb9 soc/cores/spi: make cs/loopback CSR optional. 
Useful for API retro-compatibility.
 2020-06-19 14:17:30 +02:00
Florent Kermarrec
05cb5f96a1 bios/boot: rewrite ROM boot description. 2020-06-18 12:56:29 +02:00
enjoy-digital
bdcccb9216
Merge pull request #569 from gsomlo/gls-mor1kx-data-init 
cpu/mor1kx: fix .data initialization (follow-up to PR #567)
 2020-06-18 08:43:20 +02:00
Gabriel Somlo
9ad45a6932 liblitesdcard/[spi]sdcard: avoid redundant (re-)initialization 2020-06-17 17:21:33 -04:00
Gabriel Somlo
e96cfbbc83 cpu/mor1kx: fix .data initialization (follow-up to PR #567) 2020-06-16 20:28:57 -04:00
enjoy-digital
aa0cd21378
Merge pull request #565 from gsomlo/gls-cosmetic-spi-fat 
post-FatFs cleanup
 2020-06-16 21:49:15 +02:00
enjoy-digital
05d4756eff
Merge pull request #567 from zyp/fix_data_segment 
bios/linker: Place .data in sram with initial copy in rom.
 2020-06-16 21:45:17 +02:00
Florent Kermarrec
b0f7611258 platforms/arty: move sdcard_pmod_io to JD. 2020-06-16 20:17:15 +02:00
Ilia Sergachev
3610b066c2 build/sim/core/modules: fix compilation warnings 2020-06-16 01:06:11 +02:00
Gabriel Somlo
5d9d99c0c2 liblitesdcard/sdcard: streamline initialization (cosmetic) 
Also, s/spisdcardstatus/sdcardstatus/g (this is *not* the SPI version).
 2020-06-15 15:31:41 -04:00
Gabriel Somlo
c05d0f1966 liblitesdcard/spisdcard: streamline initialization (cosmetic). 2020-06-15 15:24:40 -04:00
Vegard Storheil Eriksen
27fcddb209 soc_core: Increase sram size default to 8k. 2020-06-15 21:18:26 +02:00
Vegard Storheil Eriksen
9c68d71503 bios/linker: Place .data in sram with initial copy in rom. 2020-06-15 16:24:53 +02:00
Vegard Storheil Eriksen
336896603f bios/linker: Place .got in .rodata. 2020-06-15 16:04:02 +02:00
Gabriel Somlo
7d5ca3f926 bios/boot: addresses should use 'unsigned long' 2020-06-13 21:31:49 -04:00
Florent Kermarrec
5ddf350c2d software/spisdcard: reduce SPISDCARD_CLK_FREQ to 16MHz. 
25MHz does not seem to work on all boards/configurations, needs to be investigated.
 2020-06-11 19:18:32 +02:00
Florent Kermarrec
d6f92d1ffd build: add DFUProg. 2020-06-11 14:45:50 +02:00
Florent Kermarrec
653edd17ca bios/boot: simplify flashboot (remove specific linux boot). 
Storage in SPI Flash is generally limited and booting Linux from it is no longer very useful
since boot from SDCard is now supported. This is in the continuity of the SDCard/Ethernet
simplications to have an easier and more flexible boot scheme.
 2020-06-11 13:38:38 +02:00
Florent Kermarrec
7b65a93ca5 bios/boot: add separators, update copyrights. 2020-06-11 13:19:37 +02:00
Florent Kermarrec
f4abdd3f2c bios/boot: make Ethernet boot mode flexible (now also using boot.json similarly to SDCard boot). 
Example of boot.json:
{
	"Image":        "0x40000000",
	"rootfs.cpio":  "0x40800000",
	"rv32.dtb":     "0x41000000",
	"emulator.bin": "0x41100000"
}
 2020-06-11 13:12:58 +02:00
Florent Kermarrec
c2ae22eeb6 bios/boot: make SDCard boot more flexible using a boot.json file on the SDCard. 
The BIOS now reads the boot.json file to know which files need to be copied to RAM and where.
It will fallback to boot.bin is no boot.json is found and boot will fail if neither is found.

Example of boot.json file used to boot Linux-On-LiteX-Vexriscv:
{
	"Image":        "0x40000000",
	"rootfs.cpio":  "0x40800000",
	"rv32.dtb":     "0x41000000",
	"emulator.bin": "0x41100000"
}
 2020-06-11 11:26:10 +02:00
Florent Kermarrec
d918c0bb99 software/bios/boot/sdcardboot: let FatFs do the SDCard initialization with disk_initialize. 2020-06-11 08:33:56 +02:00
Florent Kermarrec
5197600812 software/bios/boot: add sdcardboot support for VexRiscv SMP. 2020-06-10 17:39:09 +02:00
Florent Kermarrec
72026d44f7 software/bios/main: clarify address space with @ instead of -. 2020-06-10 15:19:44 +02:00
enjoy-digital
a086237a07
Merge pull request #564 from shenki/microwatt-updates 
Microwatt updates
 2020-06-10 14:53:09 +02:00
enjoy-digital
ace81c83ee
Merge pull request #562 from gsomlo/gls-crlf 
liblitesdcard: maintain unix newline convention across all source files
 2020-06-10 14:40:28 +02:00
Florent Kermarrec
08bef5fc4c software/liblitesdcard/ffconf: enable FF_FS_MINIMIZE and FF_FS_TINY. 2020-06-10 11:46:59 +02:00
Florent Kermarrec
75225e5e33 software/bios/boot: move f_mount to copy_image_from_sdcard_to_ram and force mount. 2020-06-10 11:46:18 +02:00
Florent Kermarrec
59a048b666 software/libliteeth/tftp: switch to progress bar. 2020-06-10 10:00:05 +02:00
Florent Kermarrec
f7e06a7e3f bios/boot/copy_image_from_flash_to_ram: add missing init_progression_bar. 2020-06-10 09:59:38 +02:00
Florent Kermarrec
df9146fb78 soc/spisdcard: use 32-bit SPIMaster and do 32-bit xfers in spisdcardreceive_block to optimize speed. 2020-06-10 09:50:30 +02:00
Florent Kermarrec
d45cfc1e15 software/libbase/progress: avoid \t in progress bar, reduce HASHES_PER_LINE. 2020-06-10 09:16:06 +02:00
Florent Kermarrec
5beba178f2 software/libsdcard/spisdcard: add and use busy_wait_us to optimize speed. 2020-06-10 09:15:12 +02:00
Florent Kermarrec
dae15511a4 bios/boot/copy_image_from_sdcard_to_ram: use chunks of 32KB to increase speed. 2020-06-10 08:21:54 +02:00
Florent Kermarrec
d294e0f1de bios/boot: add progress bar to copy_image_from_flash_to_ram, use uint32_t in flash/sdcard functions. 2020-06-10 08:12:12 +02:00
Florent Kermarrec
99f40fecaa libase/progress: move __div64_32, do_div to div64.h/c as it was in Barebox. 2020-06-10 07:47:21 +02:00
Florent Kermarrec
96fc96eccd software/liblitesdcard: remove read_block prototype, minor cleanup. 2020-06-10 07:40:08 +02:00
Joel Stanley
748dcc1c26 microwatt: Add mmu.vhdl 2020-06-10 12:30:52 +09:30
Joel Stanley
b57fc8702a microwatt: Update IRQ signal in wrapper 2020-06-10 12:30:52 +09:30
Joel Stanley
68d2aa45fa microwatt: Add icache flush 2020-06-10 12:30:49 +09:30
Joel Stanley
e6909e2978 microwatt: Implement boot helper 2020-06-10 11:23:22 +09:30
Gabriel Somlo
5575a921d0 liblitesdcard: maintain unix newline convention across all source files 2020-06-09 14:09:35 -04:00
Florent Kermarrec
fe9b42facf bios/boot: use progress bar in copy_image_from_sdcard_to_ram. 2020-06-09 20:00:32 +02:00
Florent Kermarrec
21b9239dc0 libbase: add progress bar (from Barebox). 2020-06-09 20:00:05 +02:00
Florent Kermarrec
32ebbc7761 software/liblitesdcard: add retries when setting card to Idle. 2020-06-09 19:59:38 +02:00
Florent Kermarrec
04d0ba6187 software/liblitesdcard/sdcard: add FatFs disk functions. 2020-06-09 17:58:43 +02:00
Florent Kermarrec
e27ed657e9 software/liblitesdcard/spisdcard: rename #defines and allow external definition. 2020-06-09 13:50:28 +02:00
Florent Kermarrec
a9e8860e49 software/liblitesdcard: create fat directory for FatFs files. 2020-06-09 13:44:26 +02:00
Florent Kermarrec
f1aba7e45c sofware/liblitesdcard: enable Long Filename (LFN). 2020-06-09 13:35:14 +02:00
Florent Kermarrec
fb282d1a72 software/libsdcard: rewrite/simplify SPISDCard/FatFs support and only keep SDCard ver2.00+ compatibility. 2020-06-09 12:50:56 +02:00
Gabriel Somlo
78e3f25157 liblitesdcard: convert all sources to unix style newlines (cosmetic) 
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-06-06 13:24:29 -04:00
Florent Kermarrec
c1806eba11 software/liblitesdcard: remove unsused functions with FF_FS_READONLY. 2020-06-05 23:25:54 +02:00
Florent Kermarrec
f9b43c81cc software/liblitesdcard: switch to FatFs for sdcardboot. 2020-06-05 21:20:19 +02:00
Florent Kermarrec
f972c8e45e software/liblitesdcard: base it on FatFs generic example code + LiteX's SPIMaster specific functions. 2020-06-05 16:27:38 +02:00
Florent Kermarrec
5b908983a2 software/liblitesdcard: add FatFs files. 
To avoid maintaining our own code and support all Fat filesystems, let's just use FatFs library.
 2020-06-05 16:26:58 +02:00
Florent Kermarrec
7d141258be software/liblitesdcard/spisdcard: simplify/rewrite for consistency with the others parts of the project. 
- Improve code readability, remove un-needed or duplicate comments.
- Only use a spi_xfer function for both write/read.
- Set the SDCard to low clk freq before init and increase it when initialized.
 2020-06-05 12:46:23 +02:00
Florent Kermarrec
860ac1e212 software/liblitesdcard: add copyrights to spisdcard/fat16. 2020-06-04 12:14:54 +02:00
Florent Kermarrec
0ec50881f0 software/liblitesdcard/sdcard: simplify readSector. 2020-06-04 11:55:25 +02:00
Florent Kermarrec
8c6f74d483 software/liblitesdcard: fat16 boot working with both SPI and SD modes. 2020-06-04 11:40:42 +02:00
Florent Kermarrec
bdaf6ff2dd software/liblitesdcard: move fat16 code to separate file to avoid duplication. 2020-06-03 23:16:13 +02:00
Florent Kermarrec
4b3c5203ed software/bios/libsdcard: add initial boot from sdcard with litescard, rename spisdcardboot command to sdcardboot. 2020-06-03 20:03:18 +02:00
Florent Kermarrec
b30e3353b5 soc/add_sdcard: use SDClockerS7 for 7-Series and SDClockerGen for others devices. 2020-06-03 18:37:08 +02:00
Jan Kowalewski
eceee7e4c4 litex/soc/software/liblitespi: fix names associated with PHY CSRs 2020-06-03 15:37:06 +02:00
Florent Kermarrec
fb4b6c35a3 boards/ulx3s: add sdcard pins and initial LiteSDCard integration. 2020-06-03 14:36:33 +02:00
Florent Kermarrec
997a17b933 soc/add_sdcard: add minimal SDClockerECP5 on ECP5. 2020-06-03 14:34:59 +02:00
Florent Kermarrec
9a026c09f9 soc/add_sdcard: remove limitation to 7-Series but only add clocker for it. 2020-06-03 13:47:39 +02:00
Florent Kermarrec
c311f98cfa soc/add_sdcard: emulator clocking moved to litesdcard. 2020-06-03 13:43:44 +02:00
Florent Kermarrec
382f239e74 software/libsdcard: keep SDCARD_DEBUG enabled for now, fix typos. 2020-06-03 13:38:34 +02:00
Florent Kermarrec
20bbdaaf6b soc/add_sdcard: remove Timer (unused). 2020-06-03 13:13:07 +02:00
Florent Kermarrec
ab447df922 software/liblitesdcard: review/simplify (code is over-complicated, revert part of the old code and write a minimal test for now). 2020-06-03 13:12:45 +02:00
Florent Kermarrec
ee4056cfec software/liblitesdcard: remove sdtimer functions (unused). 
sdtimer was used to evaluate performance but is no longer used.
 2020-06-03 11:11:45 +02:00
Mariusz Glebocki
635a61e306 targets/arty: use sys_clk_freq = 60MHz for Symbiflow toolchain 2020-06-02 16:23:08 +02:00
Mariusz Glebocki
5071ef3ef7 build/xilinx/symbiflow: remap part name 2020-06-02 16:23:08 +02:00
Florent Kermarrec
55723f138b software/liblitedram: revert sdrsw() in sdrlevel: this is still required for sdrlevel command. 2020-06-02 16:14:53 +02:00
enjoy-digital
ddcf68c062
Merge pull request #553 from ozbenh/sim-autoinit 
sdram: Unconditionally switch to SW control before inits
 2020-06-02 15:49:00 +02:00
Mateusz Holenko
f1e7d73e48 bios: boot: Boot linux on mor1kx with external device tree and rootfs 2020-06-02 14:57:48 +02:00
Florent Kermarrec
5d202ddb97 test: update. 2020-06-02 13:51:48 +02:00
Florent Kermarrec
01f7947b56 targets: rename gateware-toolchain parameter to toolchain. 2020-06-02 13:44:23 +02:00
Florent Kermarrec
245985d6c5 targets/arty: integrate symbiflow changes to avoid duplication. 2020-06-02 13:37:19 +02:00
Florent Kermarrec
89106873db build/generic_platform: add default_clk constraints only when used. 2020-06-02 13:34:09 +02:00
Florent Kermarrec
0cd613ccb8 build/xilinx/symbiflow: reuse .xdc generation from Vivado to avoid duplication, fix copyright. 2020-06-02 13:21:12 +02:00
Florent Kermarrec
80ec5eca76 boards/arty: remove specific arty_symbiflow platform and adapt target to use standard platform. 2020-06-02 12:18:12 +02:00
Florent Kermarrec
af928b2626 xilinx/simbiflow: add simple symbiflow_device re-mapping. 2020-06-02 12:15:38 +02:00
enjoy-digital
5104d07a13
Merge pull request #551 from antmicro/mglb/symbiflow-toolchain-xilinx-7-support 
Add Symbiflow toolchain support for Xilinx 7-series
 2020-06-02 11:55:33 +02:00
Tim Ansell
77139289f8
Merge pull request #552 from ozbenh/memspeed-long 
sdram: Use unsigned long for memory test
 2020-06-01 15:23:03 -07:00
Benjamin Herrenschmidt
6239eac130 sdram: Use unsigned long for memory test 
This makes it twice as fast on 64-bit CPUs when using a 64-bit bus :-)

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 2020-06-02 08:08:42 +10:00
Mariusz Glebocki
ae121aacdf targets: add arty_symbiflow 
Signed-off-by: Mariusz Glebocki <mglebocki@antmicro.com>
 2020-06-01 21:41:56 +02:00
Mariusz Glebocki
2bb2fbdbea platforms: add arty_symbiflow 
Signed-off-by: Mariusz Glebocki <mglebocki@antmicro.com>
 2020-06-01 21:41:17 +02:00
Mariusz Glebocki
bd702397d1 build/xilinx: add Symbiflow toolchain support 
Signed-off-by: Mariusz Glebocki <mglebocki@antmicro.com>
 2020-06-01 21:36:28 +02:00
enjoy-digital
a116578c82
Merge pull request #550 from antmicro/jboc/spd-read 
bios/litedram: Add command to verify SPD contents with the one used during generation
 2020-06-01 21:17:40 +02:00
Benjamin Herrenschmidt
4a6256a50d sdram: Unconditionally switch to SW control before inits 
This will allow the controller to default to HW control which means
the sim model can be used without specific initializations

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 2020-06-01 23:44:09 +10:00
Mariusz Glebocki
a4e8323485 build/xilinx: do not assume build name is "top" 2020-06-01 13:28:54 +02:00
enjoy-digital
5cc7a98845
Merge pull request #547 from gsomlo/gls-fix-sdcard-status 
soc/software/litesdcard: update for response register back to 128 bits
 2020-06-01 11:37:05 +02:00
Florent Kermarrec
395af900fd interconnect/wishbone/DownConverter: skip accesses on slave when sel==0 and simplify. 
Improve efficiency for 64-bit CPU accessing only the 32-bit LSBs/MSBs.
 2020-06-01 11:06:23 +02:00
Florent Kermarrec
511832a911 soc/interconnect/axi: generate wishbone.sel for reads. 2020-06-01 10:58:45 +02:00
Florent Kermarrec
4f82a36afd soc/software: only keep 32-bit CSR alignment support. 
64-bit support was added for 64-bit CPU because of limitation of the hardware
on CSR accesses. Now that the Wihhbone2CSR bus handles wishbone.sel, this is no
longer required.
 2020-06-01 10:01:14 +02:00
Gabriel Somlo
28290efd00 soc/software/litesdcard: update for response register back to 128 bits 
The additional (17th) byte returned via the response register was
ignored by software (bios and kernel), so LiteSDCard was updated
to only return the (original, useful) 128 bits.

This patch updates the LiteSDCard code in the LiteX bios to only
expect those 128 bits, and to do so in a manner that's portable
across CSR data widths and alignments.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-05-30 18:12:51 -04:00
Florent Kermarrec
759367752c wishbone/wishbone2csr: use wishbone.sel on CSR write. 
CSR write is only done if wishbone.sel != 0. This should avoid the need for 64-bit
CSR alignment on 64-bit CPUs since a 64-bit Wishbone write access targeting only the
32-bit LSB or MSB will be splitted in 2x32-bit accesses: one with sel=0xf, one with sel=0.
 2020-05-30 15:22:02 +02:00
Florent Kermarrec
b1ec092e88 soc/software/litesdcard: use new send register to send command and remove CSR8_CMD_FIX. 2020-05-29 20:15:02 +02:00
Florent Kermarrec
efcba14b1b platforms/nexys_video: add spisdcard pins. 2020-05-29 19:36:33 +02:00
Florent Kermarrec
119ce56f6c targets/nexys_video: add spi-sdcard and sdcard support. 2020-05-29 19:26:29 +02:00
Florent Kermarrec
cc5950178d plaforms/nexys_video: keep up to date with litex-boards. 2020-05-29 19:26:03 +02:00
Florent Kermarrec
5cc564fb8f targets: simplify Ethernet/Etherbone integration on targets with both. 2020-05-29 19:22:35 +02:00
Florent Kermarrec
55c7461e7b bios/cmds/cmd_litesdcard: rewrite comments/descriptions. 2020-05-29 18:51:24 +02:00
Florent Kermarrec
6cb03963f3 bios/main: replace / with -. 2020-05-29 18:40:54 +02:00
enjoy-digital
5dd5f97b88
Merge pull request #545 from gsomlo/gls-fix-mmptr 
csr: fix simple accessor alignment
 2020-05-29 18:32:30 +02:00
Gabriel Somlo
3e1b17d459 csr: fix simple accessor alignment 
MMPTR should always follow CSR alignment, NOT CSR data width.
(the latter merely indicates how many bits within a MMPTR are
actually populated).

Fixup for commit #4a5072a.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-05-29 12:03:05 -04:00
Florent Kermarrec
6c1e2d8413 software/liblitesdcard: replace hexdump with dump_bytes already available in the BIOS. 2020-05-29 17:15:20 +02:00
Florent Kermarrec
9e068a7494 soc/add_sdcard: add with_emulator parameter to use SDCard emulator (from Google Project Vault) and integrate it in litex_sim. 2020-05-29 16:07:40 +02:00
Jędrzej Boczar
a433c837e0 bios/litedram: add option to verify SPD EEPROM memory contents 2020-05-29 15:14:54 +02:00
Jędrzej Boczar
1692dfbf61 build/sim/spdeeprom: use hex format when loading from file 2020-05-29 14:56:56 +02:00
enjoy-digital
62d939e85f
Merge pull request #543 from antmicro/jboc/eeprom-sim 
litex/build/sim: add module for simulating SPD EEPROM
 2020-05-28 16:46:34 +02:00
Florent Kermarrec
c4f96318ec targets/nexys4ddr: fix sdcard assert. 2020-05-28 15:31:33 +02:00
Florent Kermarrec
76cc112ecf bios: add main bus and csr bus infos, use KiB/GiB. 2020-05-28 15:05:24 +02:00
Jędrzej Boczar
a0ce4ce56b litex/build/sim: add module for simulating SPD EEPROM 2020-05-28 12:10:25 +02:00
Florent Kermarrec
02072deab1 integration/soc/add_sdcard: always use 32-bit/512bytes memories (not sure this will change?) and allocate sdwrite/sdread regions dynamically. 2020-05-27 23:47:07 +02:00
Florent Kermarrec
4b3afa75a7 integration/soc: add add_sdcard method with integration code from nexys4ddr. 
Even if not cleaned up yet, having it there will avoid duplications in targets.
 2020-05-27 23:18:15 +02:00
Benjamin Herrenschmidt
c78caeb998 csr: Fix definition(s) of CSR_BASE in generated headers 
CSR_BASE is currently defined twice. Once in mem.h as the base
of the CSR region in the SoC address space, and once in csr.h
as the base address for all CSRs.

This fixes two issues with those definitions:

 - The mem.h one is unconditional which prevents an external
redefinition (which is useful under some circumstances such as
when using an address decoder outside of LiteX with a standalone
core).

 - The csr.h one is actually the origin of the first CSR region
rather than the origin of the CSR region in the SoC space. They
are usually the same ... unless you don't have CSR bank 0 in
which case the csr.h one becomes different. This causes conflicts
with the mem.h definition and breaks projects using a standalone
cores.

The first one is fixed by adding the #ifndef/#endif around the
definition of the memory regions, the second one by passing the
csr_base to use to get_csr_header()

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 2020-05-27 21:48:00 +02:00
Benjamin Herrenschmidt
f8bb500a43 liblitedram/sdram: Add option to disable cdelay() 
When running in sim, those delays can take a *long* time, which
isn't always necessary with the simulated litedram PHY.

This allows system.h to optionally set CONFIG_SIM_DISABLE_DELAYS
which  causes cdelay to do nothing.

This is especially useful when using a verilated litedram inside
a bigger/slower simulated design as to not spend a huge amount
of time going through the initializations.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 2020-05-27 21:39:28 +02:00
Florent Kermarrec
6d72ef28a8 cpu/serv: add variants. 2020-05-27 20:00:10 +02:00
Florent Kermarrec
fd7ec50e43 soc/integration/export: add optional csr_base parameter. 2020-05-27 19:59:54 +02:00
Florent Kermarrec
795ff08a20 build/sim/verilator: add regular_comb parameter (that defaults to False) and pass it to get_verilog. 2020-05-27 19:54:52 +02:00
enjoy-digital
25d2e7c92f
Merge pull request #542 from gsomlo/gls-sdcard-followup 
software/bios: fixup sdclk command
 2020-05-27 19:04:18 +02:00
enjoy-digital
3fd6ecd86e
Merge pull request #541 from antmicro/jboc/spd-read 
Add support for I2C to read SPD EEPROM
 2020-05-27 19:03:50 +02:00
Florent Kermarrec
ab80606036 soc/core/uart: move WishboneStreamingBridge in it and rename to Stream2Wishbone. 2020-05-27 18:40:45 +02:00
Gabriel Somlo
6da98ca14d software/bios: fixup sdclk command 2020-05-27 12:38:59 -04:00
Florent Kermarrec
0a3d649ad8 interconnect/wishbone: integrate Wishbone2CSR. 2020-05-27 18:15:05 +02:00
Florent Kermarrec
b5b88d27b5 interconnect/csr_bus: add separators. 2020-05-27 18:13:57 +02:00
Florent Kermarrec
86952a6e06 interconnect/wishbone: remove CSRBank (probably not used by anyone). 2020-05-27 18:04:08 +02:00
Florent Kermarrec
e404608cf4 interconnect/wishbone: add separators and move SDRAM/Cache. 2020-05-27 17:59:33 +02:00
Florent Kermarrec
1fddd0e3d3 interconnect/wishbone: simplify DownConverter. 2020-05-27 17:34:11 +02:00
Jędrzej Boczar
1172c10afb bios: move I2C from liblitedram to libbase 2020-05-27 15:37:19 +02:00
Florent Kermarrec
e0d2682055 interconnect/wishbone: remove UpConverter (probably not used by anyone and would need to be rewritten). 
We'll provide a better implementation if this is useful.
 2020-05-27 15:27:33 +02:00
Florent Kermarrec
696b31ed18 tools/litex_sim: switch to SoCCore/add_sdram instead of SoCSDRAM. 2020-05-27 15:16:30 +02:00
Florent Kermarrec
2efcf87925 targets/nexys4ddr: update add_sdcard method. 
Tested with:
sdinit
sdtestwrite 0x10 foobar
sdtestread 0x10
 2020-05-27 14:09:05 +02:00
Jędrzej Boczar
472bf9ac71 bios/sdram: expose I2C functions 2020-05-27 11:56:59 +02:00
Florent Kermarrec
3b47d4a479 tools/litex_jtag_uart: add openocd config and telnet port parameters. 2020-05-27 08:59:12 +02:00
Florent Kermarrec
67cf67034c cpus: remove common cpu variants/extensions definition and simplify variant check. 
Having common cpu variants/extensions has no real additional value since we are supporting
very various CPUs where minimal/standard/full have different meanings. Checking against
common variants/extensions has also cause more issues recently when adding new CPUs than
the additional value it was supported to provide.

So let's just simplify things: a CPU provide the supported variants and we just check
against that.
 2020-05-26 09:36:44 +02:00
Florent Kermarrec
062ff67e12 cpu/microwatt: add standard+ghdl variant that uses GHDL Yosys plugin. 2020-05-26 08:51:33 +02:00
Florent Kermarrec
24687cbd9f tools/litex_client/RemoteClient: add base_address parameter. 
Useful when address translation is done in the SoC.
 2020-05-25 14:11:14 +02:00
Florent Kermarrec
78a9579e09 cores/uart/RS232PHYTX: fix startbit duration by pre-loading phase_accumulator_tx to tuning_word. 2020-05-25 10:46:53 +02:00
enjoy-digital
370e46529d
Merge pull request #539 from dayjaby/pr-fix_uart_startbit 
Fix UART startbit: 1 cycle later
 2020-05-25 10:33:58 +02:00
Florent Kermarrec
c75cf45ab4 tools: add litex_jtag_uart to create a virtual uart for the jtag uart. 2020-05-25 10:21:06 +02:00
Florent Kermarrec
2cf83b9f69 tools: rename litex_crossover poc to litex_crossover_uart, remove from setup for now. 2020-05-25 10:19:16 +02:00
David Jablonski
e853ad4b61 fix uart startbit: 1 cycle later 2020-05-24 16:12:07 +02:00
Florent Kermarrec
bed5aafd6c tools: add litex_crossover to be able to use lxterm (and serialboot) over a crossover UART (bridged over UART/Ethernet/PCIe/USB, etc...). 
This is still a proof of concept but can be used/tested with:
lxsim --with-etherbone --uart-name=crossover --csr-csv=csr.csv
lxserver --udp --udp-ip=192.168.1.51
lxcrossover (will indicate the virtual_tty)
lxterm virtual_tty
 2020-05-24 10:55:25 +02:00
Florent Kermarrec
3833bc3ec3 litex_sim: override uart_name to sim only for serial. 
Using uart_name=crossover is useful to simulate crossover mode.
 2020-05-24 09:52:56 +02:00
Florent Kermarrec
2fb52e66b1 integration/soc: remove TODO in header. 2020-05-23 18:54:04 +02:00
Florent Kermarrec
b65f18c357 cpu/cv32e40p: fix copyright year. 2020-05-23 18:53:03 +02:00
Florent Kermarrec
30f3517041 cpu/cv32e40p: add copyright and improve indentation. 2020-05-22 15:55:35 +02:00
enjoy-digital
4c4cd335de
Merge pull request #535 from antmicro/arty-cv32e40p 
Add support for the CV32E40P RISC-V CPU
 2020-05-22 13:44:10 +02:00
Mateusz Hołenko
9d16b0fc82 libbase: Include missing uart header 
This fixes compilation on mor1kx.
 2020-05-22 11:43:18 +02:00
Jędrzej Boczar
bdc7eb5c48 litex_sim: load SPD data from files in hexdump format as printed in BIOS 2020-05-21 16:20:06 +02:00
Jędrzej Boczar
a42dc97401 bios/sdram: add BIOS command for reading SPD 2020-05-21 14:32:31 +02:00
Jędrzej Boczar
8fd3e74ec9 bios/sdram: add firmware for reading SPD EEPROM 2020-05-21 14:07:42 +02:00
Florent Kermarrec
42350f6d83 platforms/targets: keep in sync with litex-boards. 
- LedChaser.
- use of soc.build_name in load/flash bitstream.
 2020-05-21 09:14:33 +02:00
Florent Kermarrec
2eea786436 build/sim: rename dut to sim (for consistency with other builds). 2020-05-21 09:06:29 +02:00
Florent Kermarrec
a6cbbc9d69 integration/soc: set build_name to platform.name when not specified. 2020-05-21 09:05:45 +02:00
Florent Kermarrec
16417cb8f1 software/liblitespi: fix #endif location. 2020-05-20 23:20:45 +02:00
enjoy-digital
9bdb063b3e
Merge pull request #516 from antmicro/i2s_support_arty 
Add I2S support to Arty
 2020-05-20 19:49:42 +02:00
Franck Jullien
7c5f56c207 litex/sim: fix compiler warnings 2020-05-20 15:34:19 +02:00
Pawel Sagan
ce49990084 Extend I2S capabilities 
This commit:
* adds the support for I2S standard mode,
* extends I2S left justified mode,
* allows to configure sample size for tx/rx in 1-32 bits range,
* implements I2S master mode,
* allows to concatenate channels or used the padded mode.

This required to rework the FSM.
 2020-05-20 14:31:51 +02:00
Piotr Binkowski
2d6ee5aaf2 cores/cpu: add cv32e40p 2020-05-20 13:46:37 +02:00
Piotr Binkowski
ca8cb83424 software/bios/isr: add support for cv32e40p 2020-05-20 13:46:37 +02:00
Jan Kowalewski
ab41e27e4c software/liblitespi/spiflash: fix dummy bits setup function name 2020-05-20 11:47:40 +02:00
Florent Kermarrec
bd0f21ba85 targets/netv2: remove LiteSPI integration (not mature enough to be directly integrated on targets). 
The LiteSPI integration can be prototype in the LiteSPI example designs. Once mature and
fully tested, we could integrate it to the targets.
 2020-05-20 11:18:59 +02:00
Florent Kermarrec
80eca3000b software/liblitespi/spiflash: review/simplify/update and test on arty. 2020-05-20 11:16:39 +02:00
Florent Kermarrec
4a1756208d build/xilinx: simplify LITEX_ENV_ISE/VIVADO handling. 2020-05-20 10:00:39 +02:00
Florent Kermarrec
e91c317139 software/bios: cleanup includes and specify the lib in the include. 
This ease understanding from which lib the file is included and also allow
having simple filenames in the libs.
 2020-05-20 09:55:19 +02:00
Florent Kermarrec
c3a03d0d99 software: create liblitespi and mode litespi code to it (with some parts commented out for now). 2020-05-20 09:32:45 +02:00
Jan Kowalewski
61238beeae soc/software/bios: add autoconfiguration functionality for LiteSPI core 2020-05-20 09:16:07 +02:00
Gabriel Somlo
c5524dbf20 software/bios: fix link order to avoid undefined symbol errors 
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-05-19 16:20:58 -04:00
Florent Kermarrec
b4267a7901 build/xilinx: source settings64.sh automatically just before build if LITEX_ENV_ISE/LITEX_ENV_VIVADO environment variables are set. 2020-05-19 16:21:52 +02:00
Florent Kermarrec
de7e0ee9ff integration/soc_core: avoid cpu_variant check if custom cpu_cls is passed. 2020-05-19 16:01:57 +02:00
Florent Kermarrec
6f8f0d2346 litex_setup: add litehyperbus and remove hyperbus core/test. 2020-05-19 15:49:25 +02:00
Florent Kermarrec
109fd2674a integration/builder: simplify default output_dir to "build/platform". 
All SoC are now based on the same base class and naming was too complicated.
 2020-05-19 13:59:56 +02:00
Florent Kermarrec
7192397ab4 software/libbase: remove linker-sdram (unused). 2020-05-18 23:35:48 +02:00
Florent Kermarrec
b4b84def3c software/bios: mode spisdcard code to liblitesdcard. 2020-05-18 23:33:34 +02:00
Florent Kermarrec
21e2a34c3f software/bios: rename commands to cmds and update with libs' names. 2020-05-18 23:26:51 +02:00
Florent Kermarrec
33f6ce7431 software/bios: move hw flags definitions to respective libs, remove hw/flags.h. 2020-05-18 23:09:31 +02:00
Florent Kermarrec
403355a8ed software: create liblitescard and move sdcard init/test code to it. 2020-05-18 22:49:12 +02:00
Florent Kermarrec
920d0ee536 software: create liblitedram and move sdram init/test code to it. 2020-05-18 22:42:23 +02:00
Florent Kermarrec
c95084e5c6 bios/software: rename cmd_dram/cmd_sdcard/cmd_spi_flash to cmd_litedram/cmd_litesdcard/cmd_spiflash. 2020-05-18 22:24:24 +02:00
Florent Kermarrec
573a881529 software/bios/commands: rename cmd_mdio to cmd_liteeth. 2020-05-18 22:16:20 +02:00
Florent Kermarrec
ff8d9e61bf software/bios: move mdio to libliteeth. 2020-05-18 21:09:41 +02:00
Florent Kermarrec
70a67ce7ed software/bios: rename libnet to libliteeth and move all ethernet files to it. 2020-05-18 21:04:54 +02:00
Florent Kermarrec
56b8723b72 software/bios: rename cmd_mem_access to cmd_mem. 2020-05-18 19:59:28 +02:00
Florent Kermarrec
a02077d547 cpu/microwatt/add_sources: add use_ghdl_yosys_synth parameter to convert microwatt to verilog using GHDL-Yosys-plugin and use converted verilog for build. 2020-05-18 17:30:42 +02:00
Florent Kermarrec
b5352f403c cpu/microwatt: update microwatt_wraper.vhdl 2020-05-18 16:38:08 +02:00
Florent Kermarrec
be25500e91 uptime: rework and integrate it in Timer to ease software support. 2020-05-17 11:05:14 +02:00
Florent Kermarrec
d6549ff8f1 bios: add uptime command and rewrite cmd_bios comments. 2020-05-16 10:02:31 +02:00
Florent Kermarrec
fc0e55be32 soc: improve uptime comments. 2020-05-16 10:01:39 +02:00
enjoy-digital
840679add6
Merge pull request #526 from rprinz08/master 
Make booting from SD-Card to behave same as from SPI flash
 2020-05-15 16:03:37 +02:00
Florent Kermarrec
82364de57f soc/SoCController: add uptime since start (disabled by default) and allow features to be enabled/disabled. 2020-05-15 15:00:04 +02:00
rprinz08
3f649077b1 Make booting from SD-Card to behave same as from SPI flash 2020-05-15 12:07:52 +02:00
Florent Kermarrec
3391398a5f bios/sdram: always show bitslip on two digits to keep scan aligned. 2020-05-14 15:20:52 +02:00
Benjamin Herrenschmidt
1e35b0e705 csr: Rework accessors 
Have all the new compound accessors be written in terms of the simple
ones and fix how CSR_ACCCESORS_DEFINED can be used to override the
simple ones but keep the definitions of the other ones around.

This *should* also also fix incorrect multiple accesses done
by  64-bit CPUs to 32-bit CSR busses, and make the accessors not
depend on CONFIG_CSR_ALIGNMENT being the same as sizeof(unsigned long)*8

In addition, the generated csr.h now will include system.h
always when with_access_functions is True. This guarantees that the
higher level accessors are defined. The extern prototypes for the
simple accessors when CSR_ACCCESORS_DEFINED are removed and system.h
is responsible for providing them. It is also added to hw/common.h

This allows system.h to set CSR_ACCCESORS_DEFINED when necessary, in
which case it's responsible for both declaring and defining the simple
accessors. That way, it can make them inline rather than forcing them
to be extern which at least on microwatt saves spaces.

One can continue to use -DCSR_ACCCESORS_DEFINED but in that case a system.h
will have to be provided with at least the extern definitions.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 2020-05-14 21:38:19 +10:00
enjoy-digital
a51c7a7bac
Merge pull request #518 from enjoy-digital/csr_base 
export: add define of CSR_BASE if not already defined and use it for …
 2020-05-14 08:02:37 +02:00
Arnaud Durand
9d9e7d54cd
Update litex_term help 
Specify the use of kernel address with flash flag.
 2020-05-13 22:50:09 +02:00
Florent Kermarrec
2e59dc329d platforms/nexys4ddr: add card detect pin to sdcard. 2020-05-13 19:11:46 +02:00
Florent Kermarrec
51742be2bb integration/soc: review/simplify interconnect and add logger.info. 2020-05-13 18:29:12 +02:00
Benjamin Herrenschmidt
1ed6869110 soc: Revive generation of a PointToPoint interconnect 
When there's only one master, one slave, and that slave is at 0

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 2020-05-14 00:06:53 +10:00
Florent Kermarrec
748ef1add3 export: add define of CSR_BASE if not already defined and use it for CSRs definitions/accesses. 
This will allow more flexibility when integrating standalone cores.
 2020-05-13 15:56:20 +02:00
Florent Kermarrec
9d1443c1a8 cpu/soc_core: automatically set csr mapping to 0x00000000 when using CPUNone, remove csr_base parameter that was used for that. 2020-05-13 09:31:20 +02:00
Florent Kermarrec
5ea3bae036 bios/boot: review/fix #503. 
- copy_image_from_flash_to_ram is now used by all CPUs.
- copy_image_from_flash_to_ram already show the flash address, no need to duplicate it.
 2020-05-13 08:44:17 +02:00
enjoy-digital
bf7857f553
Merge pull request #503 from rprinz08/master 
BIOS boot firmware from SPI with address offset
 2020-05-13 08:36:43 +02:00
Dave Marples
d2d82dacf2 Bios linker edits to prevent inappropriate optimisation 2020-05-12 23:32:49 +01:00
rprinz08
1f55fcf449 fixed bug in BIOS spi flash "fw" command 2020-05-12 16:58:42 +02:00
rprinz08
f062c0c44b removed FLASH_BOOT_OFFSET, replaced memcyp with copy_image_from_flash_to_ram 2020-05-12 16:57:21 +02:00
Florent Kermarrec
3fb99b7d33 cores/spi_flash: add back old SpiFlashDualQuad and rename new one as SpiFlashQuadReadWrite. 2020-05-12 16:51:47 +02:00
enjoy-digital
2a5a7536b8
Merge pull request #478 from antmicro/extended_spi_flash 
Extended SPI flash support
 2020-05-12 16:42:01 +02:00
enjoy-digital
7d79da8eda
Merge pull request #510 from mubes/colorlight_usb 
Colorlight usb
 2020-05-12 16:35:29 +02:00
Florent Kermarrec
3a6dd95d6f integration/soc: review/simplify changes for standalone cores. 
- do the CSR alignment update only if CPU is not CPUNone.
- revert PointToPoint interconnect when 1 master and 1 slave since this will
break others use cases and will prevent mapping slave to a specific location.
It's probably better to let the synthesis tools optimize the 1:1 mapping directly.
- add with_soc_interconnect parameter to add_sdram that defaults to True. When
set to False, only the LiteDRAMCore will be instantiated and interconnect with
the SoC will not be added.
 2020-05-12 16:18:26 +02:00
Dave Marples
8499733289 Fix dumb missing line 2020-05-12 14:40:11 +01:00
enjoy-digital
0d5eb13359
Merge pull request #511 from ozbenh/standalone-cores 
Improve standalone cores
 2020-05-12 14:55:44 +02:00
Florent Kermarrec
873d95e517 interconnect/wishbonebridge: refresh/simplify. 
This should also improve Wishbone timings.

Tested on iCEBreaker:
./icebreaker.py --cpu-type=None --uart-name=uartbone --csr-csv=csr.csv --build --flash

With the following script:

#!/usr/bin/env python3

import sys

from litex import RemoteClient

wb = RemoteClient()
wb.open()

# # #

print("scratch: 0x{:08x}".format(wb.regs.ctrl_scratch.read()))

errors = 0
for i in range(2):
for j in range(32):
wb.write(wb.mems.sram.base + 4*j, i + j)
for j in range(32):
if wb.read(wb.mems.sram.base + 4*j) != (i + j):
errors += 1
print("sram errors: {:d}".format(errors))

# # #

wb.close()
 2020-05-12 13:40:28 +02:00
Benjamin Herrenschmidt
f628ff6b47 WB2CSR: Use CSR address_width for the wishbone bus 
Currently, we create a wishbone interface with the default address
width (30 bits) for the bridge. Instead, create an interface that
has the same number of address bits as the CSR bus.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 2020-05-12 21:37:36 +10:00
Benjamin Herrenschmidt
520c17e96d soc_core: Add option to override CSR base 
When creating standalone IP cores such as standalone LiteDRAM without
a CPU, the CSR are presented externally via a wishbone with just enough
address bits to access individual CSRs (14), and no address decoding
otherwise. It is expected that the design using such core will have
its own address decoder gating cyc/stb.

However, such a design might still need to use LiteX code such as
the sdram init code, which relies on the generated csr.h. Thus we
want to be able to control the CSR base address used by that generated
csr.h.

This could be handled instead by having the "host" code provide
modified csr_{read,write}_simple() that include the necessary base
address. However, such an approach would make things complicated
if the design includes multiple such standalone cores with separate
CSR busses (such as LiteDRAM and LiteEth).


Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 2020-05-12 21:35:12 +10:00
Benjamin Herrenschmidt
ecbd40284a soc: Don't update CSR alignment when there is no CPU 
The alignment specified by the standalone core config should
be honored.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 2020-05-12 21:31:23 +10:00
Benjamin Herrenschmidt
f28f247130 soc: Don't create a wishbone slave to LiteDRAM with no CPU 
When creating a standalone LiteDRAM core with no CPU, there is
no need to create a wishbone slave to LiteDRAM interface.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 2020-05-12 21:30:19 +10:00
Dave Marples
33e202edd4 Bring into line with master 2020-05-12 12:28:09 +01:00
Benjamin Herrenschmidt
dcc881db92 soc: Don't create a share intercon with only one master and one slave 
This creates a lot of useless churn in the resulting verilog. Instead
use a point to point interconnect in that case.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 2020-05-12 20:58:19 +10:00
enjoy-digital
c136113a9b
Merge pull request #506 from scanakci/blackparrot_litex 
Update README and core.py for Blackparrot and change vivado command for systemverilog
 2020-05-12 11:41:25 +02:00
Dave Marples
dc1d452008 Addition of boot address parameter for trellis builds 2020-05-12 09:41:37 +01:00