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698 commits

Author SHA1 Message Date
Charles Papon
01db217ab9 Add supervisor support in the ExternalInterruptArrayPlugin 2019-05-06 16:23:43 +02:00
Charles Papon
d27fa4766d DBusCachedPlugin add earlyWaysHits in regressions 2019-05-06 00:05:40 +02:00
Charles Papon
d12decde80 Remove test which had issues with the testbench ref checks because of getting passed delayed 2019-05-05 22:46:46 +02:00
Charles Papon
5f18705358 Add DBusCachedPlugin.relaxedMemoryTranslationRegister option 2019-05-05 21:19:48 +02:00
Charles Papon
c738246610 Remove the legacy pipelining from Axi4 cacheless bridges 2019-05-01 12:03:01 +02:00
Sean Cross
d1e215e312 caches: work without writeBack stage 
In the case of an MMU miss, the data caches will create a retry branch port.
These currently implicitly go into the memory/writeBack stage, however
not all CPUs have this stage.

Place the retry branch port into the correct stage.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-26 18:02:43 +08:00
Sean Cross
b2f387ccac MmuPlugin: fix generation without writeBack stage 
If there is no writeBack stage, the elaboration step would hit a
NullPointerException when trying to insert into the writeBack stage.

Instead, pull from the most recent stage, which is where MMU access
should reside.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-26 18:01:35 +08:00
Charles Papon
d64589cc48 Add configs without memory/writeback stages in regressions 
Add rfReadInExecute configs in regressions
Fix ShiftPluginLight and DBusSimplePlugin for configs with rfReadInExecute stage configs
 2019-04-25 17:36:13 +02:00
Charles Papon
74e5cc49f9 Add the linux config into the synthesis bench 2019-04-24 12:32:37 +02:00
Charles Papon
a331f35724 Icestorm flow now use nextpnr 2019-04-24 12:32:24 +02:00
Charles Papon
b654d824ad remove DebugPlugin from linux.scala, and set static branch prediction 2019-04-23 21:55:54 +02:00
Charles Papon
266bdccc2e update Riscv software model lrsc implementation 2019-04-23 21:55:54 +02:00
Charles Papon
4078f84e8f Dhrystone regression now also run coremark 2019-04-23 21:55:54 +02:00
Charles Papon
c6dbaa52f6 Longer linux regression timeout for very slow configs 2019-04-21 22:16:42 +02:00
Charles Papon
14efe6ffda Riscv software model now implement interrupt priority accordingly to 496c59d064 (diff-a38d447c5232bd448697af4c6c8adb1a) changes 2019-04-21 20:01:39 +02:00
Charles Papon
d7ca153c8b remove interrupt assertion 2019-04-21 19:45:24 +02:00
Charles Papon
0e10c460c3 Update Zephyr tests, the mem_pool_threadsafe one was bugy by the past, and now it is just too long 2019-04-21 17:58:42 +02:00
Charles Papon
4cbb93cfc8 Look like zephyr mem_pool_threadsafe is a broken test 2019-04-21 17:48:08 +02:00
Dolu1990
1c86bf7514 Increase liveness trigger to allow large instruction cache flush 2019-04-21 15:25:39 +02:00
Charles Papon
963805ad48 Bring freertos back in tests 
Better travis test range
 2019-04-21 12:50:28 +02:00
Charles Papon
edde3e3011 Add zephyr tests 2019-04-21 02:56:44 +02:00
Charles Papon
3b0f2e9551 better travis timings 
travis job naming
reduce verilator cache size
Fix dcache test timeout
travis cleaning
travis wip
verilator wip
fix java 10 compilation
Travis wip
travis rework
 2019-04-20 14:56:56 +02:00
Charles Papon
b49076ecab add missing coremark patch 2019-04-19 19:41:05 +02:00
Charles Papon
728a5ff20f Fix coremark binaries (no csr) 2019-04-19 18:28:46 +02:00
Charles Papon
e47b76fa67 #60 Added automated linux regression in travis 
Fix DBusCached plugin access sharing for the MMU deadlock when exception is in the decode stage
Fix IBusSimplePlugin issues with used with non regular configs + MMU
Bring back the LinuxGen config into a light one
 2019-04-19 17:35:48 +02:00
Charles Papon
2810ff05b0 Fix emulator instruction emulation trap redirection to supervisor. 
Impact only AMO less configs
 2019-04-19 02:31:39 +02:00
Charles Papon
b79b02152b #60 Fix SFENCE_VMA deadlock 2019-04-18 18:33:06 +02:00
Dolu1990
d2b324e32b Add jtag and vhdl option 2019-04-15 11:01:51 +02:00
Charles Papon
6f04c02cd2 TestInduvidualFeatures now use the linux config + MMU 2019-04-14 23:06:04 +02:00
Charles Papon
8c7407967e Fix non RVC fetcher exception PC capture 2019-04-14 23:04:30 +02:00
Charles Papon
61d25e931e #60 Add sim error message on RVC instruction without RVC capabilities 2019-04-13 10:44:06 +02:00
Charles Papon
5d1ec604b2 Make regression sim great again 2019-04-13 10:41:15 +02:00
Charles Papon
9ac1d3d59e riscv software model without RVC now trap on RVC instruction before pcWrite + 2 2019-04-13 10:40:53 +02:00
Charles Papon
3301a1b364 Add CsrPlugin.userGen option which now remove privilegeReg when not set 2019-04-12 16:37:34 +02:00
Charles Papon
d5723968da Merge remote-tracking branch 'origin/master' into linux 
# Conflicts:
#	src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
#	src/test/cpp/regression/main.cpp
 2019-04-12 16:26:08 +02:00
Charles Papon
8421328ee1 restore freertos tests 2019-04-12 16:09:20 +02:00
Charles Papon
13b774b535 #69 Relax address calculation of decode branch predictor by adding KEEP synthesis attribut 2019-04-12 15:56:22 +02:00
Charles Papon
41ff87f83b Remove jalr from decode branch prediction missaligned inibition 2019-04-12 15:27:10 +02:00
Charles Papon
63cd5f42af Fix #69 discoverd fmax issue with decode stage branch predictions 2019-04-12 15:24:33 +02:00
Charles Papon
b329ee85ad #60 Fix missing ecallGen flag 2019-04-11 15:30:54 +02:00
Charles Papon
ece1e73547 Default linux config is now without RVC 
Remove all linux usless CSR from the config
Remove verilator instruction fetch check
 2019-04-11 01:18:15 +02:00
Charles Papon
caa37a8028 Reduce machine mode emulator CSR requirements and emulate more CSR (in the case they aren't supporter in hardware) 2019-04-10 19:04:52 +02:00
Charles Papon
6b22594961 Flush MMU line with exception on context switching instead than on cmd fire 2019-04-10 15:42:39 +02:00
Charles Papon
926b74a203 shorter coremark 2019-04-10 15:41:58 +02:00
Charles Papon
189cadfbb3 Add coremark 2019-04-10 15:41:38 +02:00
Charles Papon
d7f6c18c0a Fix DebugPlugin -> force machine mode, force uncached memory load 2019-04-10 00:35:15 +02:00
Charles Papon
9b6b65b8b4 Fix icache test when dynamic target branch prediction is enabled 2019-04-09 19:37:18 +02:00
Charles Papon
a6dc530441 Added lrsc/amo tests 2019-04-09 19:27:42 +02:00
Charles Papon
fd42e7701e Add hardware AMO, require AMO=yes in sim and withAmo=true in linux.scala 2019-04-09 01:22:32 +02:00
Charles Papon
21cb8615fd Clean and fix things to get all the non-linux configs and machine only configs working 2019-04-08 16:06:05 +02:00
Charles Papon
32921491b8 #60 Fix instruction cache refill 2019-04-08 14:24:37 +02:00
Charles Papon
fd15a938c5 #60 Fix machine mode emulator atomic emulation. Do not write regfile if the page was set as read only. 2019-04-08 13:20:56 +02:00
Charles Papon
c2595273ec Add a busy flag from MMU ports 
iBus/dBus now halt on MMU busy, which avoid looping forever on page fault
 2019-04-08 11:38:40 +02:00
Charles Papon
f89ee0d422 #60 Fix MMU holding invalid tlb, while linux is assuming it isn't doing so. 2019-04-07 15:44:25 +02:00
Tom Verbeure
4fd36454d7 Complain about wrong earlyBranch settings. 2019-04-06 12:58:19 -07:00
Tom Verbeure
39a4aa5e26 GenMicroNoCsr: no memory stage, no write-back stage 2019-04-06 12:38:54 -07:00
Charles Papon
6df3e57843 workaround Verilator comparaison linting 2019-04-06 02:00:47 +02:00
Charles Papon
21b4ae8f2f update todo, nothing todo ? everything done ? 2019-04-06 01:42:01 +02:00
Charles Papon
e7f3dd5553 Rework CsrPlugin exception delegation 2019-04-05 23:40:39 +02:00
Charles Papon
ddf0f06834 Add more delegation tests 
Reduce dcache test duration
 2019-04-05 22:56:12 +02:00
Charles Papon
acaa931e11 Rework CsrPlugin interrupt delegation 2019-04-05 22:55:42 +02:00
Charles Papon
9e72971ff0 Move user mode page fault checkes from iBus/dBus plugin into the MmuPlugin 
SUM was in fact already supported
 2019-04-05 21:34:44 +02:00
Charles Papon
82c894932a update todolist 2019-04-05 20:04:28 +02:00
Charles Papon
aeb418a99e Add dcache tests 2019-04-05 20:03:22 +02:00
Charles Papon
5a6665e57f Fix DataCache flush on the last line 2019-04-05 20:02:57 +02:00
Charles Papon
8459d423b8 add icache flush test 2019-04-05 18:11:33 +02:00
Charles Papon
60a41bfc75 rework i$ flush 2019-04-05 18:11:10 +02:00
Charles Papon
f5d4e745c7 Look like precise fence.i isn't required in practice 2019-04-05 18:08:25 +02:00
Charles Papon
446e9625af Centralised all todo in linux.scala 
Sorted out fence fence.i instruction in iBus/dBus plugins.
Fixed MMU permitions while in used mode and bypassing the MMU
 2019-04-05 12:17:29 +02:00
Charles Papon
888e1c0b8a Fix RVC instruction cache xtval allignement 2019-04-05 01:08:57 +02:00
Charles Papon
8e6010fd71 Got the debug plugin working with the linux config (had to disable CSR ebreak) 2019-04-05 00:25:27 +02:00
Charles Papon
4f0a02594c Change LR/SC to reserve the whole memory 
Fix MPP access from other plugins
Got all the common configuration to compile and pass regression excepted the debugger one
First synthesis results
 2019-04-04 20:34:35 +02:00
Charles Papon
f8b438d9dc cleaning 2019-04-04 12:59:08 +02:00
Charles Papon
de1c9c6fea Removing D$ reports 2019-04-03 14:47:00 +02:00
Charles Papon
3f7a859e07 Got multiway I$ D$ running linux fine. 2019-04-03 14:33:35 +02:00
Charles Papon
922c18ee49 Add data cache flush feature 2019-04-03 15:56:58 +02:00
Charles Papon
066f562c5e Got the MMU refilling itself with datacache cached memory access instead of io accesses 2019-04-03 14:32:21 +02:00
Charles Papon
8be40e637b #60 Got the new data cache design passing all tests and running linux 2019-04-02 23:44:53 +02:00
Charles Papon
fd4da77084 #60 Got the new instruction cache design passing the standard regressions 2019-04-02 00:26:53 +02:00
Charles Papon
bc0af02c97 #60 Got instruction cache running linux :D 2019-04-01 11:59:04 +02:00
Charles Papon
1dff9aff8a #60 Fix interrupt causing fetch privilege issues 2019-04-01 10:47:54 +02:00
Charles Papon
e74a5a71eb Better simulation console integration 2019-04-01 10:31:55 +02:00
Charles Papon
369a3d0f5f #60 Sync everything, added much comment on the top of Linux.scala to help reproduce 2019-03-31 23:43:56 +02:00
Charles Papon
c7314cc606 Got buildroot login, userspace, commands working 
Moved location of DTB, initrd. Will move again
Added getChar SBI in emulator
Added an QEMU mode in the emulator config.h, work with qemu riscv32 virt
 2019-03-31 15:17:45 +02:00
Dolu1990
de500ad8f9 Add qemu command 2019-03-30 18:29:17 +01:00
Dolu1990
9383445e0b Add a qemu option (wip) 2019-03-30 18:26:44 +01:00
Charles Papon
1a36f2689d #60 Fix software model. Forgot physical address for on RVC instruction 2019-03-30 11:24:29 +01:00
Charles Papon
29980016f3 #60 Fix instruction fetch exception PC by forcing LSB to be zero 2019-03-30 10:10:25 +01:00
Dolu1990
9fff419346 Better fix 2019-03-29 09:18:44 +01:00
Dolu1990
391cff69d3 #60 should fix the first instruction fetch privilege after interrupt 2019-03-29 09:02:44 +01:00
Dolu1990
0c48729611 Sync impact less changes (asfar i know) 2019-03-29 08:43:15 +01:00
Dolu1990
ad27007c3c DBusSimplePlugin AHB bridge add hazard checking, pass tests 2019-03-28 11:41:49 +01:00
Dolu1990
53c05c31c7 IBusSimplePlugin AHB bridge fix, pass tests 2019-03-28 10:12:42 +01:00
Dolu1990
b0522cb491 Add AhbLite3 simulation config 2019-03-28 08:32:12 +01:00
Dolu1990
9ac4998478 Fix emulator nested exception redirection privilege 2019-03-28 00:38:38 +01:00
Dolu1990
ac06111163 Fix MMU MPRV, Fix emulator nested exception 2019-03-27 22:58:30 +01:00
Dolu1990
0bed511a6c Fix cacheless LR/SC xtval, did some SRC/ADD_SUB/ALU redesign 2019-03-27 18:58:02 +01:00
Dolu1990
43c3922a3d Add prerequired stuff 2019-03-27 10:55:20 +01:00
Dolu1990
f113946e66 Added a neutral LINUX_SOC for sim purposes 2019-03-27 10:53:41 +01:00
Dolu1990
b69c474fa2 #60 user space reached 
/sbin/init: error while loading shared libraries: libm.so.6: cannot stat shared object: Error 38
 2019-03-27 00:26:51 +01:00
Dolu1990
7a9f7c4fb9 Untested cacheless buses to AHB bridges 2019-03-26 16:30:53 +01:00
Dolu1990
94fc2c3ecf Fix some models missmatch 
Add more SBI
Add hardware LR/SC support in dbus cacheless
 2019-03-26 01:25:18 +01:00
Dolu1990
1c3fd5c38b Fix mprv and add it into the softare model 2019-03-25 12:03:32 +01:00
Dolu1990
1ec11dc03d Fix mprv 2019-03-25 11:47:56 +01:00
Dolu1990
c34f5413a3 Add MMU MPRIV for easier machinemode emulation #60 2019-03-25 10:30:13 +01:00
Dolu1990
9d55283b3b Machine mode emulator 2019-03-25 02:00:19 +01:00
Dolu1990
e28702eb40 Add PlicCost test 2019-03-24 12:17:39 +01:00
Dolu1990
6c0608f0dd #60 
Add LitexSoC workspace / linux loading.
Need to emulate peripherals and adapte the kernel now.
Probably also need some machine mode emulation
Software time !
 2019-03-24 10:52:56 +01:00
Tom Verbeure
ea62fd0e16 Same thing for DBusSimpleBus. 2019-03-23 23:36:13 +00:00
Tom Verbeure
95c3e436dc Make toPipelinedMemoryBus() just like the other busses 2019-03-23 22:32:48 +00:00
Dolu1990
0656a49332 Make xtval more compliant 2019-03-23 20:12:36 +01:00
Dolu1990
7159237104 Fix csrrs/csrrc for xip registers 2019-03-23 18:11:26 +01:00
Dolu1990
505bff6f45 CSR Plugin now implement interruptions as specified in the spec 2019-03-23 12:56:04 +01:00
Dolu1990
3652ede130 Add mdeleg tests 2019-03-23 11:41:10 +01:00
Dolu1990
9139b4d269 Restore all tests 2019-03-22 18:03:35 +01:00
Dolu1990
597336b491 MMU sum/mxr tested and ok, all seem finen 2019-03-22 17:11:55 +01:00
Dolu1990
f7b793b7bf Add SSTATUS.SUM/MXR feature, need testing 2019-03-22 15:49:36 +01:00
Dolu1990
e4cdc2397a MMU pass all test, need to and SUM and MXR and it's all ok 2019-03-22 14:52:49 +01:00
Dolu1990
2b458fc642 Added MMU superpage support, pass MMU tests 2019-03-22 12:23:47 +01:00
Dolu1990
af2acbd46e Got the new MMU design to pass simple tests #60 2019-03-22 01:10:17 +01:00
Dolu1990
ea56481ead Add supervisor CSR in the riscv golden model 2019-03-20 23:26:08 +01:00
Dolu1990
7cbe399f1f Fix some supervisor CSR access 2019-03-20 23:25:52 +01:00
Dolu1990
6f2e5a0eb7 goldenmodel Implement some of the supervisor CSR 2019-03-20 20:28:04 +01:00
Dolu1990
39b2803914 Fix some CsrPlugin flags issues 2019-03-20 20:27:47 +01:00
Dolu1990
6c2fe934fd Bring changes and fixies from @kgugala @daveshah1. Thanks guys ! 2019-03-20 16:27:35 +01:00
Dolu1990
130a69eeae Pass regressions machinemode with CSR config including Supervisor 2019-03-20 14:14:59 +01:00
Dolu1990
d205f88fb8 riscv golden model and RTL pass all current regressions 
add RVC into the linux config
 2019-03-20 12:17:43 +01:00
Dolu1990
3c66f7c58a goldenmodel now pass more machine mode CSR tests 2019-03-20 11:46:27 +01:00
Dolu1990
ee402ec5dc clearning 2019-03-20 01:16:39 +01:00
Dolu1990
3a38fe4130 Add mmu regresion blank project 2019-03-20 01:13:05 +01:00
Dolu1990
ccc3b63d7c Enable golden model check for all regressions 
Need to implement missing CSR of the golden model
 2019-03-20 01:12:03 +01:00
Dolu1990
8f22365959 Disable MMU in machine mode 2019-03-19 22:21:30 +01:00
Dolu1990
3fbc2f4458 Fix generation 2019-03-19 20:29:28 +01:00
Dolu1990
915db9d6c9 cleaning 2019-03-18 20:50:19 +01:00
Dolu1990
001ca45c57 Add cachless dBus IBus access right checks 2019-03-18 12:52:22 +01:00
Dolu1990
c490838202 Added MMU support into cacheless DBus IBus plugins (for testing purposes) 
Probably full of bugs, need testing
 2019-03-18 12:17:43 +01:00
Dolu1990
ffa489d211 hardware refilled MmuPlugin wip 2019-03-17 21:06:47 +01:00
Tom Verbeure
b63395435f SimpleMul core. 2019-03-16 15:44:18 +00:00
Tom Verbeure
5bc53c08ce Merge branch 'master' of https://github.com/SpinalHDL/VexRiscv into MulSimple 2019-03-16 15:39:07 +00:00
Dolu1990
9a61ff8347 Merge remote-tracking branch 'origin/dev' 2019-03-10 11:14:09 +01:00
Dolu1990
bad60f39cd Fix Decoding benchmark 2019-03-10 11:12:32 +01:00
Dolu1990
434793711b fix part of #59 2019-02-26 17:26:42 +01:00
Dolu1990
e0c8ac01d2 Add custom external interrupts 2019-02-03 15:20:34 +01:00
Dolu1990
11f55359c6 IBusCache can now avoid injectorStage in singleStage mode 2019-01-30 01:37:47 +01:00
Dolu1990
56e3321394 cpp regresion now print the time of failure 2019-01-30 01:36:24 +01:00
Dolu1990
f4598fbd0a Add tightly coupled interface to the i$ 2019-01-21 23:46:18 +01:00
Dolu1990
b5caca54cd restore all feature in TestsWorkspace 2019-01-16 15:25:50 +01:00
Dolu1990
927ab6d127 Merge remote-tracking branch 'origin/master' into dev 2018-12-30 15:53:25 +01:00
Dolu1990
dd42e30c61 Merge remote-tracking branch 'origin/master' into dev 2018-12-29 14:04:07 +01:00
Dolu1990
d617bafb08 Roll back VexRiscvAvalonForSim to use caches 2018-12-25 00:15:23 +01:00
Brett Foster
961abb3cf1 Avalon: Debug Clock Domain for JTAG 
This change ensures that the clock domain for the JTAG interface
uses the debug plugin's domain. Otherwise, resetting the processor
will put the jtag debugger in to reset as well.

See SpinalHDL/VexRiscv#48
 2018-12-22 07:58:59 -08:00
Dolu1990
76ebfb2243 Fix machine mode to supervisor delegation 2018-12-10 13:15:03 +01:00
Dolu1990
d9029c2efc Fix #46 by filling missing return statements 2018-12-10 01:44:47 +01:00
Dolu1990
281d61bbe1 regression fix hex << dec #46 2018-12-09 16:37:16 +01:00
Dolu1990
1fbb81a4d9 regression fix delete [] #46 2018-12-09 15:40:02 +01:00
Dolu1990
f121ce1ed5 add sanity asserts in regression #46 2018-12-08 14:10:18 +01:00
Dolu1990
9330945623 fix regression makefile 2018-12-07 23:50:13 +01:00
Dolu1990
52419fd7ad Regression remove dplus stuff #46 2018-12-07 23:47:49 +01:00
Dolu1990
68fdbe60cc verilator regression fix missing fclose #46 2018-12-07 23:43:19 +01:00
Dolu1990
eca54585b0 Fix hardware breakpoint 2018-12-04 16:57:24 +01:00
Dolu1990
ac1ed40b80 Move things into SpinalHDL lib 2018-12-01 18:25:18 +01:00
Dolu1990
3d71045159 DebugPlugin doesn't require memory/writeback stage anymore 2018-12-01 18:24:33 +01:00
Dolu1990
58d7a4784d move HexTools into SpinalHDL lib 2018-11-30 17:39:33 +01:00
Dolu1990
b1b7da4f10 Rename SimpleBus into PipelinedMemoryBus 
Move PipelinedMemoryBus into SpinalHDL lib
 2018-11-30 17:37:17 +01:00
Dolu1990
2f6a2dfccc Add configs setup in SimpleBusInterconnect 2018-11-29 16:14:45 +01:00
Dolu1990
7075e08d9f Hazarplugin tell to branch plugin if the RS are hazardous in the execute stage 2018-11-24 13:38:54 +01:00
Dolu1990
c2b9544794 Allow iBusCached plugin to be used when no memory stage is present 2018-11-24 13:37:53 +01:00
Dolu1990
0086de9e36 Fix CsrPlugin catch illegalAccess 
Add dhrystone optimized divider
cleaning
 2018-11-20 19:39:17 +01:00
Dolu1990
75d4d049d7 Add shadow regfile 
various cleaning
 2018-11-16 17:06:11 +01:00
Dolu1990
cc48fc7403 add fenceiGenAsANop 2018-11-13 15:17:35 +01:00
Dolu1990
0d92a5e5cd Add many little options to reduce area 2018-11-12 14:14:34 +01:00
Dolu1990
fb9ea11a5e Allow VexRiscv to suppress the memory and the writeback stage, allowing to go downto a 2 stage CPU (FETCH_DECODE, EXECUTE) 2018-11-09 05:41:43 +01:00
Dolu1990
b12e15b112 branch/csr/muldiv minor improvments 2018-11-07 19:27:49 +01:00
Dolu1990
b7f3ee5e06 Fix CsrPlugin pipelined option 2018-11-05 16:22:41 +01:00
Dolu1990
662d76e3aa csrPlugin : avoid using ALU to get SRC1 (which was useless) 2018-11-03 11:29:30 +01:00
Dolu1990
978232fd63 Optimise div iterative plugin done signal 2018-11-03 11:12:37 +01:00
Dolu1990
c8ac214097 Optimize CSR 2018-10-28 02:18:27 +02:00
Dolu1990
51de2b5820 SimpleBusInterconnect now adapte address width 2018-10-28 02:18:08 +02:00
Dolu1990
00bf84b7f8 Add SimpleBusInterconnect 2018-10-25 23:47:05 +02:00
Dolu1990
4ed4af6a3e SrcPlugin add decodeAddSub option 2018-10-24 01:28:37 +02:00
Dolu1990
372063582c Improve CsrPlugin CombinatorialPaths 2018-10-23 19:07:08 +02:00
Dolu1990
7096c63d50 Add more SimpleBus utilies 2018-10-23 17:46:31 +02:00
Dolu1990
7c0f2dc713 Add SimpleBus object 2018-10-20 12:39:30 +02:00
Morard Dany
85e696b286 CsrPlugin : Add mtvecModeGen 2018-10-16 14:53:41 +02:00
Dolu1990
905abd5aaa Add wfiGenAsWait and wfiGenAsNop 
CsrPlugin cleaning
Much cleaning in general
Zephyr is running
 2018-10-16 13:07:30 +02:00
Dolu1990
f903df4b66 sync 2018-10-12 17:13:54 +02:00
Dolu1990
2b29690010 Clean branch plugin lsb bit calculation 
BranchPlugin doesn't try anymore to catch exception when RVC is on
 2018-10-12 12:24:52 +02:00
Dolu1990
eea92154ae fetcher force PC LSB to be zero 2018-10-12 12:02:52 +02:00
Dolu1990
0b8f6f6ed4 Fix broken C.LWSP reference_output 2018-10-12 12:02:02 +02:00
Dolu1990
594f7a8bf2 Seem to pass all risc-v compliance tests, excepted the C.LWSP which is a broken test 2018-10-11 22:19:17 +02:00
Dolu1990
8c25e73b9d Fix DIV negative values divided by zero 2018-10-11 22:18:21 +02:00
Dolu1990
c26b7e15cf BranchPlugin exceptions are now risc-v compliance alligned 2018-10-11 17:56:49 +02:00
Dolu1990
8b1a4a2717 Add RISCV compliance regression test, need to fix I-MISALIGN_JMP-01 mtval 2018-10-11 00:25:39 +02:00
Dolu1990
40d85b8c70 Add fenceiGenAsAJump into BranchPlugin 2018-10-10 21:13:21 +02:00
Dolu1990
68f1ff3222 Add CsrPlugin ebreak support 2018-10-10 19:23:04 +02:00
Dolu1990
0662cc2797 Add GenMicro experiment to reduce ice40 area usage. 
IBusSimplePlugin now require cmdFork parameters to be set (no default)
 2018-10-03 22:08:57 +02:00
Dolu1990
48bff80653 rework fetchPc to optionaly share the pcReg with the stage(1) 
IBusSimplePlugin now implement cmdForkPersistence option
 2018-10-03 16:24:10 +02:00
Dolu1990
c61f17aea3 Fetcher/IBusSimplePlugin wip 2018-10-03 01:02:22 +02:00
Dolu1990
0ada869b2d regression golden ref regfile is now sync with trl boot's random values 
wip
 2018-10-01 16:14:21 +02:00
Dolu1990
65a8d84d30 Introduce HAS_SIDE_EFFECT Stageable to solve sensitive instruction squeduling 
(uncached DBus TODO)
 2018-10-01 12:13:05 +02:00