31d718749a
Add copyrights
2023-02-15 12:37:33 +01:00
70f2fd6368
Fix format
2023-02-15 12:37:33 +01:00
0c774a906d
Add clk12 to platform
2023-02-15 12:37:33 +01:00
01abbc0d50
Replace deprecated register_mem with add_slave
2023-02-15 12:37:33 +01:00
934e031dca
Fix imports
2023-02-15 12:37:33 +01:00
223a69cf91
Add platform and target files for Antmicro's sdi mipi video converter board
...
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
2023-02-15 12:37:33 +01:00
ec7a5c4c0b
Correct DDR4 IO Banks of Xilinx Alveo U200
2023-02-14 06:40:12 +07:00
fdffeb8474
radiona_ulx4m_ld_v2: Do a first review/cleanup path.
2023-02-13 16:11:32 +01:00
8c9ea15d0a
Update radiona_ulx4m_ld_v2.py
2023-02-13 12:08:38 +01:00
404fefaab1
changing filename to radiona
2023-02-13 12:06:04 +01:00
99db2ae60d
Delete ulx4m_ld_v2.py
2023-02-13 11:48:51 +01:00
57c9cff39e
Update radiona_ulx4m_ld_v2.py
2023-02-13 11:45:48 +01:00
9320ae8b74
Fixing platform file
2023-02-13 11:44:59 +01:00
f7822b7dc7
Adding target to files
2023-02-13 11:40:43 +01:00
a3815efccb
Adding radiona ULX4M-LD-V2
2023-02-11 16:57:34 +01:00
a354f04143
avoid undefined clocks by moving the derive*-statements to start of the additional constraints list
2023-02-09 15:58:41 +01:00
b8abdf1b39
targets/digilent_arty: Add arguments for XDAC and DNA.
...
Avoid specific checks for Vivado toolchain (Now handled by user for f4pga toolchain)
and fix linux-on-litex-vexriscv build.
2023-01-23 08:55:10 +01:00
b9874685a5
gadgetfactory_papilio_pro: Cosmetic cleanups.
2023-01-17 15:43:12 +01:00
ec4d203eb6
Merge pull request #471 from Acathla-fr/papilio
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Target/Platform Papilio Pro added (with Arcade MegaWing)
2023-01-17 11:21:27 +01:00
801008f5ad
Merge pull request #469 from hansfbaier/hpcstore-rename
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HPC FPGA Store on AliExpress renamed itself to SITLINV
2023-01-17 11:20:19 +01:00
3b36e576ba
Add support for Xilinx Alveo U200
2023-01-17 06:44:21 +07:00
05ef1ee09e
Target/Platform Papilio Pro added (with Arcade MegaWing)
2023-01-16 13:41:24 +01:00
55fcb4cd47
xilinx_alveo_u2x0: Improve indentation on DRAMs.
2023-01-16 09:34:59 +01:00
be77f82720
platforms/xilinx_alveo_u250: Fix dram numbering.
2023-01-16 09:31:23 +01:00
e02f64a7db
platforms/gsd_butterstick: Fix copyright.
2023-01-16 08:41:10 +01:00
59a897e2dd
gsd_butterstick: Add missing pin defs
2023-01-16 17:32:39 +10:30
c0773ed9b9
HPC FPGA Store on AliExpress renamed itself to SITLINV
2023-01-16 11:31:35 +07:00
36a4100c8b
ocp_timecard: Add DDR3 SDRAM support.
2023-01-13 12:41:34 +01:00
3ca298ba42
ocp_tap_timecard: Add TODO on SMAs.
2023-01-13 11:51:09 +01:00
c753bf7fc1
ocp_tap_timecard: Fix GTPE2 location.
2023-01-13 11:47:52 +01:00
8b0d4787c7
ocp_tap_timecard: Fix CI.
2023-01-13 10:55:07 +01:00
1e35d78512
ocp_tap_timecard: Add initial SMAIOs peripherals to allow using SMA over PCIe DMA or also with direct (and slow) control/visualization with CSR registers.
2023-01-13 10:08:44 +01:00
fc7154a632
ocp_tap_timecard: Add Leds/I2C/PMOD/GPS/SMAs IOs.
2023-01-13 09:14:05 +01:00
a0fd3e7536
Add initial OCP-TAP TimeCard support with PCIe/SPIFlash/Leds/Buttons/DNA/XADC (Compiles but untested).
2023-01-12 18:50:23 +01:00
7a911b8ff6
Allow building digilent_arty using f4pga
...
Only use XADC() and DNA() functions if vivado is the current toolchain.
2023-01-06 16:09:56 -06:00
764f64ff1e
nx_vip: Add missing 'origin' to SRAM SocRegions
...
Signed-off-by: gatecat <gatecat@ds0.me>
2023-01-04 12:02:11 +01:00
f5643e7c78
machdyne: Fix LiteDRAM PHYs imports (QuarterRateGENSDRPHY not already working?/integrated).
2023-01-01 21:35:51 +01:00
563ccbd8cf
Merge pull request #464 from machdyne/master
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initial support for machdyne konfekt and noir
2023-01-01 16:12:51 +01:00
5de6865cbe
Merge pull request #463 from stone3311/master
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terasic_deca: add SPI SD card support
2023-01-01 16:10:30 +01:00
fec82c59e2
remove konfekt ethernet option
2022-12-30 17:36:52 +01:00
f0dc9a6874
initial support for machdyne konfekt and noir
2022-12-30 17:00:35 +01:00
6cfb56bb07
terasic_deca: add SPI SD card support
2022-12-28 02:13:06 +01:00
57845d1ca4
Correct pinout and IOStandard
...
Correct connector pinout
Correct pinout for ETH
LED IOStandard set to LVCMOS33
BTN[0] IOStandard set to LVCMOS33
Changes are made based on Tang_primer_20K_3690 and Tang_Primer_20K-Dock_3709 schemes.
2022-12-22 18:30:36 +03:00
4e06e5ff9c
targets/xilinx_zybo_z7: adding missing variant parameter to the platform
2022-12-14 07:47:09 +01:00
a92fdffb35
platforms/digilent_zybo_z7: reorder _io_x & _connectors_x, init cleanup
2022-12-12 22:17:39 +01:00
d28894a4b3
Reintroduce original Zybo + HDMI addition ( #461 )
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* Reintroduce original Zybo support
* Reintroduce original zybo, add HDMI + fixes for Z7
2022-12-12 22:05:47 +01:00
12db52471d
targets/jungle_electronics_fireant: Update SPIFlash (Make it similar to other boards with BIOS in SPIFlash).
2022-12-08 08:37:13 +01:00
c05ce32c8a
Merge pull request #458 from trabucayre/arty_s7_tcl_config
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Arty z7 tcl config
2022-12-08 08:31:22 +01:00
71f1e1976b
Merge pull request #459 from tcal-x/icebitsy-ledchaser
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Add LedChaser to iCEBreaker-bitsy.
2022-12-06 09:05:37 +01:00
25c40ddda7
add gpio to board
2022-12-05 21:38:56 -03:00
6e205be83b
Add LedChaser to iCEBreaker-bitsy.
...
Signed-off-by: Tim Callahan <tcal@google.com>
2022-12-04 17:58:20 -08:00
a889321535
targets/digilent_arty_z7: adding note to load gateware and bios
2022-12-03 16:54:52 +01:00
e71e3ab3ec
platforms,targets/digilent_arty_z7: use a dict for PS config instead of fetching file configuration
2022-12-03 16:54:39 +01:00
d0d90e9eef
Merge branch 'litex-hub:master' into master
2022-11-29 15:25:41 -03:00
b030630237
Merge pull request #453 from cklarhorst/zybo
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Zybo: Fix for Zynq7000 and use ps7 as submodule for Soft-CPUs
2022-11-25 21:48:43 +01:00
53b6bf035a
fixed parser
2022-11-24 16:03:12 +01:00
926ed21f0b
fixed review remarks; added zynq7000 as a submodule for using the ps as a slave
2022-11-23 17:20:25 +01:00
570ea11744
fix(plataform.basys_3): V_sync is pin R19
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Based in https://github.com/Digilent/digilent-xdc/blob/master/Basys-3-Master.xdc#LL129C34-L129C37
2022-11-23 09:16:50 -03:00
c489347a51
fixed zynq7000 integration; introduced option to add the processing-system as slave to the SoC
2022-11-18 11:19:57 +01:00
6f7716adbb
added config for ps7; introduced different variants for the zybo-board; fixed pins
2022-11-18 11:15:54 +01:00
892bf3546d
isx_im1283: connect CRG reset to PLL
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This fixes soft reset.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-16 15:12:18 +08:00
e27d8c958e
isx_im1283: add jtagbone support
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Add necessary script snippets for enabling jtagbone in the command line.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-15 21:07:10 +08:00
ae47172d2a
targets/decklink_mini_4k: Update clock constraints.
2022-11-14 10:21:42 +01:00
6e10df234f
platforms/decklink_mini_4k: Fix data2_n pin (Thanks @rdolbeau).
2022-11-14 10:21:37 +01:00
e9d7013d70
sitlinv_stlv7325: add jtagbone support
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Add necessary script snippets for enabling jtagbone in the command line.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-13 17:28:04 +08:00
c2c59f5e8c
sitlinv_stlv7325: allow to set local/remote ip
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Port the script snippet from Colorlight i5 for setting the local/remote
IP address to STLV7325.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-13 17:27:58 +08:00
3d8106f84d
stlv7325: fix Ethernet IO voltages
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The IO voltages of Ethernet pins is set to 2.5V instead of 1.5V.
Fix this in the platform definition.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-13 17:27:23 +08:00
27c3afb8fb
sitlinv_stlv7325: allow dynamic Ethernet IP
...
Currently the sitlinv_stlv7325 target script parses the option that
selects dynamic Ethernet IP; however it's not really passed to LiteETH.
Really pass this option and add an assert that does not allow dynamic
Etherbone IP like other boards.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-13 17:27:23 +08:00
4ba5793822
sitlinv_stlv7325: remove unexistent COL/CRS pins
...
The COL and CRS pins of the Ethernet PHY is not connected on the board
at all, but assigned dummy positions in the platform definition, which
leads to Vivado warning when building.
Remove these pins from the platform definition.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-13 17:27:23 +08:00
1c07fa94ca
sitlinv_stlv7325: fix ident string vendor name
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As we changed the vendor name to proper Sitlinv in the file name, the
ident string is left untouched.
Fix this too.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-13 17:27:23 +08:00
58489ebebf
targets/BaseSoC: Cleanup parameters.
2022-11-08 12:31:49 +01:00
a8c92cd86f
targets/simple: Switch back to old version for now.
2022-11-08 11:55:06 +01:00
9e7079c4c8
targets: Remove int() on BaseSoC's sys_clk_freq.
2022-11-08 11:54:17 +01:00
b0e6414519
targets: Cleanup arguments and switch --sys-clk-freq to float (avoid conversion in code).
2022-11-08 10:41:35 +01:00
16b9677acd
targets: Switch to soc_core_argdict.
...
The next move was to remove soc_core and only keep soc; so this is probably the right time to do
it in targets to avoid having to handle it later.
2022-11-07 08:43:26 +01:00
f1e24046fd
xilinx_alveo_u250: Fix.
2022-11-06 22:17:28 +01:00
6edfb2ca7a
Merge pull request #448 from trabucayre/fix_alinx_axu2cga_platform
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platforms/alinx_axu2cga: adding missing psu_config at platform level
2022-11-06 22:11:25 +01:00
9a2028a9ba
targets: Remove useless argparse imports.
2022-11-06 22:09:21 +01:00
30723b1bb0
targets: Update targets that were still using argparse.ArgumentParser.
2022-11-06 22:07:17 +01:00
24cd983b8c
platforms/alinx_axu2cga: adding missing psu_config at platform level
2022-11-06 21:52:00 +01:00
33b0400aed
targets: Update LiteXArgumentParser imports.
2022-11-06 21:39:52 +01:00
9960f38d95
targets: replace LiteXSoCArgumentParser by LiteXArgumentParser, remove tasks done LiteXArgumentParser
2022-11-06 11:27:47 +01:00
d7184fb043
stlv7325, a_e115fb: use the proper vendor name Sitlinv
...
The boards are in fact from a vendor called 成都赛特凌威科技有限公司,
and their English registered trademark (used on the banner of their
Taobao store) is Sitlinv, which sounds like 赛特凌威.
Use this vendor name instead of where it's bought.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-10-30 10:51:13 +08:00
4dc8f7223c
Merge pull request #443 from trabucayre/arty_z7_bios
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targets/digilent_arty_z7: adding software support
2022-10-28 10:42:35 +02:00
3e809c3a1e
targets: Fix some LiteXModule imports.
2022-10-28 10:35:57 +02:00
ab3ed624cc
fpgawars_alhambra2: +x.
2022-10-28 10:31:49 +02:00
5f1b80fac4
targets/digilent_arty_z7: adding software support
2022-10-27 21:47:32 +02:00
548a028730
targets: Switch to LiteXModule to simplify/cleanup code.
2022-10-27 21:21:37 +02:00
6c05ddae1b
Merge pull request #438 from shawnanastasio/nexys4_part_name
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platforms/nexys4*: Update part name
2022-10-27 12:11:07 +02:00
f9d3a39001
chore fix target, args processing
2022-10-26 20:45:53 +02:00
189ee3de39
fix target
2022-10-26 20:36:18 +02:00
54af30a4be
fix: arg cpu-variant
2022-10-26 20:23:14 +02:00
32be05cfb1
chore default CPU variant
2022-10-25 21:14:25 +02:00
125569b2cb
add FPGAWars Alhambra II
2022-10-25 21:12:02 +02:00
bd2f1c2553
targets/isx_im1283: Fix CI.
2022-10-22 16:23:50 +02:00
8e35f15c22
Merge pull request #437 from trabucayre/fix_redpitaya_mem_region
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targets/redpitaya: fix csr & reset region
2022-10-22 16:00:22 +02:00
474dcb5fb3
Merge pull request #436 from Icenowy/isx-im1283
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Add ISX iM1283 board
2022-10-22 15:56:43 +02:00
d4b2461b5a
platforms/nexys4*: Update part name
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Symbiflow/f4pga don't recognize the part name xc7a100t-CSG324-1, so
change it to xc7a100tcsg324-1 which works with both f4pga and Vivado.
2022-10-21 14:15:27 -05:00
5a8d846a86
targets: Remove add_csr calls (no longer required).
2022-10-21 08:42:24 +02:00
377cda05a3
ti60_f225_dev_kit: Switch 1.2V banks to 1.8V to fix compilation issues with latest Efinity.
...
Will need to be investigated more.
2022-10-20 18:21:52 +02:00
4a5d5318d7
targets/redpitaya: fix csr & reset region
2022-10-20 16:35:57 +02:00
745ebbbfa1
Add ISX iM1283 board
...
ISX iM1283 is a "simple eDP signal generator" which utilizes a XC7A100T
FPGA, and come with a header populated with the FPGA's JTAG.
This commit adds initial reverse engineered IOs including the DDR3 DRAM
(which cannot work reliably @ DDR3-800, so the system clock is defaultly
set to 80MHz now), two LEDs and SD slot.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-10-14 22:50:43 +08:00
cb65099399
Merge pull request #435 from trabucayre/fix_artyz7_build
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targets/digilent_arty_z7: add flash region
2022-10-14 15:49:52 +02:00
23c6acd013
platforms/ti60_f225_dev_kit: Fix IO voltage conflicts between peripherals/banks.
...
Was already reported as a warning on 2021.1.165.2.19 but now an error with 2022.1.226.
Note: To get the build working with 2022.1.226 the following change had to be done to
pt/bin/writer/pinout.py, line 2254:
- table.add_rows(table_rows)
+ for table_row in table_rows:
+ table.add_row(table_row)
This would need to be investigated more to know if related to our local setup/machine.
2022-10-14 10:22:54 +02:00
e44e63f65d
targets/digilent_arty_z7: add flash region
2022-10-13 19:48:41 +02:00
3b339ba9a3
platforms/xilinx_kc705: Fix flash proxy name.
2022-10-13 08:48:33 +02:00
99888c52ce
xilinx_kc705/i2c: Add pullups.
2022-10-11 17:26:06 +02:00
3ec18c3583
Add qmtech Cyclone IV Starter Kit
2022-10-09 16:34:44 +02:00
e6762e228c
targets/mnt_rkx7: Make USB-Host optional and disable by default (for CI).
2022-10-04 09:45:51 +02:00
d0dd009329
targets/mnt_rkx7: Integrate specific eDP video timings in target (Avoid LiteX patch).
2022-10-04 09:29:59 +02:00
c38b8b1d8c
MNT RKX7: update platform and target for D-2 release
2022-10-03 20:09:48 +02:00
cf416d0d66
stlv7325: Adjust DDR3 pins to match reference design
2022-10-01 11:15:47 +02:00
85ba931a3d
targets/litex_acorn_baseboard: fix pn_swap
2022-09-28 21:17:16 +02:00
57eb907210
aliexpress_stlv7325: Fix missing parameter for PULLUP attribute
2022-09-25 23:13:44 +02:00
8c3a5c0608
sipeed_tang_nano_9k: Fix HDMI IOs constraints.
2022-09-23 11:18:30 +02:00
9cd1c1cbd5
targets/digilent_arty: Switch with_buttons to False by default (To fix #426 ).
2022-09-23 10:07:17 +02:00
9dbee62eac
add option to use ecpprog for crosslink-nx eval board
2022-09-15 12:27:08 -07:00
3cef11e04d
platforms/newae_cw305: Add sma_clk_in/out, buttons, switches and expansion header connector.
2022-09-13 14:26:52 +02:00
f1899954e9
Add initial NewAE CW305 board support.
2022-09-13 12:38:30 +02:00
25c28d2c03
fixed issue with default programmer option
2022-09-10 18:16:04 +01:00
6768be7f66
changed use example comment
2022-09-10 17:56:02 +01:00
e8504191e3
cleanup
2022-09-10 17:54:43 +01:00
6d0a4c788e
Added DFU support to Butterstick
2022-09-10 17:45:57 +01:00
756e4f73fc
sipeed_tang_primer_20k: Cleanup CRG.
2022-09-08 17:27:41 +02:00
fadc5619f1
sipeed_tang_primer_20k/ddr3: Add litescope debug.
2022-09-07 17:46:46 +02:00
6c7157f799
sipeed_tang_primer_20k: Disable L2 cache to ease debug and add WIP status.
2022-09-07 17:07:07 +02:00
d39d87b701
sipeed_tang_primer_20k: Switch to PHYPadsReducer and enable the 2 modules.
2022-09-07 12:06:22 +02:00
1663ded641
sipeed_tang_primer_20k: Add initial DDR3 integration (WIP).
2022-09-07 11:53:24 +02:00
c9b8579ea3
sipeed_tang_primer_20k: Drive hdmi hdp to 1.
2022-09-07 11:22:02 +02:00
abd20f560b
sipeed_tang_primer: Minor cleanups (Rename standard dock to standard, reduce margin on hdmi5x).
2022-09-07 10:56:17 +02:00
1d92443604
targets/sipeed_tang_nano_9k: replace VideoHDMIPHY by VideoGowinHDMIPHY
2022-09-06 20:22:32 +02:00
4d72c75f49
platforms/sipeed_tang_primer_20k: use replace _connectors.extend by add_connector
2022-09-06 20:19:37 +02:00
0f242629ab
targets/sipeed_tang_nano_4k: replacing VideoHDMIPHY by VideoGowinHDMIPHY and adding with-video-terminal arg
2022-09-06 19:08:01 +02:00
ce5977bc1a
targets/sipeed_tang_primer_20k: fix CLKDIV (disable reset and calibration)
2022-08-31 13:32:23 +02:00
74d4a72494
radiona/ulx3s: Rename user_button to user_btn (consistency with other boards) and fix ident.
2022-08-26 22:25:54 +02:00
693cce73bd
Merge pull request #417 from Igor542/master
...
radiona_ulx3s: add buttons
2022-08-26 22:24:05 +02:00
0c14bbf0dc
sipeed_tang_primer_20k: adding dock lite support
2022-08-26 08:43:57 +02:00
9ed3b7baae
radiona_ulx3s: add buttons
2022-08-25 22:19:48 -07:00
94d079f469
sipeed_tang_nano_4k: Fix tab/space.
2022-08-24 16:07:18 +02:00
feff243f8f
Merge pull request #416 from shenki/artix-dc-scm
...
Add Antmicro Artix DC-SCM board
2022-08-24 15:22:52 +02:00
6314b34dbe
targets/digilent_arty: Cosmetic cleanup.
2022-08-24 15:17:06 +02:00
6548dec149
Merge pull request #415 from lschuermann/dev/arty-button-irq
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digilent_arty: make GPIOs interrupt-capable if SoC has IRQs enabled
2022-08-24 15:15:20 +02:00
6ba6a7e8fa
Merge pull request #414 from lambdaconcept/master
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lambdaconcept_ecpix5: fix HDMI pin
2022-08-24 15:14:11 +02:00
f48ed3d9e7
Add Antmicro Artix DC-SCM board
...
Based on commits by:
- Jedrzej Boczar <jboczar@antmicro.com>
- Karol Gugala <kgugala@antmicro.com>
Tested serial and networking on a DC-SCM with mor1k and vexriscv.
2022-08-24 13:03:36 +10:00
94ad22aceb
digilent_arty: make GPIOs interrupt-capable if SoC has IRQs enabled
...
Signed-off-by: Leon Schuermann <leon@is.currently.online>
2022-08-17 15:55:39 +02:00
c3e99a8419
lambdaconcept_ecpix5: fix HDMI pin
2022-08-11 18:45:10 +02:00
7487440725
Added Tang Nano 4k Support for GoWin Educational IDE v1.9.8.03
2022-08-05 13:28:22 -03:00
bf458e388e
digilent_arty: Add buttons support.
2022-08-05 15:25:42 +02:00
f143fae2d0
digilent_arty: Add XADC/DNA and do minor cleanups.
2022-08-05 13:00:07 +02:00
6872f7ade6
sipeed_tang_primer_20k: Add LCD pins (untested).
2022-08-05 09:42:38 +02:00
c79d01064e
sipeed_tang_primer_20k: Switch Serial to Dock IOs.
2022-08-05 09:07:20 +02:00
f2cb211432
sipeed_tang_primer_20k: Add buttons and prepare RGB Led.
...
Synthesis issue with WS2812/GowinEDA for now.
2022-08-04 16:32:50 +02:00
09b0c975f3
sipeed_tang_primer_20k: Add Ethernet/Etherbone (compiles but not yet working).
2022-07-26 12:53:42 +02:00
abe08a96aa
sipeed_tang_primer_20k: Add Video (Colorbars), compiles but does not seems to be working.
2022-07-26 12:25:10 +02:00
12b8063941
sipeed_tang_primer_20k: Add LedChaser through 204 pin SODIMM connector/Dock.
2022-07-26 11:44:03 +02:00
d49e43801e
sipeed_tang_primer_20k: Add 204 Pins SODIMM Connector.
...
Will allow defining Dock peripherals.
2022-07-26 11:30:39 +02:00
99c1e52664
targets/sipeed_tang_primier_20k: Add SPI Flash support (X1).
2022-07-26 10:35:44 +02:00
6677c1d0bd
sipeed_tang_primer_20k: Enable SDCard (SPI and SD modes).
2022-07-26 10:27:19 +02:00
cf030402d4
machdyne_krote: Fix build.
2022-07-19 12:17:14 +02:00
67ffe095cc
Merge branch 'master' of https://github.com/machdyne/litex-boards
2022-07-15 17:13:22 +02:00
22dcadcfa1
rename ld board prefix to machdyne
2022-07-15 17:13:00 +02:00
9deef65445
Merge branch 'litex-hub:master' into master
2022-07-14 16:02:00 +02:00
52ff93a194
Merge pull request #409 from antmicro/rrozak/remove-dm-pins-from-datacenter
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Remove DM signals assignment from DDR4 Datacenter platform
2022-07-11 19:34:19 +02:00
8e577662bd
Merge pull request #408 from trabucayre/lattice_nexus_ecp5_toolchain
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targets: ecp5 & nexus: add toolchain argument
2022-07-11 19:33:54 +02:00
2357212161
Remove DM signals assignment from DDR4 Datacenter platform
...
Data Masks (DM) are unsupported on x4 devices and wrong pins were assigned.
Signed-off-by: Ryszard Różak <rrozak@antmicro.com>
2022-07-11 12:29:02 +02:00
3ecec8cd16
Merge branch 'litex-hub:master' into master
2022-07-08 16:59:55 +02:00
756d019571
add support for schoko
2022-07-08 16:58:55 +02:00
4b678da142
ti60_f225_dev_kit: Add debug on ethernet.
2022-07-08 12:17:41 +02:00
3f4676c288
targets: ecp5 & nexus: add toolchain argument
2022-07-05 21:36:02 +02:00
bc66e63bad
lambdaconcept_ecpix5/flash: Switch to .svf.
2022-07-05 18:03:06 +02:00
32f507cc08
Merge pull request #406 from chmousset/fix/icebreaker_bitsy
...
[fix] instanciate PLL for valentyUSB
2022-06-29 10:31:42 +02:00
190f272c14
targets/sipeed_tang_primer_20k: Update build.
2022-06-29 10:00:47 +02:00
b61c471058
targets/avnect_aesku040: Update build.
2022-06-29 09:41:18 +02:00
d3597dea21
[fix] instanciate PLL for valentyUSB
2022-06-28 21:17:02 +02:00
6b02ea024a
ti60_f225_dev_kit: Fix ethernet build and enable debug. Now needs testing.
2022-06-28 19:54:00 +02:00
1a71932599
ti60_f225_dev_kit: Switch to Titanium RGMII PHY.
2022-06-27 19:47:22 +02:00
c14611b07c
ti60_f225_dev_kit: Add dummy 0 pin to connectors to use schematic numbering (1-40).
2022-06-27 19:47:19 +02:00
46ddc36b3c
target: basys3: Remove redundand sdcard additions
2022-06-27 14:34:49 +02:00
eadea43fa1
honours lattice toolchain args
2022-06-22 21:05:35 +02:00
1ad2022138
quicklogic_quickfeather: Move from deprecated Symbiflow to F4PGA
2022-06-17 17:00:48 +02:00
29b72fac7e
taobao_a_e115fb: Minor cleanups.
2022-06-15 11:55:22 +02:00
0ae1417eb5
a_e115fb: Add taobao prefix (Similar to what we do on aliexpress's boards from unknown vendors).
2022-06-15 11:53:11 +02:00
4e0e381f47
Merge pull request #398 from Icenowy/a-e115fb
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a_e115fb: new board
2022-06-15 11:37:36 +02:00
13fbcbb159
a_e115fb: new board
...
It's a core board with EP4CE115 by a random vendor on Taobao.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-06-13 23:13:29 +08:00
e02bee4265
efinix_ti60_f225: Prepare 1Gbps Ethernet support through RGMII extension board.
2022-06-13 16:02:26 +02:00
c420429a3c
efinix_ti60_f225: Add the 3 QSE connectors and add RGMII Ethernet QSE extension board.
2022-06-13 16:01:28 +02:00
b32969c29f
targets/Ultrascale(+): Remove BUFGCE name overrides.
...
Not required, was only useful on a specific project.
2022-06-10 19:21:04 +02:00
4a22f6bf17
targets/avnet_aesku40: Fix compilation and minor cleanups.
2022-06-07 13:08:02 +02:00
d37af4aece
Merge pull request #395 from AEW2015/master
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Support for "discontinued" Avnet aes-ku040-db-g development board
2022-06-07 12:13:47 +02:00
313e758ffe
Updated copywrite and renamed to avnet_aesku40
2022-06-03 20:49:52 -06:00
5188b17a71
sipeed_tang_nano_9k: Switch to old HyperRAM core until issue with new one is investigated. Also do some cleanup and disable video_terminal by default.
2022-06-03 12:28:38 +02:00
ddc6140e25
sipeed_tang_primer_20k: Swithc to GW2APLL.
2022-06-03 12:01:49 +02:00
6e33d9249f
sipeed_tang_primer_20k: Cleanup/Fix.
2022-06-03 11:40:10 +02:00
68733c6e92
Merge pull request #396 from Icenowy/tang20k
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sipeed_tang_primer_20k: new board
2022-06-03 10:14:55 +02:00
b97d9cd9e8
sipeed_tang_primer_20k: new board
...
Only initial support is added.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-06-03 00:24:20 +08:00
4d98dd38a7
Merge branch 'litex-hub:master' into master
2022-06-01 23:01:43 -06:00
1b96067113
added aesku40 dev board
2022-06-01 22:54:03 -06:00
48353735fa
Merge pull request #393 from swetland/ethernet
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muselab icesugar pro: add ethernet/etherbone support
2022-05-20 22:10:02 +02:00
5a714167ed
muselab icesugar pro: add ethernet/etherbone support
...
- use P4 header for a waveshare ethernet phy module
- add --with-ethernet, --with-etherbone, --eth-ip, and --eth-dynamic-ip
target configuration options
2022-05-19 14:46:09 -07:00
2214c7baec
enclustra_mercury_kx2: remove useless clk100, because it is not connected to a clock pin
2022-05-20 04:42:06 +07:00
f1e021cbbe
enclustra_mercury_kx2: add clk100, leds, base board serial, DDR3 termination, DDR3 voltage setting
2022-05-19 15:41:44 +07:00
64773b4085
Merge pull request #390 from hansfbaier/hpc-xc7k420t
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HPC Store xc7k420t
2022-05-16 11:20:15 +02:00
f14865fa42
Merge branch 'hpc-xc7k420t' of github.com:hansfbaier/litex-boards into hpc-xc7k420t
2022-05-16 12:34:30 +07:00
c5d292c7f9
Get 4 DDR modules working with Vivado
2022-05-16 12:33:04 +07:00
efa5740811
Move HDMI Support From Sipeed Tang Nano 4K.
2022-05-15 10:53:09 +08:00
26c0f546c7
Merge branch 'litex-hub:master' into hpc-xc7k420t
2022-05-14 21:40:12 +07:00
006b54e7ea
Get 3 DDR modules working with Vivado
2022-05-14 21:38:25 +07:00
1e77c28ed0
muselab_icesugar_pro/VideoHDMIPHY: Remove obsolete drive_both.
2022-05-12 16:09:40 +02:00
ee58e5dbc7
Merge pull request #388 from swetland/hdmi
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muselab: icesugarpro: fix HDMI output
2022-05-12 15:09:03 +02:00
dabf2cff06
sqrl_acorn: Switch back to PCIe Gen2 X4 and enable 64-bit addressing (Not really useful except for 64-bit addressing tests).
2022-05-12 13:32:41 +02:00
f383ad3938
Support HPC Store XC7K420T board
2022-05-12 12:55:46 +07:00
d1096a2cd0
Add HPC Store XC7K420T board
2022-05-11 08:58:50 +07:00
45494f60e0
targets: Change SoC/Software headers generation behaviour (Now only generated with --build).
...
Re-generating the SoC/Software headers was causing some un-expected behaviours for users not familiar
with the flow. For example doing a --load with a different configuration, was re-generating the Software
headers and messing up things when trying to run software on the SoC.
2022-05-06 15:14:32 +02:00
0ce7f8354c
Add initial LimeSDR Mini V2 support (With SoC + USB3 (FT245PHYSynchronous)).
...
python3 -m litex_boards.targets.limesdr_mini_v2 --csr-csv=csr.csv --build --load
litex_server --jtag --jtag-config=openocd_limesdr_mini_v2.cfg
litex_term crossover
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2022 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on May 3 2022 18:59:46
BIOS CRC passed (5f29afcc)
LiteX git sha1: a4cc859d
--=============== SoC ==================--
CPU: VexRiscv @ 80MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 128KiB
SRAM: 8KiB
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex> ident
Ident: LiteX SoC on LimeSDR-Mini-V2 2022-05-03 18:59:29
2022-05-03 19:04:06 +02:00
c93b4dc4dc
targets: Fix targets that not using full imports.
2022-05-03 18:41:18 +02:00
683226df34
litex_boards: Remove short imports since not really longer useful and mess up Python imports.
...
We could maybe find a better implementation to avoid messing up imports but not sure it's really useful.
This also enforces consistency in platforms/targets.
2022-05-03 17:53:57 +02:00
ec220e4b5b
muselab: icesugarpro: fix HDMI output
...
- enable data_n outputs
- use drive_both property of updated VideoHDMIPHY to drive both
differential outputs
- adjust default clocking to successfully close timing
(sysclk at 50Mhz, HDMI at 25MHz, HDMIx5 at 125MHz)
2022-05-03 04:04:26 -07:00
28da4f83eb
targets: Use new HyperRAM's sys_clk_freq parameter.
2022-05-02 16:43:52 +02:00
3ebc9877ad
1bitsquared_icebreaker: Rename to icebreaker (Python does not like number as prefix for imports).
2022-05-02 13:20:40 +02:00
877bc4b45e
targets: Use full imports (vendor_board).
2022-05-02 12:55:11 +02:00
9914478854
xilinx_ac701: Add SPI-Flash support.
2022-04-28 11:05:51 +02:00
ae8bdb74a9
xilinx_kc705: Add SPI-Flash support.
2022-04-28 10:27:54 +02:00
b778ba5f70
sqrl_acorn: Add XADC/DNA (For LitePCIe driver test).
2022-04-27 15:01:09 +02:00
74db821f67
colorlight_5a_75x: Switch ethernet/etherbone to 32-bit.
2022-04-25 18:50:21 +02:00
68ea5fe057
platforms/colorlight_5a_75b/v7_0: Comment rst_n to avoid deadlock on reboot command.
2022-04-25 18:50:17 +02:00
adb0922e8f
Delete additional "o" in "builder" object
...
Delete an additional "o" in "builder" object. It makes not possible to program the Basys 3 out-of-the-box.
2022-04-23 18:06:19 -06:00
575d681891
targets: Use "" for strings.
2022-04-21 15:48:29 +02:00
353aba0359
targets: Move USB-ACM/ValentyUSB clone directly to LiteX to avoid duplication in targets.
2022-04-21 15:43:50 +02:00
4fbf2fc7de
targets: Replace self.add_wb_master with self.bus.add_master.
2022-04-21 15:32:19 +02:00
39a314cdae
Rename aliexpress_u420t to aliexpress_xc7k420t.
2022-04-21 14:28:26 +02:00
88f2625c3d
targets: Fix typos.
2022-04-21 12:29:54 +02:00
a611f035d6
targets: Move CRG before SoCCore init (More logical and simplify some specific reset schemes) and switch SoCCore to one line when possible.
...
Moving CRG simplify reset with NaxRiscv debug module and is in fact more logical.
Also do some minor updates/cosmetic changes while touching CRG/SoCCore.
2022-04-21 12:19:45 +02:00
06396a2cb6
Merge pull request #384 from hansfbaier/qmtech-ep4cgx150
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add board support for QMTech EP4CGX150
2022-04-21 10:36:51 +02:00
b2a346edc8
aliexpress_u420t: Review/Simplify.
...
Specific integrated ROM/SRAM/MAIN_RAM size can be passed through command line parameters.
2022-04-21 10:32:18 +02:00
3e9e970076
Add aliexpress prefix to boards from aliexpress that seem to be from the same unknown vendor.
2022-04-21 10:06:11 +02:00
8c51cb12c8
Merge pull request #383 from sysmanalex/master
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Added Kintex-7 xc7k420t xc7k420tiffg901-2L named as u420t board
2022-04-21 10:02:05 +02:00
f986855926
Merge pull request #372 from mkj/butterstick-ethdelay
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butterstick: set ethernet rx_delay to 0ns
2022-04-21 09:00:13 +02:00
53e9e0914e
qmtech_ep4cgx150 80MHz default works well
2022-04-16 15:00:01 +07:00
b41d72e1d0
add board support for QMTech EP4CGX150
2022-04-16 06:36:24 +07:00
23b1b15486
Add initial/minimal Pluto SDR support.
2022-04-14 12:13:03 +02:00
1e00a43fdd
board u420t kintex update v0.2
2022-04-13 00:12:59 +03:00
89570b005c
Added Kintex-7 xc7k420t xc7k420tiffg901-2L named as u420t board
2022-04-12 22:38:14 +03:00
b99d788732
fairwaves/xtrx: Update with xtrx_julia improvements.
2022-04-12 17:42:52 +02:00
dd27a3473b
platforms: Add LambdaConcept's PCIe Screamer/M2.
2022-04-01 11:41:07 +02:00
00ff61baa9
targets: Simplify clock domains and remove useless reset_less.
...
rst was not directly assigned/used on reset_less clock domains, so reset_less
property was not really useful. With the changes on stream.CDC, having a rst
(Even fixed at 0) is now mandatory on clock domains involved in the CDC, so this
also fixes targets.
2022-04-01 11:30:38 +02:00
867489d855
xilinx_zcu106: Add PCIe Gen3 X4 support.
2022-04-01 10:01:06 +02:00
299d4d66d6
efinix: ti60f225 add MIPI RX
2022-03-29 15:29:59 +02:00
13e5062793
Merge pull request #379 from chmousset/add_t8_devkit
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[enh] added efinix t8f81 dev kit
2022-03-28 14:58:21 +02:00
e6a9f44580
Merge pull request #378 from antmicro/add-missing-peripherals
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DDR4 datacenter: add missing peripherals
2022-03-28 14:40:22 +02:00
83d7c3fb39
Merge pull request #377 from Johnsel/arduino_mkrvidor4000
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Board support for Arduino MKR Vidor 4000
2022-03-28 14:34:59 +02:00
7a68dcc79b
[enh] added efinix t8f81 dev kit
2022-03-26 09:52:20 +01:00
33516a40f4
antmicro_datacenter: add missing peripherals
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2022-03-25 13:49:41 +01:00
77cb866233
antmicro_datacenter: add HDMI output
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2022-03-25 10:03:07 +01:00
501c50ff79
Fixed serial port comments hinting the correct pins.
2022-03-24 08:04:47 -07:00
901942bda6
Cleanup for pushing. This commit combined with my litedram fork produces a running basic SoC + bios --=============== SoC ==================--
...
CPU:BUS:E 32-bit @ 4GiB
CSR:16-bit @ 48MT/s (CL-2 CWL-2)
--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
Write: 0x40000000-0x40200000 2.0MiB
Read: 0x40000000-0x40200000 2.0MiB
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
Write speed: 13.6MiB/s
Read speed: 21.3MiB/s
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
2022-03-24 07:39:14 -07:00
e445c9ec71
qmtech_5cefa2: make serial pins consistent with other boards
2022-03-24 18:52:28 +07:00
c081177d77
pynq_z1/zybo_z7: Update .xci (With changes from #99 ).
2022-03-24 09:15:36 +01:00
bcedf573e0
adi_adrv2crr: Add IO definition for the AD9545 reset line
...
We use PULLUP on it so that the AD9545 is by default held out
of reset without the user having to do anything ...
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2022-03-23 20:42:30 +01:00
cdb78efd3c
adi_adrv2crr: Document I2C devices attached
...
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2022-03-23 20:42:30 +01:00
6c31f16df2
adi_adrv2crr: Fix I2C signal assignement
...
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2022-03-23 20:42:30 +01:00
bb974ae1af
decklink_quad_hdmi_recorder: Add pcie_lanes parameter and 4x/8x support.
2022-03-23 15:24:49 +01:00
73458ae9d7
decklink_quad_hdmi_recorder: Add Serial/UART pins.
2022-03-23 11:08:51 +01:00
d399f33dda
Merge pull request #374 from smunaut/adrv2crr
...
adi_adrv2crr: Upgrade part to speedgrade 2
2022-03-23 09:09:57 +01:00
4ca527974b
Merge pull request #373 from goran-mahovlic/patch-1
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faster sdcard boot on 2.0
2022-03-23 08:07:49 +01:00
dc92584681
adi_adrv2crr: Upgrade part to speedgrade 2
...
Even though the schematic and bom call for speedgrade 1, this was only for
the prototypes.
All productions units have been updated to speedgrade 2.
See this thread:
https://ez.analog.com/fpga/f/q-a/112356/adrv9009-zu11eg-speed-grade
And the official HDL project for the board:
https://github.com/analogdevicesinc/hdl/blob/master/projects/adrv9009zu11eg/adrv2crr_fmc/system_project.tcl#L16
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2022-03-22 23:36:41 +01:00
ce4b627e3c
targets: Remove l2_size workaround (no longer required).
2022-03-22 19:13:23 +01:00
68c23e9251
faster sdcard boot on 2.0
2022-03-22 17:54:12 +01:00
2a206def0f
targets/ecp5/ddr3: Uniformize cd_sys2x (reset_less).
2022-03-22 17:32:35 +01:00
53c221a1fa
butterstick: set ethernet rx_delay to 0ns
...
The Microchip KSZ9031RNX PHY on the Butterstick has a default 1.2ns
internal RX delay so we shouldn't add the default 2ns MAC delay.
In testing with Linux on vexriscv I haven't seen any difference either
way, but with liteeth in Microwatt I have seen 30%+ packet loss when
receiving from certain ethernet devices (RTL8153 and AX88179 usb-gige
adapters, a GS105 switch didn't show the problem). Setting RX delay=0
resolves the problem. A TX delay is still required by the PHY.
2022-03-22 13:51:03 +08:00
b8b0aead28
Added basic support for Arduino MKR Vidor 4000
2022-03-21 18:54:29 -07:00
9d452b0d74
targets: Create target_group for target arguments.
2022-03-21 18:37:40 +01:00
d90e260414
targets/digilent_atlys: Fix target.
2022-03-21 17:38:02 +01:00
cc8da9d341
targets: Simplify imports and switch to LiteXSocArgumentParser.
...
CPU parameters are now selectively exposed to the user:
./digilent_arty.py --cpu-type=vexriscv_smp --help will show VexRiscv-SMP parameters.
./digilent_arty.py --cpu-type=naxriscv --help will show NaxRiscv parameters.
2022-03-21 16:59:40 +01:00
eb8657f515
gsd_orangecrab: Revert dm_remapping (Useful when built with VexRiscv-SMP and native LiteDRAM interface).
2022-03-18 12:56:13 +01:00
3ebad7f7cc
gsd_orangecrab/butterstick: Add assert on devices.
2022-03-18 10:44:21 +01:00
9faa805ab9
alinx_ax7010: Review/Cleanup.
2022-03-17 11:31:02 +01:00
3aa1042f5f
Merge pull request #367 from ggangliu/zynq_xc7z010
...
Add ALINX AX7010 board support
2022-03-17 09:52:04 +01:00
0f82db26da
rcs_artic_term_bmc_card: Fix is -> ==.
2022-03-17 09:45:47 +01:00
496b2cfab9
targets/gowin: Switch to get_bitstream_filename.
2022-03-17 09:40:10 +01:00
773444a7dd
targets: Switch to get_bios_filename/get_bitstream_filename.
2022-03-17 09:21:05 +01:00
94786cae19
Update and rename xilinx_alinx_ax7010.py to alinx_ax7010.py
2022-03-17 11:24:24 +08:00
0e7145b4a1
Update and rename xilinx_alinx_ax7010.py to alinx_ax7010.py
2022-03-17 11:21:42 +08:00
0745162a29
xilinx_zcu102: Review/Cleanup for consistency with others boards.
...
Also remove INTERNAL_VREF constraints that are not yet useful (required for DRAM).
2022-03-16 18:47:05 +01:00
adbcc2e547
add zcu102 target file
2022-03-16 15:55:37 +01:00
f4a48e51d7
add xilinx_zcu102 platform
2022-03-16 15:37:02 +01:00
9dad1cb244
Rename xilinx_zynq_xc7z010.py to xilinx_alinx_ax7010.py
2022-03-15 15:51:13 +08:00
5365c7fce4
Rename xilinx_zynq_xc7z010.py to xilinx_alinx_ax7010.py
2022-03-15 15:50:09 +08:00
a962d8249f
Merge pull request #366 from gsomlo/gls-nexys-video-sata-pll
...
targets/nexys-video: Add support for sata pll refclk
2022-03-13 12:30:58 +01:00
9c55773275
Add files via upload
...
Add zynq_xc7z010 board support
2022-03-12 12:33:41 +08:00
4159faf48b
Add files via upload
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Adding zynq_xc7z010 board support
2022-03-12 12:20:54 +08:00
9f9afeaafa
targets/nexys-video: Add support for sata pll refclk
2022-03-11 14:40:21 -05:00
688377de7c
lpddr4_test_board: Fix button pin
2022-03-11 15:59:43 +01:00
3b74673a93
Merge pull request #363 from curliph/master
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add Gowin programmer support
2022-03-08 17:26:50 +01:00
f52a915487
lambdaconcept_ecpix5: Add initial Video support at 640x480 (with Terminal/Framebuffer).
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I2C intialization code adapted from https://github.com/ultraembedded/ecpix-5 .
Tested with:
- python3 -m litex_boards.targets.lambdaconcept_ecpix5 --cpu-type=firev --with-video-terminal --build --load
- python3 -m litex_boards.targets.lambdaconcept_ecpix5 --cpu-type=firev --with-video-framebuffer --build --load
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2022 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Mar 8 2022 15:34:22
BIOS CRC passed (c7fe9ecd)
Migen git sha1: ac70301
LiteX git sha1: 7ebc7625
--=============== SoC ==================--
CPU: FireV-STANDARD @ 75MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 128KiB
SRAM: 8KiB
L2: 8KiB
SDRAM: 524288KiB 16-bit @ 300MT/s (CL-6 CWL-5)
--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Read leveling:
m0, b00: |01110000| delays: 02+-01
m0, b01: |00000000| delays: -
m0, b02: |00000000| delays: -
m0, b03: |00000000| delays: -
best: m0, b00 delays: 02+-01
m1, b00: |01110000| delays: 02+-01
m1, b01: |00000000| delays: -
m1, b02: |00000000| delays: -
m1, b03: |00000000| delays: -
best: m1, b00 delays: 02+-01
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
Write: 0x40000000-0x40200000 2.0MiB
Read: 0x40000000-0x40200000 2.0MiB
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
Write speed: 13.6MiB/s
Read speed: 23.4MiB/s
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex> ident
Ident: LiteX SoC on ECPIX-5 2022-03-08 15:34:19
2022-03-08 15:40:52 +01:00
39e4e211bb
targets/decklink_mini_4k: Add build/use instructions.
2022-03-08 14:14:18 +01:00
2df7fd573c
Update sipeed_tang_nano_9k.py
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Add Gowin programmer support
2022-03-08 14:04:28 +08:00
6eb906a2ca
Update sipeed_tang_nano_9k.py
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add Gowin programmer support
2022-03-08 14:00:53 +08:00
4c9bc53a3c
add Win/powershell and WSL support
2022-03-08 13:24:56 +08:00
cadfde4d39
litex_acorn_baseboard: Add SerDes refclk and m2_tx/rx pins.
2022-03-07 18:41:53 +01:00
50cc75fd56
Merge pull request #361 from smunaut/adrv2crr
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adi_adrv2crr: Add support for the ADI ADRV2CRR with ADRV9009-ZU11EG SoM
2022-03-07 09:24:36 +01:00
Antoni Pokusinski
Tomasz Michalak
Do Viet Thanh
Florent Kermarrec
Goran Mahovlic
MV
Fabien
Greg Davill
Hans Baier
Luc Lagarde
gatecat
inc
stone3311
jiv4ik
Gwenhael Goavec-Merou
JoyBed
Guilherme Salustiano
Tim Callahan
Guilherme Salustiano
mkuhn99
Icenowy Zheng
Chema
Shawn Anastasio
Franck Jullien
Lukas F. Hartmann
Vadzim Dambrouski
slagernate
Adam Zeloof
Igor Safonov
Joel Stanley
Leon Schuermann
Pierre-Olivier Vauboin
Chandler Klüser
Machdyne
Ryszard Różak
Charles-Henri Mousset
Robert Szczepanski
AEW2015
Brian Swetland
minexo79
Jorge Castro-Godínez
Alex Petrov
Alex Petrov
Alessandro Comodi
John Simons
Sylvain Munaut
Matt Johnston
Yonggang Liu
Joseph Faye
Gabriel Somlo
curliph