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319 commits

Author SHA1 Message Date
Dolu1990
d0e963559a Update readme with the new ICache implementation 2018-02-18 23:48:11 +01:00
Dolu1990
93110d3b95 Add jump priority managment in PcPlugins 2018-02-16 14:27:20 +01:00
Dolu1990
506e0e3f60 New faster/smaller/multi way instruction cache design. 
Single or dual stage
 2018-02-16 02:21:08 +01:00
Dolu1990
3853e0313b SynthesisBench cleaning/experiments 2018-02-11 14:53:42 +01:00
Dolu1990
0e6ae682b1 Add architecture section describing plugins in the readme 2018-02-09 00:44:27 +01:00
Dolu1990
57ebfee2e6 Add more axi bridges 2018-02-08 21:39:22 +01:00
Dolu1990
3ee111e100 Update readme (gcc stuff) 2018-02-05 16:34:10 +01:00
Dolu1990
d4b05ea365 Remap Briey/Murax onChipRam to 0x80000000 to avoid having memory at the null pointer location 
Commit missing file
Update dhrystone hex to use GP. 1.44 DMIPS/Mhz
 2018-02-05 16:16:27 +01:00
Dolu1990
4729e46763 Add DummyFencePlugin 2018-02-03 12:28:53 +01:00
Dolu1990
f13dba847c Add custom csr gpio example 2018-02-02 11:14:55 +01:00
Dolu1990
b7d8ed8a81 Add onWrite/onRead/isWriting/isReading on the CsrPlugin 2018-02-01 21:28:28 +01:00
Dolu1990
4ee2482cbf Fix custom_csr regression against random ibus stall 2018-01-31 18:33:21 +01:00
Dolu1990
d2e5755df4 revert removed code by mistake 2018-01-31 18:29:30 +01:00
Dolu1990
30b05eaf96 Add CsrInterface to allow custom CSR addition 
Add CustomCsrDemoPlugin as a show case
 2018-01-31 18:13:42 +01:00
Dolu1990
bdbf6ecf17 BranchPrediction DYNAMIC_TARGET add source PC tag to only consume entries on branch instructions 2018-01-29 14:52:31 +01:00
Dolu1990
0d318ab6b9 Add DYNAMIC_TARGET branch prediction (1.41 DMIPS/Mhz) 
Add longer timeouts in the regressions tests
 2018-01-29 13:17:11 +01:00
Dolu1990
307c0b6bfa Now mret and ebreak are only allowed in CSR machine mode 2018-01-28 16:34:55 +01:00
Dolu1990
93da5d29bc Fix dhrystone referance log 2018-01-28 16:34:55 +01:00
Dolu1990
26732942e5 Update DMIPS/Mhz 
Add cached config with maximal performance settings
FullBarrielShifterPlugin can now be configured to do everything in the execute stage
 2018-01-25 01:11:57 +01:00
Dolu1990
3b3bbd48b9 SpinalHDL 1.1.3 => Now Verilog rom are emited into separated bin files 2018-01-20 18:29:33 +01:00
Dolu1990
6a521a8d13 Better MuraxSim gui 
Add MuraxSim in the readme
 2018-01-09 08:59:17 +01:00
Dolu1990
9a89573942 SpinalHDL 1.1.2 
Add Murax setup with Mul Div Barriel
 2018-01-06 22:09:42 +01:00
Dolu1990
43d3ffd685 CsrPlugin : Now wait that the whole pipeline (including writeback) is empty before executing interruptions. This make the separation between context switching clear and avoid on atomic instructions failure 2018-01-04 17:37:23 +01:00
Dolu1990
2b7465e5df Add more atomic tests (PASS) 2018-01-04 16:16:22 +01:00
Dolu1990
611f2f487f Fix DataCache atomic integration into DBusCachedPlugin 
Atomic is passing basic tests
 2018-01-04 15:24:00 +01:00
Dolu1990
4637e6cb48 Fix DecodingSimplePlugin model building when reinvocation is done one a preexisting opcode. 
add Atomic test flow
 2018-01-04 14:43:30 +01:00
Dolu1990
468dd3841e Add Atomic LR SC support to the DBusCachedPlugin via reservation entries buffer 2018-01-04 13:16:40 +01:00
Dolu1990
4ed19f2cc5 SpinalHDL 1.1.1 2017-12-30 03:36:57 +01:00
Dolu1990
0d39e38906 SpinalHDL 1.1.0 2017-12-28 13:49:39 +01:00
Dolu1990
3c0588eb4b remove MuraxSim fixed path 2017-12-19 22:33:46 +01:00
Dolu1990
7f2b2181c1 SpinalHDL 1.0.3 2017-12-19 21:21:16 +01:00
Dolu1990
37849b7a66 Spinal 1.0.2 sim update 2017-12-19 00:40:52 +01:00
Dolu1990
ebda7526b5 MuraxSim 1.0.0 2017-12-17 17:57:09 +01:00
Dolu1990
dda5372a6c Fix typo 2017-12-14 01:05:06 +01:00
Dolu1990
d6e0761065 Fix led gui refresh rate 2017-12-14 01:04:31 +01:00
Dolu1990
2259c9cb0f Add SpinalHDL sim (1.0.0) 2017-12-14 00:57:12 +01:00
Dolu1990
e1b86ea511 SpinalHDL 0.11.4 update 2017-12-01 11:19:23 +01:00
Dolu1990
586d3ed286 Update formal VexRiscv to halt on missaligned dbus 2017-11-26 15:30:48 +01:00
Dolu1990
4de0aac469 Merge branch 'formal' 2017-11-24 14:03:25 +01:00
Dolu1990
b7f4f09814 Update verilator makefiles to support the last SpinalHDL changes (process merges) 2017-11-21 23:56:46 +01:00
Dolu1990
9b9bbaa4ad Add missing full config for the iBus 2017-11-21 00:09:02 +01:00
Dolu1990
ce6fd6d0aa Add VexRiscvAxi4 demo 2017-11-20 23:57:37 +01:00
Dolu1990
7c19288648 Update Synthesis bench 
Update some synthesis results
 2017-11-17 20:10:46 +01:00
Tony Kao
290dbc106e Fixes GPIO width mismatch 
Adds explicit type to apbDecoder.slave to suppress IDE errors
 2017-11-16 15:02:13 -05:00
Dolu1990
6c3fed3505 SpinalHDL 0.11.1 2017-11-15 16:44:42 +01:00
Dolu1990
be3d301eaf Merge remote-tracking branch 'origin/spinalhdl_reworkDev' 2017-11-12 13:08:05 +01:00
Dolu1990
838c13d68b spinal.core.internals literals import 2017-11-10 13:14:30 +01:00
Dolu1990
3060296b94 unsetRegIfNoAssignement -> allowUnsetRegToAvoidLatch 2017-11-10 11:33:04 +01:00
Dolu1990
c3a7f4e58c CSR unsetRegIfNoAssignement fix 
BranchPlugin doesn't emit the prediction cache when the STATIC setup is used
 2017-11-10 00:59:31 +01:00
Dolu1990
d6777ae8ec usetRegIfNoAssign upgrade 2017-11-09 20:10:56 +01:00
Dolu1990
a72c7fd0d1 Clean Murax toplevel by extracting integrated Area into dedicated components located in MuraxUtiles.scala 2017-11-07 22:19:33 +01:00
Dolu1990
714d44d248 Add fixed bug into the FormalPlugin comments 2017-11-07 13:54:07 +01:00
Dolu1990
200a73bea0 Fix FormalPlugin to pass liveness again. 2017-11-06 23:04:33 +01:00
Dolu1990
8098a03a9b with no bus stall, pass all tests except uniqueness 2017-11-06 20:26:45 +01:00
Dolu1990
e2a432eb5e add HaltOnExceptionPlugin 
wip
 2017-11-05 20:13:27 +01:00
Dolu1990
276f7895e7 Add FormalPlugin 
Add FormalSimple CPU configuration
 2017-11-04 00:55:32 +01:00
Dolu1990
ba42f71813 pass VexRiscv regressions 2017-10-30 14:29:25 +01:00
Ubuntu
008a5b7309 updated main.cpp 
added missing using namespace std
 2017-10-17 22:09:08 +00:00
Dolu1990
2bf7ca24f2 Add VexRiscvAvalonWithIntegratedJtag 2017-10-16 11:52:17 +02:00
Dolu1990
aa859aae6b Update framework.h 
Add missing using namespace std;
 2017-10-05 10:08:09 +02:00
Dolu1990
09ba7c28da Change some xx.input(REGFILE_WRITE_DATA) for xx.output(REGFILE_WRITE_DATA) 2017-08-27 15:21:44 +02:00
Dolu1990
8168c9bf3a Update simd_add makefile 2017-08-27 14:49:36 +02:00
Charles Papon
2c6889e688 Murax mainBus now handle unmapped memory access allowing the debug to access unmapped area without locking the CPU 
Murax add dhrystone config
 2017-08-10 22:48:00 +02:00
Charles Papon
aa477b2b1c DebugPlugin now prevent the CPU catching exception when debug instruction are pushed 
Fix DataCache locking when loading mem read rsp  transaction has the flag set
Briey : Now the debug module reset the whole AXI system instead of only the CPU
Now in debug, you can access unmapped memory without crashing the CPU
 2017-08-10 20:56:54 +02:00
Charles Papon
1653548140 Better readme about custum instruction testing 2017-08-08 18:36:23 +02:00
Charles Papon
54b06e6438 Add SIMD_ADD regression and config (show case) 2017-08-08 18:19:02 +02:00
Charles Papon
3307d6c3b5 Briey move CPU and UART generics from to toplevel to the toplevel configuration object 2017-08-06 15:42:37 +02:00
Charles Papon
671aa5050e Move CPU and UART configs into the murax configuration object (in place of toplevel hardcoding) 
Add MuraxConfig.fast
 2017-08-04 14:55:54 +02:00
Charles Papon
ac59eebb8d Add Murax configuration which integrate a boot programme : 
Will blink led and echo UART RX to UART TX   (in the verilator sim, type some text and press enter to send UART frame to the Murax RX pin)
 2017-08-03 21:58:23 +02:00
Dolu1990
58981c0e8e Add Murax fast in synthesis bench 2017-08-01 21:14:09 +02:00
Charles Papon
f44b345132 Add console TX in the Murax verilator 2017-07-31 21:04:41 +02:00
Charles Papon
0c9a39d3ce Connect the UART interruption to the CPU 2017-07-31 17:20:47 +02:00
Charles Papon
c16a53c388 Refractoring of some arbitration signals 
Add UART into Murax
 2017-07-31 13:34:25 +02:00
Dolu1990
8708d2482f Add more information about dependencies 2017-07-30 11:37:22 +02:00
Charles Papon
de33128e01 Add Murax 0.55 DMIPS/Mhz 2017-07-30 02:42:14 +02:00
Charles Papon
e8aa828744 PcPlugin change fastPcCalculation into relaxedPcCalculation 
relaxedPcCalculation relax timings on the IBusSimple address => better FMax when the CPU is integrated into a SoC
 2017-07-29 21:36:30 +02:00
Charles Papon
3b66d986a8 Fix cpu sending instruction memory request while being halted by the DebugPlugin 2017-07-29 18:20:22 +02:00
Charles Papon
43253f61c1 Update Murax info 2017-07-29 02:52:57 +02:00
Charles Papon
fa887d3830 Add pipelining option (hit 60 Mhz) 2017-07-29 02:52:03 +02:00
Charles Papon
3bdf020c67 Add interrupts and timer to Murax 
8KB ram is the default now
 2017-07-29 01:59:17 +02:00
Charles Papon
823ac353ff Add Murax SoC (very light, work on ice40) 2017-07-28 21:25:49 +02:00
Dolu1990
1450077b70 Add Murax SoC (wip) 2017-07-28 14:16:30 +02:00
Charles Papon
493f7721cb All FreeRTOS tests are now passing 2017-07-28 00:07:51 +02:00
Charles Papon
800e9e79a5 freertos regression now include O0 and O3 for rv32i and rv32im 2017-07-27 01:23:50 +02:00
Charles Papon
6b3e2dbe7d Add FreeRTOS test regression (FREERTOS=yes) 
Multithreaded regression
 2017-07-26 23:38:59 +02:00
Charles Papon
10d282b2ef Add DBusSimple early injection feature (better DMIPS) 2017-07-26 23:36:25 +02:00
Charles Papon
6d117f5c81 Fix DataCache bug (interaction between the victim buffer and the memory read request in execute/memory stages) 
freeRTOS pass
 2017-07-23 22:58:26 +02:00
Charles Papon
9fe4e1d54d Package refractoring VexRiscv -> vexriscv Plugin -> plugin 2017-07-23 13:28:17 +02:00
Charles Papon
4b5bf7d807 Briey Area down by 10% by spliting the memory system in two (System, Debug) 2017-07-23 01:11:33 +02:00
Charles Papon
37c338ec98 Avalon add read response support. 
Fix debug instruction injection and IBusSimplePlugin interraction
 2017-07-21 20:39:54 +02:00
Charles Papon
54f785b1a3 Add full avalon support (pass regression) 2017-07-21 17:40:45 +02:00
Charles Papon
52f5020e64 Rename some regression commands 
Add Avalon regressions (PASS)
DebugModule read response is now 1 cycle latency
 2017-07-21 14:32:49 +02:00
Charles Papon
575a410786 Avalon regression (WIP) 2017-07-20 14:20:19 +02:00
Charles Papon
570f0e1e3e D$ remove the coupling between the mem.cmd.ready >> victim logic >> cpu halt by using halfPipe => Better practical FMax 2017-07-20 14:20:19 +02:00
Dolu1990
8643086fc0 Add Briey area and timings into readme 2017-07-19 18:34:16 +02:00
Charles Papon
42e546ecd9 Add fullNoMmuNoCache config 2017-07-17 16:45:06 +02:00
Charles Papon
fcec6cba86 revert test changes 2017-07-17 15:26:37 +02:00
Charles Papon
617861ee6c Add smallAndProductive 2017-07-17 15:25:56 +02:00
Charles Papon
99c3397243 readme, better plugin example 2017-07-17 14:19:28 +02:00
Charles Papon
84bba3adf0 REG1/REG2 refractoring RS1/RS2 
Add CustomeInstruction example
 2017-07-17 14:02:56 +02:00
Dolu1990
708a8f66de typo fixes 2017-07-17 14:01:35 +02:00
Dolu1990
79c2972076 Update bench config with realistic embedded CSR 2017-07-16 14:34:42 +02:00
Dolu1990
53300c4116 Add area and FMax in readme 
Add Synthesis bench
 2017-07-16 13:50:19 +02:00
Dolu1990
37ea699c55 Add Synthesis bench 2017-07-16 03:29:50 +02:00
Charles Papon
6930e76042 Remove mepc from smallest CSR config 
Better readme
 2017-07-16 00:44:23 +02:00
Charles Papon
bc792a8655 Fix UartRx sim 2017-07-15 19:05:34 +02:00
Charles Papon
74becb6633 Add VexRiscvAvalon QSysify 2017-07-15 09:41:39 +02:00
Charles Papon
12d21a08e8 Add DebugPlugin avalon 2017-07-14 19:28:22 +02:00
Charles Papon
d3dcfcec06 Add toAvalon bridge to cached bus 
Add VexRiscvAvalon demo
 2017-07-14 18:04:41 +02:00
Charles Papon
f51f28164a Fix info to flush data cache 
Briey sim add VGA GUI (SDL2)
Add DE0-Nano Briey support
 2017-07-09 01:00:46 +02:00
Charles Papon
8d34c04425 Fix CsrPlugin case issue 
Better DBusSimplePlugin FMax with catch enables
SrcPlugin can now insert SRC1 and SRC2 in the execute mode for lower area usage and combinatorial path balancing
 2017-06-27 19:37:46 +02:00
Charles Papon
e9ab3d71d5 update readme 
add uart.elf binary for testing
 2017-06-26 14:44:52 +02:00
Charles Papon
4d7455f9c3 add retiming to the dataCache waysHit 
Add exception catches in the default briey configuration
 2017-06-26 14:02:25 +02:00
Charles Papon
e9e7cf9e7a Add briey tracing 
Better debugPlugin implementation
Fix SimpleDBus/IBus into AXI bridge (cmd transaction removing)
Add SingleInstructionLimiterPlugin for debug purposes
 2017-06-24 14:09:12 +02:00
Charles Papon
edf1b4ed5a Cleaning, better jtag perf 2017-06-18 16:10:27 +02:00
Charles Papon
bc90331c49 Cleaning 2017-06-15 13:54:34 +02:00
Charles Papon
88a2c4a603 Cleaning/Add documentation 2017-06-15 13:44:21 +02:00
Charles Papon
835dd4ad50 Add CSR 2017-06-15 11:16:11 +02:00
Charles Papon
f8678698fc Briey improve AXI FMax 
Faster debugginPlugin regression
 2017-06-11 11:52:59 +02:00
Charles Papon
cbc770deb3 Improve TCP sockets latency 2017-06-10 19:38:42 +02:00
Charles Papon
9b9d9e2582 Add Uart monitor in the briey testbench 2017-06-10 16:09:14 +02:00
Charles Papon
11a63491bd Add YAML feature to store CPU info 2017-06-09 16:06:18 +02:00
Charles Papon
4b9668c063 Remove speed factor overriding when Trace 2017-06-09 08:41:12 +02:00
Charles Papon
f46ec583d6 Briey is now working with DataCache on FPGA 2017-06-07 23:02:34 +02:00
Dolu1990
8dcf5cf68a Add missing import in Briey testbench 2017-06-07 16:56:29 +02:00
Charles Papon
8da413dec3 Briey SoC is now working with openOCD TCP JTAG connection. (GDB OK) 
Add SDRAM Verilator model
 2017-06-07 04:19:35 +02:00
Charles Papon
1e18daecc0 Add ICache and DCache axi bridges functions 
Add StaticMemoryTranslationPlugin
 2017-06-01 17:54:56 +02:00
Charles Papon
ac16558b6b Add haltItByOther 
Axi4, remove some pipelining
 2017-05-30 17:49:29 +02:00
Charles Papon
6b62d8da52 VexRiscv in Briey SoC is working on FPGA (including jtag debugging) 2017-05-29 21:17:14 +02:00
Charles Papon
213e154b40 Fix regression test debugPlugin bus 2017-05-28 17:41:09 +02:00
Charles Papon
8dddc7e334 GDB + openOCD successfully connect ! 2017-05-25 13:36:54 +02:00
Charles Papon
75f6b78daf OpenOCD successfuly connected to target 2017-05-24 23:53:31 +02:00
Charles Papon
1efed60307 Fix DebugPlugin 
Add DebugPlugin regression (PASS)
 2017-05-22 19:23:11 +02:00
Charles Papon
cc875d1c0b Add TCP server socket to manage debug access from openOCD (as instance) 2017-05-22 00:42:19 +02:00
Charles Papon
5cda2632df Start implementing debugPlugin test infrastructures 2017-05-21 23:50:40 +02:00
Charles Papon
9995c5109d move tests 2017-05-21 16:53:48 +02:00
Charles Papon
6c1d953647 DebugPlugin fully implemented 2017-05-20 18:15:15 +02:00
Charles Papon
619739d33a preliminary DebugPlugin 2017-05-20 15:16:45 +02:00
Charles Papon
a5364ad001 Add flush support instruction into the instruction cache 2017-05-19 11:20:33 +02:00
Charles Papon
736478ff1d CsrPlugin now catch illegal CSR access (wrong address + to low privilege level) 2017-05-09 00:40:44 +02:00
Charles Papon
fe184636dd Improve CsrPlugin FMax 2017-05-08 22:59:05 +02:00
Charles Papon
c69fdf7987 Add basics of the USER mode to CsrPlugin 2017-05-07 23:41:54 +02:00
Charles Papon
579e93bb5a Rename MachineCsr plugin into CsrPlugin 2017-05-07 22:26:17 +02:00
Charles Papon
392f3a7d8c Add PrivilegeService (User) (not implemented) 
Split caches from their plugins file
 2017-05-07 20:16:41 +02:00
Charles Papon
a51c27970b Add opcode for clean/invalidate the datacache 
Change mmu opcodes
 2017-05-07 16:02:55 +02:00
Charles Papon
4d6a6fbb02 Fix Instruction Data cache exceptions 
Pass all tests including CSR/FreeRTOS
 2017-05-07 12:51:47 +02:00
Charles Papon
ca1bc9cf69 DataCache plugin now support all exceptions 2017-05-07 10:44:41 +02:00
Charles Papon
5ba8ab7947 DataCache add invalidate/clean/invalidateClean on a virtual address/way 2017-05-05 00:43:41 +02:00
Charles Papon
48a5dc8e79 DCache move the exception bus outside the cache component 2017-05-04 21:01:08 +02:00
Charles Papon
534a4c3494 mmu working for instruction and data bus (both tested) 2017-05-03 18:42:54 +02:00