45e67ccf56
sync
2021-04-26 11:10:55 +02:00
0a0998fcea
#176 fix typo
2021-04-22 14:02:46 +02:00
32e4ea406f
update #176 when DebugPlugin ebreak are enabled it disable CsrPlugin ebreak. Also, DebugPlugin ebreak can be disabled via the debug bus.
2021-04-22 13:59:33 +02:00
bfe65da1eb
implement #176 DebugPlugin.allowEBreak is now disabled until the debug bus is used.
2021-04-20 23:23:18 +02:00
79bc09e69a
Decouple PMP and CSR plugins
2021-04-13 08:35:07 +02:00
15137742fc
Merge branch 'dev' into new_pmp
2021-04-12 13:23:10 +02:00
b41db0af93
Prevent PMP access from U-mode, fix tests
2021-04-12 13:20:15 +02:00
bf399cc927
Initial commit of optimized PMP plugin
2021-04-12 13:20:15 +02:00
36c896f95b
Update CFU immed field to use sext([31:24]) to match spec.
...
Signed-off-by: Tim Callahan <tcal@google.com>
2021-04-02 13:16:53 -07:00
66f5c3079b
CfuPlugin names fixes
2021-04-02 12:50:21 -07:00
73893ce5d9
CfuPlugin names fixes
2021-04-02 09:20:26 +02:00
a42c089119
IBusSimplePlugin ensure AHB persistance
2021-03-31 19:03:38 +02:00
9ac6625ef3
FpuCore improve FMA rounding
2021-03-29 16:31:18 +02:00
9462496386
Add rvc support and fix rvc with FPU
2021-03-25 14:14:19 +01:00
6f481f51ef
Fetcher.decompressor ensure that the decoded instruction do not mutate when the pipeline is stalled (fix FPU cmd fork for rvc without injector stage)
2021-03-25 14:13:12 +01:00
21c91c6b70
fpu now lift wfi
2021-03-24 16:21:37 +01:00
925edd160e
RVC implement RVF RVD
...
Rework RVC_GEN
2021-03-24 12:04:27 +01:00
8495fe3dde
Attempt at supporting C (ompressed) and F/D (floating-point) together
2021-03-24 11:07:09 +01:00
da458dea7e
litex cluster add cpuPerFpu option
2021-03-23 20:00:50 +01:00
80f64f0f9f
litex better pipelining for better fmax, create one FPU for each 4 cores
2021-03-18 11:10:22 +01:00
6956db2b21
fpu add schedulerM2sPipe optino
2021-03-18 11:10:22 +01:00
099dea743b
fpu cleanup
2021-03-18 10:54:51 +01:00
f6e620196d
litex add fpu suport
2021-03-17 13:19:41 +01:00
e23687c45d
Handle ClockDomain improvements
2021-03-16 14:46:30 +01:00
02c572b6f1
fpu improve FMax and add asyncronus regfile support
2021-03-16 14:45:59 +01:00
5aa1f2e996
fpu improve pipline cycles
2021-03-15 17:27:14 +01:00
341c159d06
data cache relax assert into error
2021-03-15 14:43:22 +01:00
3a34b8dae2
Merge branch 'dev' into fiber
...
# Conflicts:
# src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
# src/main/scala/vexriscv/plugin/MulPlugin.scala
2021-03-15 10:35:02 +01:00
ff4e5e4666
wipe generator
2021-03-11 18:02:02 +01:00
adc37b269c
FpuPlugin.pending is now 6 bits
2021-03-11 13:06:50 +01:00
845cfcb966
DebugPlugin.fromBscane2 added
2021-03-10 20:35:44 +01:00
67d2f72a4b
fiber sync
2021-03-07 20:43:02 +01:00
e384bfe145
fiber update
2021-03-05 22:04:20 +01:00
fd234bbf9e
fix cfu gen error
2021-03-05 09:41:05 +01:00
aee8841438
CFU ensure that CFU_IN_FLIGHT do not produce false positive when the pipeline is stuck
2021-03-05 09:41:05 +01:00
ec507308e7
fix cfu gen error
2021-03-04 20:29:33 +01:00
bdc52097b6
CFU ensure that CFU_IN_FLIGHT do not produce false positive when the pipeline is stuck
2021-03-04 20:15:01 +01:00
0530d22a1d
sync
2021-03-04 16:06:18 +01:00
caf1bde49b
Add MuraxAsicBlackBox example
2021-03-04 10:16:45 +01:00
4bdab667cc
fpu fix cmd / commit race condition
2021-03-02 19:39:55 +01:00
636d53cf63
fpu now track commits using a counter per pipeline per port
2021-03-02 16:13:12 +01:00
81c193af1f
Improve subnormal/normal rounding
2021-02-26 16:32:42 +01:00
de81da36eb
Fpu fix a few div special cases
2021-02-25 19:39:57 +01:00
de09ed3fcb
fpu added exact div/sqrt implementations using iterative approaches
2021-02-25 15:28:38 +01:00
be81cc1e0e
CfuPlugin.response_ok removed
2021-02-23 12:23:48 +01:00
47673863fb
fpu test cleaning
2021-02-22 19:27:55 +01:00
b1f4c06d4e
fpu fix arbitration/lock bugs
...
add getVexRiscvRegressionArgs
2021-02-22 19:27:26 +01:00
a6e89fe05c
fpu vex regression goldenModel can now assert FPU interface
2021-02-19 17:55:56 +01:00
3f226b758c
fpu fix exception flag handeling
2021-02-19 13:03:48 +01:00
e504afbf18
fpu integration wip, got mandelbrot to work in linux with no inline (crash when inlined)
2021-02-19 11:26:28 +01:00
8537d18b16
fpu improve fmax
2021-02-17 16:35:52 +01:00
1e647f799c
fpu Fix VexRiscv integration and add software f64 tests (pass)
2021-02-17 12:33:27 +01:00
06b7a91de4
MulPlugin fix buffer interraction with partial regfile bypass
2021-02-17 11:35:17 +01:00
f180ba2fc9
fpu double fixes
...
DataCache now support wide load/store
2021-02-16 15:38:51 +01:00
8b2a2afb6f
VexRIscvSmpCluster add options
2021-02-16 14:42:31 +01:00
1752b9e6d6
DataCache.toBmb with aggregation sync path pipelined
2021-02-16 14:17:21 +01:00
fe690528f7
MulPlugin.outputBuffer feature added
2021-02-16 14:16:57 +01:00
3b99090879
VexRiscvConfig.get added
2021-02-16 14:15:20 +01:00
7d3b35c32c
fpu f64/f32 pass all tests
2021-02-12 14:48:44 +01:00
9a25a12879
fpu add FCVT_X_X
2021-02-11 17:40:35 +01:00
82dfd10dba
fpu fix f32 tests for f64 fpu
2021-02-11 16:42:17 +01:00
b6eda1ad7a
fpu f64 load/store/mv/mul seems ok
2021-02-11 16:07:47 +01:00
e97c2de837
fpu f64 wip
2021-02-10 19:27:26 +01:00
88dffc21f7
fpu f64 wip
2021-02-10 13:20:17 +01:00
889cc5fde2
fpu refractoring
2021-02-10 12:16:56 +01:00
1fe993ad10
fpu fixed corner cases, FpuPlugin coupling, pass rv-test excepted div (accuracy), can run C sinf successfully
2021-02-09 18:35:47 +01:00
bf6a64b6b5
fpu sgnj / fclass / fmv pass
2021-02-08 15:29:50 +01:00
bf0829231d
fpu min max pass
2021-02-06 14:08:21 +01:00
008fadeaa9
fpu eq lt le pass testfloat
2021-02-06 13:20:27 +01:00
6170243283
fpu got exception flag right for add/sub/mul/i2f/f2i
2021-02-05 16:24:14 +01:00
f278900cbe
VexRiscvSmpCluster can now set regfile read kind
2021-02-05 11:09:18 +01:00
0f1ca72171
fix synthesis bench
2021-02-04 12:43:31 +01:00
936e5823dc
fpu test wip
2021-02-04 12:41:49 +01:00
3710fd3492
fix synthesis bench
2021-02-04 12:41:31 +01:00
02b5b9b05c
fpu load subnormal and i2f now use single cycle shifter
2021-02-03 16:48:09 +01:00
8e7e736e3e
Merge branch 'dev' into fpu
...
# Conflicts:
# src/main/scala/vexriscv/Riscv.scala
# src/main/scala/vexriscv/ip/fpu/FpuCore.scala
# src/main/scala/vexriscv/ip/fpu/Interface.scala
# src/test/scala/vexriscv/ip/fpu/FpuTest.scala
2021-02-03 16:06:17 +01:00
8eb8356dea
fpu wip
2021-02-03 14:28:02 +01:00
1d0eecdcb0
fpu f2i rounding ok and full shifter
2021-02-03 14:27:52 +01:00
ef011fa0d4
fpu moved 1 bit from round to mantissa
2021-02-02 11:29:35 +01:00
a87cb202b1
fpu i2f rounding ok
2021-02-01 16:12:38 +01:00
6aa6191240
Merge branch 'master' into dev
...
# Conflicts:
# build.sbt
# src/main/scala/vexriscv/Riscv.scala
# src/main/scala/vexriscv/ip/DataCache.scala
# src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
# src/main/scala/vexriscv/plugin/MmuPlugin.scala
# src/test/cpp/regression/makefile
# src/test/scala/vexriscv/TestIndividualFeatures.scala
2021-01-30 20:30:21 +01:00
c51b0fcafe
fpu mul now pass all roundings
2021-01-29 22:30:19 +01:00
0997592768
fpu mul sems all good excepted subnormal rounding
2021-01-29 16:13:49 +01:00
3c4df1e963
fpu moved overflow rounding to writeback
2021-01-29 14:37:52 +01:00
fc3e6a6d0a
fpu add rounding is ok excepted infinity result
2021-01-28 20:26:43 +01:00
1ae84ea83b
fpu added proper rounding for add (need to manage substraction)
2021-01-28 00:25:16 +01:00
195e4c422d
fpu now integrate f2i shifter withing the subnormal shifter
2021-01-27 12:11:30 +01:00
444bcdba0a
fpu merged i2f with load pipeline
2021-01-26 15:28:09 +01:00
3334364f5f
fpu added more tests for min max sqrt div
2021-01-26 12:50:23 +01:00
f818fb3ba4
fpu got proper subnormal support, pass add/mul
2021-01-26 10:49:53 +01:00
d6e8a5ef22
VexRiscvSmpLitex options refractoring
2021-01-23 20:16:58 +01:00
ce143e06f2
VexRiscvSmpLitex --in-order-decoder --wishbone-memory added
2021-01-23 17:48:34 +01:00
bdb5bc1180
fpu div implement some special values handeling
2021-01-22 20:47:31 +01:00
7d79685fe2
fpu mul now support special floats values and better rounding
2021-01-22 18:15:45 +01:00
4bd637cf88
fpu add now support special floats values and better rounding
2021-01-22 14:55:37 +01:00
bcd140fc42
Add vexRiscvConfig.withMmu option
2021-01-21 13:28:09 +01:00
ccd13b7e9e
fpu zero/nan wip
2021-01-21 12:13:25 +01:00
6c13e6458f
Remove registers storing PMP region bounds
2021-01-20 14:27:38 +01:00
ac5844f393
fpu add signed i2f/f2i
2021-01-20 13:15:29 +01:00
15d79ef330
fpu implement fclass and args for sub, fma, max, fcmp, fsgnj
2021-01-20 12:01:08 +01:00
828ea96006
PMP registers are now WARL
2021-01-20 09:27:35 +01:00
11349a71fa
fpu FpuPlugin now implement all instructions.
...
Remains the FPuCore to implement cmd.arg and floating point corner cases
2021-01-19 17:57:41 +01:00
9f18045329
fpu add sstatus.fs
2021-01-19 16:06:16 +01:00
a7d148d0ff
fpu add vex csr
2021-01-19 15:53:11 +01:00
f826a2ce51
fpu completion interface added + refractoring
2021-01-19 15:13:13 +01:00
8c4fae8bf2
fpu add min/sgnj/fmv
2021-01-19 13:27:42 +01:00
d7220031d4
fpu vex i2f works
2021-01-18 17:18:01 +01:00
d4b877d415
fpu vex cmp/fle works
2021-01-18 15:09:30 +01:00
6cb498cdb2
fpu merge load/commit
2021-01-18 13:09:08 +01:00
a9d8c0a19f
fpu wip
2021-01-18 11:38:26 +01:00
3cda7c1f1b
fpu wip
2021-01-15 14:03:37 +01:00
04499c0b76
FPU sqrt functional
2021-01-14 18:33:24 +01:00
85dd5dbf8e
fpu div functional, sqrt wip
2021-01-14 15:56:56 +01:00
5e6c645461
Distinguish between page faults from MMU and access faults from PMP
2021-01-14 09:45:38 +01:00
8761d0d9ee
FpuCore can add/mul/fma/store/load
2021-01-13 18:28:26 +01:00
6e0be6e18c
Cfu add state index and cfu index
2021-01-11 13:44:04 +01:00
930bdf9dda
DataCache increase syncPendingMax to 32 and use a sync queue instead of async one
2021-01-04 10:59:21 +01:00
780ad01ac0
Add AES-instruction support
2020-12-21 11:52:55 +01:00
c59499ec03
typo
2020-12-11 14:13:33 +01:00
eaff52b264
Add comments to the AesPlugin
2020-12-11 13:51:10 +01:00
6da09967f8
Add comments to the AesPlugin
2020-12-11 13:46:55 +01:00
7d699dcc13
Remove PMP from MachineOs test defaults
2020-12-10 09:42:27 +01:00
f2ce2eab00
PMP plugin passes regression tests
2020-12-07 12:04:45 +01:00
763eebeeba
Add TOR support, tests pass on GenZephyr
2020-12-04 17:13:31 +01:00
5cb5061d9b
PMP passes test with GenZephyr, but pipeline flushes have been disabled
2020-12-03 17:29:31 +01:00
9a6931a54c
CfuPlugin improve writeback buffering
2020-12-03 16:21:52 +01:00
987de8fb6a
Lock PMP address registers in golden model
2020-12-02 14:18:17 +01:00
14c39a0070
Merge remote-tracking branch 'upstream/master' into pmp
2020-12-02 14:08:32 +01:00
872aa19d83
Add PMP to golden model
2020-12-02 12:27:26 +01:00
d5b1a8f565
Add PMP test to regression suite
2020-12-01 18:38:06 +01:00
45ff78d068
VexRiscvSmpClusterGen.dBusCmdMasterPipe option added
2020-12-01 13:51:10 +01:00
c5023ad973
Add PMP regression test
2020-12-01 09:10:24 +01:00
2d0ebf1ef5
Flush pipeline after PMP CSR writes
2020-11-25 15:38:34 +01:00
e0ae46e794
Fix Csr ReadWrite interration with DBusCachedPlugin execute halt
...
# Conflicts:
# src/main/scala/vexriscv/plugin/CsrPlugin.scala
2020-11-18 14:43:24 +01:00
832218dbec
DBusCachedPlugin increase pendingMax to 64 to hide memory latency when saving a full context
2020-11-16 12:38:29 +01:00
ba523c627a
Fix Csr ReadWrite interration with DBusCachedPlugin execute halt
2020-11-16 12:37:48 +01:00
c1b0869c21
AesPlugin is now little endian
2020-11-12 15:07:27 +01:00
1b2a2ebaca
DBusCachedPlugin miss decoded aquire fix
2020-11-12 15:07:07 +01:00
05e725174c
AesPlugin added, work with dropbear encryption, seem ok for decryption (barmetal)
2020-11-02 17:14:52 +01:00
9abe19317d
RegFilePlugin.x0Init do less assumption on other plugin behaviour
2020-11-02 17:01:17 +01:00
97fe279f7b
Enable PMP register lock
2020-10-29 13:37:21 +01:00
dc9246715d
Do not allow jtag ebreak outside machine mode
2020-10-28 13:00:16 +01:00
4209dc2792
Fix CsrPlugin privilege crossing
2020-10-28 13:00:15 +01:00
576e21d75d
Do not allow jtag ebreak outside machine mode
2020-10-28 12:58:24 +01:00
abebeaea1f
Fix CsrPlugin privilege crossing
2020-10-28 12:57:20 +01:00
fc2c8a7c37
Initial commit of PMP plugin
2020-10-27 09:38:58 +01:00
fe342c347c
CfuBusParameter has now a few default values
2020-10-23 11:06:24 +02:00
6c8e97f825
Update big endian instruction encoding
...
Between draft-20181101-ebe1ca4 and draft-20190622-6993896 of the
RISC-V Instruction Set Manual, the wording was changed from requiring
"natural endianness" of instruction parcels to require them to be
little endian.
Update the big endian instruction pipe to reflect the newer requirement.
2020-10-20 18:05:31 +02:00
4ece59385d
DataCache split redo / refilling execute stage halt
2020-10-19 18:12:20 +02:00
ec55187033
improve LightShifterPlugin arbitration halt timings
2020-10-09 11:37:48 +02:00
bbaa0520c0
Fix UserInterruptPlugin interrupt enable
2020-10-09 10:45:23 +02:00
72f85ef6c0
Merge remote-tracking branch 'origin/dev' into dev-asid
2020-10-04 19:53:29 +08:00
65e6f6054b
Add ASID field to SATP
...
ASID field is missing from the SATP which causes compatibility
issues with Xous.
While this patch resolves the Xous issue, it has not been tested
on Linux.
2020-10-04 15:34:58 +08:00
98de02051e
Merge pull request #135 from zeldin/bigendian
...
Add support for big endian byte ordering
2020-10-01 16:43:00 +02:00
3f5e771a5c
dbus mmu access improvement
2020-09-17 22:06:29 +02:00
de820daf74
add earlyBranch option to Smp config
2020-09-13 18:33:06 +02:00
49488d19af
pipeline data cache unaligned access check
2020-09-07 12:01:11 +02:00
8e466dd13c
Add support for RV32E in RegFilePlugin
...
The RV32E extension removes registers x16-x31 from the ISA. This
is useful when compiling with -mem2reg to save on BRAMs. On iCE40
HX8K this option saves 1285 LC:s, which also improves the routing
situation, when using -mem2reg.
Note that the illegal instruction exception required by the RV32E
specification for accesses to registers x16-x31 is not implemented.
2020-09-06 17:05:31 +02:00
4c3cad97d3
fix CfuPlugin generation
2020-09-04 10:36:12 +02:00
c489143442
Add support for big endian byte ordering
2020-08-30 15:17:09 +02:00
7dcaa0c390
VexRiscvSmpCluster now avoid useless decoder for plic/clint
2020-08-13 11:26:11 +02:00
69d5ba239a
Smp config now initialise regfile using logic
2020-07-28 16:15:17 +02:00
cc423cbe49
Litex cluster add DMA sel feature
2020-07-21 19:42:27 +02:00
15bda15bc9
Litex cluster can now set cache layout
2020-07-21 19:35:56 +02:00
9f62f37538
improve LitexCluster area for single core configuration
2020-07-21 15:45:02 +02:00
da666ade49
Add VexRiscvLitexSmpClusterCmdGen
2020-07-21 15:07:32 +02:00
fe5401f835
BmbGenerators refractoring (bus -> ctrl)
2020-07-16 13:04:25 +02:00
da73317912
Cleanup BmbGenerators
2020-07-15 20:51:46 +02:00
5f0aec7570
BmbInterconnectGenerator refractoring
2020-07-15 17:03:05 +02:00
d0a572de98
Add openroad config
2020-07-08 01:37:10 +02:00
32f778613f
DBusCachedPlugin now support asyncTagMemory
2020-07-08 01:36:58 +02:00
60ee7e2b4c
Better VexRiscvSmpCluster config
2020-07-08 01:36:40 +02:00
51070d0e69
Fix MmuPlugin when used in multi stage config
2020-07-05 13:17:39 +02:00
06584518da
Remove CsrPlugin redoInterface combinatorial depedency from execut_isStuck
2020-07-05 13:17:07 +02:00
a404078117
Few fixes
2020-07-05 13:16:39 +02:00
c51e25f8c4
Litex SoC add coherent DMA master
2020-07-05 13:15:44 +02:00
32539dfe6d
Got VexRiscvSmpLitexCluster refractoring to work
2020-06-30 22:29:33 +02:00
0da94ac66f
Bring back smp cluster parameters
2020-06-29 15:49:01 +02:00
062509deee
Update Bmb brides and comment out SmpCluster for now
2020-06-29 11:44:10 +02:00
c12f9a378d
Fix inv regression
2020-06-20 13:18:46 +02:00
f0f2cf61da
D$ inv/ack are now fragment, which ease serialisation of wider invalidations
2020-06-19 15:57:56 +02:00
c18bc12cb2
Fix DebugPlugin.fromBmb
2020-06-19 15:57:21 +02:00
490c1f6b02
cleanup of old todo
2020-06-19 15:56:45 +02:00
b0cd88c462
SmpCluster now with proper jtag and plic
2020-06-12 16:18:41 +02:00
cb5597818d
Fix d$ generation crash
2020-06-07 11:29:07 +02:00
1f9fce6388
Fix d$ uncached writes exception handeling
2020-06-06 22:12:37 +02:00
760d2f74d0
Update litex cluster to implement utime
2020-06-05 13:31:24 +02:00
d6455817e7
smp cluster now have 2w*4KB of d$ , no more rdtime emulation
2020-06-05 10:43:03 +02:00
71760ea372
CsrPlugin now support utime csr to avoid emulation
2020-06-05 10:43:03 +02:00
3dafe8708b
Cfu update
2020-06-05 10:43:03 +02:00
0668046407
More smp cluster profiling
2020-06-05 10:40:51 +02:00
97c2dc270c
Fix typo
2020-06-04 10:11:30 +02:00
89c13bedbd
Fix litex smp cluster sim
2020-06-03 16:31:54 +02:00
73f88e47cb
Fix BmbToLitexDram coherency
2020-06-03 16:31:54 +02:00
db50f04653
Add litexMpCluster
2020-06-03 16:31:54 +02:00
08189ee907
DebugPlugin now support Bmb
2020-06-02 19:13:55 +02:00
2942d0652a
fix Briey verilator
2020-06-01 11:18:25 +02:00
5e5c730959
Add LitexSmpDevCluster with per cpu dedicated litedram ports
2020-05-29 10:56:55 +02:00
bc4a2c3747
Fix SmpCluster jtag
2020-05-27 14:19:37 +02:00
18cce053a3
Improve SingleInstructionLimiterPlugin to also include fetch stages
2020-05-27 14:19:17 +02:00
a64fd9cf3b
Add CsrPlugin external hartid
...
d$ rsp/sync now decrement pendings by signal amount
2020-05-20 13:49:10 +02:00
b901651ab5
Add default value of NONE to uinstret CSR.
2020-05-19 14:48:35 -07:00
c74b03b4de
Add uinstret support.
2020-05-19 13:40:46 -07:00
cf60989ae1
Litex smp cluster now blackboxify d$ data ram
2020-05-14 00:05:54 +02:00
42fef8bbcd
Smp cluster now use i$ reduceBankWidth
2020-05-12 23:59:38 +02:00
685c914227
Add i$ reduceBankWidth to take advantage of multi way by remaping the data location to reduce on chip ram data width
2020-05-12 23:59:38 +02:00
0471c7ad76
Fix machineCsr test
2020-05-12 23:55:47 +02:00
cb44a474fc
more smp cluster profiling
2020-05-12 13:25:55 +02:00
63511b19a2
smp cluster add more profiling
2020-05-11 10:35:24 +02:00
b592b0bff8
Add regression TRACE_SPORADIC, LINUX_SOC_SMP
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regression golden model now properly sync dut exceptions
2020-05-09 17:00:13 +02:00
0a159f06b2
update smp config
2020-05-07 22:50:36 +02:00
0e76cf9ac8
i$ now support multi cycle MMU
2020-05-07 22:50:25 +02:00
41ee8fd226
MmuPlugin now support multiple stages, D$ can now take advantage of that
2020-05-07 13:37:53 +02:00
8e025aeeaa
more litex smp cluster pipelining
2020-05-07 13:18:11 +02:00
fc0f3a2020
cleanup mmu interface
2020-05-06 18:05:20 +02:00
6323caf265
MMU now allow $ to match tag against tlb pyhsical values directly
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D$ retiming
D$ directTlbHit feature added for better timings
2020-05-06 17:09:46 +02:00
ed4a89e4af
more pipelineing in Litex SMP cluster interconnect
2020-05-06 17:06:45 +02:00
8043feebd5
More VexRiscv smp cluster probes
2020-05-06 17:06:17 +02:00
09724e907b
play around with CSR synthesis impact on design size
2020-05-05 00:32:59 +02:00
c16f2ed787
Add probes in SmpCluster sim
2020-05-04 12:54:28 +02:00
b0f7f37ac8
D$ now support memDataWidth > 32
2020-05-04 12:54:16 +02:00
93b386e16e
litex smp cluster now use OO decoder
2020-05-02 23:44:58 +02:00
f0745eb0d9
update SMP line size to 64 bytes
2020-05-02 23:44:27 +02:00
09ac23b78f
Fix SMP fence lock when 4 stages CPU
2020-05-01 12:45:16 +02:00
f5f30615ba
Got litex SMP cluster to work on FPGA
2020-05-01 11:14:52 +02:00
dc0da9662a
Update SMP fence (final)
2020-05-01 11:14:11 +02:00
7c50fa6d55
SmpCluster now use i$ line of 64 bytes
2020-04-29 14:03:00 +02:00
9e9d28bfa6
d$ now implement consistancy hazard by using writeback redo
2020-04-29 14:02:41 +02:00
86e0cbc1f3
I$ with memDataWidth > cpuDataWidth now mux memWords into cpuWords before the decode stage by default. Add twoCycleRamInnerMux option to move that to the decode stage
2020-04-29 13:59:43 +02:00
7b80e1fc30
Set SMP workspace to use i$ memDataWidth of 128 bits
2020-04-28 22:11:41 +02:00
eee9927baf
IBusCachedPlugin now support memory data width multiple of 32
2020-04-28 22:10:56 +02:00
03a0445775
Fix SMP for configuration without writeback stage.
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Include SMP core into the single core tests regressions
2020-04-28 15:50:20 +02:00
4a49b23636
Fix regression
2020-04-28 14:38:27 +02:00
3ba509931c
Add VexRiscvSmpLitexCluster with the required pipelining to get proper FMax
2020-04-27 17:38:06 +02:00
5fd0b220cd
CsrPlugin add openSbi config
2020-04-27 17:37:30 +02:00
0c59dd9ed3
SMP fence now ensure ordering for all kinds of memory transfers
2020-04-27 17:37:15 +02:00
3fb123a64a
fix withStall
2020-04-21 21:20:54 +02:00
3885e52bb7
Merge remote-tracking branch 'origin/dev' into smp
2020-04-21 17:21:48 +02:00
056bf63866
Add more consistancy tests
2020-04-21 16:03:03 +02:00
b389878d23
Add smp consistency check, fix VexRiscv invalidation read during write hazard logic
2020-04-21 12:18:10 +02:00
0e55caacab
deduplicae VexRiscv wishbone
2020-04-21 10:33:51 +02:00
b383b4b98b
Add commented usage of fromXilinxBscane2
2020-04-20 12:13:12 +02:00
8e8b64feaa
Got full linux / buildroot to boot in 4 cpu config
2020-04-19 19:49:26 +02:00
a1b6353d6b
workaround AMO LR/SC consistancy issue, but that need a proper fix
2020-04-19 19:48:57 +02:00
ad2d2e411a
Add tap less debug plugin bridges
2020-04-19 17:56:33 +02:00
af128ec9eb
revert to 4 cpu
2020-04-18 01:27:35 +02:00
4a49e6d91f
initialize the clint in sim
2020-04-18 01:26:31 +02:00
befecc7ed6
cleaning
2020-04-18 00:51:57 +02:00
8c0e534c6b
Add openSBI test, seem to work fine
2020-04-18 00:51:47 +02:00
d5a52caab8
fix smp test barrier
2020-04-16 17:27:27 +02:00
Dolu1990
Samuel Lindemer
Tim Callahan
Romain Dolbeau
Marcus Comstedt
bunnie
Tom Verbeure