4cd3f65296
Add official RISC-V debug support (WIP, but can already load / step / run code via openocd telnet)
2022-10-19 12:36:45 +02:00
959e48a353
Fpu now set csr status fs on FPU csr write
2022-10-06 11:13:57 +02:00
fda7da00c2
add litex --wishbone-force-32b
2022-09-06 11:19:29 +02:00
54412bde30
getDrivingReg() update
2022-07-21 09:10:26 +02:00
b1252f47de
csr opensbi now enable ebreak
2022-06-13 16:34:49 +02:00
1303c0ca7c
CfuPlugin.withEnable added
2022-06-09 17:57:31 +02:00
0f6d0f022c
VexRiscvBmbGenerator now also report bytesPerLine
2022-05-24 12:37:31 +02:00
e6dfcac0be
Add D$ single line flush support
2022-05-24 12:13:37 +02:00
4c4913c703
Fix MPP to only retain legal values
2022-05-24 11:14:34 +02:00
209fc719e8
VexRiscvBmbGenerator export more info
2022-05-24 10:19:35 +02:00
48cf4120f2
Add VexRiscvSmpCluster forceMisa/forceMscratch
2022-05-23 15:49:32 +02:00
0872852387
Fix DYNAMIC_TARGET / debug plugin interation corrupting the recoded next pc durring step by step #254
2022-05-17 20:44:17 +02:00
a553d3b476
Fix DYNAMIC_TARGET from triggering fetch missprediction while in debug mode #254
2022-05-17 15:27:50 +02:00
78f0a7f13e
Fix CfuPlugin/VfuPlugin fork duplication
...
https://github.com/google/CFU-Playground/issues/582
2022-05-16 10:36:21 +02:00
8df2dcbd40
Fix RVC step by step triggering next instruction branch predictor
2022-05-11 14:10:32 +02:00
ea7a18c7f4
plugin: caches: Fix "Can't resolve the literal value of"
...
Both registers were initialized with unsigned integers without a value.
This triggered:
[error] Exception in thread "main" spinal.core.SpinalExit:
[error] Can't resolve the literal value of (..._rspCounter : UInt[32 bits])
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
2022-04-20 11:19:34 +02:00
3b8270b82b
#241 Fix Murax/Briey TB timeouts
2022-04-11 11:59:41 +02:00
db34033593
#240 Code generation now warn against cpu generation without illegal instruction catch and ebreak being disabled, as it may make crash some software, ex : rust
2022-04-08 11:09:14 +02:00
2d2017465e
Fix reset vector of GenCustomSimdAdd
...
With the old reset vector half of the tests fail since
they expect the CPU to start at 0x80000000.
(e.g. I-IO, I-NOP, I-LUI, etc.)
2022-04-03 02:55:42 +02:00
ccff48f872
deprecated Data.keep
2022-03-30 16:17:57 +02:00
4bddb091ae
Update CFU example
2022-03-23 18:58:18 +01:00
5dc91a8be4
Add MuraxCfu
2022-03-23 18:54:18 +01:00
b2e61caf9e
CfuPlugin now implement upstream spec
2022-03-23 18:54:07 +01:00
9149c42065
DecoderPlugin now implement forceIllegal API
2022-03-23 18:53:43 +01:00
51b8865b66
Fix VexRiscvSmpClusterGen linux less mhartid
2022-03-18 12:36:05 +01:00
e558b79582
Fix Briey simulation floating rxd blocking the uart #238
2022-02-22 16:15:14 +01:00
807aa98d37
plugin: DBusSimplePlugin: Remove assert
...
This assert triggered sometimes at the beginning of a simulation.
Since it's not really needed anymore, we can remove it.
Signed-off-by: Daniel Schultz <daniel.schultz@aesc-silicon.de>
2022-02-10 19:55:08 +01:00
5714680278
Merge branch 'master' into dev
...
# Conflicts:
# build.sbt
2022-02-05 11:32:40 +01:00
8b2f107d46
verilator++
2022-02-04 15:10:57 +01:00
57dd80a566
plugin: CsrPlugin: Init cycle and instret registers
...
Both counters are initialized with "randBoot()". This is fine for FPGA
designs because the registers can be loaded with default values but
ASIC designs require to load the value during a reset.
Since both counters require to start at 0 (read-only CSR registers),
change both registers from "randBoot()" to "init(0)".
Error:
reg [63:0] CsrPlugin_mcycle = 64'b0000000...00000000000;
|
Warning : Ignoring unsynthesizable construct. [VLOGPT-37]
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
2022-01-26 08:59:03 +01:00
9c34a1fd2e
updated related to JtagInstructionWrapper.ignoreWidth
2022-01-14 09:59:24 +01:00
b8e904e43f
syncronize golden model with dut for lrsc reservation
2022-01-10 19:55:28 +01:00
6e77f32087
sim golden model lrsc reservation sync
2022-01-10 16:08:38 +01:00
da53de360f
Fix lrsc from last commit
2022-01-10 14:21:20 +01:00
f46ad43f39
DataCache.withInternalLrSc reserved clearing fix
2022-01-10 13:39:41 +01:00
fe6c391fe4
Fix typo in Linux.scala
...
Correct "machime" to "machine".
2022-01-04 16:31:23 +08:00
34e5cafb75
Enable scala 2.13 compatibility
2021-12-20 09:38:35 +01:00
4824827b7e
Enable scala 2.13 compatibility
2021-12-20 09:38:02 +01:00
dd12047aa7
Merge branch dev (SpinalHDL 1.6.1)
2021-12-15 09:22:46 +01:00
411d946a58
Update DebugPlugin.scala
...
Add readback of the hardware breakpoint values.
A new parameter is added to the plugin to switch readback on and off.
2021-11-11 12:12:23 +01:00
acf14385d8
#213 disable pmp test with region overlapping
2021-10-22 17:24:51 +02:00
a3807660e3
pmp perm: revert to mux for priority
2021-10-19 11:40:39 +08:00
df03c99ab2
pmp_setter: fix mask generation
2021-10-19 11:39:25 +08:00
c3c3a94c5d
IBusSimplePlugin can now use a Vec based buffer
2021-10-13 16:26:16 +02:00
97a3c1955b
VexRiscvSmpCluster add d$ i$ less arg
2021-10-11 11:57:39 +02:00
35754a0709
Fix BrieySim (SpinalSim)
2021-09-25 13:28:37 +02:00
8c0fbcadac
Add BrieySim (SpinalSim)
2021-09-25 13:18:55 +02:00
5f5f4afbf2
Briey revert RVC unwanted addition
2021-09-22 15:01:08 +02:00
b807254759
Briey and Murax verilators now use FST instead of VCD
2021-09-22 12:57:27 +02:00
65cda95176
Fix wishbone bridges with datawidth > 32
2021-09-17 09:43:30 +02:00
c1481ae244
update ScopeProperty usages
2021-09-16 19:08:41 +02:00
42bb1ab591
d$ / i$ toWishbone bridges can now be bigger than 32 bits
...
https://github.com/m-labs/VexRiscv-verilog/pull/12
2021-09-15 11:36:51 +02:00
68e704f309
restore avalon d$ tests
2021-09-02 15:42:33 +02:00
efd3cd4737
Merge branch 'master' into dev
2021-09-02 14:16:07 +02:00
cc9f3e753a
Fix d$ toAxi bridge
2021-09-02 14:14:42 +02:00
bc561c30eb
Add PmpPluginOld (support TOR)
2021-09-01 11:27:12 +02:00
5c7e4a0294
#170 wishbone example now set dBusCmdMasterPipe
2021-08-24 23:24:29 +02:00
3deeab42fd
VexRiscvSmpCluster config fix
2021-08-10 12:14:42 +02:00
805bd56077
Fix VexRiscvBmbGenerator.hardwareBreakpointCount default value
2021-07-30 16:51:07 +02:00
671bd30953
Update Bmb invalidate/sync parameters
2021-07-28 13:44:04 +02:00
ba8f5f966a
Vfu typo
2021-07-26 15:27:20 +02:00
b717f228d6
VfuPlugin wip
2021-07-26 15:17:06 +02:00
c242744d02
CfuPlugin now only fork when the rest of the pipeline is hazard free
2021-07-26 14:45:54 +02:00
f3f9b79f9a
VexRiscvSmpCluster earlyShifterInjection added
2021-07-21 18:34:57 +02:00
5fc4125763
Merge branch 'dev'
2021-07-20 11:21:11 +02:00
3028c19389
Fix #191 (data cache toAxi bridge)
2021-07-20 11:20:53 +02:00
5f2fcc7d0f
Merge branch 'dev'
...
(SpinalHDL 1.6.0)
2021-07-20 10:39:09 +02:00
0cdad37fff
VexRiscvSmpClusterGen now implement ebreak
2021-07-11 21:55:33 +02:00
c79357d1b2
VexRiscvSmpClusterGen no support atomic less configs
2021-07-05 12:38:54 +02:00
a380c3a36c
Merge branch 'spinal_1.4.4' into dev
2021-07-05 11:37:53 +02:00
551e76d244
VexRiscvSmpCluster add a few options
2021-07-02 19:04:30 +02:00
df7ac05db9
Update 2.13 compatibility
2021-06-23 11:48:38 +02:00
d67fe72de9
Merge branch 'dev'
...
# Conflicts:
# build.sbt
# src/test/cpp/regression/main.cpp
2021-06-15 15:54:13 +02:00
1497001ebd
Update FpuTest with the new rs1/rs2 store mapping
2021-06-09 13:37:31 +02:00
1ee45eeb0a
More named signals
2021-06-09 11:27:18 +02:00
0e89ebeced
Improve FPU rs1 timings
2021-06-09 11:26:58 +02:00
e1e1be5797
exception code can now be bigger than 4 bits
2021-06-08 12:19:08 +02:00
646911a373
Fix pmp write when there is hazard due to the register file.
2021-06-07 17:30:47 +02:00
87f100dac1
Merge pull request #174 from lindemer/new_pmp
...
New PMP plugin optimized for FPGAs
2021-06-03 20:16:34 +02:00
156a84e76f
Fix PMP FSM halting logic
2021-06-03 13:12:55 +02:00
342b06128f
Combine all the PMP logic into one FSM
2021-06-02 17:12:10 +02:00
2a4ca0b249
PMP CSR writes occur in execute stage
2021-06-02 16:01:30 +02:00
0272d66971
Fix CsrPlugin.redoInterface priority
2021-05-28 16:20:43 +02:00
3a4ab7ad51
Un-pend PMP CSR writes on pipeline flushes
2021-05-28 16:17:19 +02:00
d49f8d1b58
Merge branch 'dev' into new_pmp
2021-05-28 13:56:15 +02:00
24a534acff
All tests passing on new PMP plugin
2021-05-28 13:54:55 +02:00
4490254d3d
Csr/Mmu ensure implement that SFENCE_VMA flush the next instructions
...
SAT flush reworked a bit too
2021-05-28 13:35:52 +02:00
4a2dc0ff5f
Fix granularity control
2021-05-27 15:50:45 +02:00
6471014131
Simplify pmpcfg encoding
2021-05-27 14:34:51 +02:00
4b0763b43d
CsrPlugin.csrMapping now give names to inner signals
2021-05-27 10:40:55 +02:00
a5f66623b7
Add an "allow" property to individual CSRs
2021-05-26 16:34:51 +02:00
61f68f0729
Refactor for new CSR API (PMP reads still broken)
2021-05-26 15:29:27 +02:00
6066d8bc26
CsrPlugin add API to implement CSR in a decoupled way. (very low level api) #174
2021-05-26 11:44:46 +02:00
72328e7bc4
Arty now has RVC enabled !
2021-05-25 15:59:02 +02:00
8122cc9b5e
fixed priority of == & != as seemed logical to get less warnings when building
2021-05-17 18:51:33 +02:00
1c3b9e93a2
Merge pull request #182 from rdolbeau/extra_config
...
Make the [ID]TLB size configurable from Litex
2021-05-12 13:54:27 +02:00
fe739b907a
Bench DecoderPlugin
2021-05-10 10:47:15 +02:00
1bd33a369e
Make the [ID]TLB size configurable from Litex
2021-05-08 07:59:34 -04:00
e78c0546a0
fix #178
2021-05-04 21:09:42 +02:00
fa2899a1a2
Merge branch 'debugPlugin' into dev
2021-04-26 11:11:38 +02:00
45e67ccf56
sync
2021-04-26 11:10:55 +02:00
0a0998fcea
#176 fix typo
2021-04-22 14:02:46 +02:00
32e4ea406f
update #176 when DebugPlugin ebreak are enabled it disable CsrPlugin ebreak. Also, DebugPlugin ebreak can be disabled via the debug bus.
2021-04-22 13:59:33 +02:00
bfe65da1eb
implement #176 DebugPlugin.allowEBreak is now disabled until the debug bus is used.
2021-04-20 23:23:18 +02:00
79bc09e69a
Decouple PMP and CSR plugins
2021-04-13 08:35:07 +02:00
15137742fc
Merge branch 'dev' into new_pmp
2021-04-12 13:23:10 +02:00
b41db0af93
Prevent PMP access from U-mode, fix tests
2021-04-12 13:20:15 +02:00
bf399cc927
Initial commit of optimized PMP plugin
2021-04-12 13:20:15 +02:00
36c896f95b
Update CFU immed field to use sext([31:24]) to match spec.
...
Signed-off-by: Tim Callahan <tcal@google.com>
2021-04-02 13:16:53 -07:00
66f5c3079b
CfuPlugin names fixes
2021-04-02 12:50:21 -07:00
73893ce5d9
CfuPlugin names fixes
2021-04-02 09:20:26 +02:00
a42c089119
IBusSimplePlugin ensure AHB persistance
2021-03-31 19:03:38 +02:00
9ac6625ef3
FpuCore improve FMA rounding
2021-03-29 16:31:18 +02:00
9462496386
Add rvc support and fix rvc with FPU
2021-03-25 14:14:19 +01:00
6f481f51ef
Fetcher.decompressor ensure that the decoded instruction do not mutate when the pipeline is stalled (fix FPU cmd fork for rvc without injector stage)
2021-03-25 14:13:12 +01:00
21c91c6b70
fpu now lift wfi
2021-03-24 16:21:37 +01:00
925edd160e
RVC implement RVF RVD
...
Rework RVC_GEN
2021-03-24 12:04:27 +01:00
8495fe3dde
Attempt at supporting C (ompressed) and F/D (floating-point) together
2021-03-24 11:07:09 +01:00
da458dea7e
litex cluster add cpuPerFpu option
2021-03-23 20:00:50 +01:00
80f64f0f9f
litex better pipelining for better fmax, create one FPU for each 4 cores
2021-03-18 11:10:22 +01:00
6956db2b21
fpu add schedulerM2sPipe optino
2021-03-18 11:10:22 +01:00
099dea743b
fpu cleanup
2021-03-18 10:54:51 +01:00
f6e620196d
litex add fpu suport
2021-03-17 13:19:41 +01:00
e23687c45d
Handle ClockDomain improvements
2021-03-16 14:46:30 +01:00
02c572b6f1
fpu improve FMax and add asyncronus regfile support
2021-03-16 14:45:59 +01:00
5aa1f2e996
fpu improve pipline cycles
2021-03-15 17:27:14 +01:00
341c159d06
data cache relax assert into error
2021-03-15 14:43:22 +01:00
3a34b8dae2
Merge branch 'dev' into fiber
...
# Conflicts:
# src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
# src/main/scala/vexriscv/plugin/MulPlugin.scala
2021-03-15 10:35:02 +01:00
ff4e5e4666
wipe generator
2021-03-11 18:02:02 +01:00
adc37b269c
FpuPlugin.pending is now 6 bits
2021-03-11 13:06:50 +01:00
845cfcb966
DebugPlugin.fromBscane2 added
2021-03-10 20:35:44 +01:00
67d2f72a4b
fiber sync
2021-03-07 20:43:02 +01:00
e384bfe145
fiber update
2021-03-05 22:04:20 +01:00
fd234bbf9e
fix cfu gen error
2021-03-05 09:41:05 +01:00
aee8841438
CFU ensure that CFU_IN_FLIGHT do not produce false positive when the pipeline is stuck
2021-03-05 09:41:05 +01:00
ec507308e7
fix cfu gen error
2021-03-04 20:29:33 +01:00
bdc52097b6
CFU ensure that CFU_IN_FLIGHT do not produce false positive when the pipeline is stuck
2021-03-04 20:15:01 +01:00
0530d22a1d
sync
2021-03-04 16:06:18 +01:00
caf1bde49b
Add MuraxAsicBlackBox example
2021-03-04 10:16:45 +01:00
4bdab667cc
fpu fix cmd / commit race condition
2021-03-02 19:39:55 +01:00
636d53cf63
fpu now track commits using a counter per pipeline per port
2021-03-02 16:13:12 +01:00
81c193af1f
Improve subnormal/normal rounding
2021-02-26 16:32:42 +01:00
de81da36eb
Fpu fix a few div special cases
2021-02-25 19:39:57 +01:00
de09ed3fcb
fpu added exact div/sqrt implementations using iterative approaches
2021-02-25 15:28:38 +01:00
be81cc1e0e
CfuPlugin.response_ok removed
2021-02-23 12:23:48 +01:00
47673863fb
fpu test cleaning
2021-02-22 19:27:55 +01:00
b1f4c06d4e
fpu fix arbitration/lock bugs
...
add getVexRiscvRegressionArgs
2021-02-22 19:27:26 +01:00
a6e89fe05c
fpu vex regression goldenModel can now assert FPU interface
2021-02-19 17:55:56 +01:00
3f226b758c
fpu fix exception flag handeling
2021-02-19 13:03:48 +01:00
e504afbf18
fpu integration wip, got mandelbrot to work in linux with no inline (crash when inlined)
2021-02-19 11:26:28 +01:00
Dolu1990
Daniel Schultz
Andreas Wallner
Daniel Schultz
Daniel Schultz
Oscar Shiang
B.Lang
occheung
Samuel Lindemer
Alexis Marquet
Romain Dolbeau
Tim Callahan