b03b00a5c4
Improve d$ coupled timings
2023-03-03 14:13:51 +01:00
5493c55ab0
Alows Fetcher to have multiple debug injection ports
2023-03-03 09:06:20 +01:00
5f67075e30
Fix FPU with F64 support, not removing mantissa precision from F32 #317
2023-03-01 13:56:25 +01:00
6f76a45e7d
update mmu test
2023-02-23 15:54:39 +01:00
d7e9c726c3
Fix datacache initial flush
2023-02-23 14:42:21 +01:00
c5689e512c
CsrPlugin now provide regression args
2023-02-23 12:00:25 +01:00
a40d5f19b2
Fix MMU A and D flag handeling
2023-02-23 12:00:08 +01:00
344b2d4eda
TestIndividual supervisor missing CSR=yes
2023-02-23 11:59:13 +01:00
9605b663bf
D$ now support thightly coupled ram.
...
Add IBusDBusCachedTightlyCoupledRam plugin
2023-02-22 15:26:14 +01:00
220b599c9a
Fix d$ invalidation when the mmu is enabled
2023-02-22 13:16:02 +01:00
15a665af53
fix too early
2023-02-19 09:51:18 +01:00
a780eec616
Merge branch 'debug-debug' into dev
2023-02-13 10:04:41 +01:00
33e820bdf9
FPU now implement a less pessismitic dirty logic
2023-02-08 15:16:53 +01:00
3ae51cdeb8
Fix fpu csr access on fs===0 now also trap
2023-02-08 14:44:04 +01:00
692f604dd5
Fix VexRiscvSmpClusterGen without linux debug minimal features
2023-02-08 11:28:21 +01:00
cbc89093b3
fpu csr access on fs===0 now also trap
2023-02-07 10:18:08 +01:00
9acc5ddc1c
Fix FPU access trap on fs = 0 #297
2023-02-06 11:44:44 +01:00
fc9a9d25ed
sync
2023-02-06 11:43:49 +01:00
2bc6e70f03
Fix RVC decompressor don't care #296
2023-01-18 15:19:33 +01:00
7d3a862183
Fix Litex cluster scopt update
2023-01-16 18:10:51 +01:00
773f268f37
Fix FPU test syntax
2022-12-01 12:04:16 +01:00
fb084327da
Add VexRiscvBmbGenerator CsrPlugin withPrivilegedDebug assert
2022-11-28 16:30:47 +01:00
eafeb5fe49
Add EmbeddedRiscvJtag.debugCd
2022-11-28 11:04:02 +01:00
a25ae96d33
comment debug code
2022-11-21 14:02:35 +01:00
572ca3fcfa
Privileged debug fake maskmax to 31
2022-11-21 14:01:28 +01:00
5a8cdee884
Fix CsrPlugin dcsr.stepie
2022-11-21 11:55:07 +01:00
4ae7386904
Merge pull request #276 from LYWalker/master
...
Add ability to debug over Intel Virtual JTAG
2022-11-18 17:38:50 +01:00
e19e59b55c
Clear mprv on xretAwayFromMachine
2022-11-17 15:03:47 +01:00
663174bc73
Privileged debug now implement stoptime stopcount
2022-11-17 13:58:29 +01:00
36c3346e51
ensure rvc 0 is detected as a illegal instruction
2022-11-17 11:03:45 +01:00
5e17ab62d6
Fix RISC-V debug hardware breakpoints
2022-11-14 14:45:11 +01:00
fe68b8494e
Fix a few RISC-V official debug support :
...
- Disable interrupts in debug mode
- Ensure traps do not change CSR in debug mode
- step will also consider trapEvent
2022-11-11 14:05:38 +01:00
2504f9b9b9
RISC-V debug havereset implemented
2022-11-10 15:49:07 +01:00
0bfaf06a4a
main.cpp add VEXRISCV_JTAG=yes
2022-11-10 13:43:14 +01:00
f71234786f
Remove rv64 opcode (shift and lwu)
...
Thanks Milan
2022-10-27 15:44:50 +02:00
d70794f252
fix regression
2022-10-27 15:38:34 +02:00
5d0deb20b3
Fix regression compilation
2022-10-27 15:20:55 +02:00
9f6186cd9a
Add GenFullWithRiscvPrivilegedDebugJtag demo
2022-10-27 14:55:40 +02:00
6289ebcbe4
Merge branch 'riscv-debug' into dev
2022-10-27 14:46:46 +02:00
a6c29766da
CsrPlugin now force privilegeGen when withPrivilegedDebug is enabled
2022-10-26 15:48:34 +02:00
7fd55c7851
Add VexRiscvAxi4LinuxPlicClint diagram drawio
2022-10-26 10:47:23 +02:00
0e531515ac
cleaning
2022-10-26 10:25:50 +02:00
63dd787bce
VexRiscvAxi4Linux now integrate Plic and Clint
2022-10-26 10:15:21 +02:00
220af95043
Add VexRiscvAxi4Linux (untested, but generate a netlist)
2022-10-24 10:35:59 +02:00
0979f8ba80
Add whitebox example
2022-10-24 10:24:41 +02:00
17d52ce58f
privileged debug now access data cache with caching enable
2022-10-21 18:58:40 +02:00
486d17d245
CsrOpensbi now add rvc to misa
2022-10-21 18:58:13 +02:00
662943522f
Fix privileged debug trigger decode break logic
2022-10-21 17:21:13 +02:00
95c656ceef
riscv debug multiple harts
2022-10-21 12:28:17 +02:00
0313f84419
Fix RISCV debug step
2022-10-20 10:36:30 +02:00
4cd3f65296
Add official RISC-V debug support (WIP, but can already load / step / run code via openocd telnet)
2022-10-19 12:36:45 +02:00
959e48a353
Fpu now set csr status fs on FPU csr write
2022-10-06 11:13:57 +02:00
fda7da00c2
add litex --wishbone-force-32b
2022-09-06 11:19:29 +02:00
54412bde30
getDrivingReg() update
2022-07-21 09:10:26 +02:00
b1252f47de
csr opensbi now enable ebreak
2022-06-13 16:34:49 +02:00
1303c0ca7c
CfuPlugin.withEnable added
2022-06-09 17:57:31 +02:00
0f6d0f022c
VexRiscvBmbGenerator now also report bytesPerLine
2022-05-24 12:37:31 +02:00
e6dfcac0be
Add D$ single line flush support
2022-05-24 12:13:37 +02:00
4c4913c703
Fix MPP to only retain legal values
2022-05-24 11:14:34 +02:00
209fc719e8
VexRiscvBmbGenerator export more info
2022-05-24 10:19:35 +02:00
48cf4120f2
Add VexRiscvSmpCluster forceMisa/forceMscratch
2022-05-23 15:49:32 +02:00
0872852387
Fix DYNAMIC_TARGET / debug plugin interation corrupting the recoded next pc durring step by step #254
2022-05-17 20:44:17 +02:00
a553d3b476
Fix DYNAMIC_TARGET from triggering fetch missprediction while in debug mode #254
2022-05-17 15:27:50 +02:00
78f0a7f13e
Fix CfuPlugin/VfuPlugin fork duplication
...
https://github.com/google/CFU-Playground/issues/582
2022-05-16 10:36:21 +02:00
8df2dcbd40
Fix RVC step by step triggering next instruction branch predictor
2022-05-11 14:10:32 +02:00
ea7a18c7f4
plugin: caches: Fix "Can't resolve the literal value of"
...
Both registers were initialized with unsigned integers without a value.
This triggered:
[error] Exception in thread "main" spinal.core.SpinalExit:
[error] Can't resolve the literal value of (..._rspCounter : UInt[32 bits])
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
2022-04-20 11:19:34 +02:00
3b8270b82b
#241 Fix Murax/Briey TB timeouts
2022-04-11 11:59:41 +02:00
db34033593
#240 Code generation now warn against cpu generation without illegal instruction catch and ebreak being disabled, as it may make crash some software, ex : rust
2022-04-08 11:09:14 +02:00
2d2017465e
Fix reset vector of GenCustomSimdAdd
...
With the old reset vector half of the tests fail since
they expect the CPU to start at 0x80000000.
(e.g. I-IO, I-NOP, I-LUI, etc.)
2022-04-03 02:55:42 +02:00
ccff48f872
deprecated Data.keep
2022-03-30 16:17:57 +02:00
4bddb091ae
Update CFU example
2022-03-23 18:58:18 +01:00
5dc91a8be4
Add MuraxCfu
2022-03-23 18:54:18 +01:00
b2e61caf9e
CfuPlugin now implement upstream spec
2022-03-23 18:54:07 +01:00
9149c42065
DecoderPlugin now implement forceIllegal API
2022-03-23 18:53:43 +01:00
51b8865b66
Fix VexRiscvSmpClusterGen linux less mhartid
2022-03-18 12:36:05 +01:00
e558b79582
Fix Briey simulation floating rxd blocking the uart #238
2022-02-22 16:15:14 +01:00
807aa98d37
plugin: DBusSimplePlugin: Remove assert
...
This assert triggered sometimes at the beginning of a simulation.
Since it's not really needed anymore, we can remove it.
Signed-off-by: Daniel Schultz <daniel.schultz@aesc-silicon.de>
2022-02-10 19:55:08 +01:00
5714680278
Merge branch 'master' into dev
...
# Conflicts:
# build.sbt
2022-02-05 11:32:40 +01:00
8b2f107d46
verilator++
2022-02-04 15:10:57 +01:00
57dd80a566
plugin: CsrPlugin: Init cycle and instret registers
...
Both counters are initialized with "randBoot()". This is fine for FPGA
designs because the registers can be loaded with default values but
ASIC designs require to load the value during a reset.
Since both counters require to start at 0 (read-only CSR registers),
change both registers from "randBoot()" to "init(0)".
Error:
reg [63:0] CsrPlugin_mcycle = 64'b0000000...00000000000;
|
Warning : Ignoring unsynthesizable construct. [VLOGPT-37]
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
2022-01-26 08:59:03 +01:00
9c34a1fd2e
updated related to JtagInstructionWrapper.ignoreWidth
2022-01-14 09:59:24 +01:00
b8e904e43f
syncronize golden model with dut for lrsc reservation
2022-01-10 19:55:28 +01:00
6e77f32087
sim golden model lrsc reservation sync
2022-01-10 16:08:38 +01:00
da53de360f
Fix lrsc from last commit
2022-01-10 14:21:20 +01:00
f46ad43f39
DataCache.withInternalLrSc reserved clearing fix
2022-01-10 13:39:41 +01:00
fe6c391fe4
Fix typo in Linux.scala
...
Correct "machime" to "machine".
2022-01-04 16:31:23 +08:00
34e5cafb75
Enable scala 2.13 compatibility
2021-12-20 09:38:35 +01:00
4824827b7e
Enable scala 2.13 compatibility
2021-12-20 09:38:02 +01:00
dd12047aa7
Merge branch dev (SpinalHDL 1.6.1)
2021-12-15 09:22:46 +01:00
411d946a58
Update DebugPlugin.scala
...
Add readback of the hardware breakpoint values.
A new parameter is added to the plugin to switch readback on and off.
2021-11-11 12:12:23 +01:00
acf14385d8
#213 disable pmp test with region overlapping
2021-10-22 17:24:51 +02:00
a3807660e3
pmp perm: revert to mux for priority
2021-10-19 11:40:39 +08:00
df03c99ab2
pmp_setter: fix mask generation
2021-10-19 11:39:25 +08:00
c3c3a94c5d
IBusSimplePlugin can now use a Vec based buffer
2021-10-13 16:26:16 +02:00
97a3c1955b
VexRiscvSmpCluster add d$ i$ less arg
2021-10-11 11:57:39 +02:00
35754a0709
Fix BrieySim (SpinalSim)
2021-09-25 13:28:37 +02:00
8c0fbcadac
Add BrieySim (SpinalSim)
2021-09-25 13:18:55 +02:00
5f5f4afbf2
Briey revert RVC unwanted addition
2021-09-22 15:01:08 +02:00
b807254759
Briey and Murax verilators now use FST instead of VCD
2021-09-22 12:57:27 +02:00
65cda95176
Fix wishbone bridges with datawidth > 32
2021-09-17 09:43:30 +02:00
Dolu1990
Daniel Schultz
Andreas Wallner
Daniel Schultz
Daniel Schultz
Oscar Shiang
B.Lang
occheung