c1481ae244
update ScopeProperty usages
2021-09-16 19:08:41 +02:00
42bb1ab591
d$ / i$ toWishbone bridges can now be bigger than 32 bits
...
https://github.com/m-labs/VexRiscv-verilog/pull/12
2021-09-15 11:36:51 +02:00
68e704f309
restore avalon d$ tests
2021-09-02 15:42:33 +02:00
efd3cd4737
Merge branch 'master' into dev
2021-09-02 14:16:07 +02:00
cc9f3e753a
Fix d$ toAxi bridge
2021-09-02 14:14:42 +02:00
bc561c30eb
Add PmpPluginOld (support TOR)
2021-09-01 11:27:12 +02:00
5c7e4a0294
#170 wishbone example now set dBusCmdMasterPipe
2021-08-24 23:24:29 +02:00
3deeab42fd
VexRiscvSmpCluster config fix
2021-08-10 12:14:42 +02:00
805bd56077
Fix VexRiscvBmbGenerator.hardwareBreakpointCount default value
2021-07-30 16:51:07 +02:00
671bd30953
Update Bmb invalidate/sync parameters
2021-07-28 13:44:04 +02:00
ba8f5f966a
Vfu typo
2021-07-26 15:27:20 +02:00
b717f228d6
VfuPlugin wip
2021-07-26 15:17:06 +02:00
c242744d02
CfuPlugin now only fork when the rest of the pipeline is hazard free
2021-07-26 14:45:54 +02:00
f3f9b79f9a
VexRiscvSmpCluster earlyShifterInjection added
2021-07-21 18:34:57 +02:00
5fc4125763
Merge branch 'dev'
2021-07-20 11:21:11 +02:00
3028c19389
Fix #191 (data cache toAxi bridge)
2021-07-20 11:20:53 +02:00
5f2fcc7d0f
Merge branch 'dev'
...
(SpinalHDL 1.6.0)
2021-07-20 10:39:09 +02:00
0cdad37fff
VexRiscvSmpClusterGen now implement ebreak
2021-07-11 21:55:33 +02:00
c79357d1b2
VexRiscvSmpClusterGen no support atomic less configs
2021-07-05 12:38:54 +02:00
a380c3a36c
Merge branch 'spinal_1.4.4' into dev
2021-07-05 11:37:53 +02:00
551e76d244
VexRiscvSmpCluster add a few options
2021-07-02 19:04:30 +02:00
df7ac05db9
Update 2.13 compatibility
2021-06-23 11:48:38 +02:00
d67fe72de9
Merge branch 'dev'
...
# Conflicts:
# build.sbt
# src/test/cpp/regression/main.cpp
2021-06-15 15:54:13 +02:00
1497001ebd
Update FpuTest with the new rs1/rs2 store mapping
2021-06-09 13:37:31 +02:00
1ee45eeb0a
More named signals
2021-06-09 11:27:18 +02:00
0e89ebeced
Improve FPU rs1 timings
2021-06-09 11:26:58 +02:00
e1e1be5797
exception code can now be bigger than 4 bits
2021-06-08 12:19:08 +02:00
646911a373
Fix pmp write when there is hazard due to the register file.
2021-06-07 17:30:47 +02:00
87f100dac1
Merge pull request #174 from lindemer/new_pmp
...
New PMP plugin optimized for FPGAs
2021-06-03 20:16:34 +02:00
156a84e76f
Fix PMP FSM halting logic
2021-06-03 13:12:55 +02:00
342b06128f
Combine all the PMP logic into one FSM
2021-06-02 17:12:10 +02:00
2a4ca0b249
PMP CSR writes occur in execute stage
2021-06-02 16:01:30 +02:00
0272d66971
Fix CsrPlugin.redoInterface priority
2021-05-28 16:20:43 +02:00
3a4ab7ad51
Un-pend PMP CSR writes on pipeline flushes
2021-05-28 16:17:19 +02:00
d49f8d1b58
Merge branch 'dev' into new_pmp
2021-05-28 13:56:15 +02:00
24a534acff
All tests passing on new PMP plugin
2021-05-28 13:54:55 +02:00
4490254d3d
Csr/Mmu ensure implement that SFENCE_VMA flush the next instructions
...
SAT flush reworked a bit too
2021-05-28 13:35:52 +02:00
4a2dc0ff5f
Fix granularity control
2021-05-27 15:50:45 +02:00
6471014131
Simplify pmpcfg encoding
2021-05-27 14:34:51 +02:00
4b0763b43d
CsrPlugin.csrMapping now give names to inner signals
2021-05-27 10:40:55 +02:00
a5f66623b7
Add an "allow" property to individual CSRs
2021-05-26 16:34:51 +02:00
61f68f0729
Refactor for new CSR API (PMP reads still broken)
2021-05-26 15:29:27 +02:00
6066d8bc26
CsrPlugin add API to implement CSR in a decoupled way. (very low level api) #174
2021-05-26 11:44:46 +02:00
72328e7bc4
Arty now has RVC enabled !
2021-05-25 15:59:02 +02:00
8122cc9b5e
fixed priority of == & != as seemed logical to get less warnings when building
2021-05-17 18:51:33 +02:00
1c3b9e93a2
Merge pull request #182 from rdolbeau/extra_config
...
Make the [ID]TLB size configurable from Litex
2021-05-12 13:54:27 +02:00
fe739b907a
Bench DecoderPlugin
2021-05-10 10:47:15 +02:00
1bd33a369e
Make the [ID]TLB size configurable from Litex
2021-05-08 07:59:34 -04:00
e78c0546a0
fix #178
2021-05-04 21:09:42 +02:00
fa2899a1a2
Merge branch 'debugPlugin' into dev
2021-04-26 11:11:38 +02:00
45e67ccf56
sync
2021-04-26 11:10:55 +02:00
0a0998fcea
#176 fix typo
2021-04-22 14:02:46 +02:00
32e4ea406f
update #176 when DebugPlugin ebreak are enabled it disable CsrPlugin ebreak. Also, DebugPlugin ebreak can be disabled via the debug bus.
2021-04-22 13:59:33 +02:00
bfe65da1eb
implement #176 DebugPlugin.allowEBreak is now disabled until the debug bus is used.
2021-04-20 23:23:18 +02:00
79bc09e69a
Decouple PMP and CSR plugins
2021-04-13 08:35:07 +02:00
15137742fc
Merge branch 'dev' into new_pmp
2021-04-12 13:23:10 +02:00
b41db0af93
Prevent PMP access from U-mode, fix tests
2021-04-12 13:20:15 +02:00
bf399cc927
Initial commit of optimized PMP plugin
2021-04-12 13:20:15 +02:00
36c896f95b
Update CFU immed field to use sext([31:24]) to match spec.
...
Signed-off-by: Tim Callahan <tcal@google.com>
2021-04-02 13:16:53 -07:00
66f5c3079b
CfuPlugin names fixes
2021-04-02 12:50:21 -07:00
73893ce5d9
CfuPlugin names fixes
2021-04-02 09:20:26 +02:00
a42c089119
IBusSimplePlugin ensure AHB persistance
2021-03-31 19:03:38 +02:00
9ac6625ef3
FpuCore improve FMA rounding
2021-03-29 16:31:18 +02:00
9462496386
Add rvc support and fix rvc with FPU
2021-03-25 14:14:19 +01:00
6f481f51ef
Fetcher.decompressor ensure that the decoded instruction do not mutate when the pipeline is stalled (fix FPU cmd fork for rvc without injector stage)
2021-03-25 14:13:12 +01:00
21c91c6b70
fpu now lift wfi
2021-03-24 16:21:37 +01:00
925edd160e
RVC implement RVF RVD
...
Rework RVC_GEN
2021-03-24 12:04:27 +01:00
8495fe3dde
Attempt at supporting C (ompressed) and F/D (floating-point) together
2021-03-24 11:07:09 +01:00
da458dea7e
litex cluster add cpuPerFpu option
2021-03-23 20:00:50 +01:00
80f64f0f9f
litex better pipelining for better fmax, create one FPU for each 4 cores
2021-03-18 11:10:22 +01:00
6956db2b21
fpu add schedulerM2sPipe optino
2021-03-18 11:10:22 +01:00
099dea743b
fpu cleanup
2021-03-18 10:54:51 +01:00
f6e620196d
litex add fpu suport
2021-03-17 13:19:41 +01:00
e23687c45d
Handle ClockDomain improvements
2021-03-16 14:46:30 +01:00
02c572b6f1
fpu improve FMax and add asyncronus regfile support
2021-03-16 14:45:59 +01:00
5aa1f2e996
fpu improve pipline cycles
2021-03-15 17:27:14 +01:00
341c159d06
data cache relax assert into error
2021-03-15 14:43:22 +01:00
3a34b8dae2
Merge branch 'dev' into fiber
...
# Conflicts:
# src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
# src/main/scala/vexriscv/plugin/MulPlugin.scala
2021-03-15 10:35:02 +01:00
ff4e5e4666
wipe generator
2021-03-11 18:02:02 +01:00
adc37b269c
FpuPlugin.pending is now 6 bits
2021-03-11 13:06:50 +01:00
845cfcb966
DebugPlugin.fromBscane2 added
2021-03-10 20:35:44 +01:00
67d2f72a4b
fiber sync
2021-03-07 20:43:02 +01:00
e384bfe145
fiber update
2021-03-05 22:04:20 +01:00
fd234bbf9e
fix cfu gen error
2021-03-05 09:41:05 +01:00
aee8841438
CFU ensure that CFU_IN_FLIGHT do not produce false positive when the pipeline is stuck
2021-03-05 09:41:05 +01:00
ec507308e7
fix cfu gen error
2021-03-04 20:29:33 +01:00
bdc52097b6
CFU ensure that CFU_IN_FLIGHT do not produce false positive when the pipeline is stuck
2021-03-04 20:15:01 +01:00
0530d22a1d
sync
2021-03-04 16:06:18 +01:00
caf1bde49b
Add MuraxAsicBlackBox example
2021-03-04 10:16:45 +01:00
4bdab667cc
fpu fix cmd / commit race condition
2021-03-02 19:39:55 +01:00
636d53cf63
fpu now track commits using a counter per pipeline per port
2021-03-02 16:13:12 +01:00
81c193af1f
Improve subnormal/normal rounding
2021-02-26 16:32:42 +01:00
de81da36eb
Fpu fix a few div special cases
2021-02-25 19:39:57 +01:00
de09ed3fcb
fpu added exact div/sqrt implementations using iterative approaches
2021-02-25 15:28:38 +01:00
be81cc1e0e
CfuPlugin.response_ok removed
2021-02-23 12:23:48 +01:00
47673863fb
fpu test cleaning
2021-02-22 19:27:55 +01:00
b1f4c06d4e
fpu fix arbitration/lock bugs
...
add getVexRiscvRegressionArgs
2021-02-22 19:27:26 +01:00
a6e89fe05c
fpu vex regression goldenModel can now assert FPU interface
2021-02-19 17:55:56 +01:00
3f226b758c
fpu fix exception flag handeling
2021-02-19 13:03:48 +01:00
e504afbf18
fpu integration wip, got mandelbrot to work in linux with no inline (crash when inlined)
2021-02-19 11:26:28 +01:00
8537d18b16
fpu improve fmax
2021-02-17 16:35:52 +01:00
1e647f799c
fpu Fix VexRiscv integration and add software f64 tests (pass)
2021-02-17 12:33:27 +01:00
06b7a91de4
MulPlugin fix buffer interraction with partial regfile bypass
2021-02-17 11:35:17 +01:00
f180ba2fc9
fpu double fixes
...
DataCache now support wide load/store
2021-02-16 15:38:51 +01:00
8b2a2afb6f
VexRIscvSmpCluster add options
2021-02-16 14:42:31 +01:00
1752b9e6d6
DataCache.toBmb with aggregation sync path pipelined
2021-02-16 14:17:21 +01:00
fe690528f7
MulPlugin.outputBuffer feature added
2021-02-16 14:16:57 +01:00
3b99090879
VexRiscvConfig.get added
2021-02-16 14:15:20 +01:00
7d3b35c32c
fpu f64/f32 pass all tests
2021-02-12 14:48:44 +01:00
9a25a12879
fpu add FCVT_X_X
2021-02-11 17:40:35 +01:00
82dfd10dba
fpu fix f32 tests for f64 fpu
2021-02-11 16:42:17 +01:00
b6eda1ad7a
fpu f64 load/store/mv/mul seems ok
2021-02-11 16:07:47 +01:00
e97c2de837
fpu f64 wip
2021-02-10 19:27:26 +01:00
88dffc21f7
fpu f64 wip
2021-02-10 13:20:17 +01:00
889cc5fde2
fpu refractoring
2021-02-10 12:16:56 +01:00
1fe993ad10
fpu fixed corner cases, FpuPlugin coupling, pass rv-test excepted div (accuracy), can run C sinf successfully
2021-02-09 18:35:47 +01:00
bf6a64b6b5
fpu sgnj / fclass / fmv pass
2021-02-08 15:29:50 +01:00
bf0829231d
fpu min max pass
2021-02-06 14:08:21 +01:00
008fadeaa9
fpu eq lt le pass testfloat
2021-02-06 13:20:27 +01:00
6170243283
fpu got exception flag right for add/sub/mul/i2f/f2i
2021-02-05 16:24:14 +01:00
f278900cbe
VexRiscvSmpCluster can now set regfile read kind
2021-02-05 11:09:18 +01:00
0f1ca72171
fix synthesis bench
2021-02-04 12:43:31 +01:00
936e5823dc
fpu test wip
2021-02-04 12:41:49 +01:00
3710fd3492
fix synthesis bench
2021-02-04 12:41:31 +01:00
02b5b9b05c
fpu load subnormal and i2f now use single cycle shifter
2021-02-03 16:48:09 +01:00
8e7e736e3e
Merge branch 'dev' into fpu
...
# Conflicts:
# src/main/scala/vexriscv/Riscv.scala
# src/main/scala/vexriscv/ip/fpu/FpuCore.scala
# src/main/scala/vexriscv/ip/fpu/Interface.scala
# src/test/scala/vexriscv/ip/fpu/FpuTest.scala
2021-02-03 16:06:17 +01:00
8eb8356dea
fpu wip
2021-02-03 14:28:02 +01:00
1d0eecdcb0
fpu f2i rounding ok and full shifter
2021-02-03 14:27:52 +01:00
ef011fa0d4
fpu moved 1 bit from round to mantissa
2021-02-02 11:29:35 +01:00
a87cb202b1
fpu i2f rounding ok
2021-02-01 16:12:38 +01:00
6aa6191240
Merge branch 'master' into dev
...
# Conflicts:
# build.sbt
# src/main/scala/vexriscv/Riscv.scala
# src/main/scala/vexriscv/ip/DataCache.scala
# src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
# src/main/scala/vexriscv/plugin/MmuPlugin.scala
# src/test/cpp/regression/makefile
# src/test/scala/vexriscv/TestIndividualFeatures.scala
2021-01-30 20:30:21 +01:00
c51b0fcafe
fpu mul now pass all roundings
2021-01-29 22:30:19 +01:00
0997592768
fpu mul sems all good excepted subnormal rounding
2021-01-29 16:13:49 +01:00
3c4df1e963
fpu moved overflow rounding to writeback
2021-01-29 14:37:52 +01:00
fc3e6a6d0a
fpu add rounding is ok excepted infinity result
2021-01-28 20:26:43 +01:00
1ae84ea83b
fpu added proper rounding for add (need to manage substraction)
2021-01-28 00:25:16 +01:00
195e4c422d
fpu now integrate f2i shifter withing the subnormal shifter
2021-01-27 12:11:30 +01:00
444bcdba0a
fpu merged i2f with load pipeline
2021-01-26 15:28:09 +01:00
3334364f5f
fpu added more tests for min max sqrt div
2021-01-26 12:50:23 +01:00
f818fb3ba4
fpu got proper subnormal support, pass add/mul
2021-01-26 10:49:53 +01:00
d6e8a5ef22
VexRiscvSmpLitex options refractoring
2021-01-23 20:16:58 +01:00
ce143e06f2
VexRiscvSmpLitex --in-order-decoder --wishbone-memory added
2021-01-23 17:48:34 +01:00
bdb5bc1180
fpu div implement some special values handeling
2021-01-22 20:47:31 +01:00
7d79685fe2
fpu mul now support special floats values and better rounding
2021-01-22 18:15:45 +01:00
4bd637cf88
fpu add now support special floats values and better rounding
2021-01-22 14:55:37 +01:00
bcd140fc42
Add vexRiscvConfig.withMmu option
2021-01-21 13:28:09 +01:00
ccd13b7e9e
fpu zero/nan wip
2021-01-21 12:13:25 +01:00
6c13e6458f
Remove registers storing PMP region bounds
2021-01-20 14:27:38 +01:00
ac5844f393
fpu add signed i2f/f2i
2021-01-20 13:15:29 +01:00
15d79ef330
fpu implement fclass and args for sub, fma, max, fcmp, fsgnj
2021-01-20 12:01:08 +01:00
828ea96006
PMP registers are now WARL
2021-01-20 09:27:35 +01:00
11349a71fa
fpu FpuPlugin now implement all instructions.
...
Remains the FPuCore to implement cmd.arg and floating point corner cases
2021-01-19 17:57:41 +01:00
9f18045329
fpu add sstatus.fs
2021-01-19 16:06:16 +01:00
a7d148d0ff
fpu add vex csr
2021-01-19 15:53:11 +01:00
f826a2ce51
fpu completion interface added + refractoring
2021-01-19 15:13:13 +01:00
8c4fae8bf2
fpu add min/sgnj/fmv
2021-01-19 13:27:42 +01:00
d7220031d4
fpu vex i2f works
2021-01-18 17:18:01 +01:00
d4b877d415
fpu vex cmp/fle works
2021-01-18 15:09:30 +01:00
6cb498cdb2
fpu merge load/commit
2021-01-18 13:09:08 +01:00
a9d8c0a19f
fpu wip
2021-01-18 11:38:26 +01:00
3cda7c1f1b
fpu wip
2021-01-15 14:03:37 +01:00
04499c0b76
FPU sqrt functional
2021-01-14 18:33:24 +01:00
85dd5dbf8e
fpu div functional, sqrt wip
2021-01-14 15:56:56 +01:00
5e6c645461
Distinguish between page faults from MMU and access faults from PMP
2021-01-14 09:45:38 +01:00
8761d0d9ee
FpuCore can add/mul/fma/store/load
2021-01-13 18:28:26 +01:00
6e0be6e18c
Cfu add state index and cfu index
2021-01-11 13:44:04 +01:00
930bdf9dda
DataCache increase syncPendingMax to 32 and use a sync queue instead of async one
2021-01-04 10:59:21 +01:00
780ad01ac0
Add AES-instruction support
2020-12-21 11:52:55 +01:00
c59499ec03
typo
2020-12-11 14:13:33 +01:00
eaff52b264
Add comments to the AesPlugin
2020-12-11 13:51:10 +01:00
6da09967f8
Add comments to the AesPlugin
2020-12-11 13:46:55 +01:00
7d699dcc13
Remove PMP from MachineOs test defaults
2020-12-10 09:42:27 +01:00
f2ce2eab00
PMP plugin passes regression tests
2020-12-07 12:04:45 +01:00
763eebeeba
Add TOR support, tests pass on GenZephyr
2020-12-04 17:13:31 +01:00
5cb5061d9b
PMP passes test with GenZephyr, but pipeline flushes have been disabled
2020-12-03 17:29:31 +01:00
9a6931a54c
CfuPlugin improve writeback buffering
2020-12-03 16:21:52 +01:00
987de8fb6a
Lock PMP address registers in golden model
2020-12-02 14:18:17 +01:00
14c39a0070
Merge remote-tracking branch 'upstream/master' into pmp
2020-12-02 14:08:32 +01:00
872aa19d83
Add PMP to golden model
2020-12-02 12:27:26 +01:00
d5b1a8f565
Add PMP test to regression suite
2020-12-01 18:38:06 +01:00
45ff78d068
VexRiscvSmpClusterGen.dBusCmdMasterPipe option added
2020-12-01 13:51:10 +01:00
c5023ad973
Add PMP regression test
2020-12-01 09:10:24 +01:00
2d0ebf1ef5
Flush pipeline after PMP CSR writes
2020-11-25 15:38:34 +01:00
e0ae46e794
Fix Csr ReadWrite interration with DBusCachedPlugin execute halt
...
# Conflicts:
# src/main/scala/vexriscv/plugin/CsrPlugin.scala
2020-11-18 14:43:24 +01:00
832218dbec
DBusCachedPlugin increase pendingMax to 64 to hide memory latency when saving a full context
2020-11-16 12:38:29 +01:00
ba523c627a
Fix Csr ReadWrite interration with DBusCachedPlugin execute halt
2020-11-16 12:37:48 +01:00
c1b0869c21
AesPlugin is now little endian
2020-11-12 15:07:27 +01:00
1b2a2ebaca
DBusCachedPlugin miss decoded aquire fix
2020-11-12 15:07:07 +01:00
05e725174c
AesPlugin added, work with dropbear encryption, seem ok for decryption (barmetal)
2020-11-02 17:14:52 +01:00
9abe19317d
RegFilePlugin.x0Init do less assumption on other plugin behaviour
2020-11-02 17:01:17 +01:00
97fe279f7b
Enable PMP register lock
2020-10-29 13:37:21 +01:00
dc9246715d
Do not allow jtag ebreak outside machine mode
2020-10-28 13:00:16 +01:00
4209dc2792
Fix CsrPlugin privilege crossing
2020-10-28 13:00:15 +01:00
576e21d75d
Do not allow jtag ebreak outside machine mode
2020-10-28 12:58:24 +01:00
abebeaea1f
Fix CsrPlugin privilege crossing
2020-10-28 12:57:20 +01:00
fc2c8a7c37
Initial commit of PMP plugin
2020-10-27 09:38:58 +01:00
fe342c347c
CfuBusParameter has now a few default values
2020-10-23 11:06:24 +02:00
6c8e97f825
Update big endian instruction encoding
...
Between draft-20181101-ebe1ca4 and draft-20190622-6993896 of the
RISC-V Instruction Set Manual, the wording was changed from requiring
"natural endianness" of instruction parcels to require them to be
little endian.
Update the big endian instruction pipe to reflect the newer requirement.
2020-10-20 18:05:31 +02:00
4ece59385d
DataCache split redo / refilling execute stage halt
2020-10-19 18:12:20 +02:00
ec55187033
improve LightShifterPlugin arbitration halt timings
2020-10-09 11:37:48 +02:00
Dolu1990
Samuel Lindemer
Alexis Marquet
Romain Dolbeau
Tim Callahan
Marcus Comstedt