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5737 commits

Author SHA1 Message Date
bunnie
282f22f09e Add tracelength report generation by default to help with board layout 2017-12-27 22:40:39 +08:00
Florent Kermarrec
b463b2169b boards/platforms/tinyfpga_b: add defaut serial pins 2017-12-27 00:26:30 +01:00
Florent Kermarrec
fe2564e921 build/lattice/icestorm: fix missing toolchain_path 2017-12-27 00:26:07 +01:00
William D. Jones
5a2c92ba80 Add TinyFPGA platform based on Migen. 2017-12-27 00:00:05 +01:00
William D. Jones
f096030fc8 Import Icestorm backend improvements from Migen. 2017-12-26 23:57:13 +01:00
Florent Kermarrec
e7015e4191 soc/integration/soc_core: add uart_name parameters (allow selecting uart without modifications in platform file) 2017-12-26 18:11:47 +01:00
Florent Kermarrec
a3390bb403 build/xilinx/programmer: fix settings in run_vivado (update) 2017-12-19 10:29:29 +01:00
William D. Jones
dd6ca87561 Add Mercury baseboard support from Migen, import fixes. 2017-12-18 19:30:25 -05:00
Florent Kermarrec
4c82eb549f build/xilinx: add support for edif/ngc files 2017-12-16 13:20:45 +01:00
Florent Kermarrec
b31d0f37db cpu/picorv32: adapt to current version, some cleanup 2017-12-10 03:01:53 +01:00
Florent Kermarrec
4239aff68a cpu: cleanup wrappers 2017-12-10 02:52:01 +01:00
Florent Kermarrec
43429560d4 soc/integration/soc_core: add integrated_rom_init to allow initializing rom with custom code 2017-12-08 10:18:01 +01:00
Florent Kermarrec
27d37fa95d targets/sim: fix 2017-12-06 22:22:05 +01:00
Florent Kermarrec
284b16e2c1 soc/integration/soc_core: make nmi interrupt optional 2017-12-03 23:07:41 +01:00
Florent Kermarrec
c1eba9a6cc soc/integration: add integrated_main_ram_init parameter to allow using main_ram with pre-initialized firmware 2017-11-24 13:16:58 +01:00
Florent Kermarrec
831b489fd3 soc/interconnect/stream: fix specific cases for last/first signal in UpConverter 2017-11-23 17:58:02 +01:00
Florent Kermarrec
c3d902ef42 soc/software/bios/sdram: add Kintex Ultrascale support 2017-11-08 12:59:38 +01:00
Florent Kermarrec
2665a83288 soc/interconnect/stream: expose depth on SyncFIFO 2017-10-30 22:56:09 +01:00
Tim 'mithro' Ansell
56ef229029 Make the interrupt dicts read only. 2017-10-29 19:45:52 -07:00
Tim 'mithro' Ansell
295e78ee9e Make it harder to have conflicting interrupts. 2017-10-29 19:45:52 -07:00
Tim 'mithro' Ansell
ff72757b87 Bump the IRQ for liteeth based targets. 2017-10-29 19:45:52 -07:00
Tim 'mithro' Ansell
73e0036b99 Change the default IRQs. 
* Reserve IRQ 0 to be used as a "non-maskable interrupt" (NMI) in the
   future.

 * Use IRQ 2 for the LiteX. This matches the standard mor1k config which
   connects the UART to IRQ 2.

This change is needed for Linux running on LiteX as it gets grumpy with
using IRQ 0 for anything other other than an NMI.
 2017-10-29 19:45:52 -07:00
Tim 'mithro' Ansell
e07bd71b16 build/xilinx: Fixing settings finding. 
* Better error messages.
 * Search correct directories;
   - XXX/Vivado/<version>
   - XXX/<version>/ISE_DS/
 2017-10-16 18:25:51 +11:00
Florent Kermarrec
db6c88bbef soc/interconnect/stream: don't use reset less on last and first signals (not reseting these signals can cause troubles in some specific cases) 2017-10-12 11:30:56 +02:00
Tim 'mithro' Ansell
2c013948b1 Output better error message for flash_proxy. 2017-10-07 12:14:00 +11:00
Tim 'mithro' Ansell
279ec488e3 bios: Print location jumping too. 
Makes it easier to  understand what is happening (and that the BIOS is
jumping to the right place).
 2017-10-06 20:38:44 +11:00
Tim 'mithro' Ansell
8152673d18 common: Compile with debugging symbols on. 
Debugging symbols are useful when using GDB :-)
 2017-10-06 20:38:44 +11:00
Tim 'mithro' Ansell
b1b6a74170 or1k: Use EXCEPTION_STACK_SIZE of 256bytes. 
or1k defines a 128 byte "red zone" after the stack that can not be
touched by the exception handler.

We also need 128 bytes to store the 32 registers.
 2017-10-06 20:38:44 +11:00
Tim 'mithro' Ansell
07a9df3586 bios: Declare dependency on linked in .a files. 2017-10-06 20:38:44 +11:00
William D. Jones
e558473119 Add iCEStick board. Tested with litescope. 2017-10-04 01:59:53 -04:00
William D. Jones
c3383f47ba Port IceStorm backend from Migen. 2017-10-03 22:48:44 -04:00
Florent Kermarrec
ba1bf20f37 soc/cores: add cordic 2017-09-29 12:07:43 +02:00
enjoy-digital
878380abba Merge pull request #28 from enjoy-digital/eb-docs-2 
More docs for etherbone packet fields.
 2017-09-26 12:33:57 +02:00
Florent Kermarrec
e42ab27f30 gen/fhdl/verilog: revert _printcomb_simulation and _printcomb_regular (needed for icarus simulation) and add Finish command 2017-09-13 13:47:25 +02:00
Florent Kermarrec
2a8f6edded soc/integration/soc_core: add ident_version parameter to allow adding soc version to identifier 2017-09-06 15:39:54 +02:00
Tim Ansell
3a656c61d9 More docs for etherbone packet fields. 
Info comes from http://www.ohwr.org/attachments/1669/spec.pdf dated 24 July 2012
 2017-09-01 23:57:34 +10:00
Tim Ansell
c125ea6440 Adding a little docs to field descriptions. 2017-09-01 23:27:58 +10:00
Florent Kermarrec
8f3dcf90ab soc/software/bios/sdram: add optional memtest debug traces 2017-08-18 09:42:27 +02:00
Florent Kermarrec
c02de1632b soc/cores: fix vivado issue with SPIRegister (at least with Vivado 2017.x+, mosi was not generated correctly), create cs_n signal if pads does not exists 2017-07-27 18:22:01 +02:00
Florent Kermarrec
04646b24ed soc/interconnect/stream: fix make_m2s for reset_less 2017-07-24 18:18:35 +02:00
Florent Kermarrec
9509d9e361 gen/genlib/cdc/gearbox: fix possible pointers overlap by removing AsyncResetSynchronizers. 
read/write clocks don't have the same frequencies, using AsyncResetSynchronizers cause differents delay when releasing reset and can cause pointers overlap.
 2017-07-24 13:39:08 +02:00
enjoy-digital
f25e46c428 Merge pull request #26 from q3k/diamond-linux-support 
Add Diamond toolchain support for Linux.
 2017-07-20 14:41:05 +02:00
Sergiusz Bazanski
503df5e93e Add Diamond toolchain support for Linux. 
This tries to replicate the same setup as in the Windows buildsystem. We
also remove the Jedecgen step, as it doesn't seem to be supported nor
necessary in newer versions of Diamond.
 2017-07-20 13:21:10 +01:00
Florent Kermarrec
756554371a soc/tools/remote/litex_server: allow multiple instance of server 2017-07-19 21:18:12 +02:00
Florent Kermarrec
0b6d38abe9 build/xilinx/programmer: add multi jtag devices support to VivadoProgrammer 2017-07-19 14:54:19 +02:00
Florent Kermarrec
d05d170b75 soc/integration/cpu_interface: do not generate constant access functions when with_access_functions is set to False 2017-07-19 12:18:35 +02:00
Florent Kermarrec
20c859d45c soc/tools/remote/etherbone: speed optimization (~20/30%) 2017-07-17 00:25:58 +02:00
Florent Kermarrec
bdea4152e3 soc/core/uart: add UartStub to enable fast simulation with cpu 2017-07-06 19:19:10 +02:00
Sergiusz Bazanski
1885e50d54 Add Versa ECP5-5G Platform. 2017-07-05 15:01:07 +01:00
Florent Kermarrec
0894f9e6f7 targets: cleanup arty/nexys_video/kc705 and use better ddr3 timings on arty/nexys_video (found using the new bitslip/delay finder tool) 2017-07-04 09:01:29 +02:00
Florent Kermarrec
fe535db5ab merge migen ee0e709 changes 2017-07-04 08:15:40 +02:00
Florent Kermarrec
c6f6d7b491 soc/interconnect/wishbonebridge: reset_less optimizations 2017-06-30 19:41:14 +02:00
Florent Kermarrec
7fcdd94cd4 soc/interconnect/stream_packet: reset_less optimizations 2017-06-30 19:40:54 +02:00
Florent Kermarrec
227b14c3f3 soc/interconnect/stream: improve reset_less support for streams 2017-06-30 19:40:17 +02:00
Florent Kermarrec
f5a971a8d8 soc/interconnect/stream: use reset_less attr of signal for payload and param 2017-06-28 23:10:45 +02:00
Florent Kermarrec
bd876d4cd6 merge migen 9a6fdea3 changes 2017-06-28 22:47:13 +02:00
Florent Kermarrec
4d664730fe soc/software/libbase: fix get_ident 2017-06-28 18:10:56 +02:00
Florent Kermarrec
e61d9eabc6 board/targets/sim: add identifier 2017-06-28 18:08:37 +02:00
Florent Kermarrec
4433e2449a litex/build/sim: cleanup modules 2017-06-28 18:01:04 +02:00
Florent Kermarrec
c3710ec139 build/sim: cleanup serial2console and fix terminal mode 2017-06-28 17:38:09 +02:00
Florent Kermarrec
5ece895fd3 litex/build/sim: add README 2017-06-28 16:55:32 +02:00
Florent Kermarrec
4a0a431119 litex/build/sim: rename c functions from lambdasim to litex_sim (since integrated in litex) 2017-06-28 16:28:45 +02:00
Florent Kermarrec
ab6f4de521 litex/build/sim: small cleanup 2017-06-28 16:25:56 +02:00
Florent Kermarrec
1d8298af94 litex/build/sim: add tapcfg submodule for ethernet 2017-06-28 16:18:15 +02:00
Pierre-Olivier Vauboin
8510b12e93 litex/build/sim: introduce new simulator with modules support (thanks lambdaconcept) 2017-06-28 16:14:13 +02:00
Florent Kermarrec
6631aa5385 boards/platforms/arty: add pmods 2017-06-23 10:50:37 +02:00
Florent Kermarrec
1364ac3657 soc/cores/identifier: append 0 to contents to indicate end of string 2017-06-22 17:53:19 +02:00
Florent Kermarrec
f720ef5631 soc/tools: simplify litex_server usage and integrage udp, pcie 2017-06-22 11:30:33 +02:00
Florent Kermarrec
41a91829eb soc/tools: syntax fix on comm_pcie, import in __init__.py 2017-06-22 11:29:57 +02:00
Florent Kermarrec
c82c1d103f soc/tools: fix debug prints of comm_pcie 2017-06-22 10:33:08 +02:00
Florent Kermarrec
684ae45dbe soc/tools: remove csr builder from comm_udp (we should use litex_server) 2017-06-22 10:32:39 +02:00
Florent Kermarrec
4ea7026747 gen/fhdl/specials: revert migen's commit d98502c6 (specials/Memory: homogenize read-only port syntax) since causing a regression with litepcie 2017-06-10 21:53:53 +02:00
Florent Kermarrec
c44a4b051f soc/interconnect/stream: add first signal to streams (avoid over-complicated code in some cases) 2017-06-09 19:35:48 +02:00
Florent Kermarrec
c19c4b711b soc/cores/identifier: remove additionnal first character 2017-06-08 14:15:27 +02:00
Florent Kermarrec
77732fca95 soc/cores/uart: add uart multiplexer 2017-06-05 19:36:30 +02:00
Florent Kermarrec
157c2b17bc boards/platforms/nexys_video: rename hpa to hdp_en on nexy_video hdmi_in port 2017-06-05 15:13:21 +02:00
Florent Kermarrec
a36986a501 gen/fhdl/verilog: list available clock domains on keyerror 2017-06-05 14:33:46 +02:00
Florent Kermarrec
931ea5ac75 gen/genlib/cdc/gearbox: remove TODO since code is already a good compromise 
latency can't be reduced that much and reducing ressource usage (already low) would introduce unneeded complexity.
 2017-06-01 19:00:22 +02:00
Florent Kermarrec
85aea62d74 soc/core: add frequency meter 2017-06-01 00:39:19 +02:00
Florent Kermarrec
ff2a9c2176 gen/genlib/cdc/gearbox: add more margin on pointers (for cases where clocks are not perfectly aligned) 2017-05-31 13:23:31 +02:00
Florent Kermarrec
4bc6cf6165 soc/cores: dna/xadc: add missing copyright 2017-05-16 21:18:32 +02:00
Florent Kermarrec
9350a7b5e6 soc/cores: add dna and xadc (for 7-series, add support for others fpgas?) 2017-05-16 21:02:33 +02:00
Tim 'mithro' Ansell
5f9ff09c08 vivado: Fix segfault with or1k. 
The or1k doesn't have any verilog include paths added. This means the
code use to generate;
```tcl
synth_design -top top -part xc7a50t-csg325-2 -include_dirs {}
```
which causes Vivado to segfault with the following error;
```
Command: synth_design -top top -part xc7a50t-csg325-2 -include_dirs {}
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a50t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a50t'
Abnormal program termination (11)
Please check 'build/netv2_base_or1k/gateware/hs_err_pid76959.log' for details
Traceback (most recent call last):
  File "./make.py", line 82, in <module>
```
 2017-04-29 16:44:18 +10:00
Florent Kermarrec
bedd428d9d soc/integration/builder: remove error when compile_software=False and integrated ROM: when using compile_software=False user knows what he's doing. 2017-04-26 13:49:16 +02:00
Florent Kermarrec
bb582619eb gen/genlib/cdc: cleanup lcm computation, fix timeout on BusSynchronizer 2017-04-25 15:13:47 +02:00
Florent Kermarrec
0daeff8689 gen/sim/core: do not use reset_less clock_domains for the one that are created (logic may need to access reset signal) 2017-04-25 10:56:19 +02:00
Florent Kermarrec
456cce3ec6 gen/genlib/cdc: import gcd from math and not fractions (deprecated) 2017-04-25 10:55:13 +02:00
Florent Kermarrec
4c7d460475 litex/gen/util/misc: import gcd from math and not fractions (deprecated) 2017-04-24 19:25:24 +02:00
Florent Kermarrec
c0800d25a6 soc/integration/builder.py: don't take care of ROM when compile_software is forced to False 2017-04-24 19:12:30 +02:00
Florent Kermarrec
b34f74397a soc/cores: add code_8b10b from misoc 2017-04-19 11:05:21 +02:00
Florent Kermarrec
9cfc594280 soc/cores: move flash cores to cores directory 2017-04-19 10:58:15 +02:00
Florent Kermarrec
e1319924aa soc: move uart to a single file 2017-04-19 10:37:59 +02:00
Florent Kermarrec
1acca39397 soc/cores: add new spi master, remove obsolete one 2017-04-19 10:22:35 +02:00
Florent Kermarrec
f73eb5fe71 gen/genlib/misc: add BitSlip 2017-04-19 09:55:19 +02:00
Florent Kermarrec
b708b9cfba gen/genlib/cdc: add gearbox 2017-04-19 09:54:51 +02:00
Florent Kermarrec
e27bc936ef boards/platforms: add vadj, change user_sw, user_btn IOStandard to LVCMOS25 2017-04-03 17:36:45 +02:00
Florent Kermarrec
5efd6a8412 soc/interconnect/stream_packet.py: make error payload optional on Packetizer 2017-03-28 12:21:54 +02:00
Florent Kermarrec
d173d946b7 boards/platforms/papilio_pro: fix imports 2017-03-27 10:40:29 +02:00
Florent Kermarrec
b6bc040142 boards/platforms/arty: add spi pins 2017-03-20 16:11:00 +01:00
Tim 'mithro' Ansell
4ee7019852 soc_core: Add CPU_RESET_ADDR as a constant. 
So we can do a "soft reset" by jumping to this address.
 2017-03-12 22:49:36 +11:00
Florent Kermarrec
c69012d713 boards/platforms/kcu105: add user_sma_gpio 2017-03-08 16:52:31 +01:00
Tim 'mithro' Ansell
36bb0f4f3a Allow using gcc for or1k. 
* Using CLANG can set by using CLANG=1 or CLANG=0 in the environment.
 * or1k continues to default to CLANG if environment is not net.
 2017-03-05 19:01:03 +11:00
William D. Jones
4dea714ec7 Add Mercury development board (port from MiSoC) 2017-02-21 05:06:51 -05:00
Florent Kermarrec
187d9577ab boards/platforms: fix IOStandard on sfp_tx_disable_n pins 2017-02-20 18:34:49 +01:00
Florent Kermarrec
1cda83f11b build/xilinx/programmer: add target parameter to load_bitstream to select jtag programmer 2017-02-20 17:37:03 +01:00
Florent Kermarrec
d8c7702be8 boards/platforms/kcu105: add sma/sfp ios 2017-02-20 15:55:41 +01:00
Florent Kermarrec
9774cbd20e boards/platforms/kc705: add sma/sfp/xadc ios 2017-02-20 12:22:23 +01:00
Florent Kermarrec
60f7e9c14f build/lattice/diamond: add jedec file generation 2017-02-18 17:33:50 +01:00
Florent Kermarrec
384f4f428e build/xilinx/vivado: set_property library only supported for vhdl 2017-02-17 11:42:55 +01:00
Florent Kermarrec
ac70083453 boards/plaforms: add FMC LPC connector to nexys_video 2017-02-16 19:16:07 +01:00
Florent Kermarrec
afd0a0c7f3 boards/targets: add dram to arty and nexys_video 2017-02-16 18:52:27 +01:00
Florent Kermarrec
5fde6d6d3d build/lattice/diamond: remove use of tools.mkdir_noerror 2017-02-16 11:48:22 +01:00
Florent Kermarrec
3711ae0615 boards/targets: remove build and load parameters on arty and nexys_video (consistency with others targets) 2017-02-10 12:32:33 +01:00
Florent Kermarrec
c98a90520e boards/kc705: store bios in flash as it's done for others litex targets (we could use flash in custom designs) 2017-02-10 09:30:10 +01:00
Florent Kermarrec
a3ef0fd53d boards/platforms/kcu105: add ddr4 dram pinout 2017-02-09 15:26:22 +01:00
Florent Kermarrec
892f019871 boards/platforms/nexys_video: fix IOStandards on hdmi_in 2017-02-06 18:18:36 +01:00
Florent Kermarrec
be4fbdcaeb boards/platforms/kcu105: add DP4 to DP7 to HPC connector 2017-02-02 18:44:12 +01:00
Florent Kermarrec
4177023a20 build/xilinx/programmer: remove open_hw_target parameters on VivadoProgrammer (now works for ultrascale) 2017-02-01 14:33:26 +01:00
Florent Kermarrec
790020de9f soc/cores/flash/spi_flash: remove bitbanging comment (no longer supported) 2017-02-01 12:21:56 +01:00
Florent Kermarrec
7b6f06cc07 boards/platforms/kcu105: fix GBTCLK0_M2C/GBTCLK1_M2C pins 2017-02-01 11:58:41 +01:00
Florent Kermarrec
0b86295c6d boards/platforms/kcu105: add user_sma_clock_p/n 2017-02-01 10:36:57 +01:00
Florent Kermarrec
df464aeaf3 boards/platforms/kcu105: add user_btns, user_dip_btns, clk300, i2c, spi_flash, rotary hdmi, pcie 2017-01-31 09:57:36 +01:00
Florent Kermarrec
194cf6c959 boards/platforms/kcu105: add LPC connector 2017-01-31 09:28:22 +01:00
Florent Kermarrec
c2dd7b1235 boards/platforms/kcu105: add user sma clock and HPC connector 2017-01-30 18:47:22 +01:00
Florent Kermarrec
f0020a6490 boards/platforms: add minimal kcu105 platform 2017-01-30 17:33:19 +01:00
Florent Kermarrec
de336a86e5 soc/integration/soc_core: use cpu_reset_address = self.mem_map["rom"] when using integrated_rom 2017-01-30 14:10:57 +01:00
Florent Kermarrec
67645ce7dd boards/platform/arty: add spiflash_4x/spiflash_1x to test SpiFlashDualQuad and SpiFlashSingle 2017-01-26 13:28:19 +01:00
Florent Kermarrec
4b77b850ce add SpiFlashSingle and rename SpiFlash to SpiFlashDualQuad 2017-01-26 13:28:18 +01:00
Tim 'mithro' Ansell
2444c090ab Adding paths for vivado. 2017-01-20 10:30:34 +11:00
enjoy-digital
6d0096a18e Merge pull request #14 from mithro/spiflash2 
spi_flash: fix bitbang with spi_width=1
 2017-01-17 04:41:05 +01:00
Florent Kermarrec
455cb3ebe3 soc/software/main: fix double serialboot (merge issue) 2017-01-17 04:37:18 +01:00
Tim 'mithro' Ansell
bd0eb48357 Fixing missing csr_constant/config support. 
Missed as part of misoc merge at ff31959aea.
 2017-01-14 19:24:04 +11:00
Tim 'mithro' Ansell
9c0e978556 Fixing accidental revert in merge commit. 2017-01-14 00:13:53 +11:00
Florent Kermarrec
ff31959aea merge most of misoc 54e1ef82 and migen e93d0601 changes 2017-01-13 03:55:00 +01:00
enjoy-digital
2507eff890 Merge pull request #15 from joeladdison/master 
Add strcasecmp function to lib
 2017-01-12 04:24:28 +01:00
Florent Kermarrec
f0202db90f gen/genlib/cdc: add GrayDecoder from misoc 2017-01-12 04:15:33 +01:00
Joel Addison
31dbd35c2e Add strcasecmp function to lib 2017-01-12 14:00:05 +11:00
Florent Kermarrec
ab5b9389b7 soc/tools/litex_term.py: fix reader for c = b"\r" case 2017-01-11 01:56:31 +01:00
Florent Kermarrec
30f7dd69bd soc/interconnect/stream/: add busy signal to PipelinedActor 2017-01-10 02:18:21 +01:00
Sebastien Bourdeauducq
e39c470bbc spi_flash: fix bitbang with spi_width=1 2016-12-26 14:11:49 +01:00
Tim 'mithro' Ansell
b81839bf1a Raise AttributeError. 
Makes hasattr work correctly.
 2016-12-23 11:14:18 +01:00
Tim 'mithro' Ansell
284c94f1d3 Fix Makefile dependency inclusion for other software. 2016-12-19 14:29:33 +01:00
enjoy-digital
ffc342f49c Merge pull request #11 from mithro/file-dont-change 
Only require rebuild on actual changes
 2016-12-17 14:43:34 +01:00
Tim 'mithro' Ansell
1f6dc446d2 Allow CSRElement objects to be autocompleted. 2016-12-17 14:14:53 +01:00
Tim 'mithro' Ansell
722edfe9e8 Provide csr_data_width via the constants. 2016-12-17 14:14:53 +01:00
Tim 'mithro' Ansell
8bccd2d988 bios: Include dependency rebuild info. 2016-12-17 14:14:14 +01:00
Tim 'mithro' Ansell
46bbec5494 main.o is not a phony target. 2016-12-15 19:56:58 +01:00
Tim 'mithro' Ansell
4522157ddd Use write_to_file helper. 2016-12-15 19:51:36 +01:00
Tim 'mithro' Ansell
8179a9ea2e Don't modify file if contents hasn't changed. 2016-12-15 19:14:12 +01:00
Tim 'mithro' Ansell
9d716def9d Make the csv directory if it doesn't exist. 2016-12-15 17:19:51 +01:00
Florent Kermarrec
8b5166f294 litex/boards: add machxo3 starter kit platform 2016-12-02 17:28:32 +01:00
Florent Kermarrec
873e50430e litex/build: move xcf_template to platform (xcf is specific to platform) 2016-12-02 17:23:40 +01:00
Florent Kermarrec
daa9473809 soc/software/bios/main: revision command becomes ident 2016-11-30 15:45:06 +01:00
Florent Kermarrec
0f57451f30 soc/software/bios: remove dataflow 2016-11-30 15:44:30 +01:00
whitequark
460185fa8e litex_term: nicer progress bar 2016-11-30 15:36:13 +01:00
Florent Kermarrec
4f3ce6db2b build/xilinx/vivado: fix settings source on linux 2016-11-30 15:28:38 +01:00
enjoy-digital
7bb2be41e8 Merge pull request #9 from mithro/vprintf-fix 
libbase: Adding missing vprintf function.
 2016-10-30 09:43:43 +01:00
Tim 'mithro' Ansell
548fd33d20 libbase: Adding missing vprintf function. 
Fixes #8.

```
int vprintf(const char *format, va_list ap);

The functions vprintf(), vfprintf(), vsprintf(), vsnprintf() are equivalent to
the functions printf(), fprintf(), sprintf(), snprintf(), respectively, except
that  they  are  called  with  a  va_list instead of a variable number of
arguments.
```
 2016-10-30 16:25:06 +11:00
Tim 'mithro' Ansell
35ba9cf735 soc/software/Makefile: Fix Makefile depend generation. 
Previously the flags were not actually set and the *.d files were never
actually generated.
 2016-10-28 01:25:47 +11:00
Florent Kermarrec
7a9cf57cfe boards/targets/sim: fix 2016-10-14 17:49:04 +02:00
Robert Jordens
677243bd8c ElasticBuffer: infer reset 2016-10-14 09:43:09 +02:00
Florent Kermarrec
4362e5c528 gen/genlib/cdc: add ElasticBuffer 2016-10-13 17:04:39 +02:00
Florent Kermarrec
b74132f563 boards/platforms: add papilio_pro 2016-09-01 16:27:49 +02:00
Florent Kermarrec
99f2e31b2e soc/tools/remote: allow direct use of comm_udp and some fixes 2016-07-18 17:04:58 +02:00
Florent Kermarrec
d59757eb4a build/xilinx/ise: remove debug print 2016-06-29 23:32:43 +02:00
Florent Kermarrec
9499147bd4 build/xilinx/ise: fix top name 2016-06-29 23:22:57 +02:00
Florent Kermarrec
3bb2bc35e2 boards/targets/sim: desactivate refresh for simulation 2016-06-20 16:00:19 +02:00
Florent Kermarrec
f193873bb8 soc/tools/remove/comm_uart: limit write bursts to 8 32bits words 2016-05-30 16:16:05 +02:00
Florent Kermarrec
6a35337a09 gen/sim/vcd: allow continous update of vcd file and dynamic signals 
With continous update, VCD header needs to be writen at the beginning of the simulation.
When a new signal is created, we rewrite the header and the content.
 2016-05-28 10:25:48 +02:00
Florent Kermarrec
fa7ac6c9a2 build/sim/dut_tb: add bottom line on surface to show frame count 2016-05-23 10:20:05 +02:00
Florent Kermarrec
65f74959b3 gen/sim/core: add Display support 2016-05-18 15:47:10 +02:00
Florent Kermarrec
6fe3e1237d gen/fhdl/structure: fix Display 2016-05-18 12:41:29 +02:00
Florent Kermarrec
36fd466324 build/sim/dut_tb: rename needs to wait 2016-05-12 15:39:51 +02:00
Florent Kermarrec
e890a566a9 buid/sim: add vga framebuffer with SDL 2016-05-04 20:17:02 +02:00
Florent Kermarrec
55c9c653e0 adapt to litedram changes 2016-05-04 00:59:02 +02:00
Florent Kermarrec
7a7b9420e6 soc/integration/soc_dram: sync with litedram 2016-05-03 19:44:33 +02:00
Florent Kermarrec
dca8b3c92e boards/targets/sim: update litedram 2016-05-01 10:26:21 +02:00
Florent Kermarrec
69f0035315 gen/fhdl: add Display for debug in simulation 2016-04-29 23:03:43 +02:00
Florent Kermarrec
e79b2e3fef boards/targets: SDRAM modules are now litedram.modules 2016-04-29 19:05:23 +02:00
Florent Kermarrec
3d71ba6e66 targets: remove sdram_controller_type parameter (minicon removed) 2016-04-29 17:51:16 +02:00
Florent Kermarrec
8c7332e75e soc/integration/soc_sdram: use new LiteDRAM names 2016-04-29 17:40:55 +02:00
Florent Kermarrec
dc52d33fba soc_sdram: remove minicon support (we will make lasmicon more configurable to reduce ressource usage) 2016-04-29 16:24:24 +02:00
Florent Kermarrec
44d766c09f software/sdram: cleanup artix7 init 2016-04-29 15:55:10 +02:00
Florent Kermarrec
66362b1280 move sdram code to litedram (https://github.com/enjoy-digital/litedram) 2016-04-29 07:45:15 +02:00
Florent Kermarrec
42767286ca gen/fhdl/verilog: add do in reserved_keywords 2016-04-27 17:43:25 +02:00
Florent Kermarrec
80d673e502 soc/integration/soc_sdram: always generate L2_SIZE constant 2016-04-27 12:34:18 +02:00
Florent Kermarrec
4e451a78d6 soc/software/bios/sdram: add sdrlevel_artix7 (bitslip and delays have to be found manually) 2016-04-27 12:33:44 +02:00
Florent Kermarrec
ab8569916b boards/platforms/arty: use 1.5V and the 16bits instead of only 8bits 2016-04-26 23:29:35 +02:00
Florent Kermarrec
e6681bbb9c soc/interconnect/wishbone: add FlipFlop (should be removed) 2016-04-25 19:14:20 +02:00
Florent Kermarrec
b6d8999471 platforms/arty: add missing address pins, was not going to work :( 2016-04-25 16:56:23 +02:00
Florent Kermarrec
f6e1c45d57 gen/genlib/record: fix connect 2016-04-21 19:05:01 +02:00
Florent Kermarrec
e80cfedd7f gen/genlib/record: fix connect 2016-04-21 12:16:26 +02:00
Florent Kermarrec
9ae16c2f40 boards/platforms/nexys_video: use TDMS_33 on hdmi 2016-04-21 11:13:29 +02:00
Florent Kermarrec
3d98be0997 use new Record.connect omit parameter (replace leave_out) 2016-04-21 09:39:21 +02:00
Florent Kermarrec
c330e7be49 gen/genlib/record: rename leave_out by omit and add keep parameter to Record.connect 2016-04-21 09:39:12 +02:00
Florent Kermarrec
ee378b2557 boards/plaforms/nexys_video: fix hdmi_out pinout 2016-04-19 19:04:05 +02:00
Florent Kermarrec
849434c1bd soc/software/bios: show cpu on first banner line 2016-04-19 09:19:37 +02:00
enjoy-digital
76bb0ef456 Merge pull request #2 from mithro/master 
More fixes.
 2016-04-19 09:07:23 +02:00
Florent Kermarrec
1b9ab2f1fc soc/integration/cpu_interface: fix clang detection 2016-04-19 08:06:56 +02:00
Tim 'mithro' Ansell
d9b598368f Make verilator build output error messages. 2016-04-19 16:02:26 +10:00
Tim 'mithro' Ansell
8998ae5c92 bios: Print CPU architecture on boot. 2016-04-19 16:02:26 +10:00
enjoy-digital
e0e56e3655 Merge pull request #1 from mithro/master 
Bunch of small fixes
 2016-04-19 07:49:24 +02:00
Tim 'mithro' Ansell
514496d744 libcompiler_rt: Fixing Makefile for CPU endianness. 2016-04-19 14:55:01 +10:00
Florent Kermarrec
5ba03160ed soc/cores: fix spi 2016-04-19 06:49:23 +02:00
Florent Kermarrec
7b7f1dd68c Merge branch 'master' of https://github.com/enjoy-digital/litex 2016-04-19 06:05:22 +02:00
Tim 'mithro' Ansell
e7f3c585b7 Allow using gcc for or1k. 
* Using CLANG can set by using CLANG=1 or CLANG=0 in the environment.
 * or1k continues to default to CLANG if environment is not net.
 2016-04-19 14:03:24 +10:00
Tim 'mithro' Ansell
2f834d0aa2 bios: Use single characters for boot modes. 
* The function keys never really worked properly.
 * Also add commands for the ROM/Flash/etc.
 2016-04-19 13:42:56 +10:00
Florent Kermarrec
429f533bd0 soc/cores/sdram/settings: simplify modules and fix timing margins computation 2016-04-18 18:22:53 +02:00
Florent Kermarrec
41f6408d56 Merge branch 'master' of https://github.com/enjoy-digital/litex 2016-04-15 08:09:42 +02:00
Florent Kermarrec
7b3699839e build/xilinx/ise: use Tim's fix on add_period_constraint and add_false_path_constraint 2016-04-14 21:48:52 +02:00
Florent Kermarrec
3d222d9e63 soc/interconnect/dma_lasmi: change endpoint names 2016-04-13 18:28:52 +02:00
Florent Kermarrec
fcd8d792a1 Merge branch 'master' of https://github.com/enjoy-digital/litex 2016-04-13 01:19:21 +02:00
Florent Kermarrec
6e0045e6be soc/integration/soc_sdram: allow passing controller settings in register_sdram 2016-04-12 20:16:47 +02:00
Florent Kermarrec
40eb779e67 software/include/base: fix system.h for or1k 2016-04-10 17:21:54 +02:00
Florent Kermarrec
238d69f186 software/common: use -std=gnu99 for GCC 2016-04-10 17:21:17 +02:00
Florent Kermarrec
b2eaf412c1 soc/interconnect/stream/PipelinedActor: add latency attribute 2016-04-07 12:10:32 +02:00
Florent Kermarrec
9fa9bdcf68 build/sim: adapt verilator simulation to new stream signals 2016-04-07 08:56:53 +02:00
Florent Kermarrec
8ced064160 soc/software/libcompiler_rt: fix mulsi3 compilation 2016-04-07 08:28:38 +02:00
Florent Kermarrec
80d78698e3 soc/software/libnet/microudp: fix debug flag 2016-04-07 08:28:38 +02:00
Florent Kermarrec
454d5d13e2 soc/software: fix libcompiler_rt mulsi3.c compile 2016-04-04 08:36:23 +02:00
Florent Kermarrec
17f6cb1f17 initial RISC-V support (with picorv32), still some software to do (manage IRQ, L2 cache flush) 2016-04-01 00:09:17 +02:00
Florent Kermarrec
7e62cdf601 soc/software/bios: update default ip addresses (local: 192.168.1.50 / remote: 192.168.1.100) 2016-03-31 10:55:11 +02:00
Florent Kermarrec
1d4f44e7db soc/interconnect/stream_sim: add more genericity to PacketStreamer/PacketLogger to use them for all cores 2016-03-31 00:02:22 +02:00
Florent Kermarrec
b8d89535fd soc/cores/sdram/phy: fix S6QuarterRateDDRPHY 2016-03-29 14:59:30 +02:00
Florent Kermarrec
f512971d9e gen/sim: hack to update vcd output file during simulation (allow visualizing progress directly and having a vcd file even when simulation fails or doesn't stop) 2016-03-25 13:22:26 +01:00
Florent Kermarrec
0ef1d44c44 gen/sim, fhdl: remove port.we_granularity limitation on simulations 
We have to find a way to eliminate all replaced memory ports from specials,
here we use a workaround and remove remaining _MemPorts before simulating.

If possible, proper way would be to remove replaced ports from specials.
Another solution can to remove all ports that are no longer associated with
a Memory.
 2016-03-23 09:46:54 +01:00
Florent Kermarrec
9517b9b870 soc/interconnect/stream_sim: use passive generators and some cleanup 2016-03-23 01:04:33 +01:00
Florent Kermarrec
5e16516706 gen: add missing sim files 2016-03-21 23:52:52 +01:00
Florent Kermarrec
dd2397b57c gen: remove vpi (no longer used) 2016-03-21 20:07:03 +01:00
Florent Kermarrec
cf29ee0b91 soc/interconnect/stream_sim: adapt to new simulator 2016-03-21 19:56:43 +01:00
Florent Kermarrec
703b30e078 gen/build: merge with migen 0575c749e35a7180f0dca408e426af8eef22b568 and reintegrate migen simulator 
* fhdl/visit: determinism
* structure/Case/makedefault: fix corner cases
* fhdl/tools: apply lowerer to specials in deterministic order
* fhdl/verilog: fix variable name conflict
* fhdl/verilog: simpler names for IOs. Closes #40
* fhdl/namer: deterministic naming of signals with name_override
* use https url for m-labs.hk
* pipistrello: make PMOD an extension header
* vivado: find clock nets by get_nets, not get_ports
* build: support platform-independent false path designation
* sim: add more signals to VCD (#36)
* build/xilinx: fix error message when Xilinx toolchain directory exists but does not contain a ISE version directory. Closes #39
* kc705: make xadc an extension header
* kc705: add xadc/ams gpios
* Merge branch 'master' of github.com:m-labs/migen
* conda: fix for conda-build > 1.19
* platforms/kc705: enable on-die termination for user_sma_clock
* README: update
* Revert "conda: use BUILDNUMBER from environment."
This reverts commit b2eedfd2e24f0b83c2fb118a3f98cf349b256e91.
* conda: use BUILDNUMBER from environment.
* typo
* Exception now has helpful string.
* README: remove outdated build badge
* sim: run MemoryToArray before lowering specials
* fhdl/simplify/MemoryToArray: remove spurious memory ports from specials
* sim: make unlowered specials an error
* sim: lower specials, closes #34
* sim: support evaluating Replicate()
* Revert "README.md->rst"
* Prevent backslashes in (Windows) paths from being escaped by OpenOCD's TCL implementation.
* Revert "conda: run tests as a part of package build."
* Revert "setuptools: include examples as migen.examples."
* Revert "test: also look for examples in [.../dist-packages]/migen/examples/."
* conda: use source from the current checkout.
* travis: disable (superseded by our buildbot).
* test: also look for examples in [.../dist-packages]/migen/examples/.
* setuptools: include examples as migen.examples.
* conda: run tests as a part of package build.
* build: return to current working directory after building
* sim/vcd: support signals not appearing in FHDL
* sim: deterministic clock iteration
* sim: add support for passive generators
* fhdl/structure: fix last test in _Value.__bool__ (a instead of b)
 2016-03-21 19:15:40 +01:00
Florent Kermarrec
71a719be44 soc/interconnect/stream: use valid/ready/last signals instead of stb/ack/eop (similar to AXI) 2016-03-16 20:13:47 +01:00
Florent Kermarrec
9032665750 soc/interconnect/wishbonebridge: fix import 2016-03-16 19:34:50 +01:00
Florent Kermarrec
d7112efdba soc/interconnect/stream_packet: remove Buffer (we will use simple fifo for now) 2016-03-16 19:33:29 +01:00
Florent Kermarrec
39aacf2df4 soc/interconnect/stream: remove busy signal, BufferizeEndpoints refactoring 2016-03-16 19:33:00 +01:00
Florent Kermarrec
e0e2427795 soc: replace all Sink/Source with stream.Endpoint 2016-03-16 18:05:57 +01:00
Florent Kermarrec
c860581b86 soc/interconnect/stream: use new Converter/StrideConverter 2016-03-16 17:00:58 +01:00
Florent Kermarrec
8c272c1f6f soc/interconnect/stream: fix missing param 2016-03-16 16:21:32 +01:00
Florent Kermarrec
cb47373383 soc/interconnect/stream: remove packetized parameter and use of sop 2016-03-16 11:54:28 +01:00
Florent Kermarrec
44a5b95281 soc/interconnect/stream: set packetized to True by default (we are going to remove this parameter) 2016-03-15 15:52:57 +01:00
Florent Kermarrec
a016ededa0 soc/integration/builder: remove use of symlinks (simply use make -C dst_dir -f src_dir/Makefile, thanks robert) 2016-03-04 20:56:05 +01:00
Florent Kermarrec
042c36ee1b soc/tools/litex_term: continue cleanup 2016-02-19 17:44:25 +01:00
Florent Kermarrec
2fa848c15f soc/tools/litex_term: continue cleanup 2016-02-19 14:35:18 +01:00
Florent Kermarrec
247ecc5d8a soc/tools/litex_term: continue cleanup 2016-02-19 13:38:34 +01:00
Florent Kermarrec
ed2e623994 soc/tools/litex_term: remove write_exact, use more bytes 2016-02-19 00:20:10 +01:00
Florent Kermarrec
4bdefbdfba soc/tools/litex_term: remove character function 2016-02-19 00:02:38 +01:00
Florent Kermarrec
5b8566d20f soc/tools/litex_term: replace get_file_data with f.read() 2016-02-18 23:55:41 +01:00
Florent Kermarrec
68c2d3b7a0 soc/tools/remove: fix import 2016-02-18 12:55:18 +01:00
Florent Kermarrec
fd2997bf4a build/xilinx: cleanup Vivado/ISE special_overrides 2016-02-18 00:36:53 +01:00
Florent Kermarrec
8ee3874088 soc/integration/soc_core: instanciate wishbone/csr/interrupts only if we have at least a wishbone master 2016-02-18 00:11:25 +01:00
Florent Kermarrec
34b45e3618 gen/build: use verilog 2001-style synthesis attributes for vivado (will need rework) 2016-02-11 22:54:26 +01:00
Florent Kermarrec
2218ece98a soc/interconnect/stream: fix merge issue (missing params connect) 2016-02-01 00:08:27 +01:00
Florent Kermarrec
6c71811138 soc/tools/litex_term: also rename inside file 2016-01-16 21:26:33 +01:00
Florent Kermarrec
601c91a3e2 soc/tools: rename to litex_term, litex_server, litex_client 2016-01-16 21:22:21 +01:00
Florent Kermarrec
162900144a soc/tools/remove_server: cleanup 2016-01-16 21:12:19 +01:00
Florent Kermarrec
b856b54720 soc/tools/flterm: get rid of serial.tools.miniterm import and fix echo on linux 2016-01-16 21:05:03 +01:00
Florent Kermarrec
002508a69a soc/integration: return vns with soc and builder 2016-01-14 17:15:39 +01:00
Florent Kermarrec
2c32791a28 soc/software/bios/main: add capability to configure TEST_USER_ABORT_DELAY 2016-01-14 16:53:04 +01:00
Florent Kermarrec
492f276247 soc/software/bios/main: give priority to romboot over serialboot/netboot 2016-01-14 16:46:42 +01:00
Florent Kermarrec
9913da5ac9 boards/targets: change mode (add +x) 2016-01-01 18:37:20 +01:00
Florent Kermarrec
7b879b36c6 soc/tools/remove/server: avoid closing server when client closes connection 2015-12-27 22:33:08 +01:00
Florent Kermarrec
0498a31818 some cleanup 
- remove Sink/Source connect specialization.
- remove use of Record.connect
- use sink/source on Buffer
 2015-12-27 13:09:58 +01:00
Florent Kermarrec
219fbef26c soc/tools/remove/client: set socket timeout to 5s 2015-12-27 11:26:58 +01:00
Florent Kermarrec
6ea65f957c soc/interconnect/stream: expose Endpoint 2015-12-19 21:49:45 +01:00
Florent Kermarrec
6a4e3bb5c0 build/xilinx/vivado: use build_name as top in synth_design 2015-12-09 11:40:27 +01:00
Florent Kermarrec
3191533889 soc/software/libnet: add debug defines on microudp 2015-12-07 12:03:36 +01:00
Florent Kermarrec
4fed1cc7a7 soc/integration/builder: move csr_csv generation outside of generate include 
we mostly use csr_csv for designs without CPU
 2015-12-03 15:16:22 +01:00
Florent Kermarrec
90f03133ef build/sim/verilator: add toolchain_path parameter 2015-12-02 15:35:55 +01:00
Florent Kermarrec
e8262ed447 build: pass build_name to get_verilog (same name for top module and top level file) 2015-12-02 14:18:09 +01:00
Florent Kermarrec
b7a1888a36 gen/fhdl/verilog: add regular comb parameter to allow implementation of simulation code (for icarus) 
We will remove that when we will be using new migen simulator
 2015-12-02 14:16:23 +01:00
Florent Kermarrec
646d3b19b4 boards/nexys_video: use ethernet constraints similar to kc705 2015-12-01 11:50:05 +01:00
Florent Kermarrec
ca6b9aa6e3 boards/targets: add default rom/ram configuration for arty 2015-12-01 10:20:16 +01:00
Florent Kermarrec
e5d35ccb6d boards/targets: add nexys_video 2015-12-01 10:19:41 +01:00
Florent Kermarrec
4bfd1fdce6 boards/plaforms: fix IOStandard of eth_rst_n 2015-11-30 22:27:40 +01:00
Florent Kermarrec
b6a6b5d540 boards/platforms: add cpu_reset to nexys_video and some fixes around DDR3 2015-11-30 21:53:01 +01:00
Florent Kermarrec
5694dca0fc boards/platforms: add hdmi_in/hdmi_out/ethernet/dram to nexys_video 2015-11-30 20:46:57 +01:00
Florent Kermarrec
7e1df951ba boards/platforms: add nexys_video (basic) 2015-11-30 20:25:00 +01:00
Florent Kermarrec
a716c562f0 gen/build: use name_override for all IOs defined in Platform file (avoid random naming of IOs) 2015-11-30 18:26:33 +01:00
Florent Kermarrec
53c86e34f4 build: ensure we return to working directory after building 2015-11-30 13:33:39 +01:00
Florent Kermarrec
f6aeb6e41a soc/interconnect/stream: improve Pipeline to allow passing endpoints 2015-11-28 18:31:47 +01:00
Florent Kermarrec
d85d2b7b9b soc/interconnect/stream_packet: add check of field's width vs signal's width in Header.get_field 2015-11-27 20:14:01 +01:00
Florent Kermarrec
c0539fff3e boards: add new digilent arty 2015-11-27 00:29:30 +01:00
Florent Kermarrec
c24727ab4c soc/integration: allow using builder with soc.cpu_type == None 2015-11-26 17:44:50 +01:00
Florent Kermarrec
7298fff1e6 soc/interconnect/stream_packet: fix Counter removing 2015-11-24 20:30:53 +01:00
Florent Kermarrec
8ebffc563a soc/tools/remote/csr_builder: manage memory regions and some fixes on CSRRegister 2015-11-23 19:13:37 +01:00
Florent Kermarrec
254504e73f soc/integration/builder: export constants and memory_regions with csr_csv 2015-11-23 19:12:58 +01:00
Florent Kermarrec
f6a2d5847a soc/tools/remote/client: make csr_csv parameter optional and default value to None 2015-11-23 18:39:28 +01:00
Florent Kermarrec
6f4dd14ffa soc/software/boot: add #ifndef on LOCALIP and REMOTEIP to allow definition in the SoC with add_constant 2015-11-23 11:08:04 +01:00
Florent Kermarrec
cb22a207f1 build/generic_platform: add support for int parameter for Pins (useful for core generation) 2015-11-19 14:57:09 +01:00
Florent Kermarrec
8056653004 soc/tools/remote/server: add --debug parameter 2015-11-17 15:43:10 +01:00
Florent Kermarrec
6870707620 soc/tools/remoter/server: fix exit on KeyboardInterrupt 2015-11-17 15:31:23 +01:00
Florent Kermarrec
8ff31557c6 soc/tools/remoter/server: add some printfs 2015-11-17 15:18:46 +01:00
Florent Kermarrec
1a92489555 soc/tools/remote: add comm_pcie and comm_udp (to be tested) 2015-11-17 15:07:00 +01:00
Florent Kermarrec
d6fdd76930 soc/tools/remote: small cleanup and remove csr_data_width from server side 2015-11-17 11:35:22 +01:00
Florent Kermarrec
71483b8935 soc/tools: initialize wishbone remote control (for now only uart) 2015-11-17 01:05:52 +01:00
Florent Kermarrec
1cde84dccf soc/cores/uart remove software (will be re-written and will move to soc/tools) 2015-11-16 17:07:22 +01:00
Florent Kermarrec
1f80bb9561 soc/interconnect/stream_packet: remove Counter 2015-11-16 16:53:23 +01:00
Florent Kermarrec
ec35290c45 soc/interconnect/wishbonebridge: remove Counter 2015-11-16 16:48:37 +01:00
Florent Kermarrec
6fd0b73817 build: remove edif support 2015-11-16 16:26:38 +01:00
Florent Kermarrec
e407a1cdda gen/fhdl/verilog: remove asic_syntax and expose reg_initialization, dummy_signal and blocking_assign 2015-11-16 16:18:09 +01:00
Florent Kermarrec
2f52d364af soc/interconnect/stream/SyncFIFO: expose fifo level 2015-11-16 16:11:31 +01:00
Florent Kermarrec
7ed2576ce1 soc/integration/cpu_interface: add bases, constants and memories output to csv files 2015-11-15 00:04:44 +01:00
Florent Kermarrec
af909b43d5 soc/cores/uart: add UARTWishboneBridgeDriver software 2015-11-14 21:23:20 +01:00
Florent Kermarrec
3a2e6117f4 soc/interconnect/stream: add Cast and others small fixes 2015-11-14 12:17:09 +01:00
Florent Kermarrec
041483dbe1 soc/integration/builder: only copy Makefiles when not using symlinks 2015-11-14 03:36:46 +01:00
Florent Kermarrec
a2aa5726bf soc/cores: remove liteeth_mini and use liteeth 2015-11-14 03:22:43 +01:00
Florent Kermarrec
16ba646b1b add TODOs 2015-11-14 03:15:10 +01:00
Florent Kermarrec
cf4c7da2e7 fix soc/integration/soc_core.py 2015-11-14 02:44:12 +01:00
Florent Kermarrec
032f5a9620 soc/interconnect: add stream_sim 2015-11-14 00:43:49 +01:00
Florent Kermarrec
ba959c832d soc/interconnect: rename packet to stream_packet 2015-11-14 00:42:58 +01:00
Florent Kermarrec
fc3ffe87ac for now use our fork of migen (to be able to simulate our designs) 2015-11-13 18:31:46 +01:00
Florent Kermarrec
ae3d54499a litex/gen: reintegrate migen with modifications to be able to simulate with vpi until all missing features of the new simulator are implemented 2015-11-13 14:44:16 +01:00
Florent Kermarrec
7d6cee6751 soc/interconnect/stream: add BufferizeEndpoints 2015-11-12 18:54:15 +01:00
Florent Kermarrec
83427c87cd soc/interconnect/stream: add Pipeline 2015-11-12 01:41:23 +01:00
Florent Kermarrec
81c6facca2 soc/interconnect/stream: reintroduce params 2015-11-12 01:12:15 +01:00
Florent Kermarrec
f6b30fcae2 soc/interconnect: add packet 2015-11-12 00:54:40 +01:00
Florent Kermarrec
525da89c7d soc/interconnect: add wishbonebridge and uart bridge 2015-11-12 00:52:36 +01:00
Florent Kermarrec
89b189ce4a soc/interconnect/stream: reintroduce PipelinedActor/Buffer 2015-11-12 00:51:32 +01:00
Florent Kermarrec
194e6137ae soc/integration/soc_core: add support for SoCs without CPU 2015-11-12 00:50:23 +01:00
Florent Kermarrec
c076c2cbd6 boards/targets: remove papilio_pro/pipistrello 2015-11-11 17:38:03 +01:00
Florent Kermarrec
352cb91688 soc/integration/builder: add use_symlinks parameter and desactivate symlinks by default 
On windows machines, console need to be run as Administrator to create symlinks which is bit painful.
 2015-11-11 17:37:28 +01:00
Florent Kermarrec
1cec0f8086 boards/targets/sim: add ethernet support 2015-11-11 14:23:39 +01:00
Florent Kermarrec
1f6983da2c soc/cores/liteeth_mini: add phy model for verilator simulation 2015-11-11 14:22:27 +01:00
Florent Kermarrec
481163b233 soc/cores: reintroduce liteeth_mini (until we switch to liteeth) 2015-11-11 14:01:48 +01:00
Florent Kermarrec
714a3d88e2 add LICENSE, update copyrights, add Migen install instructions 2015-11-11 13:22:39 +01:00
Florent Kermarrec
bda196fbc8 soc/software/bios/sdram: split memtest and allow external #define of memtest sizes 2015-11-11 13:10:03 +01:00
Florent Kermarrec
619cd8e695 avoid forking migen, we will add custom modules in litex/gen but will use upstream migen for common modules 2015-11-11 12:10:55 +01:00
Florent Kermarrec
3f43a49382 soc: merge with misoc 3fcc4f116c3292020cb811d179e45ae45990101b 
changes:
-software/bios: remove dataflow
-cores/identifier: replace with user-defined string
-interconnect/CSRBankArray: support read-only mappings
-targets: Added Numato Mimas V2 target
-Our libunwind changes were merged upstream.
-wishbone: update TODO
-replace Counter in Converters
-Fix CSRBankArray
-flterm: properly exit on ^C.
 2015-11-10 16:51:51 +01:00
Florent Kermarrec
3297210e48 boards/targets/sim: get SDRAM working in simulation with sdram/model 2015-11-10 12:57:23 +01:00
Florent Kermarrec
4afe4a07e4 soc/software: remove memtest (should be re-written) 2015-11-10 12:22:08 +01:00
Florent Kermarrec
6764c06b62 soc/sofware: remove libdyld 2015-11-10 12:21:23 +01:00
Florent Kermarrec
f72e172ac3 soc/software: remove libunwind 2015-11-10 12:16:34 +01:00
Florent Kermarrec
85e6716b6b litex/build/xilinx/programmer: remove UrJTAG and Adept 2015-11-10 12:01:25 +01:00
Florent Kermarrec
a775672314 litex: get verilator simulation working and add sim target as example 2015-11-07 23:51:37 +01:00
Florent Kermarrec
6a0f85dc42 litex: reorganize things, first work working version 2015-11-07 17:48:55 +01:00
Florent Kermarrec
637634f312 import migen in litex/gen 2015-11-07 12:22:32 +01:00
Florent Kermarrec
b028569784 import misoc in litex/soc 2015-11-07 12:19:30 +01:00