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729 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq d4baac6c0f bus/csr: allow specifying existing interface 2012-11-17 19:44:25 +01:00
Sebastien Bourdeauducq 86090e1cbd bus/asmibus: swap port position to be consistent with wishbone API 2012-11-17 19:42:39 +01:00
Sebastien Bourdeauducq ece786d6aa bus/wishbone: allow specifying existing interface 2012-11-17 19:42:06 +01:00
Sebastien Bourdeauducq d0d4c48098 bus/transactions: add busname parameter 2012-11-17 19:36:08 +01:00
Sebastien Bourdeauducq 897a2e3f9c actorlib/sim: split TokenExchanger 2012-11-17 14:15:51 +01:00
Sebastien Bourdeauducq eb156af20c pytholite/io: support token pull 2012-11-16 23:48:41 +01:00
Sebastien Bourdeauducq dd9a102a78 pytholite/io: support token push 2012-11-16 19:24:45 +01:00
Sebastien Bourdeauducq bf5ce8dc20 pytholite: move expression and register handling to separate modules 2012-11-11 23:48:23 +01:00
Sebastien Bourdeauducq f59fd69e34 pytholite/compiler: recognize composite I/O pattern 2012-11-11 18:03:16 +01:00
Sebastien Bourdeauducq 0b5652bb79 pytholite/compiler: visit_assign_special 2012-11-11 15:52:06 +01:00
Sebastien Bourdeauducq 687d18a150 pytholite: move FSM management to separate module 2012-11-11 14:30:25 +01:00
Sebastien Bourdeauducq 409a5570e4 pytholite/compiler: refactor visit_block 2012-11-11 14:17:52 +01:00
Sebastien Bourdeauducq fb63698ef4 pytholite/compiler: clean up visit_statement 2012-11-10 23:30:14 +01:00
Sebastien Bourdeauducq 6ebd1e4503 pytholite: forward 'yield call' statements to io module 2012-11-10 22:59:14 +01:00
Sebastien Bourdeauducq 48acb1bcfd pytholite: introduce io module 2012-11-10 21:51:19 +01:00
Sebastien Bourdeauducq 6776f06a42 pytholite/compiler: support bitslice 2012-11-10 18:04:05 +01:00
Sebastien Bourdeauducq 37f113c3ea pytholite/compiler: support range(constants) in for loops 2012-11-10 15:26:13 +01:00
Sebastien Bourdeauducq 370bab1190 pytholite/compiler: cleanup print statements 2012-11-10 15:10:57 +01:00
Sebastien Bourdeauducq 39c7dc7d63 pytholite/compiler: support for loops (iterating on lists only) 2012-11-10 15:02:55 +01:00
Sebastien Bourdeauducq 93db3edd00 pytholite/compiler: support while loops 2012-11-10 14:37:33 +01:00
Sebastien Bourdeauducq a901ef46ab Revert "pytholite/compiler: SymbolStack" 
This reverts commit f57da497b2.
 2012-11-10 12:09:45 +01:00
Sebastien Bourdeauducq f57da497b2 pytholite/compiler: SymbolStack 2012-11-09 23:02:16 +01:00
Sebastien Bourdeauducq 5750c7c07e pytholite/compiler: improve naming of selection signals 2012-11-09 20:19:22 +01:00
Sebastien Bourdeauducq 4921a34616 pytholite/compiler: fix handling of constants 2012-11-09 20:17:57 +01:00
Sebastien Bourdeauducq 26cf1b8840 fhdl: make constants hashable 2012-11-09 20:17:43 +01:00
Sebastien Bourdeauducq c1b8492b61 pytholite/compiler: go to next state 2012-11-09 20:12:15 +01:00
Sebastien Bourdeauducq e1075a962c pytholite/compiler: support if statements 2012-11-09 19:37:52 +01:00
Sebastien Bourdeauducq 92ff5095da pytholite/compiler: support comparisons in expressions 2012-11-09 18:41:32 +01:00
Sebastien Bourdeauducq a645e0b24e pytholite/compiler: create FSM 2012-11-09 17:37:42 +01:00
Sebastien Bourdeauducq 7744655ef2 fhdl/visit: add missing self 2012-11-09 17:37:24 +01:00
Sebastien Bourdeauducq 13af0ce556 fhdl: visit module (untested) 2012-11-09 16:00:11 +01:00
Sebastien Bourdeauducq 9c182c47d1 pytholith: add register muxes 2012-11-08 21:49:20 +01:00
Sebastien Bourdeauducq 18758d87f6 pytholite: do not use ast.NodeVisitor 2012-11-06 13:52:19 +01:00
Sebastien Bourdeauducq 56d4cdeb48 fhdl/structure: make all values hashable 2012-11-06 13:51:51 +01:00
Sebastien Bourdeauducq 3042f047fe pytholite: visit AST and list registers 2012-10-31 15:59:12 +01:00
Sebastien Bourdeauducq b171b3b3c2 pytholite: transformable elements 2012-10-29 18:13:03 +01:00
Sebastien Bourdeauducq 31cdb02eff bank/description: regprefix 2012-10-15 21:21:59 +02:00
Sebastien Bourdeauducq 7a1a781f49 actorlib/spi: typo 2012-10-15 21:21:42 +02:00
Sebastien Bourdeauducq daee4fb58c transform/unroll_sync: autodetect in/out 2012-10-15 20:32:07 +02:00
Sebastien Bourdeauducq fecab5518b transform/unroll_sync: support generator function 2012-10-15 19:42:30 +02:00
Sebastien Bourdeauducq 9efc581bee transform/unroll: support empty dictionaries 2012-10-12 21:54:48 +02:00
Sebastien Bourdeauducq eacba52fba transform/unroll: support for variables 2012-10-12 19:54:03 +02:00
Sebastien Bourdeauducq e5fc9cc675 transform: unroll 2012-10-12 13:16:39 +02:00
Sebastien Bourdeauducq d329d40fe9 actorlib/spi: SingleGenerator 2012-10-09 21:11:15 +02:00
Sebastien Bourdeauducq c473718a12 actorlib/spi/collector: atomic update for write_count 2012-10-09 19:08:09 +02:00
Sebastien Bourdeauducq 85081793cf bank: remove RE signal for field registers 2012-10-09 19:07:53 +02:00
Sebastien Bourdeauducq e410973352 bank: support for atomic writes 2012-10-08 18:43:18 +02:00
Sebastien Bourdeauducq 24877f271b actorlib/spi: fix memory port we/wd 2012-10-04 20:10:24 +02:00
Sebastien Bourdeauducq 035870703f flow/actorlib: Simple Processor Interface (WIP) 2012-10-04 18:22:22 +02:00
Sebastien Bourdeauducq 8101b68965 fhdl: fix instance get_io 2012-09-28 18:02:03 +02:00
Sebastien Bourdeauducq c273866b08 fhdl: support expressions in instance ports 2012-09-22 20:51:10 +02:00
Sebastien Bourdeauducq 2fc9cae88a fhdl: support inverted clock ports in instances 2012-09-22 20:50:49 +02:00
Sebastien Bourdeauducq 2e14569b5c fhdl/verilog: sort clock domains by name 2012-09-11 10:00:03 +02:00
Sebastien Bourdeauducq 9a18a9df3f fhdl: list signals in execution order 2012-09-11 09:59:37 +02:00
Sebastien Bourdeauducq e16353a281 Multi-clock design support + new instance API 2012-09-10 23:45:02 +02:00
Sébastien Bourdeauducq 6490785b6c Merge pull request #3 from brandonhamilton/upstream 
Optionally accept iverilog simulator options
 2012-09-09 10:52:52 -07:00
Sebastien Bourdeauducq b45c9546eb fhdl/namer: better handling of indices 2012-09-09 19:33:55 +02:00
Sebastien Bourdeauducq 589251fffd fhdl/tracer: support BUILD_LIST opcode 2012-09-09 18:53:24 +02:00
Sebastien Bourdeauducq 910c350021 fhdl/namer: use execution order indices for variable names as well 2012-09-09 17:31:35 +02:00
Sebastien Bourdeauducq f3e3a3eec7 fhdl/namer: number objects according to execution order 2012-09-09 12:27:32 +02:00
Sebastien Bourdeauducq 51f9a2a963 fhdl/namer: simplify + more relevant names 2012-09-09 01:26:33 +02:00
Sebastien Bourdeauducq 4164fb4ac9 bus/csr: configurable data width 2012-08-26 21:19:34 +02:00
Sebastien Bourdeauducq 5bf19c155f sim: ensure clean IPC shutdown 2012-08-05 00:16:11 +02:00
Sebastien Bourdeauducq 47c341ecdf flow/isd: add freeze register 2012-08-04 23:39:52 +02:00
Sebastien Bourdeauducq 6de517f59c flow/network: remove print 2012-08-03 18:50:57 +02:00
Sebastien Bourdeauducq 25cb25a8ae flow/network: option to add debugger 2012-08-03 18:49:35 +02:00
Sebastien Bourdeauducq fd0e281dfc flow: in-system debugger module 2012-08-03 18:49:04 +02:00
Sebastien Bourdeauducq adacdadd58 flow/hooks/DFGHook: add iterator on hooks 2012-08-03 18:48:35 +02:00
Sebastien Bourdeauducq 37fe6d64c3 flow: EndpointHook -> EndpointSimHook 2012-08-03 12:58:41 +02:00
Sebastien Bourdeauducq 30f1e77c18 corelogic/ReorderBuffer: do not touch empty count when issuing and reading at the same time 2012-07-13 20:21:04 +02:00
Sebastien Bourdeauducq 8de192dfbd x.bv.width -> len(x) 2012-07-13 18:32:54 +02:00
Sebastien Bourdeauducq 9cdc88eadf fhdl: len() for Constant 2012-07-13 18:16:50 +02:00
Sebastien Bourdeauducq 8c169a99df corelogic/misc: remove multimux 2012-07-13 18:05:57 +02:00
Sebastien Bourdeauducq 599ed8d470 fhdl: fix value_bv for operators 2012-07-13 17:40:49 +02:00
Sebastien Bourdeauducq b4613d913f bus/wishbone: remove use of deprecated multimux 2012-07-13 17:17:20 +02:00
Sebastien Bourdeauducq 7f47a2568a fhdl: remove _StatementList 2012-07-13 17:07:56 +02:00
Sebastien Bourdeauducq 8062e48697 bus/asmibus: fix per-port tag generation 2012-07-12 19:37:50 +02:00
Sebastien Bourdeauducq c543edf6f3 actorlib/dma_asmi: out-of-order reader and class factory 2012-07-12 18:34:13 +02:00
Sebastien Bourdeauducq 43653dbe1a corelogic: reorder buffer (untested) 2012-07-12 18:33:28 +02:00
Sebastien Bourdeauducq eed8fa374d fhdl/arrays: use correct BV for intermediate signals 2012-07-11 12:06:32 +02:00
Sebastien Bourdeauducq ed27783a53 fhdl: arrays (TODO: use correct BV for intermediate signals) 2012-07-09 15:16:38 +02:00
Sebastien Bourdeauducq c82a468506 bus: CSR initiator 2012-07-07 22:36:15 +02:00
Sebastien Bourdeauducq 0b19112f8f actorlib/misc/IntSequence: add offset feature 2012-07-07 00:10:23 +02:00
Sebastien Bourdeauducq 518501c493 flow/perftools: refactor to use hooks 2012-07-06 23:36:23 +02:00
Sebastien Bourdeauducq 6cf38bfcba flow: hooks 2012-07-06 23:36:10 +02:00
Sebastien Bourdeauducq a49dcb328a actorlib/structuring/Cast: rawbits parameter 2012-06-29 16:10:50 +02:00
Sebastien Bourdeauducq fa5a9915c3 doc: actor network 2012-06-25 16:07:45 +02:00
Sebastien Bourdeauducq 920aa5dc60 actorlib: merge composer into ala + derive ComposableSource from ActorNode 2012-06-25 11:34:58 +02:00
Sebastien Bourdeauducq bbfa120e2f doc: arithmetic and logic actors 2012-06-24 19:56:31 +02:00
Sebastien Bourdeauducq fd233d5b3c Move arithmetic actors to actorlib 2012-06-24 19:13:49 +02:00
Sebastien Bourdeauducq 1edaec0d75 control.For -> misc.IntSequence 2012-06-22 15:01:47 +02:00
Sebastien Bourdeauducq 4785ca526b flow/perftool: fix cpt equation 2012-06-21 00:41:22 +02:00
Sebastien Bourdeauducq cbc387f69e actorlib/sim/SimActor: remove dead time between transactions 2012-06-20 22:39:52 +02:00
Sebastien Bourdeauducq 6aff41a883 actorlib/structuring/Pack: drive busy signal 2012-06-20 22:39:03 +02:00
Sebastien Bourdeauducq 34d8ae3c11 flow: perftools 2012-06-20 21:59:17 +02:00
Sebastien Bourdeauducq 6fac3f027f examples/dataflow: structuring test 2012-06-20 18:25:01 +02:00
Sebastien Bourdeauducq 7d0e179a03 actorlib: structuring (untested) 2012-06-20 16:35:01 +02:00
Sebastien Bourdeauducq 1576cb0950 actorlib/control: simplify + fix 2012-06-17 21:19:47 +02:00
Sebastien Bourdeauducq 66ac62d0bb flow/network: fix handling of edges with subrecords at both ends 2012-06-17 18:31:45 +02:00
Sebastien Bourdeauducq 75d569a12c actorlib/control: use numbers of bits instead of maxima 2012-06-17 18:29:57 +02:00
Sebastien Bourdeauducq 4873cfe1a7 flow/plumbing: Combinator/Splitter should not inherit CombinatorialActor 2012-06-17 13:45:18 +02:00
Sebastien Bourdeauducq 98c9da95d1 flow/network: handle default endpoints correctly in _infer_plumbing_layout 2012-06-16 22:41:15 +02:00
Sebastien Bourdeauducq 9af87367eb flow/network: require ActorNode be passed to add_connection 2012-06-16 22:40:26 +02:00
Sebastien Bourdeauducq b0b0380ea7 flow/network: fix ActorNode default params 2012-06-16 22:39:31 +02:00
Sebastien Bourdeauducq 1a576e5c83 flow/actor: fix busy signal generation for pipelined actors 2012-06-16 22:38:45 +02:00
Sebastien Bourdeauducq 9228e8a96d flow/actor: add single_sink/single_source retrieval methods 2012-06-16 22:38:16 +02:00
Sebastien Bourdeauducq c1450daa93 flow: insert splitters 2012-06-16 21:23:42 +02:00
Sebastien Bourdeauducq bde8361e19 flow: insert combinators and infer plumbing layout 2012-06-16 17:30:54 +02:00
Sebastien Bourdeauducq da522cd58d Abstract actor graphs 2012-06-15 17:52:19 +02:00
Sebastien Bourdeauducq b14be4c8a3 actorlib: ASMI sequential reader 2012-06-12 21:04:47 +02:00
Sebastien Bourdeauducq ce9e35b8ef fix SimActor get_fragment 2012-06-12 17:52:08 +02:00
Sebastien Bourdeauducq 8a23451237 PureSimulable 2012-06-12 17:08:56 +02:00
Sebastien Bourdeauducq a591510189 ASMI simulation models 2012-06-12 16:57:00 +02:00
Sebastien Bourdeauducq b7a84b3750 wishbone: base TargetModel class 2012-06-10 17:05:10 +02:00
Sebastien Bourdeauducq ec501e7797 bus/wishbone: target model 2012-06-10 16:40:33 +02:00
Sebastien Bourdeauducq f061b25a24 bus/wishbone/Tap: remove ack feature 2012-06-10 12:46:24 +02:00
Sebastien Bourdeauducq 009f26bb9d flow/network: refactor graph 2012-06-08 22:49:49 +02:00
Sebastien Bourdeauducq de408b2cba flow/ala: fix typo 2012-06-08 22:48:47 +02:00
Sebastien Bourdeauducq 356051e8a8 actorlib: WB reader simulation OK 2012-06-08 21:31:05 +02:00
Sebastien Bourdeauducq 11674242c4 Use super() instead of calling parent constructors directly 2012-06-08 18:06:12 +02:00
Sebastien Bourdeauducq 152a7e282e actorlib/sim: use set instead of list to represent active transactions 2012-06-08 17:56:52 +02:00
Sebastien Bourdeauducq 910c7806cf actorlib: generator-based generic simulation actor 2012-06-08 17:54:03 +02:00
Sebastien Bourdeauducq b145f9e5e2 sim: multiread/multiwrite 2012-06-08 17:52:32 +02:00
Sebastien Bourdeauducq f38ef626de corelogic/record: better repr 2012-06-08 17:49:31 +02:00
Sebastien Bourdeauducq 1c0f636c8d flow: generic parameter passing to Actor from sequential/pipelined 2012-06-07 18:24:33 +02:00
Sebastien Bourdeauducq a1fc86af8f flow: fix actor repr 2012-06-07 15:48:35 +02:00
Sebastien Bourdeauducq 680a34465d flow: refactor scheduling models 2012-06-07 14:44:43 +02:00
Sebastien Bourdeauducq 493b181af1 bank/description: pad unaligned multi-word registers at the top 2012-05-21 22:55:23 +02:00
Sebastien Bourdeauducq 9449bbea0a Add LICENSE file 2012-05-21 19:56:23 +02:00
Sebastien Bourdeauducq 68cd445662 bus/wishbone2asmi: fix cache tag size 2012-05-15 15:18:03 +02:00
Sebastien Bourdeauducq 0bea1e2589 asmi: dat_wm high to disable data write 2012-05-15 14:41:54 +02:00
Sebastien Bourdeauducq f2c20e4af0 bus/asmibus/hub: hack to prevent comb loops 2012-04-30 17:11:42 -05:00
Sebastien Bourdeauducq 398ece8fe2 fhdl/verilog: add option to display which comb blocks are run 
This is a debug hack to help find combinatorial loops in designs.
 2012-04-30 16:38:40 -05:00
Sebastien Bourdeauducq 0b62e573ae sim: pass extra keyword arguments to Verilog converter 2012-04-30 16:38:17 -05:00
Sebastien Bourdeauducq 6a52e44d09 fhdl: support len() on signals 2012-04-08 18:06:22 +02:00
Sebastien Bourdeauducq b9c533be51 bank/csrgen: allow specifying existing CSR interface 2012-04-06 14:59:09 +02:00
Brandon Hamilton 49b58a03a0 Optionally accept iverilog simulator options 2012-04-03 12:58:19 +02:00
Sebastien Bourdeauducq 2a4e49e381 fhdl: phase out pads 2012-04-02 19:21:43 +02:00
Sebastien Bourdeauducq 623e8e436a fhdl/verilog: do not attempt to initialize instance and mem output signals 2012-04-02 12:59:42 +02:00
Sebastien Bourdeauducq 6e3b25ebb6 bus/dfi: reset active low signals to 1 2012-04-01 17:43:24 +02:00
Sebastien Bourdeauducq d3c6b8d16f sim/proxy: support lists 2012-04-01 17:19:53 +02:00
Sebastien Bourdeauducq f3ae22f488 fhdl/verilog: initialize internal read-only signals with their reset values 2012-04-01 16:39:11 +02:00
Sebastien Bourdeauducq 0dfc215fe8 corelogic/roundrobin: handle correctly special case with 1 request source 2012-03-31 18:01:40 +02:00
Sebastien Bourdeauducq 94b02aa8ed bus/asmicon: initiator 2012-03-30 22:16:31 +02:00
Sebastien Bourdeauducq bb864c65dc sim: proxy 2012-03-30 16:40:26 +02:00
Sebastien Bourdeauducq 081b658e2d Update copyright notices 2012-03-23 16:41:30 +01:00
Sebastien Bourdeauducq d47b564fad corelogic/fsm: typo 2012-03-18 22:12:46 +01:00
Sebastien Bourdeauducq 5f28103769 corelogic/fsm: delayed enters 2012-03-18 00:09:40 +01:00
Sebastien Bourdeauducq a4294762d0 corelogic/roundrobin: CE switching 2012-03-16 16:54:47 +01:00
Sebastien Bourdeauducq e969b9afc3 corelogic: convert timeline to function and move to misc 2012-03-15 20:25:44 +01:00
Sebastien Bourdeauducq 1665f293a6 bus/asmibus/hub: require finalization before get_slots 2012-03-14 16:19:29 +01:00
Sebastien Bourdeauducq 5c0cc6292c fhdl: export log2_int 2012-03-14 12:19:42 +01:00
Sebastien Bourdeauducq bfcd4e636b fhdl: handle negative constants correctly 2012-03-08 20:49:24 +01:00
Sebastien Bourdeauducq ab800fa2ed bus: generic transaction model 2012-03-08 18:14:06 +01:00
Sebastien Bourdeauducq 678a89d572 sim: fix zero encoding 2012-03-08 15:34:08 +01:00
Sebastien Bourdeauducq decbd069fa sim: fix message debug formatting 2012-03-08 15:27:35 +01:00
Sebastien Bourdeauducq 98e96b3952 sim: make initialization cycle optional (selectable by function attribute) 2012-03-06 19:43:59 +01:00
Sebastien Bourdeauducq 8160ced2e9 sim: memory access 2012-03-06 19:29:39 +01:00
Sebastien Bourdeauducq db8f8bf2e3 fhdl: register memory objects with namespace 2012-03-06 18:33:44 +01:00
Sebastien Bourdeauducq 6f829c7afc sim: support for signed numbers 2012-03-06 16:46:18 +01:00
Sebastien Bourdeauducq 90184b22d2 fhdl/verilog: fix signed constant conversion 2012-03-06 16:45:44 +01:00
Sebastien Bourdeauducq 9da512dbf5 sim: VCD generation 2012-03-06 15:26:04 +01:00
Sebastien Bourdeauducq 22b3c11b93 sim: clean startup/shutdown 2012-03-06 15:00:02 +01:00
Sebastien Bourdeauducq 06de17b16c sim: remove temporary files and socket 2012-03-06 14:20:26 +01:00
Sebastien Bourdeauducq 7230508e7c fhdl/namer: do not reference objects with __del__ methods to avoid uncollectable cycles 2012-03-06 14:18:22 +01:00
Sebastien Bourdeauducq 2c375e900f sim: remove default sockaddr 2012-03-06 13:58:49 +01:00
Sebastien Bourdeauducq 8d16fde48c fhdl: add simulation functions in fragment 2012-03-06 13:58:22 +01:00
Sebastien Bourdeauducq aac9752558 sim: basic functionality working 2012-03-05 20:31:41 +01:00
Sebastien Bourdeauducq 29859acc34 sim: two way IPC working 2012-03-04 19:17:03 +01:00
Sebastien Bourdeauducq 8586daf2dd sim: IPC module (lacks str/int encoding) 2012-03-03 18:55:38 +01:00
Sebastien Bourdeauducq 1b8cb5b46c bus/dfi: fix multiphase naming 2012-02-19 17:57:04 +01:00
Sebastien Bourdeauducq d8d4e81b6e bank/csrgen: fix RE generation 2012-02-18 18:56:18 +01:00
Sebastien Bourdeauducq 55a265d967 bank: add RE signal for registers made of fields 2012-02-17 23:52:06 +01:00
Sebastien Bourdeauducq 92dfbb92dd bus: add interconnect statements function 2012-02-17 23:51:32 +01:00
Sebastien Bourdeauducq f995e8b92e fhdl: check we pass BV to signals 2012-02-17 23:50:54 +01:00
Sebastien Bourdeauducq a1ad30faab fhdl/verilog: properly connect instance inouts 2012-02-17 11:08:41 +01:00
Sebastien Bourdeauducq ca7056b07f fhdl: support forwarding of bidirectional signals from instance ports 2012-02-16 18:34:32 +01:00
Sebastien Bourdeauducq c08687b9c6 bus/dfi: filter signals by direction 2012-02-15 21:48:05 +01:00
Sebastien Bourdeauducq ef7aea0f31 bank: omit device write register when access_bus==READ_ONLY and access_dev==WRITE_ONLY 2012-02-15 18:23:31 +01:00
Sebastien Bourdeauducq fa9cf3e466 bus: add DFI 2012-02-15 18:09:14 +01:00
Sebastien Bourdeauducq 91e279ee04 bank/csrgen: use new bus API 2012-02-15 16:42:17 +01:00
Sebastien Bourdeauducq af5230c8ee bus: fix simple interconnect 2012-02-15 16:42:05 +01:00
Sebastien Bourdeauducq 0493212124 bus: simplify and cleanup 
Unify slave and master interfaces
Remove signal direction suffixes
Generic simple interconnect
Wishbone point-to-point interconnect
Description filter (get_name)
Misc cleanups
 2012-02-15 16:30:16 +01:00
Sebastien Bourdeauducq 46b1f74e98 bus/asmibus/hub: forward data and tag_call 2012-02-14 14:00:17 +01:00
Sebastien Bourdeauducq 0c214b484e Use double quotes for all strings 2012-02-14 13:12:43 +01:00
Sebastien Bourdeauducq e11d9b9322 bus/wishbone2asmi: cache hits working 2012-02-13 23:11:16 +01:00
Sebastien Bourdeauducq 1662e1b3bc corelogic: support reverse in displacer/chooser 2012-02-13 23:10:27 +01:00
Sebastien Bourdeauducq 264be80f2d Fix syntax errors and other stupid problems 2012-02-13 22:28:02 +01:00
Sebastien Bourdeauducq 8a61d9d121 bus/csr: Rename a->adr d->dat to be consistent with the other buses 2012-02-13 21:46:39 +01:00
Sebastien Bourdeauducq 060426cb59 bus/wishbone2asmi: set WM, and send 0 when inactive 2012-02-13 16:49:43 +01:00
Sebastien Bourdeauducq cad9d3b960 bus: Wishbone to ASMI caching bridge (untested) 2012-02-13 16:29:38 +01:00
Sebastien Bourdeauducq 244bf17db7 corelogic/misc: displacer + chooser 2012-02-11 20:57:08 +01:00
Sebastien Bourdeauducq e10e4360f3 corelogic/misc/multimux: less confusing variable name 2012-02-11 20:56:51 +01:00
Sebastien Bourdeauducq 7894411418 bus/asmibus: fix typo 2012-02-11 20:56:01 +01:00
Sebastien Bourdeauducq 28b0c340af corelogic/record: add to_signal convenience function 2012-02-11 20:55:23 +01:00
Sebastien Bourdeauducq e62ac1d3a1 corelogic/misc: contiguous split 2012-02-11 11:52:15 +01:00
Sebastien Bourdeauducq ef436a1ec9 bus/asmibus: add get_slots, fix get_fragment 2012-02-10 17:49:06 +01:00
Sebastien Bourdeauducq 945d655d45 bus: ASMI hub (untested) 2012-02-10 15:21:04 +01:00
Sebastien Bourdeauducq 47883675db bus/wishbone2csr: truncate WB data 2012-02-06 18:43:34 +01:00
Sebastien Bourdeauducq 1eb348c573 fhdl: do not attempt slicing non-array signals to keep Verilog happy 2012-02-06 18:07:02 +01:00
Sebastien Bourdeauducq fcd6583cbb bank: event manager 2012-02-06 17:39:32 +01:00
Sebastien Bourdeauducq 3a2a0c4dd8 bank: support registers larger than the bus word width 2012-02-06 16:15:27 +01:00
Sebastien Bourdeauducq f3ddfffc47 bank: refactoring 2012-02-06 13:55:50 +01:00
Sebastien Bourdeauducq 1a86f26a66 bank/csrgen: use enumerate 2012-02-06 11:18:30 +01:00
Sebastien Bourdeauducq 629e771fc0 fhdl/structure: binary constant builder 2012-02-05 19:32:11 +01:00
Lars-Peter Clausen 8380318e84 Use enumerate(x) instead of zip(range(x), x) 
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2012-02-02 21:28:00 +01:00
Lars-Peter Clausen 2b3f00cbc1 fhdl/namer: Add support for STORE_DEREF opcode 
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2012-02-02 21:15:10 +01:00
Sebastien Bourdeauducq 6a9b59786b fhdl/namer: extract variable names with bytecode inspection 2012-01-28 23:17:44 +01:00
Sebastien Bourdeauducq 5c2df45577 fhdl: do not prefix instance signal names 2012-01-28 11:39:28 +01:00
Sebastien Bourdeauducq a99c2acfa8 Remove explicit bus names and rely on the new automatic namer 2012-01-27 22:20:57 +01:00
Sebastien Bourdeauducq 685b5eb08f fhdl: support memory read enable 2012-01-27 21:39:23 +01:00
Sebastien Bourdeauducq 0cc7e2ac1e fhdl: make WRITE_FIRST default 2012-01-27 21:35:58 +01:00
Sebastien Bourdeauducq 5405a83ff9 fhdl: memories working 2012-01-27 20:22:17 +01:00
Sebastien Bourdeauducq a5bd111370 fhdl/verilog: clean up signal classification and support memory descriptions 2012-01-27 16:54:48 +01:00
Sebastien Bourdeauducq 6b1d775e9f fhdl/structure: memory description 2012-01-27 16:53:34 +01:00
Sebastien Bourdeauducq 1966117e17 flow/ala: fix typo for And (thanks Lars) 2012-01-22 00:32:02 +01:00
Sebastien Bourdeauducq 076c171c7b Use meaningful class names 2012-01-20 23:07:32 +01:00
Sebastien Bourdeauducq d3d5b481fe Include fragment pads in pre-naming dictionary 2012-01-20 22:59:40 +01:00
Sebastien Bourdeauducq 039c6d8eb4 namer/trace_back: behave on None code_context 2012-01-20 22:52:50 +01:00
Sebastien Bourdeauducq e9be3241f6 Fix instance support 2012-01-20 22:36:17 +01:00
Sebastien Bourdeauducq e4f531a739 Include unused I/Os in pre-naming dictionary and register signals with name_override 2012-01-20 22:20:32 +01:00
Sebastien Bourdeauducq 904d14d4cf Remove NoContext 2012-01-20 22:15:44 +01:00
Sebastien Bourdeauducq 05b20d4987 Only include context prefix when necessary 2012-01-19 19:25:04 +01:00
Sebastien Bourdeauducq fc473e31eb Fix disjoint namespace test 2012-01-19 19:24:43 +01:00
Sebastien Bourdeauducq 00d3eb7989 Always include last step in names 2012-01-19 18:42:43 +01:00
Sebastien Bourdeauducq 4eac60d181 New naming system: second attempt 2012-01-19 18:25:25 +01:00
Sebastien Bourdeauducq 4c85d921b3 corelogic/record: empty default name 2012-01-16 19:38:14 +01:00
Sebastien Bourdeauducq bdde97f5fd New naming system beginning to work 2012-01-16 18:42:55 +01:00
Sebastien Bourdeauducq ab8e08a2ed fhdl: new naming system (broken) 2012-01-16 18:09:52 +01:00
Sebastien Bourdeauducq e6bfad498d actorlib/control: 'for' generator 2012-01-15 22:08:33 +01:00
Sebastien Bourdeauducq c3d7b98b43 dma_wishbone: small syntax simplification thanks to None statements 2012-01-15 17:46:15 +01:00
Sebastien Bourdeauducq aa8b8da684 fhdl: allow None statements 2012-01-15 17:45:54 +01:00
Sebastien Bourdeauducq 85491efc68 wishbone_dma: convert to new endpoint API and fix some bugs 2012-01-15 16:41:15 +01:00
Sebastien Bourdeauducq 77b3c8e3bb bus: list signals 2012-01-15 15:48:51 +01:00
Sebastien Bourdeauducq 3c7161cc34 flow: saner endpoint management 2012-01-15 15:09:44 +01:00
Sebastien Bourdeauducq 20425703fa Wishbone: omit fixed LSBs 2012-01-13 17:29:05 +01:00
Sebastien Bourdeauducq 077fd9fdbc actorlib: Wishbone DMA read master (WIP) 2012-01-10 17:10:18 +01:00
Sebastien Bourdeauducq c93eb5f482 record: return offset 2012-01-10 17:10:03 +01:00
Sebastien Bourdeauducq a6e5f3e766 flow: simplify actor fragment interface 2012-01-10 15:54:51 +01:00
Sebastien Bourdeauducq 683e6b4a6c record: support aligned flattening 2012-01-09 19:16:11 +01:00
Sebastien Bourdeauducq b06e70d849 corelogic: FSM 2012-01-09 16:28:48 +01:00
Sebastien Bourdeauducq 47ae303846 record: cleanup 2012-01-09 15:20:09 +01:00
Sebastien Bourdeauducq cef1c5d3af record: better exception code 2012-01-09 15:17:24 +01:00
Sebastien Bourdeauducq 89bf704b2b record: preserve order 2012-01-09 15:14:42 +01:00
Sebastien Bourdeauducq bdcaeb159b flow: draw network graph 2012-01-09 14:21:54 +01:00
Sebastien Bourdeauducq d26ded93d8 flow: actor busy signal 2012-01-09 14:21:45 +01:00
Sebastien Bourdeauducq d2d55372d8 Composer (WIP) 2012-01-08 13:56:11 +01:00
Sebastien Bourdeauducq 34c69db14a endpoint: add _i/_o suffix on signal names 2012-01-07 21:21:46 +01:00
Sebastien Bourdeauducq cdd9977a40 fhdl: better signal naming heuristic 2012-01-07 15:30:14 +01:00
Sebastien Bourdeauducq b6763c28ea constant: equality 2012-01-07 12:29:47 +01:00
Sebastien Bourdeauducq 7b395b565e verilog: split comb block, use assign statements 2012-01-07 12:19:06 +01:00
Sebastien Bourdeauducq f209bf6b33 convtools -> tools 2012-01-07 00:39:28 +01:00
Sebastien Bourdeauducq 0b195a244d flow: network 2012-01-07 00:33:28 +01:00
Sebastien Bourdeauducq 3c1dada9cf record: compatibility check 2012-01-06 23:00:23 +01:00
Sebastien Bourdeauducq 588f1a259e flow: plumbing 2012-01-06 17:24:05 +01:00
Sebastien Bourdeauducq 8f1bf508ca actor: simplified automatic control 2012-01-06 15:35:17 +01:00
Sebastien Bourdeauducq a3bf877802 ALA: use records for tokens 2012-01-06 14:32:00 +01:00
Sebastien Bourdeauducq 038992e7d2 corelogic: record 2012-01-06 11:20:44 +01:00
Sebastien Bourdeauducq d7a3bed44c Signal repr 2012-01-06 11:20:33 +01:00
Sebastien Bourdeauducq 9366a226bb Convert -> convert 2012-01-05 19:27:33 +01:00
Sebastien Bourdeauducq edf90870c2 flow: sum and division actors 2011-12-23 00:35:53 +01:00
Sebastien Bourdeauducq 76db20cd9f fhdl: encapsulate replicated constants 2011-12-23 00:35:13 +01:00
Sebastien Bourdeauducq f0aac4b50f flow: actor class 2011-12-22 19:37:16 +01:00
Sebastien Bourdeauducq 566295dea3 csr: use optree 2011-12-22 19:36:56 +01:00
Sebastien Bourdeauducq ba40f58491 corelogic: operator tree 2011-12-22 15:46:19 +01:00
Sebastien Bourdeauducq 8a394f9159 verilog: comb reset 2011-12-22 00:04:53 +01:00
Sebastien Bourdeauducq 4d6be55e9f verilog: break down Convert function 2011-12-21 23:08:50 +01:00
Sebastien Bourdeauducq 26e0b817e8 verilog: ignore variable property in combinatorial block 2011-12-21 23:00:36 +01:00
Sebastien Bourdeauducq 7456195775 Consistent names 2011-12-21 22:57:07 +01:00
Sebastien Bourdeauducq 94c5fba067 corelogic: fix signal exports 2011-12-18 21:54:28 +01:00
Sebastien Bourdeauducq 4f4d809a4e fhdl: better matching of assignment 2011-12-18 21:49:48 +01:00
Sebastien Bourdeauducq 107f03fd4b Remove uses of declare_signal 2011-12-18 21:47:48 +01:00
Sebastien Bourdeauducq dd42b2daff fhdl: also take into account object attributes in _make_signal_name. Get rid of declare_signal 2011-12-18 21:47:29 +01:00
Sebastien Bourdeauducq 41e2430e2b fhdl: automatic signal name from assignment 2011-12-18 21:26:51 +01:00
Sebastien Bourdeauducq 135a2eb868 bank: support raw registers 2011-12-18 00:28:04 +01:00
Sebastien Bourdeauducq d21e095397 fhdl: fix series of if/elif/else 2011-12-17 20:31:42 +01:00
Sebastien Bourdeauducq 1a845d4553 32-device, 8-bit CSR bus 2011-12-17 15:54:49 +01:00
Sebastien Bourdeauducq 6f8a6db40a verilog: get the simulator to run the combinatorial process at the beginning 2011-12-17 15:20:22 +01:00
Sebastien Bourdeauducq ec47394012 verilog: support for float parameters in instances 2011-12-17 14:59:27 +01:00
Sebastien Bourdeauducq ee6ca729a2 verilog: user-definable reset and clock 2011-12-16 22:25:05 +01:00
Sebastien Bourdeauducq c7b9dfc203 fhdl: simpler syntax 2011-12-16 21:30:14 +01:00
Sebastien Bourdeauducq 39b7190334 Pay a bit more attention to PEP8 2011-12-16 16:02:55 +01:00
Sebastien Bourdeauducq 929cc98070 wishbone2csr: wait for WB deack 2011-12-13 17:38:59 +01:00
Sebastien Bourdeauducq 22d03b4943 timeline: only trigger in rest state 2011-12-13 15:25:46 +01:00
Sebastien Bourdeauducq c840848dba verilog: use blocking assignment in combinatorial process 2011-12-13 14:09:12 +01:00
Sebastien Bourdeauducq 92f24b784d wishbone: decoder: fix slave cyc generation in registered mode 2011-12-13 14:08:39 +01:00
Sebastien Bourdeauducq 0ea7a9b2e6 wishbone2csr: fix double-write bug 2011-12-13 00:25:46 +01:00
Sebastien Bourdeauducq 923fc52e68 wishbone: only send ack to the active master in arbiter 2011-12-13 00:25:25 +01:00
Sebastien Bourdeauducq a72faaecdd fhdl: allow a namespace to be specified for Verilog conversion 2011-12-13 00:24:40 +01:00
Sebastien Bourdeauducq eee6980a36 fhdl: support Constant parameters for Verilog conversion 2011-12-11 20:17:51 +01:00
Sebastien Bourdeauducq dafef5d744 fhdl: fix list references (thanks Lars) 2011-12-11 20:17:29 +01:00
Sebastien Bourdeauducq 16a6029a1b bus: fix CSR interconnect data readback 2011-12-11 20:17:12 +01:00
Sebastien Bourdeauducq dad9120653 bus: 14-bit CSR addresses 2011-12-11 20:16:50 +01:00
Sebastien Bourdeauducq 7582b76406 bank: fix csrgen address decoder 2011-12-11 20:15:30 +01:00
Sebastien Bourdeauducq 05d91c7104 bus: Wishbone to CSR bridge 2011-12-11 15:04:34 +01:00
Sebastien Bourdeauducq af74a89b8a corelogic: timeline module 2011-12-11 01:11:13 +01:00
Sebastien Bourdeauducq 019ef16db4 fhdl: remove broken fragment iadd 2011-12-11 01:10:59 +01:00
Sebastien Bourdeauducq b00581616e convtools: insert reset on variables 2011-12-11 01:10:37 +01:00
Sebastien Bourdeauducq d3127fd5d8 autofragment: remove debug 2011-12-10 20:48:23 +01:00
Sebastien Bourdeauducq 44f44b8a05 fhdl: autofragment 2011-12-10 20:47:21 +01:00
Sebastien Bourdeauducq 4b15a84505 fhdl: fix += for empty fragment 2011-12-10 20:47:06 +01:00
Sebastien Bourdeauducq a49ecc4331 fhdl: pad support in fragments 2011-12-10 20:25:24 +01:00
Sebastien Bourdeauducq 4d1a960308 wishbone: decoder + shared bus interconnect 2011-12-09 13:11:52 +01:00
Sebastien Bourdeauducq fa63cc1ec8 fhdl: replication support 2011-12-09 13:11:34 +01:00
Sebastien Bourdeauducq 5c7131dc86 wishbone: arbiter 2011-12-08 23:21:25 +01:00
Sebastien Bourdeauducq c1041b9a5f simplebus: export GetSigName function 2011-12-08 23:06:04 +01:00
Sebastien Bourdeauducq b2bc5ad4f4 corelogic: multimux module 2011-12-08 23:04:34 +01:00
Sebastien Bourdeauducq b0c5b74c22 verilog: handle default in case statements 2011-12-08 23:04:20 +01:00
Sebastien Bourdeauducq 512655c108 fhdl: improve automatic signal naming 2011-12-08 21:28:20 +01:00
Sebastien Bourdeauducq 5034af3038 Corelogic conversion example 2011-12-08 21:25:05 +01:00
Sebastien Bourdeauducq 62f70a54f0 corelogic: MC divider module 2011-12-08 21:19:40 +01:00
Sebastien Bourdeauducq 84eb964adc fhdl: support negation operator 2011-12-08 21:15:44 +01:00
Sebastien Bourdeauducq bf021efa2b verilog: fix unary operator conversion 2011-12-08 21:15:24 +01:00
Sebastien Bourdeauducq 78f18ad593 corelogic: round-robin module 2011-12-08 21:15:02 +01:00
Sebastien Bourdeauducq 7c99e51b90 Named buses 2011-12-08 19:16:08 +01:00
Sebastien Bourdeauducq 5720a51dad wishbone: add missing SEL 2011-12-08 19:09:32 +01:00
Sebastien Bourdeauducq ed05ec5f6a instances: signal override 2011-12-08 18:56:14 +01:00
Sebastien Bourdeauducq c43f3da534 Wishbone declarations 2011-12-08 18:47:41 +01:00
Sebastien Bourdeauducq a6b86168ce Simple bus base class 2011-12-08 18:47:32 +01:00
Sebastien Bourdeauducq 1b637cea61 Instance support 2011-12-08 16:35:32 +01:00
Sebastien Bourdeauducq fab02f84cb fhdl: fix implicit slice index 2011-12-07 22:21:30 +01:00
Sebastien Bourdeauducq 82f77180d5 fhdl: cleanup value bv 2011-12-07 22:21:10 +01:00
Sebastien Bourdeauducq 0e8d894a35 Variable conversion 2011-12-05 22:00:06 +01:00
Sebastien Bourdeauducq 4340680704 Cleanup 2011-12-05 19:25:32 +01:00
Sebastien Bourdeauducq ec51f09c98 Case support + register bank generator 2011-12-05 17:43:56 +01:00
Sebastien Bourdeauducq 458cfc8623 CSR bus definitions 2011-12-05 00:16:44 +01:00
Sebastien Bourdeauducq e099f4d52f Reset insertion 2011-12-04 22:41:50 +01:00
Sebastien Bourdeauducq cd8544c758 Verilog generator 2011-12-04 22:26:32 +01:00
Sebastien Bourdeauducq 499b95a519 Initial import, FHDL basic structure, divider example 2011-12-04 16:44:38 +01:00