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637 commits

Author SHA1 Message Date
Sebastien Bourdeauducq
69dbf84e54 sim/generic: support implicit get_fragment 2013-03-12 16:54:01 +01:00
Sebastien Bourdeauducq
ecfe1646ec fhdl/verilog: implicit get_fragment 2013-03-12 16:16:06 +01:00
Sebastien Bourdeauducq
4ada2ead05 fhdl/specials/Memory: automatic name# 2013-03-12 15:58:39 +01:00
Sebastien Bourdeauducq
04df076fba bank: automatic register naming 2013-03-12 15:45:24 +01:00
Sebastien Bourdeauducq
7e2581bf17 fhdl/tracer: recognize CALL_FUNCTION_VAR opcode 2013-03-12 13:48:09 +01:00
Sebastien Bourdeauducq
12158ceadf fhdl/tracer: recognize LOAD_DEREF opcode 2013-03-12 10:31:56 +01:00
Sebastien Bourdeauducq
3c75121783 fhdl/tracer: remove leading underscores from names 2013-03-11 22:21:58 +01:00
Sebastien Bourdeauducq
80970b203c bus/asmibus: use implicit finalization 2013-03-11 17:11:59 +01:00
Sebastien Bourdeauducq
b042757187 Fix Register name conflict between Pytholite and Bank 2013-03-10 19:47:21 +01:00
Sebastien Bourdeauducq
f93695f60e bank/eventmanager: use module and autoreg 2013-03-10 19:29:05 +01:00
Sebastien Bourdeauducq
174e8cb8d6 bus/asmibus: use fhdl.module API 2013-03-10 19:28:22 +01:00
Sebastien Bourdeauducq
17e0dfe120 fhdl/module: replace autofragment 2013-03-10 19:27:55 +01:00
Sebastien Bourdeauducq
cddbc1157d bank/description/AutoReg: check that get_memories and get_registers are callable 2013-03-10 18:11:29 +01:00
Sebastien Bourdeauducq
68fe4c269c bank/csrgen: BankArray 2013-03-10 00:45:16 +01:00
Sebastien Bourdeauducq
f1474420df bank/description: AutoReg 2013-03-10 00:43:16 +01:00
Sebastien Bourdeauducq
d0676e2dd1 migen/fhdl/autofragment: factorize 2013-03-09 23:23:24 +01:00
Sebastien Bourdeauducq
d0d2df3c4b fhdl/autofragment: remove legacy functions 2013-03-09 23:05:45 +01:00
Sebastien Bourdeauducq
72fb6fd6bd fhdl/tools/flat_iteration: generalize 2013-03-09 23:03:15 +01:00
Sebastien Bourdeauducq
f53acb92e7 fhdl/autofragment: fix submodules 2013-03-09 21:15:38 +01:00
Sebastien Bourdeauducq
6da8eb906f fhdl/autofragment: empty build_fragment by default 2013-03-09 19:10:47 +01:00
Sebastien Bourdeauducq
2b8dc52c13 Use common definition for FinalizeError 2013-03-09 19:03:13 +01:00
Sebastien Bourdeauducq
b75fb7f97c csr/SRAM: support for writes with memory widths larger than bus words 2013-03-09 00:50:57 +01:00
Sebastien Bourdeauducq
6fa30053bf fhdl/verilog: tristate outputs are always wire 2013-03-06 11:30:52 +01:00
Sebastien Bourdeauducq
9b4ca987e0 bus/csr: support memories with larger word width than the bus (read only) 2013-03-03 19:27:13 +01:00
Sebastien Bourdeauducq
bb5ee8d3bd fhdl/autofragment: bugfixes + add auto_attr 2013-03-03 17:53:06 +01:00
Sebastien Bourdeauducq
cc8118d35c fhdl/autofragment: FModule 2013-03-02 23:30:54 +01:00
Sebastien Bourdeauducq
d2491828a4 csr/SRAM: prefix page register with memory name 2013-03-01 12:06:12 +01:00
Sebastien Bourdeauducq
c10622f5e2 fhdl/verilog: insert reset before listing signals 2013-02-27 18:10:04 +01:00
Sebastien Bourdeauducq
d2cbc70190 bank/description: memprefix 2013-02-25 23:14:15 +01:00
Sebastien Bourdeauducq
a81781f589 fhdl/specials: allow setting memory name 2013-02-25 23:14:03 +01:00
Sebastien Bourdeauducq
425de02f42 uio/ioo: fix specials 2013-02-25 23:13:38 +01:00
Sebastien Bourdeauducq
55ab01f928 fhdl/specials/Instance: _printintbool -> verilog_printexpr 2013-02-24 13:08:01 +01:00
Sebastien Bourdeauducq
a878db1e3c genlib: clock domain crossing elements 2013-02-23 19:03:35 +01:00
Sebastien Bourdeauducq
7c4e6c35e5 fhdl/verilog: support special lowering and overrides 2013-02-23 19:03:16 +01:00
Sebastien Bourdeauducq
f9acee4e68 corelogic -> genlib 2013-02-22 23:19:37 +01:00
Sebastien Bourdeauducq
38664d6e16 fhdl: inline synthesis directive support 2013-02-22 19:10:02 +01:00
Sebastien Bourdeauducq
49cfba50fa New 'specials' API 2013-02-22 17:56:35 +01:00
Sebastien Bourdeauducq
1b18194b1d fhdl: TSTriple 2013-02-19 17:26:02 +01:00
Sebastien Bourdeauducq
dc93a231c6 fhdl: tristate support 2013-02-15 00:17:24 +01:00
Sebastien Bourdeauducq
63d399b6ad fhdl/autofragment: from_attributes 2013-02-11 18:34:01 +01:00
Sebastien Bourdeauducq
92b67df41c sim: default runner to Icarus Verilog 2013-02-09 17:04:53 +01:00
Sebastien Bourdeauducq
bd6856ba7a flow/perftools: finish removing ActorNode 2013-02-09 17:03:48 +01:00
Sebastien Bourdeauducq
473fd20f8c fhdl/structure: store clock domain name 2013-01-24 13:49:49 +01:00
Sebastien Bourdeauducq
3201554f76 fhdl/verilog: fix spurious clock/reset signals on multiple calls to convert() 2013-01-23 15:13:06 +01:00
Sebastien Bourdeauducq
314a6c7743 corelogic: complex arithmetic support 2013-01-05 14:18:36 +01:00
Sebastien Bourdeauducq
badba89686 fhdl: support nested statement lists 2013-01-05 14:18:15 +01:00
Sebastien Bourdeauducq
47f5fc70e4 pytholite: fix bug with constant assignment to register 2012-12-19 16:21:57 +01:00
Sebastien Bourdeauducq
9c65402fda pytholite: prune unused registers 2012-12-19 16:03:05 +01:00
Sebastien Bourdeauducq
3fae6c8f03 Do not use super() 2012-12-18 14:54:33 +01:00
Sebastien Bourdeauducq
b06fbdedd6 fhdl/tools: bitreverse 2012-12-14 23:56:16 +01:00
Sebastien Bourdeauducq
1f350adf14 actorlib/sim/SimActor: do not drive busy low when generator yields None 2012-12-14 23:56:03 +01:00
Sebastien Bourdeauducq
a67f483f0f Token: support idle_wait 2012-12-14 19:16:22 +01:00
Sebastien Bourdeauducq
6f99241585 Move Token to migen.flow.transactions 2012-12-14 15:55:38 +01:00
Sebastien Bourdeauducq
28b4d99d31 replace some forgotten is_abstract() 2012-12-12 22:36:45 +01:00
Sebastien Bourdeauducq
a7227d7d2b Remove ActorNode 2012-12-12 22:20:48 +01:00
Sebastien Bourdeauducq
8163ed4828 Merge branch 'master' of github.com:milkymist/migen 2012-12-06 20:57:30 +01:00
Sebastien Bourdeauducq
483b821342 fhdl/structure: do not create Signal in Instance when parameter is int 2012-12-06 20:56:46 +01:00
Sebastien Bourdeauducq
280a87ea69 elsewhere: do not create interface in default param 2012-12-06 17:34:48 +01:00
Sebastien Bourdeauducq
62187aa23d migen/bank: do not create interface in default param 2012-12-06 17:28:28 +01:00
Sebastien Bourdeauducq
c3fdf42825 bus/csr: add SRAM 2012-12-06 17:16:17 +01:00
Sebastien Bourdeauducq
e89c66bf14 bank/csrgen: interface -> bus 2012-12-06 17:15:34 +01:00
Sebastien Bourdeauducq
273d9d285b bank/description: define reset value of read signal 2012-12-05 16:40:44 +01:00
Sebastien Bourdeauducq
34ce934809 actorlib/sim: drive busy high until generator is finished 2012-12-05 16:40:12 +01:00
Sebastien Bourdeauducq
4bcb39699b bus/wishbone/sram: accept memories < 32 bits 2012-12-01 13:04:22 +01:00
Sebastien Bourdeauducq
523816982a bus/wishbone: add SRAM 2012-12-01 12:59:09 +01:00
Sebastien Bourdeauducq
adb1565d7a pytholite: fix bit width of selection signal 2012-11-30 17:07:32 +01:00
Sebastien Bourdeauducq
cfb23c442f pytholite: support signed registers 2012-11-30 17:07:12 +01:00
Sebastien Bourdeauducq
7093939309 corelogic/roundrobin: fix request width (again) 2012-11-29 23:47:51 +01:00
Sebastien Bourdeauducq
31c722f993 corelogic/roundrobin: fix request width 2012-11-29 23:47:08 +01:00
Sebastien Bourdeauducq
70e97e0456 Fix various errors from new bitwidth/signedness system conversion 2012-11-29 23:36:55 +01:00
Sebastien Bourdeauducq
261166d92b fhdl/verilog: make signal behave as integers in arithmetic (MyHDL style) 
See http://jandecaluwe.com/hdldesign/counting.html
 2012-11-29 22:59:54 +01:00
Sebastien Bourdeauducq
55d143a454 fhdl/structure: add unary minus 2012-11-29 22:52:57 +01:00
Sebastien Bourdeauducq
d8e478efee Replace Signal(bits_for(... with Signal(max=... 2012-11-29 21:53:36 +01:00
Sebastien Bourdeauducq
50ed73c937 New specification for width and signedness 2012-11-29 21:22:38 +01:00
Sebastien Bourdeauducq
6eebfce44a Refactor Case 2012-11-29 01:11:15 +01:00
Sebastien Bourdeauducq
070652cc39 pytholite/reg: use source id in dictionary 2012-11-29 00:09:35 +01:00
Sebastien Bourdeauducq
fee22a4631 Remove Constant 2012-11-28 23:18:43 +01:00
Sebastien Bourdeauducq
59831e0485 fhdl/structure: improved bits_for function 2012-11-28 18:39:44 +01:00
Sebastien Bourdeauducq
11b1e53224 visit/NodeTransformer: copy most nodes 2012-11-28 17:50:55 +01:00
Sebastien Bourdeauducq
a2bcbfdf8f fhdl/tools: use NodeTransformer to lower arrays 2012-11-28 17:46:15 +01:00
Sebastien Bourdeauducq
3bc15024ac fhdl/tools: use NodeVisitor 2012-11-26 21:40:23 +01:00
Sebastien Bourdeauducq
e3a983d731 Remove unroll 2012-11-26 20:07:48 +01:00
Sebastien Bourdeauducq
1460f069f6 fhdl/structure: remove deprecated MemoryPort 2012-11-26 19:36:43 +01:00
Sebastien Bourdeauducq
5183774ec8 bus/wishbone2asmi: do not use MemoryPort 2012-11-26 19:14:59 +01:00
Sebastien Bourdeauducq
fc85ca53ad actorlib/spi: do not use MemoryPort 2012-11-26 18:27:59 +01:00
Sebastien Bourdeauducq
dac0d11e52 actorlib/sim: Dumper 2012-11-24 00:00:07 +01:00
Sebastien Bourdeauducq
27d87c9412 fhdl/structure: disable we_granularity when larger than width 2012-11-23 23:08:12 +01:00
Sebastien Bourdeauducq
d2c61e6a90 sim/generic/multiread: do not return spurious items 2012-11-23 23:07:25 +01:00
Sebastien Bourdeauducq
74721b206f pytholite: fix import of _Slice 2012-11-23 21:20:18 +01:00
Sebastien Bourdeauducq
95122bb778 pytholite/io: support memory 2012-11-23 20:36:09 +01:00
Sebastien Bourdeauducq
f42683b71e fhdl/structure/Memory: fix we width 2012-11-23 19:21:52 +01:00
Sebastien Bourdeauducq
0f6215a13a fhdl/structure: add Memory.get_port API 2012-11-23 19:17:49 +01:00
Sebastien Bourdeauducq
9d3e218863 fhdl: use object creation counter (HUID) as hash. This finally makes the generated code textually the same across runs. 2012-11-23 18:38:03 +01:00
Sebastien Bourdeauducq
3971600917 fhdl/structure: use sets for memories and instance collections 2012-11-23 17:20:08 +01:00
Sebastien Bourdeauducq
f3efd74dfd uio: support memories 2012-11-23 16:23:24 +01:00
Sebastien Bourdeauducq
ab31b4d99c bus: memory initiator 2012-11-23 16:22:50 +01:00
Sebastien Bourdeauducq
0b7dd7bdce pytholite/io: fix Wishbone writes + support sel attribute 2012-11-23 13:40:46 +01:00
Sebastien Bourdeauducq
4c216d8f11 pytholite/io: support Wishbone reads 2012-11-23 13:09:55 +01:00
Sebastien Bourdeauducq
0b24a2ff36 pytholite/io: support Wishbone writes 2012-11-23 12:41:50 +01:00
Sebastien Bourdeauducq
f098c5c695 pytholite/compiler: pass keyword arguments to gen_io 2012-11-23 12:40:57 +01:00
Sebastien Bourdeauducq
51e2e6ecd0 fhdl/verilog: remove empty cases 2012-11-18 16:32:51 +01:00
Sebastien Bourdeauducq
89643bc434 sim/ipc/Message: convert values 2012-11-17 23:19:40 +01:00
Sebastien Bourdeauducq
e92af9de59 pytholite/transel: use python3-compatible comparison methods 2012-11-17 23:16:07 +01:00
Sebastien Bourdeauducq
b6b4c5d70e uio/ioo: fix UnifiedIOSimulation 2012-11-17 22:25:42 +01:00
Sebastien Bourdeauducq
1cabcb3c3f uio: support generator trampolining in simulation 2012-11-17 19:59:22 +01:00
Sebastien Bourdeauducq
be68ecfc72 uio: add simulation I/O object 2012-11-17 19:55:33 +01:00
Sebastien Bourdeauducq
7add4c6f3c uio: unified I/O object 2012-11-17 19:54:50 +01:00
Sebastien Bourdeauducq
d10df1a8ab actorlib/sim: swap TokenExchanger parameters 2012-11-17 19:46:28 +01:00
Sebastien Bourdeauducq
d4baac6c0f bus/csr: allow specifying existing interface 2012-11-17 19:44:25 +01:00
Sebastien Bourdeauducq
86090e1cbd bus/asmibus: swap port position to be consistent with wishbone API 2012-11-17 19:42:39 +01:00
Sebastien Bourdeauducq
ece786d6aa bus/wishbone: allow specifying existing interface 2012-11-17 19:42:06 +01:00
Sebastien Bourdeauducq
d0d4c48098 bus/transactions: add busname parameter 2012-11-17 19:36:08 +01:00
Sebastien Bourdeauducq
897a2e3f9c actorlib/sim: split TokenExchanger 2012-11-17 14:15:51 +01:00
Sebastien Bourdeauducq
eb156af20c pytholite/io: support token pull 2012-11-16 23:48:41 +01:00
Sebastien Bourdeauducq
dd9a102a78 pytholite/io: support token push 2012-11-16 19:24:45 +01:00
Sebastien Bourdeauducq
bf5ce8dc20 pytholite: move expression and register handling to separate modules 2012-11-11 23:48:23 +01:00
Sebastien Bourdeauducq
f59fd69e34 pytholite/compiler: recognize composite I/O pattern 2012-11-11 18:03:16 +01:00
Sebastien Bourdeauducq
0b5652bb79 pytholite/compiler: visit_assign_special 2012-11-11 15:52:06 +01:00
Sebastien Bourdeauducq
687d18a150 pytholite: move FSM management to separate module 2012-11-11 14:30:25 +01:00
Sebastien Bourdeauducq
409a5570e4 pytholite/compiler: refactor visit_block 2012-11-11 14:17:52 +01:00
Sebastien Bourdeauducq
fb63698ef4 pytholite/compiler: clean up visit_statement 2012-11-10 23:30:14 +01:00
Sebastien Bourdeauducq
6ebd1e4503 pytholite: forward 'yield call' statements to io module 2012-11-10 22:59:14 +01:00
Sebastien Bourdeauducq
48acb1bcfd pytholite: introduce io module 2012-11-10 21:51:19 +01:00
Sebastien Bourdeauducq
6776f06a42 pytholite/compiler: support bitslice 2012-11-10 18:04:05 +01:00
Sebastien Bourdeauducq
37f113c3ea pytholite/compiler: support range(constants) in for loops 2012-11-10 15:26:13 +01:00
Sebastien Bourdeauducq
370bab1190 pytholite/compiler: cleanup print statements 2012-11-10 15:10:57 +01:00
Sebastien Bourdeauducq
39c7dc7d63 pytholite/compiler: support for loops (iterating on lists only) 2012-11-10 15:02:55 +01:00
Sebastien Bourdeauducq
93db3edd00 pytholite/compiler: support while loops 2012-11-10 14:37:33 +01:00
Sebastien Bourdeauducq
a901ef46ab Revert "pytholite/compiler: SymbolStack" 
This reverts commit f57da497b2.
 2012-11-10 12:09:45 +01:00
Sebastien Bourdeauducq
f57da497b2 pytholite/compiler: SymbolStack 2012-11-09 23:02:16 +01:00
Sebastien Bourdeauducq
5750c7c07e pytholite/compiler: improve naming of selection signals 2012-11-09 20:19:22 +01:00
Sebastien Bourdeauducq
4921a34616 pytholite/compiler: fix handling of constants 2012-11-09 20:17:57 +01:00
Sebastien Bourdeauducq
26cf1b8840 fhdl: make constants hashable 2012-11-09 20:17:43 +01:00
Sebastien Bourdeauducq
c1b8492b61 pytholite/compiler: go to next state 2012-11-09 20:12:15 +01:00
Sebastien Bourdeauducq
e1075a962c pytholite/compiler: support if statements 2012-11-09 19:37:52 +01:00
Sebastien Bourdeauducq
92ff5095da pytholite/compiler: support comparisons in expressions 2012-11-09 18:41:32 +01:00
Sebastien Bourdeauducq
a645e0b24e pytholite/compiler: create FSM 2012-11-09 17:37:42 +01:00
Sebastien Bourdeauducq
7744655ef2 fhdl/visit: add missing self 2012-11-09 17:37:24 +01:00
Sebastien Bourdeauducq
13af0ce556 fhdl: visit module (untested) 2012-11-09 16:00:11 +01:00
Sebastien Bourdeauducq
9c182c47d1 pytholith: add register muxes 2012-11-08 21:49:20 +01:00
Sebastien Bourdeauducq
18758d87f6 pytholite: do not use ast.NodeVisitor 2012-11-06 13:52:19 +01:00
Sebastien Bourdeauducq
56d4cdeb48 fhdl/structure: make all values hashable 2012-11-06 13:51:51 +01:00
Sebastien Bourdeauducq
3042f047fe pytholite: visit AST and list registers 2012-10-31 15:59:12 +01:00
Sebastien Bourdeauducq
b171b3b3c2 pytholite: transformable elements 2012-10-29 18:13:03 +01:00
Sebastien Bourdeauducq
31cdb02eff bank/description: regprefix 2012-10-15 21:21:59 +02:00
Sebastien Bourdeauducq
7a1a781f49 actorlib/spi: typo 2012-10-15 21:21:42 +02:00
Sebastien Bourdeauducq
daee4fb58c transform/unroll_sync: autodetect in/out 2012-10-15 20:32:07 +02:00
Sebastien Bourdeauducq
fecab5518b transform/unroll_sync: support generator function 2012-10-15 19:42:30 +02:00
Sebastien Bourdeauducq
9efc581bee transform/unroll: support empty dictionaries 2012-10-12 21:54:48 +02:00
Sebastien Bourdeauducq
eacba52fba transform/unroll: support for variables 2012-10-12 19:54:03 +02:00
Sebastien Bourdeauducq
e5fc9cc675 transform: unroll 2012-10-12 13:16:39 +02:00
Sebastien Bourdeauducq
d329d40fe9 actorlib/spi: SingleGenerator 2012-10-09 21:11:15 +02:00
Sebastien Bourdeauducq
c473718a12 actorlib/spi/collector: atomic update for write_count 2012-10-09 19:08:09 +02:00
Sebastien Bourdeauducq
85081793cf bank: remove RE signal for field registers 2012-10-09 19:07:53 +02:00
Sebastien Bourdeauducq
e410973352 bank: support for atomic writes 2012-10-08 18:43:18 +02:00
Sebastien Bourdeauducq
24877f271b actorlib/spi: fix memory port we/wd 2012-10-04 20:10:24 +02:00
Sebastien Bourdeauducq
035870703f flow/actorlib: Simple Processor Interface (WIP) 2012-10-04 18:22:22 +02:00
Sebastien Bourdeauducq
8101b68965 fhdl: fix instance get_io 2012-09-28 18:02:03 +02:00
Sebastien Bourdeauducq
c273866b08 fhdl: support expressions in instance ports 2012-09-22 20:51:10 +02:00
Sebastien Bourdeauducq
2fc9cae88a fhdl: support inverted clock ports in instances 2012-09-22 20:50:49 +02:00
Sebastien Bourdeauducq
2e14569b5c fhdl/verilog: sort clock domains by name 2012-09-11 10:00:03 +02:00
Sebastien Bourdeauducq
9a18a9df3f fhdl: list signals in execution order 2012-09-11 09:59:37 +02:00
Sebastien Bourdeauducq
e16353a281 Multi-clock design support + new instance API 2012-09-10 23:45:02 +02:00
Sébastien Bourdeauducq
6490785b6c Merge pull request #3 from brandonhamilton/upstream 
Optionally accept iverilog simulator options
 2012-09-09 10:52:52 -07:00
Sebastien Bourdeauducq
b45c9546eb fhdl/namer: better handling of indices 2012-09-09 19:33:55 +02:00
Sebastien Bourdeauducq
589251fffd fhdl/tracer: support BUILD_LIST opcode 2012-09-09 18:53:24 +02:00
Sebastien Bourdeauducq
910c350021 fhdl/namer: use execution order indices for variable names as well 2012-09-09 17:31:35 +02:00
Sebastien Bourdeauducq
f3e3a3eec7 fhdl/namer: number objects according to execution order 2012-09-09 12:27:32 +02:00
Sebastien Bourdeauducq
51f9a2a963 fhdl/namer: simplify + more relevant names 2012-09-09 01:26:33 +02:00
Sebastien Bourdeauducq
4164fb4ac9 bus/csr: configurable data width 2012-08-26 21:19:34 +02:00
Sebastien Bourdeauducq
5bf19c155f sim: ensure clean IPC shutdown 2012-08-05 00:16:11 +02:00
Sebastien Bourdeauducq
47c341ecdf flow/isd: add freeze register 2012-08-04 23:39:52 +02:00
Sebastien Bourdeauducq
6de517f59c flow/network: remove print 2012-08-03 18:50:57 +02:00
Sebastien Bourdeauducq
25cb25a8ae flow/network: option to add debugger 2012-08-03 18:49:35 +02:00
Sebastien Bourdeauducq
fd0e281dfc flow: in-system debugger module 2012-08-03 18:49:04 +02:00
Sebastien Bourdeauducq
adacdadd58 flow/hooks/DFGHook: add iterator on hooks 2012-08-03 18:48:35 +02:00
Sebastien Bourdeauducq
37fe6d64c3 flow: EndpointHook -> EndpointSimHook 2012-08-03 12:58:41 +02:00
Sebastien Bourdeauducq
30f1e77c18 corelogic/ReorderBuffer: do not touch empty count when issuing and reading at the same time 2012-07-13 20:21:04 +02:00
Sebastien Bourdeauducq
8de192dfbd x.bv.width -> len(x) 2012-07-13 18:32:54 +02:00
Sebastien Bourdeauducq
9cdc88eadf fhdl: len() for Constant 2012-07-13 18:16:50 +02:00
Sebastien Bourdeauducq
8c169a99df corelogic/misc: remove multimux 2012-07-13 18:05:57 +02:00
Sebastien Bourdeauducq
599ed8d470 fhdl: fix value_bv for operators 2012-07-13 17:40:49 +02:00
Sebastien Bourdeauducq
b4613d913f bus/wishbone: remove use of deprecated multimux 2012-07-13 17:17:20 +02:00
Sebastien Bourdeauducq
7f47a2568a fhdl: remove _StatementList 2012-07-13 17:07:56 +02:00
Sebastien Bourdeauducq
8062e48697 bus/asmibus: fix per-port tag generation 2012-07-12 19:37:50 +02:00
Sebastien Bourdeauducq
c543edf6f3 actorlib/dma_asmi: out-of-order reader and class factory 2012-07-12 18:34:13 +02:00
Sebastien Bourdeauducq
43653dbe1a corelogic: reorder buffer (untested) 2012-07-12 18:33:28 +02:00
Sebastien Bourdeauducq
eed8fa374d fhdl/arrays: use correct BV for intermediate signals 2012-07-11 12:06:32 +02:00
Sebastien Bourdeauducq
ed27783a53 fhdl: arrays (TODO: use correct BV for intermediate signals) 2012-07-09 15:16:38 +02:00
Sebastien Bourdeauducq
c82a468506 bus: CSR initiator 2012-07-07 22:36:15 +02:00
Sebastien Bourdeauducq
0b19112f8f actorlib/misc/IntSequence: add offset feature 2012-07-07 00:10:23 +02:00
Sebastien Bourdeauducq
518501c493 flow/perftools: refactor to use hooks 2012-07-06 23:36:23 +02:00
Sebastien Bourdeauducq
6cf38bfcba flow: hooks 2012-07-06 23:36:10 +02:00
Sebastien Bourdeauducq
a49dcb328a actorlib/structuring/Cast: rawbits parameter 2012-06-29 16:10:50 +02:00
Sebastien Bourdeauducq
fa5a9915c3 doc: actor network 2012-06-25 16:07:45 +02:00
Sebastien Bourdeauducq
920aa5dc60 actorlib: merge composer into ala + derive ComposableSource from ActorNode 2012-06-25 11:34:58 +02:00
Sebastien Bourdeauducq
bbfa120e2f doc: arithmetic and logic actors 2012-06-24 19:56:31 +02:00
Sebastien Bourdeauducq
fd233d5b3c Move arithmetic actors to actorlib 2012-06-24 19:13:49 +02:00
Sebastien Bourdeauducq
1edaec0d75 control.For -> misc.IntSequence 2012-06-22 15:01:47 +02:00
Sebastien Bourdeauducq
4785ca526b flow/perftool: fix cpt equation 2012-06-21 00:41:22 +02:00
Sebastien Bourdeauducq
cbc387f69e actorlib/sim/SimActor: remove dead time between transactions 2012-06-20 22:39:52 +02:00
Sebastien Bourdeauducq
6aff41a883 actorlib/structuring/Pack: drive busy signal 2012-06-20 22:39:03 +02:00
Sebastien Bourdeauducq
34d8ae3c11 flow: perftools 2012-06-20 21:59:17 +02:00
Sebastien Bourdeauducq
6fac3f027f examples/dataflow: structuring test 2012-06-20 18:25:01 +02:00
Sebastien Bourdeauducq
7d0e179a03 actorlib: structuring (untested) 2012-06-20 16:35:01 +02:00
Sebastien Bourdeauducq
1576cb0950 actorlib/control: simplify + fix 2012-06-17 21:19:47 +02:00
Sebastien Bourdeauducq
66ac62d0bb flow/network: fix handling of edges with subrecords at both ends 2012-06-17 18:31:45 +02:00
Sebastien Bourdeauducq
75d569a12c actorlib/control: use numbers of bits instead of maxima 2012-06-17 18:29:57 +02:00
Sebastien Bourdeauducq
4873cfe1a7 flow/plumbing: Combinator/Splitter should not inherit CombinatorialActor 2012-06-17 13:45:18 +02:00
Sebastien Bourdeauducq
98c9da95d1 flow/network: handle default endpoints correctly in _infer_plumbing_layout 2012-06-16 22:41:15 +02:00
Sebastien Bourdeauducq
9af87367eb flow/network: require ActorNode be passed to add_connection 2012-06-16 22:40:26 +02:00
Sebastien Bourdeauducq
b0b0380ea7 flow/network: fix ActorNode default params 2012-06-16 22:39:31 +02:00
Sebastien Bourdeauducq
1a576e5c83 flow/actor: fix busy signal generation for pipelined actors 2012-06-16 22:38:45 +02:00
Sebastien Bourdeauducq
9228e8a96d flow/actor: add single_sink/single_source retrieval methods 2012-06-16 22:38:16 +02:00
Sebastien Bourdeauducq
c1450daa93 flow: insert splitters 2012-06-16 21:23:42 +02:00
Sebastien Bourdeauducq
bde8361e19 flow: insert combinators and infer plumbing layout 2012-06-16 17:30:54 +02:00
Sebastien Bourdeauducq
da522cd58d Abstract actor graphs 2012-06-15 17:52:19 +02:00
Sebastien Bourdeauducq
b14be4c8a3 actorlib: ASMI sequential reader 2012-06-12 21:04:47 +02:00
Sebastien Bourdeauducq
ce9e35b8ef fix SimActor get_fragment 2012-06-12 17:52:08 +02:00
Sebastien Bourdeauducq
8a23451237 PureSimulable 2012-06-12 17:08:56 +02:00
Sebastien Bourdeauducq
a591510189 ASMI simulation models 2012-06-12 16:57:00 +02:00
Sebastien Bourdeauducq
b7a84b3750 wishbone: base TargetModel class 2012-06-10 17:05:10 +02:00
Sebastien Bourdeauducq
ec501e7797 bus/wishbone: target model 2012-06-10 16:40:33 +02:00
Sebastien Bourdeauducq
f061b25a24 bus/wishbone/Tap: remove ack feature 2012-06-10 12:46:24 +02:00
Sebastien Bourdeauducq
009f26bb9d flow/network: refactor graph 2012-06-08 22:49:49 +02:00
Sebastien Bourdeauducq
de408b2cba flow/ala: fix typo 2012-06-08 22:48:47 +02:00
Sebastien Bourdeauducq
356051e8a8 actorlib: WB reader simulation OK 2012-06-08 21:31:05 +02:00
Sebastien Bourdeauducq
11674242c4 Use super() instead of calling parent constructors directly 2012-06-08 18:06:12 +02:00
Sebastien Bourdeauducq
152a7e282e actorlib/sim: use set instead of list to represent active transactions 2012-06-08 17:56:52 +02:00
Sebastien Bourdeauducq
910c7806cf actorlib: generator-based generic simulation actor 2012-06-08 17:54:03 +02:00
Sebastien Bourdeauducq
b145f9e5e2 sim: multiread/multiwrite 2012-06-08 17:52:32 +02:00
Sebastien Bourdeauducq
f38ef626de corelogic/record: better repr 2012-06-08 17:49:31 +02:00
Sebastien Bourdeauducq
1c0f636c8d flow: generic parameter passing to Actor from sequential/pipelined 2012-06-07 18:24:33 +02:00
Sebastien Bourdeauducq
a1fc86af8f flow: fix actor repr 2012-06-07 15:48:35 +02:00
Sebastien Bourdeauducq
680a34465d flow: refactor scheduling models 2012-06-07 14:44:43 +02:00
Sebastien Bourdeauducq
493b181af1 bank/description: pad unaligned multi-word registers at the top 2012-05-21 22:55:23 +02:00
Sebastien Bourdeauducq
9449bbea0a Add LICENSE file 2012-05-21 19:56:23 +02:00
Sebastien Bourdeauducq
68cd445662 bus/wishbone2asmi: fix cache tag size 2012-05-15 15:18:03 +02:00
Sebastien Bourdeauducq
0bea1e2589 asmi: dat_wm high to disable data write 2012-05-15 14:41:54 +02:00
Sebastien Bourdeauducq
f2c20e4af0 bus/asmibus/hub: hack to prevent comb loops 2012-04-30 17:11:42 -05:00
Sebastien Bourdeauducq
398ece8fe2 fhdl/verilog: add option to display which comb blocks are run 
This is a debug hack to help find combinatorial loops in designs.
 2012-04-30 16:38:40 -05:00
Sebastien Bourdeauducq
0b62e573ae sim: pass extra keyword arguments to Verilog converter 2012-04-30 16:38:17 -05:00
Sebastien Bourdeauducq
6a52e44d09 fhdl: support len() on signals 2012-04-08 18:06:22 +02:00
Sebastien Bourdeauducq
b9c533be51 bank/csrgen: allow specifying existing CSR interface 2012-04-06 14:59:09 +02:00
Brandon Hamilton
49b58a03a0 Optionally accept iverilog simulator options 2012-04-03 12:58:19 +02:00
Sebastien Bourdeauducq
2a4e49e381 fhdl: phase out pads 2012-04-02 19:21:43 +02:00
Sebastien Bourdeauducq
623e8e436a fhdl/verilog: do not attempt to initialize instance and mem output signals 2012-04-02 12:59:42 +02:00
Sebastien Bourdeauducq
6e3b25ebb6 bus/dfi: reset active low signals to 1 2012-04-01 17:43:24 +02:00
Sebastien Bourdeauducq
d3c6b8d16f sim/proxy: support lists 2012-04-01 17:19:53 +02:00
Sebastien Bourdeauducq
f3ae22f488 fhdl/verilog: initialize internal read-only signals with their reset values 2012-04-01 16:39:11 +02:00