066f562c5e
Got the MMU refilling itself with datacache cached memory access instead of io accesses
2019-04-03 14:32:21 +02:00
8be40e637b
#60 Got the new data cache design passing all tests and running linux
2019-04-02 23:44:53 +02:00
fd4da77084
#60 Got the new instruction cache design passing the standard regressions
2019-04-02 00:26:53 +02:00
bc0af02c97
#60 Got instruction cache running linux :D
2019-04-01 11:59:04 +02:00
1dff9aff8a
#60 Fix interrupt causing fetch privilege issues
2019-04-01 10:47:54 +02:00
e74a5a71eb
Better simulation console integration
2019-04-01 10:31:55 +02:00
369a3d0f5f
#60 Sync everything, added much comment on the top of Linux.scala to help reproduce
2019-03-31 23:43:56 +02:00
c7314cc606
Got buildroot login, userspace, commands working
...
Moved location of DTB, initrd. Will move again
Added getChar SBI in emulator
Added an QEMU mode in the emulator config.h, work with qemu riscv32 virt
2019-03-31 15:17:45 +02:00
de500ad8f9
Add qemu command
2019-03-30 18:29:17 +01:00
9383445e0b
Add a qemu option (wip)
2019-03-30 18:26:44 +01:00
1a36f2689d
#60 Fix software model. Forgot physical address for on RVC instruction
2019-03-30 11:24:29 +01:00
29980016f3
#60 Fix instruction fetch exception PC by forcing LSB to be zero
2019-03-30 10:10:25 +01:00
9fff419346
Better fix
2019-03-29 09:18:44 +01:00
391cff69d3
#60 should fix the first instruction fetch privilege after interrupt
2019-03-29 09:02:44 +01:00
0c48729611
Sync impact less changes (asfar i know)
2019-03-29 08:43:15 +01:00
ad27007c3c
DBusSimplePlugin AHB bridge add hazard checking, pass tests
2019-03-28 11:41:49 +01:00
53c05c31c7
IBusSimplePlugin AHB bridge fix, pass tests
2019-03-28 10:12:42 +01:00
b0522cb491
Add AhbLite3 simulation config
2019-03-28 08:32:12 +01:00
9ac4998478
Fix emulator nested exception redirection privilege
2019-03-28 00:38:38 +01:00
ac06111163
Fix MMU MPRV, Fix emulator nested exception
2019-03-27 22:58:30 +01:00
0bed511a6c
Fix cacheless LR/SC xtval, did some SRC/ADD_SUB/ALU redesign
2019-03-27 18:58:02 +01:00
43c3922a3d
Add prerequired stuff
2019-03-27 10:55:20 +01:00
f113946e66
Added a neutral LINUX_SOC for sim purposes
2019-03-27 10:53:41 +01:00
b69c474fa2
#60 user space reached
...
/sbin/init: error while loading shared libraries: libm.so.6: cannot stat shared object: Error 38
2019-03-27 00:26:51 +01:00
7a9f7c4fb9
Untested cacheless buses to AHB bridges
2019-03-26 16:30:53 +01:00
94fc2c3ecf
Fix some models missmatch
...
Add more SBI
Add hardware LR/SC support in dbus cacheless
2019-03-26 01:25:18 +01:00
1c3fd5c38b
Fix mprv and add it into the softare model
2019-03-25 12:03:32 +01:00
1ec11dc03d
Fix mprv
2019-03-25 11:47:56 +01:00
c34f5413a3
Add MMU MPRIV for easier machinemode emulation #60
2019-03-25 10:30:13 +01:00
9d55283b3b
Machine mode emulator
2019-03-25 02:00:19 +01:00
e28702eb40
Add PlicCost test
2019-03-24 12:17:39 +01:00
6c0608f0dd
#60
...
Add LitexSoC workspace / linux loading.
Need to emulate peripherals and adapte the kernel now.
Probably also need some machine mode emulation
Software time !
2019-03-24 10:52:56 +01:00
ea62fd0e16
Same thing for DBusSimpleBus.
2019-03-23 23:36:13 +00:00
95c3e436dc
Make toPipelinedMemoryBus() just like the other busses
2019-03-23 22:32:48 +00:00
0656a49332
Make xtval more compliant
2019-03-23 20:12:36 +01:00
7159237104
Fix csrrs/csrrc for xip registers
2019-03-23 18:11:26 +01:00
505bff6f45
CSR Plugin now implement interruptions as specified in the spec
2019-03-23 12:56:04 +01:00
3652ede130
Add mdeleg tests
2019-03-23 11:41:10 +01:00
9139b4d269
Restore all tests
2019-03-22 18:03:35 +01:00
597336b491
MMU sum/mxr tested and ok, all seem finen
2019-03-22 17:11:55 +01:00
f7b793b7bf
Add SSTATUS.SUM/MXR feature, need testing
2019-03-22 15:49:36 +01:00
e4cdc2397a
MMU pass all test, need to and SUM and MXR and it's all ok
2019-03-22 14:52:49 +01:00
2b458fc642
Added MMU superpage support, pass MMU tests
2019-03-22 12:23:47 +01:00
af2acbd46e
Got the new MMU design to pass simple tests #60
2019-03-22 01:10:17 +01:00
ea56481ead
Add supervisor CSR in the riscv golden model
2019-03-20 23:26:08 +01:00
7cbe399f1f
Fix some supervisor CSR access
2019-03-20 23:25:52 +01:00
6f2e5a0eb7
goldenmodel Implement some of the supervisor CSR
2019-03-20 20:28:04 +01:00
39b2803914
Fix some CsrPlugin flags issues
2019-03-20 20:27:47 +01:00
6c2fe934fd
Bring changes and fixies from @kgugala @daveshah1. Thanks guys !
2019-03-20 16:27:35 +01:00
130a69eeae
Pass regressions machinemode with CSR config including Supervisor
2019-03-20 14:14:59 +01:00
d205f88fb8
riscv golden model and RTL pass all current regressions
...
add RVC into the linux config
2019-03-20 12:17:43 +01:00
3c66f7c58a
goldenmodel now pass more machine mode CSR tests
2019-03-20 11:46:27 +01:00
ee402ec5dc
clearning
2019-03-20 01:16:39 +01:00
3a38fe4130
Add mmu regresion blank project
2019-03-20 01:13:05 +01:00
ccc3b63d7c
Enable golden model check for all regressions
...
Need to implement missing CSR of the golden model
2019-03-20 01:12:03 +01:00
8f22365959
Disable MMU in machine mode
2019-03-19 22:21:30 +01:00
3fbc2f4458
Fix generation
2019-03-19 20:29:28 +01:00
915db9d6c9
cleaning
2019-03-18 20:50:19 +01:00
001ca45c57
Add cachless dBus IBus access right checks
2019-03-18 12:52:22 +01:00
c490838202
Added MMU support into cacheless DBus IBus plugins (for testing purposes)
...
Probably full of bugs, need testing
2019-03-18 12:17:43 +01:00
ffa489d211
hardware refilled MmuPlugin wip
2019-03-17 21:06:47 +01:00
b63395435f
SimpleMul core.
2019-03-16 15:44:18 +00:00
5bc53c08ce
Merge branch 'master' of https://github.com/SpinalHDL/VexRiscv into MulSimple
2019-03-16 15:39:07 +00:00
9a61ff8347
Merge remote-tracking branch 'origin/dev'
2019-03-10 11:14:09 +01:00
bad60f39cd
Fix Decoding benchmark
2019-03-10 11:12:32 +01:00
434793711b
fix part of #59
2019-02-26 17:26:42 +01:00
e0c8ac01d2
Add custom external interrupts
2019-02-03 15:20:34 +01:00
11f55359c6
IBusCache can now avoid injectorStage in singleStage mode
2019-01-30 01:37:47 +01:00
56e3321394
cpp regresion now print the time of failure
2019-01-30 01:36:24 +01:00
f4598fbd0a
Add tightly coupled interface to the i$
2019-01-21 23:46:18 +01:00
b5caca54cd
restore all feature in TestsWorkspace
2019-01-16 15:25:50 +01:00
927ab6d127
Merge remote-tracking branch 'origin/master' into dev
2018-12-30 15:53:25 +01:00
dd42e30c61
Merge remote-tracking branch 'origin/master' into dev
2018-12-29 14:04:07 +01:00
d617bafb08
Roll back VexRiscvAvalonForSim to use caches
2018-12-25 00:15:23 +01:00
961abb3cf1
Avalon: Debug Clock Domain for JTAG
...
This change ensures that the clock domain for the JTAG interface
uses the debug plugin's domain. Otherwise, resetting the processor
will put the jtag debugger in to reset as well.
See SpinalHDL/VexRiscv#48
2018-12-22 07:58:59 -08:00
76ebfb2243
Fix machine mode to supervisor delegation
2018-12-10 13:15:03 +01:00
d9029c2efc
Fix #46 by filling missing return statements
2018-12-10 01:44:47 +01:00
281d61bbe1
regression fix hex << dec #46
2018-12-09 16:37:16 +01:00
1fbb81a4d9
regression fix delete [] #46
2018-12-09 15:40:02 +01:00
f121ce1ed5
add sanity asserts in regression #46
2018-12-08 14:10:18 +01:00
9330945623
fix regression makefile
2018-12-07 23:50:13 +01:00
52419fd7ad
Regression remove dplus stuff #46
2018-12-07 23:47:49 +01:00
68fdbe60cc
verilator regression fix missing fclose #46
2018-12-07 23:43:19 +01:00
eca54585b0
Fix hardware breakpoint
2018-12-04 16:57:24 +01:00
ac1ed40b80
Move things into SpinalHDL lib
2018-12-01 18:25:18 +01:00
3d71045159
DebugPlugin doesn't require memory/writeback stage anymore
2018-12-01 18:24:33 +01:00
58d7a4784d
move HexTools into SpinalHDL lib
2018-11-30 17:39:33 +01:00
b1b7da4f10
Rename SimpleBus into PipelinedMemoryBus
...
Move PipelinedMemoryBus into SpinalHDL lib
2018-11-30 17:37:17 +01:00
2f6a2dfccc
Add configs setup in SimpleBusInterconnect
2018-11-29 16:14:45 +01:00
7075e08d9f
Hazarplugin tell to branch plugin if the RS are hazardous in the execute stage
2018-11-24 13:38:54 +01:00
c2b9544794
Allow iBusCached plugin to be used when no memory stage is present
2018-11-24 13:37:53 +01:00
0086de9e36
Fix CsrPlugin catch illegalAccess
...
Add dhrystone optimized divider
cleaning
2018-11-20 19:39:17 +01:00
75d4d049d7
Add shadow regfile
...
various cleaning
2018-11-16 17:06:11 +01:00
cc48fc7403
add fenceiGenAsANop
2018-11-13 15:17:35 +01:00
0d92a5e5cd
Add many little options to reduce area
2018-11-12 14:14:34 +01:00
fb9ea11a5e
Allow VexRiscv to suppress the memory and the writeback stage, allowing to go downto a 2 stage CPU (FETCH_DECODE, EXECUTE)
2018-11-09 05:41:43 +01:00
b12e15b112
branch/csr/muldiv minor improvments
2018-11-07 19:27:49 +01:00
b7f3ee5e06
Fix CsrPlugin pipelined option
2018-11-05 16:22:41 +01:00
662d76e3aa
csrPlugin : avoid using ALU to get SRC1 (which was useless)
2018-11-03 11:29:30 +01:00
978232fd63
Optimise div iterative plugin done signal
2018-11-03 11:12:37 +01:00
c8ac214097
Optimize CSR
2018-10-28 02:18:27 +02:00
51de2b5820
SimpleBusInterconnect now adapte address width
2018-10-28 02:18:08 +02:00
00bf84b7f8
Add SimpleBusInterconnect
2018-10-25 23:47:05 +02:00
4ed4af6a3e
SrcPlugin add decodeAddSub option
2018-10-24 01:28:37 +02:00
372063582c
Improve CsrPlugin CombinatorialPaths
2018-10-23 19:07:08 +02:00
7096c63d50
Add more SimpleBus utilies
2018-10-23 17:46:31 +02:00
7c0f2dc713
Add SimpleBus object
2018-10-20 12:39:30 +02:00
85e696b286
CsrPlugin : Add mtvecModeGen
2018-10-16 14:53:41 +02:00
905abd5aaa
Add wfiGenAsWait and wfiGenAsNop
...
CsrPlugin cleaning
Much cleaning in general
Zephyr is running
2018-10-16 13:07:30 +02:00
f903df4b66
sync
2018-10-12 17:13:54 +02:00
2b29690010
Clean branch plugin lsb bit calculation
...
BranchPlugin doesn't try anymore to catch exception when RVC is on
2018-10-12 12:24:52 +02:00
eea92154ae
fetcher force PC LSB to be zero
2018-10-12 12:02:52 +02:00
0b8f6f6ed4
Fix broken C.LWSP reference_output
2018-10-12 12:02:02 +02:00
594f7a8bf2
Seem to pass all risc-v compliance tests, excepted the C.LWSP which is a broken test
2018-10-11 22:19:17 +02:00
8c25e73b9d
Fix DIV negative values divided by zero
2018-10-11 22:18:21 +02:00
c26b7e15cf
BranchPlugin exceptions are now risc-v compliance alligned
2018-10-11 17:56:49 +02:00
8b1a4a2717
Add RISCV compliance regression test, need to fix I-MISALIGN_JMP-01 mtval
2018-10-11 00:25:39 +02:00
40d85b8c70
Add fenceiGenAsAJump into BranchPlugin
2018-10-10 21:13:21 +02:00
68f1ff3222
Add CsrPlugin ebreak support
2018-10-10 19:23:04 +02:00
0662cc2797
Add GenMicro experiment to reduce ice40 area usage.
...
IBusSimplePlugin now require cmdFork parameters to be set (no default)
2018-10-03 22:08:57 +02:00
48bff80653
rework fetchPc to optionaly share the pcReg with the stage(1)
...
IBusSimplePlugin now implement cmdForkPersistence option
2018-10-03 16:24:10 +02:00
c61f17aea3
Fetcher/IBusSimplePlugin wip
2018-10-03 01:02:22 +02:00
0ada869b2d
regression golden ref regfile is now sync with trl boot's random values
...
wip
2018-10-01 16:14:21 +02:00
65a8d84d30
Introduce HAS_SIDE_EFFECT Stageable to solve sensitive instruction squeduling
...
(uncached DBus TODO)
2018-10-01 12:13:05 +02:00
7770eefa3b
wip
2018-09-30 12:57:08 +02:00
39c6bc11d6
Pass basic regression again
2018-09-29 19:04:20 +02:00
5ad7c39f47
wip
2018-09-29 12:04:58 +02:00
37a1970ad6
wip
2018-09-28 16:02:33 +02:00
9a3510f63d
Map all supervisor registers
2018-09-27 19:03:57 +02:00
acd1ca422a
wip
2018-09-27 18:24:40 +02:00
6dde73f97c
Murax demo with XIP is now fully defined in SpinalHDL
2018-09-27 00:55:30 +02:00
aff436ddcf
Sync with SpinalHDL head
...
Add mmu test into the dhrystone regression command
2018-09-24 18:31:33 +02:00
1e3b75ef1d
xip typo
2018-09-23 22:06:21 +02:00
86efb75f6a
rework fetcher
2018-09-23 22:05:53 +02:00
56fd73fbbc
Add missing bin files
2018-09-23 19:26:11 +02:00
bdc3246f5a
Fix xip gitignore
2018-09-23 19:23:43 +02:00
5024cc5616
Hardware breakpoint feature added
...
Murax XIP debugging passed tests
2018-09-20 13:11:20 +02:00
ff1d1072a7
XIP is physicaly working on murax
2018-09-19 00:09:14 +02:00
b51ac03a5e
murax xip flash integration wip
2018-09-18 16:53:26 +02:00
3e17461cc7
Add optional XIP to Murax
2018-09-16 11:00:56 +02:00
d7cba38ec2
move to SpinalHDL 1.1.7, add more default value for plugins parameters
2018-09-11 16:08:28 +02:00
791608f655
Move swing stuff into main test package
2018-08-29 14:55:25 +02:00
0255f51cc5
Add unpipelined Wishbone support for uncached version
2018-08-24 16:41:34 +02:00
7ed6835e97
Add C++ VexRiscv model to cross check the hardware simulation
2018-08-22 02:08:55 +02:00
38af5dbdd5
riscv emulator WIP (RVC missing)
2018-08-21 01:03:51 +02:00
dca1e5f438
revert RVC from murax
2018-08-17 23:12:45 +02:00
8ebb3af4fc
Merge remote-tracking branch 'origin/master' into reworkFetcher
...
Conflicts:
README.md
src/main/scala/vexriscv/TestsWorkspace.scala
src/test/scala/vexriscv/Play.scala
2018-08-17 20:56:51 +02:00
9c7e089329
Fix ExternalInterruptArrayPlugin CSR ids
2018-08-17 20:38:33 +02:00
1d3ac7830b
restore tests without CSR catch all
2018-08-17 19:33:41 +02:00
330ee14a23
final fetchRework commit ?
2018-08-17 19:13:23 +02:00
91773ec7d5
Sync, Seem to pass all except dynamic_o0 which is probably a freertos test setup issue
2018-08-14 11:51:53 +02:00
ae85698a2b
MulSimple
2018-08-09 22:15:26 -07:00
32fe1dcbd4
Add google cloud VM regressions scripts
2018-07-07 21:47:09 +02:00
3ea4f28354
wip
2018-07-07 11:39:42 +02:00
9c1a8ea219
Fix EPC
...
Fix Freertos binaries
wip
2018-07-03 23:17:32 +02:00
ffe5fa23f0
wip
2018-06-25 09:36:07 +02:00
d73aa9ce00
rework csr exception/interrupt handeling wip
2018-06-24 00:14:55 +02:00
dd47db9ad0
wip
2018-06-20 12:35:12 +02:00
8886f7e6d4
test wip
2018-06-19 16:15:42 +02:00
1090111a6f
TestIndividual is now fully random
2018-06-15 13:00:59 +02:00
b2cd8c5314
Fix exception pipelining
2018-06-15 13:00:26 +02:00
83864710a3
Fix IBusCached single cycle interaction with mmu bus
...
Add random test configs
2018-06-09 08:40:19 +02:00
08a1212fca
Add DBus simple/cached regressions
2018-06-07 02:31:18 +02:00
6bc5431fcd
Add iBusCached regressions
2018-06-07 00:57:26 +02:00
5e7dd02bf7
Fix relaxedPc/DYNAMIC_TARGET interaction
2018-06-06 18:30:30 +02:00
dc968020c4
Fix relaxedBusCmdValid pendingCmd overflow
2018-06-06 15:20:37 +02:00
7768f065e4
Add many cpu configs on regressions tests (some config are broken)
2018-06-06 02:23:07 +02:00
8729530a8d
Fix Dynamicfetch/!rvc config
2018-06-05 02:33:18 +02:00
930563291c
Allow RVC/dynamic_target/fetch bus latency > 1 all together
...
Fix freeretos rvc regressions
2018-06-05 02:21:05 +02:00
702db29edd
Fix dynamic prediction RVC allignement
2018-06-04 20:03:08 +02:00
fc835f370e
Fix DynamicPrediction with RVC missprediction between ret instruction and first instruction of the next function
2018-06-04 19:45:15 +02:00
52f1cdbca7
Fix some missing Barriel -> barriel fixes
2018-06-03 21:46:40 -07:00
9f0387350b
Add Freertos RVC binaries regression
2018-06-03 17:10:58 +02:00
e9bbbb3965
BarrielShifter -> BarrelShifter
2018-06-03 07:40:11 +00:00
7375855e58
DYNAMIC_PREDICTION used with RVC pass tests (1 cycle fetch)
2018-06-03 00:50:18 +02:00
98b68093f4
dynamic_prediction + RVC => instruction fetch stopped midair
2018-05-28 21:28:39 +02:00
863ac3f34d
dynamic prediction now use history from first aligned word of the instruction instead of the last one.
2018-05-28 11:03:13 +02:00
8a0c238bf3
dynamic prediction ok with rvc, todo dynamic_target with rvc
2018-05-28 10:59:22 +02:00
0335543309
More Unrolls
2018-05-28 07:20:26 +00:00
1613191779
Unrool -> Unroll
2018-05-28 07:18:13 +00:00
7493e70265
Merge remote-tracking branch 'origin/master' into reworkFetcher
2018-05-28 09:02:30 +02:00
5943ee727e
Fill travis, DhrystoneBench is now a Unit test
2018-05-28 09:02:01 +02:00
1752b5f184
Give name to inter stages registers
2018-05-27 23:39:49 +02:00
5704f22739
wip
2018-05-27 23:33:57 +02:00
346338f084
Better HexTools
2018-05-26 11:51:42 +02:00
6142b04603
Move HexTools into Spinal
2018-05-26 11:43:16 +02:00
c8677cca9b
Better HexTools
2018-05-26 11:32:36 +02:00
b0777bc646
Merge remote-tracking branch 'origin/master' into reworkFetcher
2018-05-24 14:05:35 +02:00
6004dcc365
Fix typo
2018-05-24 14:04:50 +02:00
9815763b7f
Merge remote-tracking branch 'origin/master' into reworkFetcher
...
Conflicts:
src/main/scala/vexriscv/plugin/PcManagerSimplePlugin.scala
src/test/cpp/regression/main.cpp
2018-05-24 14:04:01 +02:00
c4f33b30e2
Update SynthesisBench murax
2018-05-24 14:03:28 +02:00
485f35a1b5
IBusCachedPlugin default is two cycle cache with single cycle ram.
2018-05-24 13:46:31 +02:00
2f8ccc55b6
Fix branch plugin decode prediction exception by using the instruction decoder
2018-05-24 12:52:00 +02:00
a53f8fdc35
Clean configs
2018-05-23 16:57:32 +02:00
eb5bc4a791
Fix RVC decompressor (ALU immediats)
2018-05-22 17:23:20 +02:00
ff760a0bf0
DYNAMIC_TARGET branch prediction back for not compressed ISA (PASS)
2018-05-21 13:45:08 +02:00
7ffbfab312
Reintroduce MMU feature (pass tests)
2018-05-16 20:32:12 +02:00
c8cec59f1d
Update IBusCachedPlugin parameters
2018-05-16 12:11:53 +02:00
3b54ecf303
Restore two cycle instruction cache features
2018-05-15 23:03:33 +02:00
4e7152ae5a
IcestormFlow add ultraplus support
2018-05-14 20:18:53 +02:00
df3d9ccb13
rework IBusSimplePlugin parameters
2018-05-14 10:31:40 +02:00
c0271d382f
More assertion (csrPlugin)
2018-05-14 10:13:44 +02:00
9caa7163ae
IBusSimplePlugin add relaxedBusCmdValid feature
2018-05-14 10:04:19 +02:00
610bd01f3b
remove rspStageGen
2018-05-14 09:21:28 +02:00
7b37669a0f
Add exception catch to iBusSimplePLugin (pass)
2018-05-09 18:43:48 +02:00
acccbf40e2
RVC debug pass tets
2018-05-09 00:28:14 +02:00
0056da1342
DebugPlugin work
2018-05-08 02:01:34 +02:00
e65757e34c
wip before moving the fetchHalt
2018-05-06 16:38:00 +02:00
294293cb70
Reintroduce debug plugin (instruction injector need optimisations)
2018-05-05 23:05:32 +02:00
a50fbf0d7a
Fix IBusCachedPlugin Pass all dhrystone tests
2018-04-30 13:35:17 +02:00
558af595a1
Add ice40 synthesis results
2018-04-26 13:14:37 +02:00
bdcf3f6234
Add HexTools and add a Briey main which load the ram
2018-04-26 10:27:39 +02:00
cfc324aa0f
Allow csr mtvec to not have reset values
2018-04-24 23:33:48 +02:00
a9cbc48eb2
PcManagerPlugin is can now handle an external reset vector signal
2018-04-24 23:11:11 +02:00
978eb9b6b2
DBusCachedPlugin add CSR info
2018-04-22 11:46:01 +02:00
74f2a4194a
Add ExternalInterruptArrayPlugin
2018-04-20 17:56:21 +02:00
6598e82920
wishbone => word address, not byte address
2018-04-19 11:22:06 +02:00
455607b6b4
Fix dBus IO access
2018-04-18 14:11:59 +02:00
6e59ddcc73
Cached wishbone demo is passing regression tests
2018-04-18 13:51:33 +02:00
b37fc3fcc8
Add VexRiscv Wishbone demo for sim (generation ok)
2018-04-18 12:54:20 +02:00
a66efcb35b
Add wishbone support for i$ / d$ (not tested)
2018-04-17 23:56:44 +02:00
4440047fb6
ICache compressed is working
2018-04-16 10:34:18 +02:00
76352b44fa
wip
2018-04-13 12:51:27 +02:00
19d5d1ecf1
wip
2018-04-09 09:18:08 +02:00
4dd2997ad5
wip
2018-04-09 09:12:30 +02:00
e00c0750eb
wip
2018-04-03 18:37:05 +02:00
d9f2e03753
statuc prediction is fully funcitonnal
2018-04-02 17:43:58 +02:00
76ca852478
Static prediction is fully functionnal
2018-04-02 17:43:06 +02:00
0919308a8f
IBusSimplePlugin add relaxedPcCalculation
2018-03-23 22:49:32 +01:00
c48c7170e8
Added many pipelining option into IBusSimplePlugin
2018-03-23 19:07:03 +01:00
351ad10925
RVC Add dhrystone regressions (PASS)
2018-03-21 23:36:57 +01:00
0c7c2a1fba
IBusPlugin add support of bus error when using compressed instruction
2018-03-21 22:34:54 +01:00
31a464ffdc
VexRiscv now pass Riscv-test compressed stuff
2018-03-21 20:50:07 +01:00
af638e7bde
RV32IC is passing some of the compressed Riscv-test tests
2018-03-21 20:30:09 +01:00
f872d599e2
Add decodePcGen
2018-03-20 18:34:36 +01:00
1fb138de1f
IBusSimplePlugin fully functional Need to restore branch prediction
2018-03-20 00:01:28 +01:00
ac74fb9ce8
iBusSimplePlugin done, DebugPlugin need minor rework
2018-03-18 13:21:21 +01:00
64022557bf
Add synthesis attribut to the PcManagerSimplePlugin to optimize the pc calculation for vhdl
2018-03-15 18:56:25 +01:00
63c1b738ff
Add synthesis attribut to the PcManagerSimplePlugin to optimize the pc calculation inferation timings
2018-03-14 00:56:23 +01:00
d9b7426cde
undo InOutWrapper from Murax
2018-03-14 00:47:23 +01:00
91031f8d75
DivPlugin is now based MulDivIterativePlugin (Smaller)
2018-03-10 13:31:35 +01:00
e437a1d44e
Add division support in the MulDivInterativePlugin
2018-03-09 22:41:47 +01:00
36438bd306
iterative mul improvments
2018-03-09 20:00:50 +01:00
674ab2c594
experimental iterative mul/div combo
2018-03-09 19:07:26 +01:00
5228a53293
MuraxSim improve simulation Speed
2018-03-06 12:20:39 +01:00
9b2cd7b234
MuraxSim add switch
2018-03-06 12:17:15 +01:00
53970dd284
SpinalHDL 1.1.4
...
Now the CsrPlugin is waiting that the memory/writeback stages are empty before reading/writing things
2018-03-05 14:34:59 +01:00
ccad64def5
Pipeline CSR isWrite
2018-02-26 10:19:33 +01:00
2b6185b063
Decoding logic : Add primes duplication removal
2018-02-25 08:57:31 +01:00
2b6f43cef8
Fix Murax memory mapping range
2018-02-25 08:57:31 +01:00
Charles Papon
Tom Verbeure
Brett Foster
Morard Dany
Dolu1990