b1b920531a
build/xilinx/common/platform/programmer: cleanup pass
2019-12-06 22:23:04 +01:00
edaa66bbed
boards: add Lambdaconcept's PCIe Screamer (R02)
2019-12-06 18:20:59 +01:00
a8635c48a4
targets/versa_ecp5: fix compilation with diamond
2019-12-06 16:15:08 +01:00
30a18808ad
boards/targets: keep attributes are no longer needed since automatically added when applying constraints to signals.
2019-12-06 15:58:06 +01:00
23c33cfa99
build: automatically add keep attribute to signals with timing constraints.
...
Avoid having to specify it manually or eventually forget to do it and have a constraints that is not applied correctly.
2019-12-06 15:41:15 +01:00
4c9af635d2
build/altera/quartus: allow adding period constraints on nets and add optional additional sdc/qsf commands
...
Additional sdc/qsf commands can be added from the design like:
platform.sdc_additional_commands.append("create_clock ...")
platform.sdc_additional_commands.append("set_false_path ...")
2019-12-06 15:19:07 +01:00
22e6f5ac1d
build/lattice/trellis: nextpnr now handle LPF timing constraints and multiple clock domains, freq_constraint is no longer needed.
2019-12-06 12:57:59 +01:00
8fb3f9a90d
build/lattice: cleanup/simplify (no functional changes)
...
icestorm still need to be cleaned up
2019-12-06 12:54:52 +01:00
946478a71e
build/lattice: cleanup/simplify
2019-12-06 12:13:20 +01:00
60edca2345
build/microsemi: cleanup/simplify (no functional change)
2019-12-06 12:12:43 +01:00
50fdc5ce41
build/altera: cleanup/simplify (no functional change)
...
Altera build backend was a bit messy and needed some cleanup to ease future maintenance and new features.
2019-12-06 11:08:46 +01:00
b17dfafa55
Merge pull request #313 from mmicko/yosys_ise_flow_fix
...
Yosys - ISE flow fix
2019-12-05 19:05:44 -08:00
8d90f4e97b
build/xilinx/vivado: use VHDL 2008 as default
2019-12-03 15:27:20 +01:00
cfd17321e2
targets/nexys4ddr: remove MEMTEST_ADDR_SIZE limitation (no longer needed)
2019-12-03 10:11:15 +01:00
201d60f37a
targets/netv2: switch to MVP DDR3 (K4B2G1646F instead of MT41J128M16)
2019-12-03 09:05:52 +01:00
6b82064723
targets: uniformize, improve presentation
2019-12-03 08:58:01 +01:00
6de20f185a
soc/interconnect/csr: add fields support for CSRStorage's write simulation method
2019-12-02 09:44:44 +01:00
2567a0ae1d
soc/cores/gpio: add GPIO Tristate
2019-12-01 21:26:37 +01:00
f411d6d362
trellis: Support the CABGA256 package
2019-11-30 02:50:41 +01:00
783dfa508c
Properly select family for those currently supported
2019-11-29 19:11:22 +01:00
6560911df2
Integrate with latest yosys changes
2019-11-29 17:12:08 +01:00
581c23725e
spi_flash: correct documentation on SPI mode
...
The SPI mode is actually mode3, since the output value is updated on the
falling edge of CLK and the input value is updated on the rising edge.
This also clarifies some of the documentation based on experience with
the core.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-11-25 12:35:13 +08:00
de205d4a84
tools/remote/comm_udp: only use one socket
2019-11-22 15:28:35 +01:00
bdaca40fe4
build/generic_platform: avoid duplicate in GenericPlatform.sources
2019-11-22 15:28:07 +01:00
6883a43680
soc/cores/clock: change drp_locked to CSRStatus and connect it :)
2019-11-20 19:37:16 +01:00
36107cdfd7
soc/cores/clock: reset PLL/MMCM on all 7-series/Ultrascale with self.reset signal
2019-11-20 19:24:40 +01:00
e8e70b164a
Merge pull request #309 from antmicro/mmcm-fix
...
soc/cores/clock: add lock reg and assign reset
2019-11-20 19:20:15 +01:00
fd14b76594
soc/cores/clock: add lock reg and assign reset
...
It was necessary to add drp_locked CSR for reading LOCK signal from
MMCM. Additionally, input signal RESET from MMCM was not driven by
any signal to do a proper reset of MMCM module thus it was impossible
to perform entirely correct dynamic clock reconfiguration.
2019-11-20 16:22:49 +01:00
04017519c8
soc/interconnect/axi: add Wishbone2AXILite
2019-11-20 12:32:22 +01:00
d905521185
build/tools/get_migen/litex_git_revision: avoid git fatal error message is not installed as a git repository
2019-11-19 09:11:11 +01:00
02bfda5e38
Merge pull request #308 from gsomlo/gls-sdram-init
...
soc_sdram, bios/sdram: support sdram init for csr_data_width <= 32
2019-11-18 18:24:35 +01:00
3ef13fd27a
soc_sdram, bios/sdram: support sdram init for csr_data_width <= 32
...
Enable SDRAM to be initialized when csr_data_width > 8 bits.
Currently, csr_data_width up to 32 bits is supported.
Read leveling tested with csr_data_width [8, 16, 32] on the
ecp5-versa5g and trellisboard (using yosys/trellis/nextpnr),
and on the nexys4ddr (using Vivado).
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-11-18 09:00:19 -05:00
1efb18f1ea
soc/interconnect/packet/Depacketizer: another simplifcation pass
2019-11-18 09:06:56 +01:00
af52203c00
soc/interconnect/packet/Depacketizer: cleanup "ALIGNED-DATA-COPY" state
2019-11-17 11:57:14 +01:00
8272a00d6e
soc/interconnect/packet/Depacketizer: replace no_payload with sink_d.last
2019-11-17 11:50:09 +01:00
6059712794
test/test_packet: add randomness on ready output, fix corner-cases on Packetizer/Depacketizer
2019-11-16 14:39:18 +01:00
9642893371
test/test_packet: add randomness on valid input, fix corner-cases on Packetizer
2019-11-16 08:49:04 +01:00
888fd55bd8
Merge pull request #307 from sergachev/master
...
change >512 B CSR memory exception to a warning
2019-11-15 18:17:35 +01:00
2f2cfc9951
soc/interconnect/packet: fix synthesis (synthesis tools can do all sort of optimizations, but we still need to provide valid verilog :))
2019-11-15 16:19:05 +01:00
444ae951e9
change >512 B CSR memory exception to a warning
2019-11-15 15:34:12 +01:00
31661e9e2d
soc/interconnect/packet: connect error/last_be only present on both sink and source
2019-11-15 14:57:31 +01:00
2946581e50
soc/interconnect/packet: simplify/refactor Packetizer/Depacketizer to keep it simple
...
To avoid complex FSMs, let the synthesis tool do the simplifications when the FSM states are not reachable.
2019-11-15 14:39:55 +01:00
86662b54d0
soc/interconnect/packet: update copyright
2019-11-15 11:25:38 +01:00
5c19b133ac
soc/interconnect/packet: add > 8-bit support to Packetizer/Depacketizer
...
With high speed link (10gbps XGMII ethernet for example), stream data_width is generally
> 8-bit which make header/data un-aligned on bytes boundaries. The change allows the
Packetizer/Depacketizer to work on stream with a data_width > 8-bit.
2019-11-15 11:24:17 +01:00
5f151152ca
build/sim: cleanup run_as_root
2019-11-15 10:57:31 +01:00
446ae57b75
build/sim/modules: add XGMII 10Gbps ethernet module
...
Used to simulate SoCs with XGMII 10Gbps ethernet and to do LiteEth verification
2019-11-15 10:51:55 +01:00
56fbd2f250
sim/ethernet: remove trailing whitespaces
2019-11-15 10:39:49 +01:00
eb3888f68e
tools/litex_sim: cleanup/update (no functional change)
2019-11-14 11:19:23 +01:00
4798d6b750
tools/litex_term: remove automatic reboot when flashing and clear mem_regions to avoid re-flashing on next reboot(s)
2019-11-11 18:38:10 +01:00
a17e307acf
bios/flash: minor cleanup on serialboot flashing, add flash address support
2019-11-09 00:05:36 +01:00
2d6100bdbe
Merge pull request #305 from FrankBuss/master
...
adding support to flash an FBI image
2019-11-08 23:51:49 +01:00
05e8abfee3
soc_core: add integrated-rom-file parameter to allow initializing rom from command line
2019-11-08 23:32:10 +01:00
0a030fe17d
cores/code_8b10b/Decoder: add basic invalid symbols detection
...
Check that we have 4,5 or 6 ones in the symbol. This does not report all
invalid symbols but still allow detecting issues with the link.
2019-11-08 19:43:01 +01:00
9857d9d9d2
adding support to flash an FBI image
2019-11-08 17:16:28 +01:00
c96f31a9ad
software/bios: rename ef command to fe (for consistency)
2019-11-08 13:14:21 +01:00
4a12a92d62
software/libbase/spiflash: rename CHIP_ERASE_CMD to CE_CMD (for consistency)
2019-11-08 13:13:54 +01:00
7fb9cfeb64
Merge pull request #302 from FrankBuss/master
...
erase flash command added
2019-11-08 13:04:33 +01:00
db4739df81
soc_core: remove add_cpu method (when no real CPU but only wishbone masters, self.cpu is declared as CPUNone)
2019-11-08 12:55:29 +01:00
468df3c857
erase flash command added
2019-11-07 19:19:54 +01:00
f1714405c3
integration/export: do not include soc.h in csr.h when with_access_functions=False
...
Idealy we should have another parameter for that.
2019-11-07 09:02:31 +01:00
b52dcde9ba
soc_sdram/kcu105: add optional main_ram_size_limit and use it on KCU105 to limit to 1GB instead of 2GB.
...
CSR map will need to be updated to support the 2GB.
2019-11-07 09:00:54 +01:00
9053d0803a
soc_sdram: remove use_full_memory_we parameter (always used as True)
2019-11-07 08:56:52 +01:00
1b94699d12
soc_sdram: update copyrights
2019-11-07 08:44:34 +01:00
28708f4208
cpu/rocket: parameterize axi interface data width
...
Rocket variants can be configured with axi port data widths that
are multiples of the native word size (64 bits in our case). In
the future, we will add variants with mem_axi data width > 64 bit,
to match the native data width of the LiteDRAM controller on
various development boards (e.g., 128 bits on the ecp5versa, and
256 bits on the trellisboard).
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-11-01 08:55:27 -04:00
014db66444
soc_sdram: remove upper limit on usable main RAM
...
Revert commit #68a503174.
2019-11-01 08:55:15 -04:00
ec831f5b63
cpu/rocket, soc_sdram: Connect mem_axi to LiteDRAM, bypass WB bus
...
Connect Rocket's dedicated port for cached RAM accesses (mem_axi)
directly to the LiteDRAM data port, bypassing the shared LiteX
(Wishbone) bus.
When both Rocket's mem_axi and LiteDRAM's port have the same data
width, use a native point-to-point AXI connection.
Otherwise, convert both ends to Wishbone, and use the Wishbone
data width converter to bridge the gap.
FIXME: In the future, this part should be replaced with a native
AXI data width converter!
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-11-01 08:52:39 -04:00
9c3c43c94a
interconnect/csr_bus/SRAM: add mem_size check
...
Memory size is limited to 512 bytes:
- CSR region size is 0x800 (4096)
- default csr_data_width is 8
maximum size = 4096/8 = 512 bytes.
2019-11-01 11:33:50 +01:00
edb1731ef9
soc_core/soc_core_args: specify default cpu (vexriscv)
2019-11-01 11:30:50 +01:00
cc607f022a
lattice/diamond/tcl: always use / separators, even on windows
2019-11-01 10:11:12 +01:00
59acf0ea1c
cpu/minerva: elaborate minerva verilog to build directory
2019-11-01 09:59:13 +01:00
a762d29b19
soc/integration/builder: pass output_dir to platform, make sure gateware/software directory are created before finalizing
2019-11-01 09:59:06 +01:00
855d0e925d
cpu/minerva: generate minerva.v near core.py not in submodule
2019-10-31 21:16:27 +01:00
85d6607257
cpu/minverva: give more explicit error message when not able to elaborate cpu
2019-10-31 08:52:04 +01:00
4408dad9d2
Improve the error message on memory region conflict.
...
Before;
```
ValueError: Memory region conflict between rom and main_ram
```
After;
```
ValueError: Memory region conflict between rom (<SoCMemRegion 0x10000000 0x10000 cached>) and main_ram (<SoCMemRegion 0x0 0x20000000 cached>)
```
Fixes #296 .
2019-10-30 19:32:20 -07:00
607e1cc4f6
Fix file names for the mor1kx processor.
...
Fixes #292 .
2019-10-30 13:50:01 -07:00
a54b80b9b4
targets: use type="io" instead of io_region=True
2019-10-30 16:42:31 +01:00
a0c0a6fd05
integration/SoCMemRegion: use type instead of io_region/linker_region and export type to csv/json
...
Supported types: "cached", "io", "cached+linker", "io+linker", default="cached"
2019-10-30 16:42:26 +01:00
9fcf297387
soc_core: add check_regions_overlap method, add linker_region support (overlap is not checked on linker_regions)
2019-10-28 18:34:03 +01:00
4014fbffe1
soc_core/add_memory_region: fix memory overlap detection
2019-10-28 17:07:37 +01:00
ab8af28213
cpu/minerva: elaborate from nmigen sources during build, enable hardware multiplier
2019-10-28 10:23:08 +01:00
49372852da
build/lattice/trellis: optionally allow failure if p&r timing not met
...
When timing requirements are strict, allow the build process to fail upon
failure to meet timing. This facilitates running the build process from a
loop, repeatedly, until a "lucky" p&r solution is found, e.g.:
while true; do
litex/boards/targets/versa_ecp5.py --gateware-toolchain trellis \
--sys-clk-freq=60e06 --cpu-type rocket --cpu-variant linux \
--with-ethernet --yosys-nowidelut \
--nextpnr-timingstrict
if [ "$?" == "0" ]; then
echo "Success" | mail -s "Build Succeeded" your@email.here
break
fi
done
This augments commit #683e0668, which unconditionally forced p&r to
succeed, regardless of whether timing was met, via '--timing-allow-fail'.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-10-24 13:56:20 -04:00
b6d35c92ae
Merge pull request #283 from kbeckmann/kbeckmann/bios_increment_address
...
bios: Increment address when writing to flash
2019-10-20 15:30:22 +02:00
ef78ae951f
bios: Increment address when writing to flash
2019-10-19 22:58:24 +02:00
683e066812
build/lattice/trellis: use --timing-allow-fail to allow generating bistream when timings are not met
...
This is the default behaviour of the others tools and allow testing designs on hardware with small violations.
2019-10-18 14:12:01 +02:00
4cf346a1d4
soc/cores/icap/ICAPBitstream: always keep fifo.source.ready to 1
2019-10-18 10:27:37 +02:00
8b5da9c623
cores/icap/ICAPBitstream: add source ready signal.
2019-10-18 09:33:31 +02:00
626533ce9d
soc/integration/__init__: remove imports (not used and causing issues
2019-10-17 12:44:37 +02:00
675b455259
build: always use platform.add_source and avoid manipulate platform.sources directly
2019-10-17 12:17:36 +02:00
43f5d1ef13
build/generic_platform: replace set with list for sources/verilog_include_paths
...
Python does not have native OrderedSet and we need to be able to preserve the order of the sources
for some backends (Verilator for instance), so use list instead of set.
2019-10-17 09:52:49 +02:00
97a77b950c
cores/icap/ICAPBitstream: simplify, add icap_clk_div parameter, describe how to use it.
2019-10-16 15:00:58 +02:00
98c224be15
build/generic_platform: keep language to None if None after tools.language_by_filename
2019-10-15 12:14:37 +02:00
14dae8bd73
soc_core: fix default --uart_name
2019-10-14 22:15:02 +02:00
ba26441889
integration/soc_core: expose more SoC parameters
2019-10-14 09:12:25 +02:00
0e467168fd
picorv32: Fix minimal variant params
...
The param p_ENABLE_COUNTERS was misspelled.
2019-10-13 12:56:55 +02:00
ef504f62af
soc_core: fix soc_core_argdict
2019-10-12 23:05:53 +02:00
cd8213b988
cpu/lm32: add missing buses
2019-10-12 19:20:50 +02:00
5a0358754d
soc_core/soc_core_argdict: use inspect to get all parameters and simplify
2019-10-12 19:18:57 +02:00
96c369f3e4
integration: simplify cpu buses auto-conversion (always use Converter, thanks gsomlo)
2019-10-11 21:55:26 +02:00
29e51f5e97
interconnect/wishbone: fix Converter case when buses are identical
2019-10-11 21:49:11 +02:00
ae9c25b74f
platforms/versa_ecp5: add serdes refclk/sma
2019-10-11 19:51:38 +02:00
9a82933858
cpu/rocket: expose 64-bit buses (use automatic down-conversion of SoCCore)
2019-10-11 09:01:50 +02:00
ca81cc209b
soc_core: add automatic down-conversion of CPU buses to 32-bit (if needed)
2019-10-11 09:01:08 +02:00
03faf06c82
soc/interconnect/axi: re-align to improve readability
2019-10-11 08:41:05 +02:00
7dea9afd7d
software/bios: simplify banners
2019-10-11 08:38:12 +02:00
6bd1889330
cpu/picorv32: remove obsolete comment
2019-10-10 22:29:54 +02:00
28517d20ca
cpu/picorv32: use a single idbus
2019-10-10 22:02:04 +02:00
5daf1a2296
cpu: cleanup/re-align
2019-10-10 21:52:09 +02:00
467d35edee
cpu/rocket: rename ibus/dbus to mem_wb/mmio_wb and add size suffix
2019-10-10 21:40:29 +02:00
1045cda39e
cpu: add buses list and use it in soc_core to add bus masters
2019-10-10 21:35:06 +02:00
42ccc91f74
integration: move soc constants to soc.h of csr.h
...
software retro-compat with soc.h included in csr.h
2019-10-10 21:15:49 +02:00
ed3c53d7cd
build/generic_platform: only add sources if language is not None
2019-10-10 19:39:33 +02:00
f3ba078882
xilinx/vivado: replace "xy" == language with language == "xy"
2019-10-10 19:36:17 +02:00
17756f631b
Merge pull request #277 from railnova/feature/vivado_sysverilog_support
...
[feature] Add SystemVerilog support for the Vivado builder
2019-10-10 19:31:09 +02:00
b25194826e
integration/soc_zynq: shadow_base no longer recommended (replace with io_regions)
2019-10-10 19:23:01 +02:00
496ba7e594
bios/main: use same banner than README (MiSoC cited in README/LICENSE)
2019-10-10 19:21:32 +02:00
840f01b6d5
software/bios: don't show peripherals init banner if nothing to init, add Ethernet init printf
2019-10-10 19:18:28 +02:00
f2369a4c9e
Add system Verilog support for the Vivado builder
2019-10-10 14:10:28 +02:00
f8f643a02f
cpu/rocket: swap main_mem and io regions
...
The total size of RAM (main_mem) can be expected to vary significantly,
and often exceed the size needed for MMIO allocations by a large margin.
As such, place Rocket's MMIO (io regions) below 0x8000_0000, and start
the RAM (main_mem) at 0x8000_0000, with nothing above it to limit its
future growth.
Also, bump the pre-built Rocket verilog submodule to an updated version,
which also comes with matching changes to the way MMIO and RAM accesses
are mapped and routed to their respective AXI interfaces.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-10-09 14:25:41 -04:00
b627a8fe71
cpu: add default io_regions to CPUNone (all address range can be used as IO)
2019-10-09 12:06:21 +02:00
a6b3aa3c62
soc_core: improve check_io_region error message
2019-10-09 10:47:19 +02:00
dc656d48c2
targets/sim: switch from shadow_base to io_regions
2019-10-09 10:38:22 +02:00
10146abf0a
cpu/rocket: move csr to IO region
2019-10-09 10:24:01 +02:00
7f1d4623ff
build/xilinx/vivado: fix default synth-mode
2019-10-09 10:19:18 +02:00
a4ef9b29b9
soc_core/cpu: add io_regions and deprecate shadow_base (with API retro-compat)
...
The shadow_base parameter has always been difficult to apprehend, replace it with
io_regions (uncached regions) defined user or the CPU.
The equivalent of a shadow_base parameter of 0x80000000 in the old API is:
io_regions = {0x80000000: 0x80000000} # origin, length
It's still possible to use shadow_base with retro-compat, but user is encouraged
to update and features will be removed in the future.
2019-10-09 10:15:42 +02:00
53777391e8
builder: use the SoC's existing shadow base with get_csr_header()
...
Both the SoC and get_csr_header() have independently set defaults
for the value of 'shadow_base'. If the SoC's value was modified,
ensure that get_csr_header() uses the modified value instead of
its own default.
Signed-off-by: Gabriel Somlo <somlo@cmu.edu>
2019-10-08 14:28:50 -04:00
92975b139e
targets/arty: allow setting synth-mode to yosys with command line: --synth-mode=yosys
2019-10-07 10:38:26 +02:00
4a1cefe946
build/xilinx/vivado: add vivado_build_args/vivado_build_argdict for yosys synthesis mode
2019-10-07 10:37:16 +02:00
3e22d4b9e6
xilinx/common: be sure language is not vhdl when yosys synthesis is used
2019-10-07 10:36:32 +02:00
975bd9be8b
cpu/vexriscv: use specific mem_map for linux variant
2019-10-07 08:50:03 +02:00
2dfe7441d6
Merge pull request #271 from gsomlo/gls-yosys-nowidelut
...
RFC: optional '-nowidelut' flag for yosys synth_ecp5
2019-10-06 14:55:44 +02:00
6aa76b1df8
trellis, versa_ecp5: optional '-nowidelut' flag for yosys synth_ecp5
...
Passing '-nowidelut' to yosys' synth_ecp5 command improves area utilization
to the point where a (linux variant) rocket-chip based design will fit on a
versa_ecp5 board. Usually '-nowidelut' incurs a timing penalty, but that is
then mitigated by using DSP inference (enabled by default from yosys commit
8474c5b3).
Off by default, this flag can be enabled by adding '--yosys-nowidelut=True'
to the litex/boards/targets/versa_ecp5.py command line.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-10-06 08:37:43 -04:00
2f7bd97129
fix comments
2019-10-06 10:47:28 +02:00
960b25a541
Merge pull request #270 from gsomlo/gls-csr-upper
...
soc/integration: ensure CSR constants are in uppercase
2019-10-01 21:40:56 +02:00
41ad08e8ef
soc/cores/icap: simplify ICAPBitstream (untested)
2019-10-01 21:30:14 +02:00
0c2993866c
soc/cores/icap: rename ICAP to ICAPBistream and revert old ICAP
2019-10-01 21:04:49 +02:00
4bb2827e05
Merge pull request #269 from antmicro/rework_icap
...
soc: cores: support sending custom bitstream to ICAP
2019-10-01 20:55:28 +02:00
c8790d342a
soc/integration: ensure CSR constants are in uppercase
...
Fixup over commit 8be5824e
2019-10-01 12:15:25 -04:00
4423a46ba2
soc: cores: support sending custom bitstream to ICAP
...
This adds FIFO that can be used to send any
sequence of commands to the ICAP controller.
2019-10-01 13:44:45 +02:00
427d7af767
soc/interconnect: rename stream_packet to packet & cleanup (with retro-compat)
2019-09-30 23:41:07 +02:00
59bf04d965
soc/interconnect/stream: add separators, mode Actor modules just after Endpoint
2019-09-30 23:33:25 +02:00
59995c5359
soc_zynq: update get_csr_header
2019-09-30 16:00:11 +02:00
4d90058b18
soc/integration: move cpu_interface retro-compatibility to litex/__init__
2019-09-30 11:32:07 +02:00
8be5824e25
soc/integration: use dicts for constants/mem_regions/csr_regions to cleanup/simplify iterations on theses
2019-09-30 10:59:36 +02:00
7b72148c4e
cpu: remove initial SERV support (we'll work in a branch to experiment with it)
2019-09-30 08:35:18 +02:00
63a813af9c
soc_core: fix cpu_type=None case and add test for it
2019-09-30 08:26:38 +02:00
3d257d7266
soc_sdram: remove axi usecase, this was only useful to do some preliminary axi tests.
...
Proper AXI support will be added in the future for SoCs.
2019-09-29 17:33:16 +02:00
e8e57b4f87
soc_core: cleanup/re-align
2019-09-29 17:31:37 +02:00
334ae336bf
soc/integration: rename cpu_interface to export (with retro-compat), re-arrange a bit, add separators
2019-09-29 17:23:26 +02:00
48e5a1d140
soc/cores: uniformize (continue)
2019-09-29 17:04:21 +02:00
e9ed4761b5
soc/cores/gpio: uniformize with others cores
2019-09-29 16:10:44 +02:00
78cecbe36b
soc/cores: rename frequency_meter to freqmeter and uniformize with others cores
2019-09-29 16:08:39 +02:00
7575ecc6ad
soc/cores/ecc: improve readibility, uniformize with others cores
2019-09-29 16:02:04 +02:00
c6fe3f3145
soc/cores/clocks: improve readibility
2019-09-29 15:58:22 +02:00
6fcb12a98f
soc_core: use cpu.data_width to compute csr_alignment (and remove Rocket workaround)
2019-09-29 15:47:10 +02:00
b826c1705f
soc/cores/cpus: improve ident/align, uniformize between cpus
2019-09-29 15:41:36 +02:00
355072c285
soc/cores/cpu: add CPU class and make all CPU inheritate from it
...
Also rename reserved_interrupts to interrupts (empty dict is no reserved interrupts)
2019-09-29 15:27:41 +02:00
2c3ad3f96d
soc_sdram: move ControllerInjector to LiteDRAM (LiteDRAMCore)
2019-09-29 14:44:44 +02:00
101f1b1cef
soc/integration: add common.py and move helpers from soc_core to it
2019-09-29 14:22:26 +02:00
68ba1c60be
soc_core: avoid manual listing of support CPUs, just use CPU.keys()
2019-09-28 22:19:23 +02:00
9095b80e89
soc_core: remove add_cpu_or_bridge retro-compatibility (most of the designs have been updated since the change)
2019-09-28 19:01:41 +02:00
8dd2dc1ce8
integration/soc_core: remove csr_map_update (no longer used)
2019-09-28 18:59:30 +02:00
da91aa43f7
soc_core/cpu: move memory map override to CPUs, select reset_address after eventual memory map has override been done
2019-09-28 14:15:48 +02:00
8099b0beb6
soc/cores/cpu: add set_reset_address method and use it instead of passing reset_address as a parameter
2019-09-28 12:35:41 +02:00
7660dc22e1
soc/cores/cpu: do instance in do_finalize for all cpus (allow updating parameters until the design is generated)
2019-09-28 12:09:55 +02:00
a3816096a7
cores/cpu: define CPUS and simplify instance
2019-09-28 00:55:08 +02:00
9f6a2ae73e
soc_core/serv: use UART_POLLING (no interrupt support)
2019-09-28 00:42:00 +02:00
49594ed7d4
software/libbase/uart: add polling mode
2019-09-28 00:35:26 +02:00
3f95b9c0de
add SERV CPU initial support (not working)
2019-09-28 00:34:55 +02:00
015b65fe88
targets/ulx3s: revert to cl=2
2019-09-25 14:09:44 +02:00
a9d55b04c0
boards/netv2: switch to MVP, add spiflashx4 and hdmi in/out
2019-09-25 14:07:28 +02:00
1425a68d9e
wishbone2csr: refactor using FSM, reduce latency (make it asynchronous) and set csr.adr only when access is done (allow use of CSR/CSRBase we signal)
...
Making it asynchronous does not seem to deteriorate timing or resource usage, if it's the case for some designs, we'll add a register parameter.
2019-09-24 17:55:29 +02:00
ffd2be2ba0
csr: add we signal to CSR, CSRStatus
...
Doing actions on register read is generally not a good design practice (it's
better to do separate register write to trigger actions) but in some very
specific cases being able to know that register has been read can solve cases
that are difficult to do with the recommended practives and that can justify
doing an exception.
This commit add a we signal to CSR, CSRStatus and this allow the logic to know
when the CSR, CSRStatus is read.
2019-09-24 17:51:06 +02:00
47dc332498
build/xilinx/programmer: fix vivado_cmd
2019-09-24 14:40:48 +02:00
ed9bff2eb9
soc/integration/doc: replace "== None" by "is None"
2019-09-24 10:11:31 +02:00
836d5b88c5
Merge pull request #266 from xobs/add-moduledoc-autodoc
...
Add ModuleDoc and AutoDoc
2019-09-24 10:09:22 +02:00
78fb0fb9dc
tools/litex_read_verilog: also delete yosys_v2j.ys
2019-09-24 08:49:00 +02:00
0ea7a1fd05
soc_core/sdram: Don't blow up if _wb_sdram_ifs or _csr_masters are empty
...
For example a standalone controller with no exposed CSRs (probably not
a very useful configuration but I really don't like python backtraces)
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2019-09-24 08:41:59 +02:00
68cea8c32f
timer: inherit ModuleDoc
...
With the new ModuleDoc class, we can inherit `ModuleDoc` and
automatically get module-level documentation.
This patch also corrects a typo in `timer` that causes an error in
sphinx.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-24 14:34:41 +08:00
131971986c
integration: add ModuleDoc and AutoDoc
...
It is important to be able to document modules other than CSRs.
This patch adds ModuleDoc and AutoDoc, both of which can be used
together to document modules.
ModuleDoc can be used to transform the __doc__ string of a class into a
reference-manual section. Alternately, it can be used to add additional
sections to a module.
AutoDoc is used to gather all submodule ModuleDoc objects in order to
traverse the tree of documentation.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-24 14:30:28 +08:00
742da31bc0
Merge pull request #264 from antmicro/mor1kx_linux
...
Enable to run Linux on mork1x
2019-09-23 23:19:45 +02:00
06d0806494
soc_core: set csr to 0x00000000 when there is no wishbone
2019-09-23 15:57:14 +02:00
ad8830d977
soc_sdram: Don't add the L2 Cache when there's no wishbone bus
2019-09-23 15:53:07 +02:00
5844376d53
soc_core: adapt memory map for mainline Linux with mor1kx
...
Mainline Linux expects it to be loaded at the physical address of 0x0.
Change the MAIN_RAM base address to 0x0 and update exception vector
during the booting process.
2019-09-23 15:34:52 +02:00
201218b2c3
boards/targets: increase integrated ROM size if EthernetSoC is used
...
Currently section '.rodata' of the LiteX BIOS doesn't fit in the 'rom'
region if mor1kx is used with EthernetSoC. Increase the integrated ROM
size from 0x8000 to 0x10000 in EthernetSoC.
2019-09-23 15:34:34 +02:00
ae38fd4244
soc_core: revert wishbone2csr to __init__ but add with_wishbone parameter
2019-09-23 12:59:43 +02:00
8c979565a8
soc_sdram: change l2_size checks order
2019-09-23 10:15:27 +02:00
a9acab99b3
soc_core: move CSR bridge to finalize (only generate it if there is a wishbone master), revert default parameter when cpu_type is None (we have systems with cpu_type=None but that are using these peripherals)
2019-09-23 09:58:47 +02:00
dde6dd027b
integration/builder: avoid specific _generate_standalone_includes
2019-09-23 09:26:47 +02:00
735ea196dd
This will allow it to be built for microwatt out of tree
...
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2019-09-23 08:40:54 +02:00
c28086cde8
soc_core: When cpu_type is "None", let's not generate useless UART, timer, ROMs, wishbone to CSR bridge etc...
...
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2019-09-23 08:35:50 +02:00
f909e4d706
integration/builder: When the CPU is "None", we used to not generate any code.
...
With this change, we will now generate csr.h and sdram_phy.h, which
will be needed by the initialization code running on the host CPU.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2019-09-23 08:31:21 +02:00
1a6dddd57c
spi_flash: document register fields
...
Document the various fields present in the SPI flash bitbang interface.
This adds documentation for the Single and DualQuad modules.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-20 12:42:43 +08:00
9ea11cf5ab
vivado just needs to be in the path for the programmer as well
2019-09-19 20:35:55 -07:00
60d8572c3e
csr_eventmanager: add `name` and `description` args
...
Add `name` and `description` as optional arguments to the various
EventSource types. These default to `None`, so this should be a
backwards-compatible change.
Use the same trick as CSRs, where we default the `name` to be the
instantiated object name as read from the Migen `get_obj_var_name()`
call.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-19 17:23:03 +08:00
e2c78572a2
cores/timer: add general documentation on Timer implementation and behavior.
2019-09-19 09:27:24 +02:00
e97c1e36fb
soc_sdram: improve readibility and convert l2_size to minimal allowed if provided l2_size is lower
2019-09-19 05:36:57 +02:00
99ed0877ac
csr: add description to CSRStorage/CSRStatus attributes (thanks xobs)
2019-09-18 10:47:54 +02:00
f2e84a5800
soc/cores/timer: fix typo (thanks xobs)
2019-09-18 10:45:38 +02:00
28885064f7
soc/cores/timer/doc: rewrite a little bit, avoid some redundancy, change ident.
2019-09-18 10:14:47 +02:00
cb7d941aaa
timer: add documentation
...
Now that CSRs have documentation support, add documentation to the basic
`Timer` module.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-18 15:06:20 +08:00
cca0478a5e
soc/cores/spi: use new CSRField (no functional change)
2019-09-16 17:02:55 +02:00
80b2bef387
soc/cores/bitbang: use new CSRField (no functional change)
2019-09-16 16:56:00 +02:00
9bda614a3e
csr: update copyrights
2019-09-16 08:49:00 +02:00
29134cc659
csr: more documentation
2019-09-16 08:45:29 +02:00
74e756aa30
csr/CSRStorage: remove storage_full (was only needed by alignment_bits)
2019-09-16 08:38:26 +02:00
5dc440e80d
csr: use IntEnum for CSRAccess
2019-09-16 08:36:25 +02:00
d2646f138e
csr/CSRStorage: remove alignment_bits: complexify too much code for the few use-cases it's really useful
2019-09-15 19:47:48 +02:00
8e14694eb5
csr/fields: document, add separators, 100 characters per line
2019-09-15 19:11:25 +02:00
4e84729cf9
csr/fields: add access parameter
2019-09-14 22:16:18 +02:00
23b01f8f02
csr/fields: add pulse mode support
2019-09-14 21:49:34 +02:00
8c080e5fb6
soc/interconnect/csr: add initial field support
2019-09-13 20:01:31 +02:00
c120f6d457
build/openocd: add set_qe parameter to flash
...
QE bit is not set on blank SPI flashes and need to be set when SPI X4 is enabled in the bistream to load the FPGA.
2019-09-12 17:07:56 +02:00
6a0a1c9d87
tools/litex_term/upload: bufferize only chunks of the file instead of the entire file to speedup upload when used on embedded devices (RPI for example)
2019-09-12 10:21:37 +02:00
16b6b357ca
soc/integration/cpu_interface: don't raise OSError if we are not going to compile software and compilation toolchain is not found
2019-09-11 18:30:28 +02:00
62f53d5035
soc/integration/builder: call do_exit with vns when build is done.
2019-09-10 12:41:05 +02:00
cb5f1467cf
Merge branch 'master' of http://github.com/enjoy-digital/litex
2019-09-09 15:12:24 +02:00
004c96b508
soc/itnegration: update litedram
2019-09-09 15:12:08 +02:00
2400f0f43d
fix crc32
2019-09-09 13:19:43 +02:00
19f58dd971
interconnect/wishbone: add FlipFlop to allow UpConverter to be used
...
Note: a test should be added for Converter and DownConverter/UpConverter should be cleaned up
2019-09-09 11:47:36 +02:00
bd6ec63be4
build/openocd: add stream method for JTAG UART
2019-09-06 11:57:18 +02:00
b356204f95
soc_core: add JTAG UART support (uart_name="jtag_uart)
2019-09-06 11:56:42 +02:00
d0ebbda4b3
soc/cores/jtag: add Xilinx JTAG TAPs support and simple JTAG PHY (can be used for JTAG UART)
2019-09-06 11:55:41 +02:00
2638393b53
soc_zynq: fix indent
2019-09-05 15:59:35 +02:00
9051cf97e4
soc_zynq: fix typo
2019-09-05 15:55:18 +02:00
67a09aef05
soc/interconnect/stream: add Monitor module
...
Generic module to monitor endpoints activity: tokens/overflows/underflows that
can be plugged on a endpoint. Can be useful for various purpose:
- endpoint bandwidth calculation.
- underflows/overflows detection.
- etc...
2019-09-05 11:54:14 +02:00
6f150a5626
Merge pull request #254 from mithro/crc-smaller
...
Add @xobs' smaller CRC version
2019-09-03 07:23:32 +02:00
2a41f0d2a4
Use `SMALL_CRC` to enable smaller CRC versions.
...
@xobs created a smaller code size version of the CRC functions. Enable
these if someone uses the `SMALL_CRC` define.
2019-09-02 14:48:30 -07:00
083337441a
Remove extra whitespace.
2019-09-02 14:47:20 -07:00
c0e723868e
libbase: crc16: commit smaller version of crc16
...
Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-02 14:44:18 -07:00
a59d0efca0
libbase: crc32: add smaller version
...
Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-02 14:44:18 -07:00
3ff6a18a45
Only write file if contents will change.
2019-09-02 14:26:41 -07:00
a2938a7ae7
soc/cores: simplify JTAGAtlantic (only keep alt_jtag_atlantic instance), move to jtag and allow selecting it as uart with uart_name"jtag_atlantic"
2019-08-31 18:34:08 +02:00
19d3acfc71
Merge pull request #251 from micro-FPGA/master
...
atlantic JTAG UART working module
2019-08-31 18:33:27 +02:00
fb00ee85a2
Create atlantic.py
...
atlantic JTAG uart for Intel FPGA's, working and tested on Intel C10LP EK
2019-08-30 09:35:10 +02:00
41fe7cae0b
core/spi: add minimal SPISlave
2019-08-29 09:46:20 +02:00
b845755995
gen/fhdl/verilog: allow single element verilog inline attribute
2019-08-28 05:24:11 +02:00
5a7b4c3406
targets/nexys_video: generate clk100
2019-08-27 14:06:13 +02:00
c179741cf3
software/bios: switch to standard CRLF
...
Avoid setting terminal to "implicit CR in every LF" mode.
2019-08-27 09:45:44 +02:00
0328ba7d6c
tools/litex_term: add automatic check to see if we need to insert LF or not
2019-08-26 18:17:43 +02:00
ffebd2076c
bios/tools: allow disabling CRC check on serialboot (to speedup debug/loading large images when only serial is available)
2019-08-26 17:15:01 +02:00
4842bdcf08
tools/litex_term: add sdl_payload_length
2019-08-26 12:10:11 +02:00
6d844a038a
software: use native toolchain for same host, target architectures
...
LiteX rightfully assumes that most often the target software must
be cross-compiled from an x86 host platform. However, LiteX can be
also built on a 'linux-riscv64' platform (e.g. Fedora's riscv64
port), where the software for riscv64 targets should be compiled
using the native toolchain.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-08-23 09:04:55 -04:00
92e5b4b2cd
Merge pull request #2 from enjoy-digital/master
...
update with hyperram and other changes
2019-08-16 14:36:59 +02:00
4990bf33c0
soc/core: simplify/cleanup HyperRAM core
...
- rename core to hyperbus.
- change layout (cs_n with variable length instead of cs0_n, cs1_n).
- use DifferentialOutput when differential clock is used.
- add test (python3 -m unittest test.test_hyperbus).
Usage example:
from litex.soc.cores.hyperbus import HyperRAM
self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
self.add_wb_slave(mem_decoder(self.mem_map["hyperram"]), self.hyperram.bus)
self.add_memory_region("hyperram", self.mem_map["hyperram"], 8*1024*1024)
2019-08-16 14:04:58 +02:00
f47e4978f2
libero enable enhanced constraints
...
Libero 12.0 does not support any more classic constraint flow
2019-08-16 10:31:53 +02:00
d1502d4195
soc/cores: add initial simple hyperram core
2019-08-16 09:48:17 +02:00
6e6fe83af3
build/altera/quartus: add add_ip method to use Quartus QSYS files
...
platform.add_ip("my_ip.qsys")
2019-08-15 13:45:29 +02:00
2899928aba
cpu_interface: add json csr map export, simplify csv csr map export using json
2019-08-15 09:27:33 +02:00
9d4b7cd515
bios/sdram: set init done after memtest (for standalone LiteDRAM controllers)
2019-08-14 19:09:58 +02:00
0cd4e45f48
build/xilinx/vivado: use "" for strings
2019-08-14 19:03:10 +02:00
8d161a47cf
build/xilinx/vivado: remove with_phys_opt
2019-08-14 19:02:01 +02:00
f6638ded13
Merge pull request #243 from sergachev/master
...
build/xilinx/vivado: improve directive support
2019-08-14 18:58:15 +02:00
861eea8a07
build/xilinx/vivado: improve directive support
2019-08-14 17:49:13 +02:00
db4c609a33
[fix] prevent Vivado from inferring DSP48 in AXIBurst2Beat
2019-08-14 11:30:39 +02:00
6d5fddc160
cores/spi_flash/S7SPIFlash: make cs_n optional in pads (when driven externally)
2019-08-14 07:35:45 +02:00
a5eaf172c5
more understandable error when missing a memory
2019-08-13 10:14:16 +02:00
6c298cb708
build/lattice/trellis: use abc9 techmapping pass with yosys
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-08-09 09:12:22 -04:00
31bfb54667
software/libbase/mdio: set data before clock, revert two cycle turnaround and test with different phys
2019-08-09 13:26:31 +02:00
e670cb9176
cores/cpu: add riscv-none-embed toolchain support to riscv32 cpus
2019-08-09 12:33:10 +02:00
6d94c07d70
software/libase/mdio: cleanup and reduce raw_turnaround by 1 cycle
2019-08-09 10:33:42 +02:00
0c287b11ba
cores/clock/S7PLL: fix -1/-3 speedgrade vco max freq swap
2019-08-09 09:27:32 +02:00
82cd557c24
software/bios: add Ethernet PHY MDIO read/write/dump commands
2019-08-09 09:26:41 +02:00
0ba9ab92b4
altera/common: fix AsyncResetSynchronizer polarity and simplify
2019-08-08 16:19:22 +02:00
124dff8f3f
build/xilinx/common: improve presentation
2019-08-08 16:08:55 +02:00
60873a5b73
microsemi/common: improve presentation
2019-08-08 16:06:40 +02:00
36d9d78c5e
build/altera/common: improve presentation
2019-08-08 16:02:34 +02:00
95953d2928
platforms/default_clk_period: use 1e9/freq
2019-08-07 08:36:04 +02:00
f1d8c70bd8
targets/minispartan6/crg: only keep S6PLL code
2019-08-07 08:29:59 +02:00
d3d0a6231c
cores/clock: juse use 1e9/freq instead of period_ns
2019-08-07 08:29:20 +02:00
a881817fb3
cores/clock/s6pll: add phase support
2019-08-07 08:18:54 +02:00
6b7ca0cff7
cores/clock/xilinx: change clkfbout_mult loop order to select highest vco_freq
2019-08-07 08:17:44 +02:00
1884649de1
litex_term: make sure to unconfigure console when board is unplugged
2019-08-06 08:46:25 +02:00
e052d7f645
soc/integration/builder: -x
2019-08-06 07:56:45 +02:00
236070fdcf
cores: -x on spi.py
2019-08-05 10:36:43 +02:00
a9fe2788a2
wishbone/SRAM: make read_only emited verilog code compatible with all tools
...
Quartus was not able to implement ROM correctly, see #228
2019-08-05 09:08:56 +02:00
ce5c58592b
soc/cores/uart: add FT245 FIFO mode support (sync & async)
2019-08-04 12:22:35 +02:00
a496760cb6
build/altera/quartus: use .bat on win32/cygwin
2019-08-02 10:27:38 +02:00
7e0ea07076
build/xilinx/vivado: change severity of Common 17-55 critical warning to warning
2019-08-01 21:03:05 +02:00
92d93ad221
cores/pwm: remove default CSR reset values.
2019-07-29 08:38:28 +02:00
25ca0a8b71
soc: generate git header and show migen/litex git sha1 in bios
2019-07-27 20:27:53 +02:00
fdb119cb7b
support vivado incremental implementation
2019-07-25 19:18:11 +02:00
932475a29b
cpu/vexriscv: bump submodule
2019-07-25 08:43:35 +02:00
bc7ab637dd
bios/sdram: fix compilation warning
2019-07-25 07:46:14 +02:00
1cfb36e1e4
soc_core: round memory regions size/length to next power of 2 (if not already a power of 2)
2019-07-23 20:35:28 +02:00
3e89c56468
cpu/vexriscv: bump submodule
2019-07-23 11:49:18 +02:00
e673fce445
bios/boot: fix default EMULATOR_RAM_BASE
2019-07-23 10:28:19 +02:00
0acacbaa82
cores/clock: cleanup
2019-07-23 09:54:30 +02:00
edf8aa8cfd
cores/clock: add initial iCE40 support
2019-07-23 09:27:20 +02:00
6d54335839
cores/spi_flash/add_clk_primitive: return if clk primitive is not needed
2019-07-22 21:55:07 +02:00
462d12bacc
bios/boot: define EMULATOR_RAM_BASE if not defined, add KERNEL_IMAGE_RAM_OFFSET
2019-07-22 21:54:24 +02:00
fc12961e7e
soc_core: fix cpu_variant definition
2019-07-22 12:46:39 +02:00
af61688d1d
bios/boot: fix booting rework
...
- keep emulator.bin in a specific ram (for now)
- print message when falling back to boot.bin
- print destination on tftp download (to ease debug)
2019-07-22 11:47:41 +02:00
4b686dbdb2
soc_core: fix cpu_variant config (we don't want the extension)
2019-07-22 11:44:32 +02:00
7d9cf1d2bd
Merge pull request #216 from antmicro/booting_vexriscv_linux
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Rework booting Linux on VexRiscv
2019-07-22 11:44:20 +02:00
95cfd0b9e5
cores/spi_flash: add SpiFlashCommon and use it to add clk primitives (7-Series/ECP5 support for now)
2019-07-22 10:28:03 +02:00
bfdcf4b2a0
platforms/versa_ecp5: add spiflash pads
2019-07-22 10:25:55 +02:00
41eb21b343
soc_core: optimize mem_decoder
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Non-optimized version was tested on 7-series and was additional resource usage
was not noticeable. This does not seems to be the case on iCE40 (see #220 ), so
hand optimize it. On 256MB aligned addresses, it should be equivalent to the
old decoder used by previously in LiteX.
The only requirement is that to have address aligned on size, which was already
the case. An assertion will trigger it this condition is not respected.
2019-07-22 08:53:54 +02:00
0eff65bb31
cores/up5ksram: optimize bus.adr decoding
2019-07-22 07:55:47 +02:00
bb99c4685a
cores/up5kspram: simplify and add support for all width/depth configurations
2019-07-21 19:28:31 +02:00
eaf84b8581
cores/pwm: remove clock_domain support (better to use ClockDomainsRenamer), make csr optional
2019-07-20 12:57:32 +02:00
Florent Kermarrec
Tim Ansell
Konrad Beckmann
Miodrag Milanovic
Sean Cross
Pawel Czarnecki
Gabriel Somlo
Ilia Sergachev
Vamsi K Vytla
fb@frank-buss.de
Jan Kowalewski
Martin Cornil
Benjamin Herrenschmidt
Filip Kokosinski
Antti Lukats
chmousset
Daniel Kucera
Ilia Sergachev
Mateusz Holenko