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1388 commits

Author SHA1 Message Date
Jakub Cebulski
00f973ea35 spi_flash: extend non-bitbanged flash support 
This commit adds support for memory mapped writes
in the same configuration as memory mapped reads
are currently supported.

It also adds support for accessing registers
and erasing sectors in non-bitbanged single SPI
mode.
 2020-04-28 15:02:55 +02:00
Florent Kermarrec
6d0896de1d cpu/serv: switch to pythondata package instead of local git clone. 2020-04-28 10:34:39 +02:00
enjoy-digital
4d86ab9ded
Merge pull request #399 from mithro/litex-sm2py 
Converting LiteX to use Python modules.
 2020-04-28 08:34:19 +02:00
Florent Kermarrec
5ef869b9eb soc/cpu: add memory_buses to cpus and use them in add_sdram. 
This allows the CPU to have direct buses to the memory and replace the Rocket specific code.
 2020-04-27 23:53:52 +02:00
Florent Kermarrec
467fee3e23 soc/cpu: rename cpu.buses to cpu.periph_buses. 2020-04-27 23:08:15 +02:00
enjoy-digital
317ea7edd1
Merge branch 'master' into litex-sm2py 2020-04-27 22:24:10 +02:00
Florent Kermarrec
4dece4ce24 soc/cpu: simplify integration of CPU without interrupts (and automatically use UART_POLLING mode in this case). 2020-04-27 19:06:16 +02:00
enjoy-digital
c5ef9c7356
Merge pull request #473 from fjullien/memusage 
bios: print memory usage
 2020-04-27 18:24:43 +02:00
Franck Jullien
3892d7a90a bios: print memory usage 
Print memory usage during the compilation of bios.elf.
 2020-04-27 16:33:34 +02:00
enjoy-digital
443cc72d0a
Merge pull request #476 from enjoy-digital/serv 
Add SERV support (The SErial RISC-V CPU)
 2020-04-27 13:59:28 +02:00
Florent Kermarrec
1d1a4ecd28 software/irq: cleanup and make explicit that irqs are not supported with Microwatt and SERV, fix compilation warning. 2020-04-27 13:47:13 +02:00
Florent Kermarrec
fb9e369a19 serv: connect reset. 2020-04-27 13:26:45 +02:00
Florent Kermarrec
71778ad226 serv: update copyrights (Greg Davill found the typos/issues). 2020-04-27 10:27:44 +02:00
Florent Kermarrec
1f9db583fd serv/cores: fix verilog top level (use serv_rf_top instead of serv_top), working :). 2020-04-26 21:05:47 +02:00
Florent Kermarrec
2efd939d06 serv: fix ibus/dbus byte/word addressing inconsistency, add missing ibus.sel (thanks @GregDavill). 2020-04-26 16:26:57 +02:00
Florent Kermarrec
96e7e6e89a bios/sdram: reduce number of scan loops during cdly scan to speed it up. 2020-04-25 12:51:33 +02:00
Florent Kermarrec
85a059bf77 bios/sdram: add some margin on cdly ideal_delay, do the read_leveling even if write_leveling is not optimal. 
We need to provide enough information to ease support and understand the issue. The write leveling/read leveling
are doing there best to calibrate the DRAM correctly and memtest gives the final result.
 2020-04-25 12:11:10 +02:00
Florent Kermarrec
aaed4b9475 bios/sdram: review/cleanup Command/Clock calibration, set window at the start instead of middle. 
Working on KC705 that previously required manual adjustment.
 2020-04-25 11:00:21 +02:00
enjoy-digital
33c7b2ce6b
Merge pull request #472 from antmicro/jboc/sdram-calibration 
bios/sdram: add automatic cdly calibration during write leveling
 2020-04-25 09:59:08 +02:00
Jakub Cebulski
a344e20b5e spi_flash: fix building without bitbang 2020-04-24 17:45:17 +02:00
Jędrzej Boczar
ab92e81e31 bios/sdram: add automatic cdly calibration during write leveling 2020-04-24 14:00:42 +02:00
Florent Kermarrec
22c3923644 initial SERV integration. 2020-04-23 08:18:41 +02:00
Florent Kermarrec
0b3c4b50fa soc/cores/spi: add optional aligned mode. 
In aligned mode, MOSI and MISO bits are located on the LSBs and first transmitted MOSI bit is length - 1 bit.
 2020-04-22 13:15:51 +02:00
Florent Kermarrec
6bb22dfe6b cores/spi: simplify. 2020-04-22 12:20:23 +02:00
Florent Kermarrec
c0f3710d66 bios/sdram: update/simplify with new exported LiteDRAM parameters. 2020-04-16 10:42:01 +02:00
Florent Kermarrec
c9ab593989 bios/sdram/ECP5: set ERR_DDRPHY_BITSLIP to 4. 
Bitslip software control is now used on ECP5 to move dqs_read.
 2020-04-15 19:30:28 +02:00
Mateusz Holenko
77a05b78e8 soc_core: Fix region type generation 
Include information about being a linker region.
 2020-04-14 21:45:32 +02:00
Florent Kermarrec
d44fe18bd9 stream/AsyncFIFO: add default depth (useful when used for CDC). 2020-04-14 17:35:19 +02:00
Florent Kermarrec
4fe31f0760 cores: add External Memory Interface (EMIF) Wishbone bridge. 
Useful to interface Processors/DSPs with LiteX. EMIF is generally used on Texas Instrument DSPs.
 2020-04-12 16:34:33 +02:00
Tim 'mithro' Ansell
ebcb2a4406 Rename litex-data-XXX-YYY to pythondata-XXX-YYY 2020-04-11 18:37:06 -07:00
Tim 'mithro' Ansell
e618d41ffb Fixing mor1kx data finding. 2020-04-11 18:37:06 -07:00
Tim 'mithro' Ansell
83b2581331 Fix the libcompiler_rt path. 2020-04-11 18:37:06 -07:00
Tim 'mithro' Ansell
1c1c5bcbda Remove submodules. 2020-04-11 18:37:06 -07:00
Tim 'mithro' Ansell
d5a21a7522 Converting litex to use Python modules. 2020-04-11 18:37:06 -07:00
Florent Kermarrec
79913e8614 litex.build: update from migen.genlib.io litex.build.io. 2020-04-10 09:49:45 +02:00
David Sawatzke
d69b4443b3 Add riscv64-none-elf triple 2020-04-09 05:36:10 +02:00
Florent Kermarrec
14bf8b8190 soc/cores/clock: add Max10PLL. 2020-04-08 08:54:12 +02:00
Florent Kermarrec
2470ef5096 soc/cores/clock: add Cyclone10LPPLL. 2020-04-08 08:33:57 +02:00
Florent Kermarrec
f8d6d0fda8 soc/cores/clock/CycloneVPLL: fix typos. 2020-04-08 08:25:46 +02:00
Florent Kermarrec
970c8de4c2 soc/cores/clock: rename Altera to Intel. 2020-04-08 08:16:37 +02:00
Florent Kermarrec
383fcd36d6 soc/cores/clock: add CycloneVPLL. 2020-04-07 17:24:12 +02:00
Florent Kermarrec
0f17547c5b soc/cores/clock: add initial AlteraClocking/CycloneIV support. 2020-04-07 16:59:53 +02:00
Florent Kermarrec
0f352cd648 soc/cores: use reset_less on datapath/configuration CSRStorages. 2020-04-06 13:17:14 +02:00
Florent Kermarrec
a67ab41835 interconnect/csr: add reset_less parameter. 
In cases CSRStorage can be considered as a datapath/configuration register and does not need to be reseted.
 2020-04-06 13:15:08 +02:00
Florent Kermarrec
05b1b7787b interconnect/csr, wishbone: use reset_less on datapath signals. 2020-04-06 13:11:50 +02:00
Florent Kermarrec
b95965de73 cores/code_8b10b: set reset_less to True on datapath signals. 
Reset is only required on control signals.
 2020-04-06 11:35:18 +02:00
Florent Kermarrec
a35df4f7d1 stream: set reset_less to True on datapath signals. 
Reset is only required on control signals.
 2020-04-06 11:33:49 +02:00
Florent Kermarrec
6043108376 soc/cores/clock/ECP5PLL: add CLKI_DIV support. 2020-04-03 11:14:57 +02:00
Florent Kermarrec
91981b960c soc/cores/uart: use reset_less on accumulator, reg, bitcount to reduce. 
This reduces logic a bit. It does not make large difference on usual design with
only 1 UART, but is interesting on designs with hundreds of UARTs used to "document"
FPGA boards :) (similar to https://github.com/enjoy-digital/camlink_4k/blob/master/ios_stream.py)
 2020-03-31 16:54:38 +02:00
Florent Kermarrec
87160059d3 soc/cores/spi_flash: add ECP5SPIFlash (non-memory-mapped). 2020-03-31 16:17:12 +02:00
Gabriel Somlo
8473ed567a software/bios: add spisdcardboot() to boot_sequence() 
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-03-27 15:24:09 -04:00
Gabriel Somlo
e9054ef65a software/libbase/spisdcard: add delay to goidle loop 
In `spi_sdcard_goidle()`, insert a `busy_wait()` into the CMD55+ACMD41
loop to avoid exhausting the retry counter before the card has a chance
to be ready (required on the trellisboard, also tested OK on nexys4ddr).

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-03-27 15:24:09 -04:00
Gabriel Somlo
c6b6dee2e7 software/bios: factor out busy_wait() function 
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-03-27 15:24:09 -04:00
Gabriel Somlo
540218b2d8 software/libbase/spisdcard: fix width of address parameter 
Host address parameter types should match CPU word width, so
use `unsigned long` to be correct on both 32 and 64 bit CPUs.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-03-27 15:24:09 -04:00
Florent Kermarrec
2e48ab568b soc/cores/spi: make dynamic clk divider optional (can be enabled with add_clk_divider method) and only use it in add_spi_sdcard. 2020-03-27 18:44:48 +01:00
Florent Kermarrec
73b4347587 software/libbase/spisdcard: add USE_SPISDCARD_RECLOCKING define to easily disable reclocking. 2020-03-26 07:46:32 +01:00
Florent Kermarrec
b509df8bb6 integration/soc/add_uart: add USB CDC support (with ValentyUSB core). 2020-03-25 19:07:06 +01:00
Florent Kermarrec
09a3ce0ee5 integration/soc/add_uart: add Model/Sim. 2020-03-25 18:56:58 +01:00
Florent Kermarrec
3f43c6a223 integration/soc/add_uart: cleanup. 2020-03-25 18:54:29 +01:00
Florent Kermarrec
8f2e36927d bios/boot: update comments. 2020-03-25 09:21:28 +01:00
enjoy-digital
1746b57a1b
Merge pull request #437 from feliks-montez/bugfix/fix-serialboot-frames 
flush rx buffer when bad crc and fix frame payload length
 2020-03-25 09:18:31 +01:00
Florent Kermarrec
bba5f1828b cores/clock/ECP5PLL: add phase support. 2020-03-24 19:09:05 +01:00
bunnie
5a402264d0 Fix off-by-one error on almost full condition for prefetch 
This causes a DRC error on the Xilinx tools when the prefetch
lines setting is 1. Don't know why this wasn't caught earlier,
but it just popped up in CI.
 2020-03-24 08:04:35 +01:00
Feliks
ebdc38fc91 flush rx buffer when bad crc and fix frame payload length 2020-03-23 23:04:36 -04:00
Florent Kermarrec
d62ef38c4b soc/doc/csr: allow CSRField.reset to be a Migen Constant. 2020-03-23 18:47:41 +01:00
Florent Kermarrec
4adac90d88 cpu/vexriscv/mem_map_linux: move main_ram to allow up to 1GB. 2020-03-23 15:35:33 +01:00
Florent Kermarrec
63ab2ba40c software/bios/boot/linux: move emulator.bin to main_ram and allow defining custom ram offsets. 2020-03-23 15:06:32 +01:00
Florent Kermarrec
5ad7a3b7df integration/soc: add add_etherbone method. 2020-03-21 19:54:36 +01:00
Florent Kermarrec
d6b0819e4c integration/soc/add_ethernet: add name parameter (defaults to ethmac). 2020-03-21 19:36:31 +01:00
enjoy-digital
c547b2cc29
Merge pull request #436 from rob-ng15/master 
Reclock spi sdcard access after initialisation
 2020-03-21 09:26:25 +01:00
enjoy-digital
011773af8d
Merge pull request #435 from enjoy-digital/spi_master_clk_divider 
soc/core/spi: add Clk Divider CSR (defaults to sys_clk_freq/spi_clk_f…
 2020-03-21 09:25:37 +01:00
rob-ng15
2bf31a31da
Reclock spi sdcard access after initialisation 
Depends upon https://github.com/enjoy-digital/litex/pull/435

After initialising the card, reclock the card, aiming for ~16MHz (divider is rounded up, as slower speed is safer), but a maximum of half of the processor speed.

Tested with the card being clocked to 12.5MHz on de10nano
 2020-03-21 07:37:21 +00:00
Florent Kermarrec
f03d862c06 targets: switch to add_ethernet method instead of EthernetSoC. 2020-03-20 23:46:15 +01:00
Florent Kermarrec
61c9e54a90 soc/core/spi: add Clk Divider CSR (defaults to sys_clk_freq/spi_clk_freq). 2020-03-20 19:49:42 +01:00
Florent Kermarrec
fca52d110d Merge branch 'master' of http://github.com/enjoy-digital/litex 2020-03-20 18:54:51 +01:00
rob-ng15
f3c233776e
Use <stdint.h> to provide structure sizes 2020-03-20 11:35:05 +00:00
rob-ng15
c2ebbcbf6c
Use <stdint.h> for structure sizes 2020-03-20 11:34:24 +00:00
Florent Kermarrec
ccf7363932 integration/soc: add add_spi_flash method to add SPI Flash support to the SoC. 2020-03-20 10:24:31 +01:00
Florent Kermarrec
d276036f24 integration/soc: add add_spi_sdcard method to add SPI mode SDCard support to the SoC. 2020-03-20 09:57:37 +01:00
enjoy-digital
6044570928
Merge pull request #433 from gsomlo/gls-rocket-spisdcard 
Support SPI-mode SDCard booting on Litex+Rocket (64bit) configuration
 2020-03-20 09:41:56 +01:00
Gabriel Somlo
a33916bc6b software/libbase/spisdcard: fix 4-byte FAT fields on 64-bit CPUs 
On 64-bit architectures (e.g., Rocket), 'unsigned long' means
eight (not four) bytes. Use 'unsigned int' wherever a FAT data
structure requires a four-byte field!

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-03-19 21:51:44 -04:00
Piotr Esden-Tempski
279886721b Don't let python convert lane number to float. 
While at it also:
* Don't multilane for reg >= 8 bit width.
* Only check if we should switch to multilane after finding min field width.
 2020-03-19 18:12:41 -07:00
Gabriel Somlo
1f90abea8e bios: make SPI SDCard boot configs other than linux-on-litex-vexriscv 
When NOT on linux-on-litex-vexriscv, we load 'boot.bin' to MAIN_RAM_BASE,
and jump to it.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-03-19 19:37:47 -04:00
Gabriel Somlo
c2938dc973 bios/boot.c: cosmetic: re-indent spisdcardboot() for consistency 2020-03-19 19:37:47 -04:00
Florent Kermarrec
37f25ed37a software/libbase/bios: rename spi.c/h to spisdcard.h, also rename functions. 2020-03-19 11:02:15 +01:00
Florent Kermarrec
939256340f software/bios/main: revert USDDRPHY_DEBUG (merge issue with SPI SD CARD PR). 2020-03-19 10:47:28 +01:00
enjoy-digital
8fe9e72f7b
Merge pull request #429 from rob-ng15/master 
SPI hardware bitbanging from SD CARD
 2020-03-19 10:41:09 +01:00
Gabriel Somlo
b2103f4ad8 bios/sdcard: provide sdclk_set_clk() stub for clocker-less targets 
Targets which lack an adjustable clocker will not expose the required
registers. Provide a stub sdclk_set_clk() routine for those situations.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-03-18 15:11:23 -04:00
rob-ng15
27720409ce
SPI hardware bitbanging from SD CARD 2020-03-17 09:51:11 +00:00
rob-ng15
d45dda731a
SPI hardware bitbanging from SD CARD 2020-03-17 09:50:45 +00:00
rob-ng15
50b6db6a6b
SPI hardware bitbanging from SD CARD 2020-03-17 09:50:16 +00:00
Florent Kermarrec
2c4b89639f soc/cores/clock: make sure specific clkoutn_divide_range is only used as a fallback solution. 2020-03-16 11:44:39 +01:00
Piotr Esden-Tempski
57576fa8fc Add bit more logic to decide when to switch to multilane CSR documentation. 
Now we only generate multilane bitfield documentation when the CSR has
fields, and the smallest field is less than 8bit long. As this is when
we start running into space problems with the field names.
 2020-03-13 14:48:56 -07:00
Piotr Esden-Tempski
dda7a8c5f3 Split CSR documentation diagrams with more than 8 bits into multiple lanes. 
In cases when each CSR bit has a name and we use CSR with more than 8
bits, the register diagram quickly becomes crowded and hard to read.

With this patch we split the register into multiple lanes of 8 bits
each.
 2020-03-13 14:48:23 -07:00
Florent Kermarrec
aec1bfbeb4 cores/clock: simplify Fractional Divide support on S7MMCM. 
Specific clkoutn_divide_range can now be provided by specialized XilinxClocking classes.
When provided, the specific range will be used. Floats are also now supported in the
range definition/iteration.
 2020-03-13 15:56:39 +01:00
enjoy-digital
f34593a17d
Merge pull request #421 from betrusted-io/clk0_fractional 
add fractional division options to clk0 config on PLL
 2020-03-13 14:15:24 +01:00
Florent Kermarrec
eb9f54b2bc test: add initial (minimal) test for clock abstraction modules. 
Also fix divclk_divide_range on S6DCM.
 2020-03-13 12:38:23 +01:00
Piotr Esden-Tempski
d063acb767 Updating the vendored wavedrom js files. 2020-03-12 22:35:04 -07:00
Florent Kermarrec
a27385a79c soc/intergration: rename mr_memory_x parameter to memory_x. 2020-03-12 12:20:48 +01:00
Piotr Esden-Tempski
4d02263223 Add --mr-memory-x parameter to generate memory regions memory.x file. 
This file is used by rust embedded target pacs.
 2020-03-11 18:12:18 -07:00
Florent Kermarrec
e9f0ff68ce Merge branch 'master' of http://github.com/enjoy-digital/litex 2020-03-11 12:57:29 +01:00
Florent Kermarrec
979f98ea31 software: revert LTO changes (Disable it). 
It seems LTO is not yet fully working with all configurations, so it's better
reverting the changes for now.
- cause issues with LM32 available compilers.
- seems to cause issues with min/lite variant of VexRiscv.
- seems to cause issues with some litex-buildenv configurations. (see https://github.com/enjoy-digital/litex/issues/417).
 2020-03-11 12:57:00 +01:00
Sean Cross
01b6969375
Merge pull request #422 from xobs/core-doc-fixes 
Core doc fixes
 2020-03-11 19:38:42 +08:00
enjoy-digital
4ccf62afc1
Merge pull request #423 from gsomlo/gls-ethmac-fixes 
integration/soc: add_ethernet: honor self.map["ethmac"], if present
 2020-03-11 12:33:50 +01:00
Florent Kermarrec
bb8905fa5d cores/gpio: add CSR descriptions. 2020-03-11 12:06:15 +01:00
Florent Kermarrec
4dabc5a625 cores/icap: add CSR descriptions. 2020-03-11 11:04:42 +01:00
Florent Kermarrec
77132a48b0 cores/spi: add CSR descriptions. 2020-03-11 10:58:32 +01:00
Florent Kermarrec
6d861c6e57 cores/pwm: add CSR descriptions. 2020-03-11 10:38:28 +01:00
Florent Kermarrec
cbc1f5949d cores/xadc: add CSR descriptions. 2020-03-11 10:05:14 +01:00
Gabriel Somlo
a904034811 integration/soc: add_ethernet: honor self.map["ethmac"], if present 
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-03-10 19:49:34 -04:00
Florent Kermarrec
3c0b97eec8 cores/clock/USIDELAYCTRL: use separate reset/ready counters and set cd_sys.rst internally. 
This is the behaviour that was duplicated in each target. Integrating it here
will allow simplifying the targets.
 2020-03-10 16:46:54 +01:00
Sean Cross
a2f61b4e80 soc/cores/spi_opi: documentation fixes 
The ModuleDoc-generated documentation for the spi_opi module produced
slightly invalid output due to ambiguities in how rst assigns headers.
As a result, sections from the spi_opi document would appear as full
sections.

This cleans up these errors so that it parses properly under sphinx.

Signed-off-by: Sean Cross <sean@xobs.io>
 2020-03-10 20:40:04 +08:00
Sean Cross
d2f6139dc7 soc/cores/i2s: fix rst parsing errors 
The ModuleDoc-generated documentation for the i2s module produced
slightly invalid output due to ambiguities in how rst assigns headers.
As a result, sections from the i2s document would appear as full
sections.

This cleans up these errors so that it parses properly under sphinx.

Signed-off-by: Sean Cross <sean@xobs.io>
 2020-03-10 20:37:55 +08:00
Florent Kermarrec
bcbf558b6b bios: add more Ultrascale SDRAM debug with sdram_cdly command to set clk/cmd delay. 2020-03-10 13:08:49 +01:00
bunnie
5b92bf2d57 add fractional division options to clk0 config on PLL 
S7 MMCMs allow fractional divider on clock 0. Add a fallback
to try fractional values on clock 0 if a solution can't be found.

This is necessary for e.g. generating both a 100MHz and 48MHz
clock from a 12MHz source with margin=0
 2020-03-10 18:48:30 +08:00
enjoy-digital
c4ce6da6c8
Merge pull request #419 from gsomlo/gls-ultra-sdram-fixup 
software/bios: fixup for Ultrascale SDRAM debug
 2020-03-10 11:43:23 +01:00
Florent Kermarrec
b509068790 cores/clock: add logging to visualize clkin/clkouts and computed config. 2020-03-10 11:13:16 +01:00
Florent Kermarrec
04b8a91255 integration/soc: add FPGA device and System clock to logs. 2020-03-10 11:10:23 +01:00
Gabriel Somlo
4d15e1f7f8 software/bios: fixup for Ultrascale SDRAM debug 
Keep CSR accesses independent of csr_data_width and csr_alignment.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-03-09 15:32:08 -04:00
Florent Kermarrec
ba2f31d43d integration/soc: set use_rom when cpu_reset_address is defined in a rom region. 2020-03-09 19:36:47 +01:00
Florent Kermarrec
4656b1b2ad software/common: fix LTO checks. 2020-03-09 19:08:27 +01:00
Florent Kermarrec
2a91deadcb soc/cores/clock/iCE40PLL: add SB_PLL40_PAD support. 2020-03-09 19:03:05 +01:00
Florent Kermarrec
72af1b39eb software/bios: add Ultrascale SDRAM debug functions. 2020-03-09 10:55:31 +01:00
Florent Kermarrec
b02c23391a integration/soc/SoCRegion: add size_pow2 and use this internally for checks since decoder is using rounded size to next power or 2. 2020-03-08 19:17:31 +01:00
Florent Kermarrec
e801dc0261 soc: allow creating SoC without BIOS. 
By default the behaviour is unchanged and the SoC will provide a ROM:
./arty.py

Bus Regions: (4)
rom                 : Origin: 0x00000000, Size: 0x00008000, Mode: R, Cached: True Linker: False
sram                : Origin: 0x01000000, Size: 0x00001000, Mode: RW, Cached: True Linker: False
main_ram            : Origin: 0x40000000, Size: 0x10000000, Mode: RW, Cached: True Linker: False
csr                 : Origin: 0x82000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False

The integrated rom can be disabled with:
./arty.py --integrated-rom-size=0

but the SoC builder will check for a user provided rom, and if not provided will complains:
ERROR:SoC:CPU needs rom Region to be defined as Bus or Linker Region.

When a rom is provided, the CPU will use the rom base address as cpu_reset_address.

If the user just wants the CPU to start at a specified address without providing a rom,
the cpu_reset_address parameter can be used:

./arty.py --integrated-rom-size=0 --cpu-reset-address=0x01000000

If the provided reset address is not located in any defined Region, an error will
be produced:
ERROR:SoC:CPU needs reset address 0x00000000 to be in a defined Region.

When no rom is provided, the builder will not build the BIOS.
 2020-03-06 20:05:27 +01:00
Florent Kermarrec
ecca3d801d integration/builder: rename software methods to _prepare_rom_software/_generate_rom_software/_initialize_rom_software. 2020-03-06 14:53:59 +01:00
Florent Kermarrec
69ffafd81d integration/builder: generate csr maps before compiling software. 2020-03-06 14:20:32 +01:00
Florent Kermarrec
e2dab06386 Add SVD export capability to Builder (csr_svd parameter) and targets (--csr-svd argument) and fix svd regression. 
This allows generating SVD export files during the build as we are already doing for .csv or .json.

Use with Builder:
builder = Builder(soc, csr_svd="csr.svd")

Use with target:
./arty.py --csr-svd=csr.svd
 2020-03-06 14:12:58 +01:00
Florent Kermarrec
e124aed9a2 software/common.mak: fix LTO refactoring issue. 2020-03-05 23:42:36 +01:00
Karol Gugala
da580e31fd Fix copyrights 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
 2020-03-05 17:44:10 +01:00
Florent Kermarrec
3770195048 bios/sdcard: update sdclk_mmcm_write with LiteSDCard clocker changes. 2020-03-04 18:33:08 +01:00
Florent Kermarrec
4c83c975b1 doc: align to improve readability. 2020-03-04 16:46:56 +01:00
Florent Kermarrec
4f935714de soc/doc: remove soc.get_csr_regions support. 
Now that SoC documentation is integrated in LiteX, this is no longer needed.
 2020-03-04 16:27:11 +01:00
Florent Kermarrec
6893222cf1 bios/main: rename flushl2 command to flush_l2_cache, add flush_cpu_dcache command and expose them in help. 2020-03-04 15:53:18 +01:00
Florent Kermarrec
0b923aa497 build: assume vendor tools are in the PATH and remove automatic sourcing, source and toolchain_path parameters. 
Automatic sourcing was not consistent between build backends (and only really supported by ISE/Vivado)
and had no real additional value vs the complexity needed to support it. Now just assume required vendor
tools are in the PATH.

This also removes distutils dependency.
 2020-03-04 09:13:26 +01:00
Florent Kermarrec
1d7c6943af software/common: add LTO enable flag and cleanup. 2020-03-04 08:11:21 +01:00
Florent Kermarrec
598ad692a0 Merge branch 'master' of https://github.com/enjoy-digital/litex 2020-03-02 09:31:45 +01:00
Florent Kermarrec
a67e19c660 integration/soc_core: change disable parameters to no-xxyy. 2020-03-02 09:31:32 +01:00
enjoy-digital
ddb264f3fd
Merge pull request #405 from sajattack/sifive-triple 
add riscv-sifive-elf triple
 2020-03-02 09:30:05 +01:00
Florent Kermarrec
156a85b15b integration/soc: add auto_int type and use it on all int parameters. 
Allow passing parameters as int or hex values.
 2020-03-02 09:08:30 +01:00
Florent Kermarrec
7e96c911b9 targets/nexys4ddr: use SoCCore and add_sdram to avoid use of specific SoCSDRAM. 2020-03-02 09:01:05 +01:00
Florent Kermarrec
cb0371b330 integration/soc: add ethphy CSR in target. 2020-03-02 08:42:59 +01:00
Florent Kermarrec
9735bd5bf2 integration/soc: add add_ethernet method. 2020-03-01 20:50:13 +01:00
Florent Kermarrec
1c74143a39 integration/soc: mode litedram imports to add_sdram, remove some separators. 2020-03-01 18:58:55 +01:00
Paul Sajna
68c013d13f add riscv-sifive-elf triple 2020-03-01 01:39:03 -08:00
Florent Kermarrec
59e99bfbcd soc/uart: add configurable UART FIFO depth. 2020-02-28 22:34:11 +01:00
Florent Kermarrec
9199306a65 cores/uart: cleanup 2020-02-28 22:12:05 +01:00
Florent Kermarrec
ea8563339f soc/cores/uart/UARTCrossover: reduce fifo_depth to 1. 2020-02-28 22:03:40 +01:00
Florent Kermarrec
12a7528667 interconnect/stream/SyncFIFO: allow depth down to 0. 2020-02-28 21:54:02 +01:00
Florent Kermarrec
9e31bf357e interconnect/axi: remove Record inheritance on AXIInterface/AXILiteInterface. 2020-02-28 16:33:18 +01:00
Florent Kermarrec
1e0e96f9a0 interconnect/axi: add AXI Stream definition and get_ios/connect_to_pads methods. 2020-02-28 16:25:09 +01:00
Florent Kermarrec
6be7e9c33d interconnect/axi: set default data_width/address_width to 32-bit. 2020-02-28 13:20:01 +01:00
Florent Kermarrec
a7c5dd5d3e cores/gpio: use separate TSTriple for each bit. 
This fixes per bit OE control.
 2020-02-28 09:10:28 +01:00
Florent Kermarrec
78a3223573 software/bios/sdram: allow setting CLK/CMD delay from user design and configure it before write/read leveling. 
Setting a manual delay on CLK/CMD vs DQ/DQS is required on some configuration to center the write leveling window:

Before (delay = 0 taps):
Write leveling:
m0: |11000000000000011111111111| delay: 15
m1: |00000000000000111111111111| delay: 14
m2: |11110000000000000111111111| delay: 17
m3: |11110000000000000011111111| delay: 18
m4: |11111111110000000000000111| delay: 00
m5: |11111111110000000000000111| delay: 00
m6: |11111111111000000000000001| delay: 00
m7: |11111111111000000000000011| delay: 00

After (delay = 12 taps):
Write leveling:
m0: |11111111111111000000000000| delay: 00
m1: |11111111111100000000000001| delay: 00
m2: |00011111111111110000000000| delay: 03
m3: |00011111111111110000000000| delay: 03
m4: |00000000111111111111110000| delay: 08
m5: |00000000111111111111110000| delay: 08
m6: |00000000001111111111111000| delay: 10
m7: |00000000001111111111111000| delay: 10
 2020-02-27 12:26:27 +01:00
Florent Kermarrec
935e4effd2 interconnect/axi: remove mode on AXIInterface (not used and breaking LiteDRAM tests) 2020-02-26 15:13:29 +01:00
Florent Kermarrec
d324c54eee integration/soc: -x on soc.py 2020-02-26 14:43:01 +01:00
Florent Kermarrec
ee27a9e534 soc/cores/bitbang: fix missing self.comb on miso. 2020-02-25 15:57:14 +01:00
Florent Kermarrec
e2aebb427e software: disable LTO with LM32 (not supported by old GCC versions easily available). 2020-02-25 15:32:36 +01:00
Tim 'mithro' Ansell
718a65c3c9 software: enable link time optimization (LTO) 
Co-authored-by: Pawel Czarnecki <pczarnecki@internships.antmicro.com>
 2020-02-24 16:12:21 +01:00
Xiretza
7a87d4e262
Fix ECP5PLL VCO frequency range 
See https://www.latticesemi.com/view_document?document_id=50461 ("ECP5
and ECP5-5G Family Data Sheet"), section 3.19 "sysCLOCK PLL Timing".
 2020-02-24 14:39:59 +01:00
Florent Kermarrec
0c7e0bf025 integration/soc: improve presentation of SoCLocHandler's locations. 2020-02-24 13:37:38 +01:00
Florent Kermarrec
0042a02807 interconnect/axi: remove bus_name on connect_to_pads 2020-02-24 13:24:32 +01:00
Florent Kermarrec
a3584147a5 litex_gen/axi: simplify the way the bus is exposed as ios and connected to pads. 2020-02-24 12:48:52 +01:00
Florent Kermarrec
d86db6f12b litex_gen/wishbone: simplify the way the bus is exposed as ios and connected to pads. 2020-02-24 12:48:20 +01:00
enjoy-digital
0083e0978b
Merge pull request #396 from antmicro/external-wb 
Add a script that allows to generate standalone cores
 2020-02-24 10:01:16 +01:00
Gabriel Somlo
173117ad4b Add 'volatile' qualifier to new CSR accessors 
Through their use of the MMPTR() macro, the "classic"
csr_[read|write]simple() accsessors identify the MMIO
subregister with the 'volatile' qualifier.

Adjust the new, csr_[rd|wr]_uint[8|16|32|64]() accessors
to also utilize the 'volatile' qualifier. Since accesses
are implicit (a[i], where a is an 'unsigned long *'),
change 'a' to be a 'volatile unsigned long *' instead.

No difference was noticed in opcodes generated using the
gcc9 risc-v cross-compiler on x86_64 with standard LiteX
cflags (vexriscv and rocket were tested), but since
reports exist that 'volatile' matters on some combinations
of compilers and targets, add the 'volatile' qualifier just
to be on the safe side.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com
 2020-02-21 14:10:13 -05:00
Karol Gugala
79a14001b0 axi: add to_pads method 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2020-02-21 12:22:18 +01:00
Jan Kowalewski
e0bcb57d3d wishbone: add extracting module signals to the top 2020-02-21 11:20:32 +01:00
Florent Kermarrec
53ee9a5e05 cpu/blackparrot: first cleanup pass 2020-02-20 18:50:13 +01:00
Florent Kermarrec
f3829cf081 integration/soc: set base_address on LiteDRAMWishbone2Native, fix addressing with >= 1GB SDRAMs. 2020-02-20 16:16:36 +01:00
Gabriel Somlo
d4d2b7f7c6 bios: add litesdcard test routines to boot menu 
This is a straightforward import of the sdcard initialization and
testing routines from the LiteSDCard demo example, made available
as mainline LiteX bios boot-prompt commands.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-02-19 20:16:13 -05:00
Florent Kermarrec
774a55a2aa soc_core: fix missing init on main_ram 2020-02-19 14:59:58 +01:00
enjoy-digital
5d580ca4e1
Merge pull request #389 from antmicro/linux_flash_offsets 
bios/boot: allow to customize flash offsets of Linux images
 2020-02-18 17:54:13 +01:00
Florent Kermarrec
00895518e5 cores/cpu: use standard+debug variant when only debug is specified. 2020-02-18 16:59:55 +01:00
Mateusz Holenko
659c244a0b bios/boot: allow to customize flash offsets of Linux images 2020-02-18 13:38:09 +01:00
Florent Kermarrec
ae45be4773 soc/cores/clock: add reset_cycles parameter to S7IDELAYCTRL/USIDELAYCTRL 2020-02-18 10:15:01 +01:00
Florent Kermarrec
9baa3ad5bb soc/csr_bus: fix aligned_paging computation (should be done with SoC's Bus data width not bus.alignment) 2020-02-18 09:13:32 +01:00
Florent Kermarrec
854e7cc908 integration/soc: improve Region logger 2020-02-18 08:27:59 +01:00
Florent Kermarrec
9cb8f68e82 bios/boot: update and fix flashboot, improve verbosity 2020-02-17 19:21:54 +01:00
Florent Kermarrec
6ed0f445b6 soc: increase supporteds address_width/paging 2020-02-17 08:36:40 +01:00
Florent Kermarrec
5b3808cb81 soc_core: expose CSR paging 2020-02-17 08:34:10 +01:00
Florent Kermarrec
0497f3ca71 soc/csr_bus: improve CSR paging genericity 2020-02-17 08:28:56 +01:00
Florent Kermarrec
67e8a042f8 integration/soc: add configurable CSR Paging 2020-02-16 12:32:05 +01:00
Florent Kermarrec
6576470179 soc_core: add back identifier 2020-02-15 19:04:47 +01:00
Florent Kermarrec
18a9d4ff2f interconnect/stream: cleanup imports/idents 2020-02-14 08:08:19 +01:00
Florent Kermarrec
e4712ff7f3 soc_core: fix cpu_variant renaming regression 2020-02-13 08:34:39 +01:00
Sean Cross
baa29f1b03 doc: fix regression with new irq manager 
Previously, we were accessing the `soc.soc_interrupt_map` property in
order to be able to enumerate the interrupts.  This has been subsumed
into a more general `irq` object that manages the interrupts.

Use `soc.irq.locs` instead of `soc.soc_interrupt_map` as the authority
on interrupts for both doc and export.

This fixes #385.

Signed-off-by: Sean Cross <sean@xobs.io>
 2020-02-13 08:32:44 +08:00
Florent Kermarrec
1620f9c5b0 soc/CSR: show alignment in report and add info when updating. 2020-02-12 21:55:30 +01:00
Florent Kermarrec
5b34f4cd34 soc/add_cpu: use cpu.data_width as CSR alignment, fix regression on Rocket 2020-02-12 21:25:52 +01:00
Florent Kermarrec
2f69f607e3 integration/soc: fix refactoring issues 2020-02-12 18:16:38 +01:00
Florent Kermarrec
1d6ce66bf7 soc/integration/builder: update copyright, align arguments 2020-02-12 16:43:11 +01:00
Xiretza
b56545791c
Unify output directory handling in builder 2020-02-12 15:47:16 +01:00
Florent Kermarrec
e9c665a539 soc_core/soc_sdram: add disclaimer 2020-02-11 18:28:05 +01:00
Florent Kermarrec
5558865cbf soc_core: provide full retro-compatibily when add_wb_slave is called before add_memory_region 2020-02-11 18:21:41 +01:00
Florent Kermarrec
1b5caf56fb soc: fix busword typo 2020-02-11 17:57:05 +01:00
enjoy-digital
240a55bace
Merge branch 'master' into new_soc 2020-02-11 17:22:06 +01:00
Florent Kermarrec
d5ad1d56f2 soc/integration: move mem_decoder to soc_core 2020-02-11 17:19:22 +01:00
Florent Kermarrec
0a737cb624 soc/integration/common: simplify get_version 2020-02-11 17:16:24 +01:00
Florent Kermarrec
399b65fa17 soc/add_uart: fix bridge 2020-02-11 16:55:37 +01:00
Florent Kermarrec
160c55d1d4 soc_core/soc_sdram: remove disclaimer (we'll add it later when designs will be adapted) 2020-02-11 16:44:25 +01:00
Florent Kermarrec
b2c66b1efd soc: avoid double definition of main_ram 2020-02-11 16:39:37 +01:00
Florent Kermarrec
5f9946085b soc: improve log colors on error reporting 2020-02-11 16:24:57 +01:00
Florent Kermarrec
b22d2ca02b soc: add linker regions management 2020-02-11 15:28:02 +01:00
Florent Kermarrec
abc31a92c6 soc: improve log presentation/colors 2020-02-11 14:50:16 +01:00
Florent Kermarrec
91e2797bb4 soc: fix cpu_reset_address 2020-02-11 14:17:32 +01:00
Florent Kermarrec
21d38701df soc: fix build_time format 2020-02-11 13:23:53 +01:00
Florent Kermarrec
4d761e1afd cores/cpu: remove separators on io_regions (requires python 3.6) 2020-02-11 13:12:54 +01:00
Florent Kermarrec
b43d830fda soc/add_sdram: simplify L2 Cache, use FullMemoryWE on L2 Cache by default (seems better on all devices) 2020-02-11 09:30:45 +01:00
Florent Kermarrec
ea8e745ac2 soc_core/common: move old mem_decoder to soc_core, simplify get_version 2020-02-11 08:44:23 +01:00
Xiretza
e301df7f56
Allow all memory regions to be used as IO with CPUNone 2020-02-10 19:56:36 +01:00
Florent Kermarrec
16d1972bf8 integration/common: fix mem_decoder (shadow base has been deprecated) 2020-02-10 19:40:56 +01:00
Florent Kermarrec
dd0c71d7a1 soc/SoCRegion/Decoder: pass bus to decoder and remove mask on origin 2020-02-10 19:34:18 +01:00
Florent Kermarrec
e8e4537e14 soc/add_sdram: avoid L2 cache when l2_cache_size == 0. 2020-02-10 19:02:44 +01:00
Florent Kermarrec
dcbdb73231 soc: remove unneeded \n 2020-02-10 18:38:59 +01:00
Florent Kermarrec
d320be8ecb soc: use io_regions for alloc_region 2020-02-10 18:19:35 +01:00
Florent Kermarrec
cbcd953dd7 soc_core: use add_rom 2020-02-10 17:43:29 +01:00
Florent Kermarrec
487ac3da9a soc/add_cpu: simplify CPUNone integration 2020-02-10 17:40:46 +01:00
Florent Kermarrec
f7d4648ca1 soc/SoCBusHandler: add add_adapter method and use it to convert Master/Slave before connecting to the Bus 2020-02-10 17:17:31 +01:00
Florent Kermarrec
379d47a843 soc/add_sdram: add sdram csr 2020-02-10 17:02:20 +01:00
Florent Kermarrec
3921b6345c soc/add_sdram: fix rocket, shorten comments 2020-02-10 16:55:15 +01:00
Florent Kermarrec
14b627b466 soc/add_sdram: improve API 2020-02-10 16:38:20 +01:00
Florent Kermarrec
1faefdc0fa soc: add LiteXSoC class and mode add_identifier/uart/sdram to it 2020-02-10 16:28:11 +01:00
Florent Kermarrec
11dbe19084 soc_core/sdram: cleanup, add disclaimer 2020-02-10 16:21:21 +01:00
Florent Kermarrec
5eb88cd904 soc: add add_sdram 2020-02-10 16:01:19 +01:00
Florent Kermarrec
39011593ac soc: add csr_regions, update copyright 2020-02-10 15:11:37 +01:00
Florent Kermarrec
d2b069516a soc: add cpu rom/sram check 2020-02-10 14:48:46 +01:00
Florent Kermarrec
de100fddf5 soc: add SOCIORegion and manage it 2020-02-10 14:36:53 +01:00
Florent Kermarrec
6b8c425f9b soc: reorder main components/peripherals 2020-02-10 13:07:09 +01:00
Florent Kermarrec
84b5df7871 soc: add add_cpu method 2020-02-09 21:56:32 +01:00
Florent Kermarrec
7ee9ce38a7 .gitmodules/black-parrot: switch to https://github.com/enjoy-digital/black-parrot (without the submodules) 2020-02-09 19:53:04 +01:00
Florent Kermarrec
b676a559fd soc: fix unit-tests 2020-02-09 19:01:03 +01:00
Florent Kermarrec
0a5883901a soc: integrate constants/build 2020-02-08 22:08:37 +01:00
Florent Kermarrec
014d5a56a8 soc: show sorted regions (by origin) / locs 2020-02-08 21:34:26 +01:00
Florent Kermarrec
c69b6b7c12 soc: simplify color theme 2020-02-08 21:30:34 +01:00
enjoy-digital
1dced8183e
Merge pull request #278 from scanakci/blackparrot_litex 
Blackparrot litex
 2020-02-08 10:30:55 +01:00
Florent Kermarrec
3cb90297ac soc: add add_uart method 2020-02-08 10:19:18 +01:00
Florent Kermarrec
e5cacb8bbd soc_core: cleanup imports 2020-02-07 23:16:29 +01:00
Florent Kermarrec
33d498b826 soc_core: get_csr_address no longer used 2020-02-07 23:11:08 +01:00
Florent Kermarrec
1feff1d7d5 soc: integrate CSR master/interconnect/collection and IRQ collection 2020-02-07 19:50:35 +01:00
Florent Kermarrec
3ba7c29ed9 soc: add add_constant/add_config methods 2020-02-07 19:09:54 +01:00
Florent Kermarrec
29bbe4c02a soc: add add_csr_bridge method 2020-02-07 18:49:20 +01:00
Florent Kermarrec
b84c291c34 soc: add add_controller/add_identifier/add_timer methods 2020-02-07 18:31:50 +01:00
Florent Kermarrec
9445c33e9d soc: add add_ram/add_rom methods 2020-02-07 16:06:32 +01:00
Florent Kermarrec
e5a8ac1dab soc: add automatic bus data width convertion to add_master/add_slave 2020-02-07 15:31:59 +01:00
Florent Kermarrec
8f67f1157d soc/soc_core: cleanup, remove some unused attributes 2020-02-07 15:19:02 +01:00
Florent Kermarrec
2c6e5066a7 soc: move SoCController from soc_core to soc 2020-02-07 14:52:53 +01:00
Florent Kermarrec
848fa20d1e soc: create SoCLocHandler and use it to simplify SoCCSRHandler and SoCIRQHandler 2020-02-07 13:25:54 +01:00
Florent Kermarrec
39458c92eb soc: add use_loc_if_exists on SoCIRQ.add to use current location is already defined 2020-02-06 19:50:44 +01:00
Florent Kermarrec
1eff0799a4 soc: add use_loc_if_exists on SoCCSR.add to use current location is already defined 2020-02-06 18:50:17 +01:00
Florent Kermarrec
8bc420679a soc/integration: initial adaptation to new SoC class 2020-02-06 18:21:13 +01:00