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Author SHA1 Message Date
Piotr Esden-Tempski
57576fa8fc Add bit more logic to decide when to switch to multilane CSR documentation. 
Now we only generate multilane bitfield documentation when the CSR has
fields, and the smallest field is less than 8bit long. As this is when
we start running into space problems with the field names.
 2020-03-13 14:48:56 -07:00
Piotr Esden-Tempski
dda7a8c5f3 Split CSR documentation diagrams with more than 8 bits into multiple lanes. 
In cases when each CSR bit has a name and we use CSR with more than 8
bits, the register diagram quickly becomes crowded and hard to read.

With this patch we split the register into multiple lanes of 8 bits
each.
 2020-03-13 14:48:23 -07:00
Florent Kermarrec
aec1bfbeb4 cores/clock: simplify Fractional Divide support on S7MMCM. 
Specific clkoutn_divide_range can now be provided by specialized XilinxClocking classes.
When provided, the specific range will be used. Floats are also now supported in the
range definition/iteration.
 2020-03-13 15:56:39 +01:00
enjoy-digital
f34593a17d
Merge pull request #421 from betrusted-io/clk0_fractional 
add fractional division options to clk0 config on PLL
 2020-03-13 14:15:24 +01:00
Florent Kermarrec
eb9f54b2bc test: add initial (minimal) test for clock abstraction modules. 
Also fix divclk_divide_range on S6DCM.
 2020-03-13 12:38:23 +01:00
Florent Kermarrec
c304c4db27 targets/icebreaker: add description of the board, link to crowdsupply campagin and to the more complete example. 2020-03-13 09:37:42 +01:00
Piotr Esden-Tempski
d063acb767 Updating the vendored wavedrom js files. 2020-03-12 22:35:04 -07:00
Florent Kermarrec
a27385a79c soc/intergration: rename mr_memory_x parameter to memory_x. 2020-03-12 12:20:48 +01:00
Piotr Esden-Tempski
4d02263223 Add --mr-memory-x parameter to generate memory regions memory.x file. 
This file is used by rust embedded target pacs.
 2020-03-11 18:12:18 -07:00
Florent Kermarrec
e9f0ff68ce Merge branch 'master' of http://github.com/enjoy-digital/litex 2020-03-11 12:57:29 +01:00
Florent Kermarrec
979f98ea31 software: revert LTO changes (Disable it). 
It seems LTO is not yet fully working with all configurations, so it's better
reverting the changes for now.
- cause issues with LM32 available compilers.
- seems to cause issues with min/lite variant of VexRiscv.
- seems to cause issues with some litex-buildenv configurations. (see https://github.com/enjoy-digital/litex/issues/417).
 2020-03-11 12:57:00 +01:00
Sean Cross
01b6969375
Merge pull request #422 from xobs/core-doc-fixes 
Core doc fixes
 2020-03-11 19:38:42 +08:00
enjoy-digital
4ccf62afc1
Merge pull request #423 from gsomlo/gls-ethmac-fixes 
integration/soc: add_ethernet: honor self.map["ethmac"], if present
 2020-03-11 12:33:50 +01:00
Florent Kermarrec
bb8905fa5d cores/gpio: add CSR descriptions. 2020-03-11 12:06:15 +01:00
Florent Kermarrec
4dabc5a625 cores/icap: add CSR descriptions. 2020-03-11 11:04:42 +01:00
Florent Kermarrec
77132a48b0 cores/spi: add CSR descriptions. 2020-03-11 10:58:32 +01:00
Florent Kermarrec
6d861c6e57 cores/pwm: add CSR descriptions. 2020-03-11 10:38:28 +01:00
Florent Kermarrec
cbc1f5949d cores/xadc: add CSR descriptions. 2020-03-11 10:05:14 +01:00
Gabriel Somlo
a904034811 integration/soc: add_ethernet: honor self.map["ethmac"], if present 
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-03-10 19:49:34 -04:00
Florent Kermarrec
846a2720b7 targets/kcu105: move cd_pll4x. 2020-03-10 17:02:28 +01:00
Florent Kermarrec
c97fabb285 targets/kcu105: simplify CRG using USIDELAYCTRL. 2020-03-10 16:48:07 +01:00
Florent Kermarrec
3c0b97eec8 cores/clock/USIDELAYCTRL: use separate reset/ready counters and set cd_sys.rst internally. 
This is the behaviour that was duplicated in each target. Integrating it here
will allow simplifying the targets.
 2020-03-10 16:46:54 +01:00
Sean Cross
a2f61b4e80 soc/cores/spi_opi: documentation fixes 
The ModuleDoc-generated documentation for the spi_opi module produced
slightly invalid output due to ambiguities in how rst assigns headers.
As a result, sections from the spi_opi document would appear as full
sections.

This cleans up these errors so that it parses properly under sphinx.

Signed-off-by: Sean Cross <sean@xobs.io>
 2020-03-10 20:40:04 +08:00
Sean Cross
d2f6139dc7 soc/cores/i2s: fix rst parsing errors 
The ModuleDoc-generated documentation for the i2s module produced
slightly invalid output due to ambiguities in how rst assigns headers.
As a result, sections from the i2s document would appear as full
sections.

This cleans up these errors so that it parses properly under sphinx.

Signed-off-by: Sean Cross <sean@xobs.io>
 2020-03-10 20:37:55 +08:00
Florent Kermarrec
bcbf558b6b bios: add more Ultrascale SDRAM debug with sdram_cdly command to set clk/cmd delay. 2020-03-10 13:08:49 +01:00
bunnie
5b92bf2d57 add fractional division options to clk0 config on PLL 
S7 MMCMs allow fractional divider on clock 0. Add a fallback
to try fractional values on clock 0 if a solution can't be found.

This is necessary for e.g. generating both a 100MHz and 48MHz
clock from a 12MHz source with margin=0
 2020-03-10 18:48:30 +08:00
enjoy-digital
c4ce6da6c8
Merge pull request #419 from gsomlo/gls-ultra-sdram-fixup 
software/bios: fixup for Ultrascale SDRAM debug
 2020-03-10 11:43:23 +01:00
Florent Kermarrec
b509068790 cores/clock: add logging to visualize clkin/clkouts and computed config. 2020-03-10 11:13:16 +01:00
Florent Kermarrec
04b8a91255 integration/soc: add FPGA device and System clock to logs. 2020-03-10 11:10:23 +01:00
Florent Kermarrec
02cba41d64 targets/icebreaker: create CRG after SoC. 2020-03-10 11:09:56 +01:00
Gabriel Somlo
4d15e1f7f8 software/bios: fixup for Ultrascale SDRAM debug 
Keep CSR accesses independent of csr_data_width and csr_alignment.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-03-09 15:32:08 -04:00
Florent Kermarrec
ba2f31d43d integration/soc: set use_rom when cpu_reset_address is defined in a rom region. 2020-03-09 19:36:47 +01:00
Florent Kermarrec
8808c884c5 boards/platforms/icebreaker: cleanup a bit. 2020-03-09 19:16:02 +01:00
Florent Kermarrec
4656b1b2ad software/common: fix LTO checks. 2020-03-09 19:08:27 +01:00
Florent Kermarrec
2a91deadcb soc/cores/clock/iCE40PLL: add SB_PLL40_PAD support. 2020-03-09 19:03:05 +01:00
Florent Kermarrec
38d7f8a6e6 build/lattice/icestorm: add timingstrict parameter and default to False. (similar behavior than others backends) 2020-03-09 19:02:23 +01:00
Florent Kermarrec
1e9aa64387 targets/icebreaker: simplify, use standard VexRiscv, add iCE40PLL and run BIOS from SPI Flash. 2020-03-09 19:01:16 +01:00
Florent Kermarrec
197bdcb026 lattice/icestorm: enable DSP inference with Yosys and avoid setting SPI Flash in deep sleep mode after configuration which prevent running ROM CPU code from SPI Flash. 2020-03-09 16:51:18 +01:00
Florent Kermarrec
37869e38b8 boards: add initial icebreaker platform/target from litex-boards. 2020-03-09 11:56:55 +01:00
Florent Kermarrec
72af1b39eb software/bios: add Ultrascale SDRAM debug functions. 2020-03-09 10:55:31 +01:00
Florent Kermarrec
6480d1803e boards/platforms/kcu105: avoid unnecessary {{}} on INTERNAL_VREF. 2020-03-09 09:37:31 +01:00
Florent Kermarrec
b02c23391a integration/soc/SoCRegion: add size_pow2 and use this internally for checks since decoder is using rounded size to next power or 2. 2020-03-08 19:17:31 +01:00
Florent Kermarrec
e801dc0261 soc: allow creating SoC without BIOS. 
By default the behaviour is unchanged and the SoC will provide a ROM:
./arty.py

Bus Regions: (4)
rom                 : Origin: 0x00000000, Size: 0x00008000, Mode: R, Cached: True Linker: False
sram                : Origin: 0x01000000, Size: 0x00001000, Mode: RW, Cached: True Linker: False
main_ram            : Origin: 0x40000000, Size: 0x10000000, Mode: RW, Cached: True Linker: False
csr                 : Origin: 0x82000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False

The integrated rom can be disabled with:
./arty.py --integrated-rom-size=0

but the SoC builder will check for a user provided rom, and if not provided will complains:
ERROR:SoC:CPU needs rom Region to be defined as Bus or Linker Region.

When a rom is provided, the CPU will use the rom base address as cpu_reset_address.

If the user just wants the CPU to start at a specified address without providing a rom,
the cpu_reset_address parameter can be used:

./arty.py --integrated-rom-size=0 --cpu-reset-address=0x01000000

If the provided reset address is not located in any defined Region, an error will
be produced:
ERROR:SoC:CPU needs reset address 0x00000000 to be in a defined Region.

When no rom is provided, the builder will not build the BIOS.
 2020-03-06 20:05:27 +01:00
Florent Kermarrec
ecca3d801d integration/builder: rename software methods to _prepare_rom_software/_generate_rom_software/_initialize_rom_software. 2020-03-06 14:53:59 +01:00
Florent Kermarrec
69ffafd81d integration/builder: generate csr maps before compiling software. 2020-03-06 14:20:32 +01:00
Florent Kermarrec
e2dab06386 Add SVD export capability to Builder (csr_svd parameter) and targets (--csr-svd argument) and fix svd regression. 
This allows generating SVD export files during the build as we are already doing for .csv or .json.

Use with Builder:
builder = Builder(soc, csr_svd="csr.svd")

Use with target:
./arty.py --csr-svd=csr.svd
 2020-03-06 14:12:58 +01:00
Florent Kermarrec
e124aed9a2 software/common.mak: fix LTO refactoring issue. 2020-03-05 23:42:36 +01:00
Karol Gugala
da580e31fd Fix copyrights 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
 2020-03-05 17:44:10 +01:00
Gabriel Somlo
020bef4197 targets/nexys4ddr: fix sdcard clocker initialization 2020-03-05 09:02:29 -05:00
enjoy-digital
9249fc90cf
Merge pull request #410 from antmicro/netv2-edid 
platform/netv2: add proper I2C pins for HDMI IN0
 2020-03-05 11:43:02 +01:00
Piotr Binkowski
72f63243cd platform/netv2: add proper I2C pins for HDMI IN0 2020-03-05 11:27:47 +01:00
Florent Kermarrec
ad11ff39ad targets/ecp5: make sure all BaseSoC/EthernetSoc default to trellis. 2020-03-05 11:19:29 +01:00
Florent Kermarrec
3770195048 bios/sdcard: update sdclk_mmcm_write with LiteSDCard clocker changes. 2020-03-04 18:33:08 +01:00
Florent Kermarrec
4c83c975b1 doc: align to improve readability. 2020-03-04 16:46:56 +01:00
Florent Kermarrec
4f935714de soc/doc: remove soc.get_csr_regions support. 
Now that SoC documentation is integrated in LiteX, this is no longer needed.
 2020-03-04 16:27:11 +01:00
Florent Kermarrec
6893222cf1 bios/main: rename flushl2 command to flush_l2_cache, add flush_cpu_dcache command and expose them in help. 2020-03-04 15:53:18 +01:00
Florent Kermarrec
0b923aa497 build: assume vendor tools are in the PATH and remove automatic sourcing, source and toolchain_path parameters. 
Automatic sourcing was not consistent between build backends (and only really supported by ISE/Vivado)
and had no real additional value vs the complexity needed to support it. Now just assume required vendor
tools are in the PATH.

This also removes distutils dependency.
 2020-03-04 09:13:26 +01:00
Florent Kermarrec
1d7c6943af software/common: add LTO enable flag and cleanup. 2020-03-04 08:11:21 +01:00
Florent Kermarrec
b29f443fe5 litex_sim: fix with_uart parameter. 2020-03-03 19:04:18 +01:00
Florent Kermarrec
98e41e2e0d targets/nexys4ddr: add default kwargs parameters. 2020-03-02 09:44:20 +01:00
Florent Kermarrec
598ad692a0 Merge branch 'master' of https://github.com/enjoy-digital/litex 2020-03-02 09:31:45 +01:00
Florent Kermarrec
a67e19c660 integration/soc_core: change disable parameters to no-xxyy. 2020-03-02 09:31:32 +01:00
enjoy-digital
ddb264f3fd
Merge pull request #405 from sajattack/sifive-triple 
add riscv-sifive-elf triple
 2020-03-02 09:30:05 +01:00
Florent Kermarrec
156a85b15b integration/soc: add auto_int type and use it on all int parameters. 
Allow passing parameters as int or hex values.
 2020-03-02 09:08:30 +01:00
Florent Kermarrec
7e96c911b9 targets/nexys4ddr: use SoCCore and add_sdram to avoid use of specific SoCSDRAM. 2020-03-02 09:01:05 +01:00
Florent Kermarrec
cb0371b330 integration/soc: add ethphy CSR in target. 2020-03-02 08:42:59 +01:00
Florent Kermarrec
f27225c2de targets/nexys4ddr: use soc.add_ethernet method. 2020-03-01 21:21:01 +01:00
Florent Kermarrec
9735bd5bf2 integration/soc: add add_ethernet method. 2020-03-01 20:50:13 +01:00
Florent Kermarrec
1c74143a39 integration/soc: mode litedram imports to add_sdram, remove some separators. 2020-03-01 18:58:55 +01:00
Paul Sajna
68c013d13f add riscv-sifive-elf triple 2020-03-01 01:39:03 -08:00
Florent Kermarrec
59e99bfbcd soc/uart: add configurable UART FIFO depth. 2020-02-28 22:34:11 +01:00
Florent Kermarrec
9199306a65 cores/uart: cleanup 2020-02-28 22:12:05 +01:00
Florent Kermarrec
ea8563339f soc/cores/uart/UARTCrossover: reduce fifo_depth to 1. 2020-02-28 22:03:40 +01:00
Florent Kermarrec
12a7528667 interconnect/stream/SyncFIFO: allow depth down to 0. 2020-02-28 21:54:02 +01:00
Florent Kermarrec
9e31bf357e interconnect/axi: remove Record inheritance on AXIInterface/AXILiteInterface. 2020-02-28 16:33:18 +01:00
Florent Kermarrec
1e0e96f9a0 interconnect/axi: add AXI Stream definition and get_ios/connect_to_pads methods. 2020-02-28 16:25:09 +01:00
Florent Kermarrec
6be7e9c33d interconnect/axi: set default data_width/address_width to 32-bit. 2020-02-28 13:20:01 +01:00
Florent Kermarrec
8e1d528663 targets: default to trellis toolchain on all ECP5 targets (now able to build all supported targets). 2020-02-28 09:48:48 +01:00
Florent Kermarrec
a7c5dd5d3e cores/gpio: use separate TSTriple for each bit. 
This fixes per bit OE control.
 2020-02-28 09:10:28 +01:00
Florent Kermarrec
400492e234 lattice/yosys: don't use quiet operation since logs are useful and for consistency with others build backends. 2020-02-28 08:32:29 +01:00
Florent Kermarrec
c4fd6a7f2f targets/kc705: use DDRPHY_CMD_DELAY to center write leveling. 2020-02-27 13:00:35 +01:00
Florent Kermarrec
78a3223573 software/bios/sdram: allow setting CLK/CMD delay from user design and configure it before write/read leveling. 
Setting a manual delay on CLK/CMD vs DQ/DQS is required on some configuration to center the write leveling window:

Before (delay = 0 taps):
Write leveling:
m0: |11000000000000011111111111| delay: 15
m1: |00000000000000111111111111| delay: 14
m2: |11110000000000000111111111| delay: 17
m3: |11110000000000000011111111| delay: 18
m4: |11111111110000000000000111| delay: 00
m5: |11111111110000000000000111| delay: 00
m6: |11111111111000000000000001| delay: 00
m7: |11111111111000000000000011| delay: 00

After (delay = 12 taps):
Write leveling:
m0: |11111111111111000000000000| delay: 00
m1: |11111111111100000000000001| delay: 00
m2: |00011111111111110000000000| delay: 03
m3: |00011111111111110000000000| delay: 03
m4: |00000000111111111111110000| delay: 08
m5: |00000000111111111111110000| delay: 08
m6: |00000000001111111111111000| delay: 10
m7: |00000000001111111111111000| delay: 10
 2020-02-27 12:26:27 +01:00
Florent Kermarrec
eab5161d47 boards: keep in sync with LiteX-boards 2020-02-27 11:18:14 +01:00
Florent Kermarrec
935e4effd2 interconnect/axi: remove mode on AXIInterface (not used and breaking LiteDRAM tests) 2020-02-26 15:13:29 +01:00
Florent Kermarrec
d324c54eee integration/soc: -x on soc.py 2020-02-26 14:43:01 +01:00
Florent Kermarrec
ee27a9e534 soc/cores/bitbang: fix missing self.comb on miso. 2020-02-25 15:57:14 +01:00
enjoy-digital
a2d6986910
Merge pull request #402 from antmicro/litex-gen-fix-uart-pins 
tools: litex_gen: fix missing UART pins
 2020-02-25 15:53:13 +01:00
Florent Kermarrec
e2aebb427e software: disable LTO with LM32 (not supported by old GCC versions easily available). 2020-02-25 15:32:36 +01:00
Jan Kowalewski
75b000a32f tools: litex_gen: fix missing UART pins 2020-02-25 14:24:29 +01:00
Tim 'mithro' Ansell
718a65c3c9 software: enable link time optimization (LTO) 
Co-authored-by: Pawel Czarnecki <pczarnecki@internships.antmicro.com>
 2020-02-24 16:12:21 +01:00
Xiretza
7a87d4e262
Fix ECP5PLL VCO frequency range 
See https://www.latticesemi.com/view_document?document_id=50461 ("ECP5
and ECP5-5G Family Data Sheet"), section 3.19 "sysCLOCK PLL Timing".
 2020-02-24 14:39:59 +01:00
Florent Kermarrec
0c7e0bf025 integration/soc: improve presentation of SoCLocHandler's locations. 2020-02-24 13:37:38 +01:00
Florent Kermarrec
0042a02807 interconnect/axi: remove bus_name on connect_to_pads 2020-02-24 13:24:32 +01:00
Florent Kermarrec
5aba1fe824 tools/litex_gen: add bus parameter and AXI (Lite) support. 2020-02-24 12:49:42 +01:00
Florent Kermarrec
a3584147a5 litex_gen/axi: simplify the way the bus is exposed as ios and connected to pads. 2020-02-24 12:48:52 +01:00
Florent Kermarrec
d86db6f12b litex_gen/wishbone: simplify the way the bus is exposed as ios and connected to pads. 2020-02-24 12:48:20 +01:00
Florent Kermarrec
18c57a64a3 tools: rename litex_extract to litex_gen (use similar name than litedram/liteeth generators) and cleanup/simplify. 2020-02-24 10:25:18 +01:00
enjoy-digital
0083e0978b
Merge pull request #396 from antmicro/external-wb 
Add a script that allows to generate standalone cores
 2020-02-24 10:01:16 +01:00
Gabriel Somlo
173117ad4b Add 'volatile' qualifier to new CSR accessors 
Through their use of the MMPTR() macro, the "classic"
csr_[read|write]simple() accsessors identify the MMIO
subregister with the 'volatile' qualifier.

Adjust the new, csr_[rd|wr]_uint[8|16|32|64]() accessors
to also utilize the 'volatile' qualifier. Since accesses
are implicit (a[i], where a is an 'unsigned long *'),
change 'a' to be a 'volatile unsigned long *' instead.

No difference was noticed in opcodes generated using the
gcc9 risc-v cross-compiler on x86_64 with standard LiteX
cflags (vexriscv and rocket were tested), but since
reports exist that 'volatile' matters on some combinations
of compilers and targets, add the 'volatile' qualifier just
to be on the safe side.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com
 2020-02-21 14:10:13 -05:00
Piotr Binkowski
9e2aede8a8 tools: add script for extracting wishbone cores 2020-02-21 16:33:26 +01:00
Karol Gugala
79a14001b0 axi: add to_pads method 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2020-02-21 12:22:18 +01:00
Jan Kowalewski
e0bcb57d3d wishbone: add extracting module signals to the top 2020-02-21 11:20:32 +01:00
Florent Kermarrec
53ee9a5e05 cpu/blackparrot: first cleanup pass 2020-02-20 18:50:13 +01:00
Florent Kermarrec
f3829cf081 integration/soc: set base_address on LiteDRAMWishbone2Native, fix addressing with >= 1GB SDRAMs. 2020-02-20 16:16:36 +01:00
Florent Kermarrec
3a6f97fff3 build/sim: add Verilator FST tracing support. 2020-02-20 13:53:31 +01:00
Gabriel Somlo
516cf40506 targets/nexys4ddr: add optional sdcard support 
Add the option to select LiteSDCard support in BaseSoC, via the
'--with-sdcard' command line argument.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-02-19 20:16:13 -05:00
Gabriel Somlo
d4d2b7f7c6 bios: add litesdcard test routines to boot menu 
This is a straightforward import of the sdcard initialization and
testing routines from the LiteSDCard demo example, made available
as mainline LiteX bios boot-prompt commands.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-02-19 20:16:13 -05:00
Gabriel Somlo
7a2e33b817 targets/nexys4ddr: add ethernet via method instead of inheritance 
Switch adding LiteETH support to BaseSoc via a method instead of
inheritance. This allows further optional peripherals to be added
in the future, via additional methods.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-02-19 20:16:13 -05:00
Florent Kermarrec
774a55a2aa soc_core: fix missing init on main_ram 2020-02-19 14:59:58 +01:00
enjoy-digital
5d580ca4e1
Merge pull request #389 from antmicro/linux_flash_offsets 
bios/boot: allow to customize flash offsets of Linux images
 2020-02-18 17:54:13 +01:00
Florent Kermarrec
00895518e5 cores/cpu: use standard+debug variant when only debug is specified. 2020-02-18 16:59:55 +01:00
Mateusz Holenko
659c244a0b bios/boot: allow to customize flash offsets of Linux images 2020-02-18 13:38:09 +01:00
Florent Kermarrec
ae45be4773 soc/cores/clock: add reset_cycles parameter to S7IDELAYCTRL/USIDELAYCTRL 2020-02-18 10:15:01 +01:00
Florent Kermarrec
9baa3ad5bb soc/csr_bus: fix aligned_paging computation (should be done with SoC's Bus data width not bus.alignment) 2020-02-18 09:13:32 +01:00
Florent Kermarrec
854e7cc908 integration/soc: improve Region logger 2020-02-18 08:27:59 +01:00
Florent Kermarrec
9cb8f68e82 bios/boot: update and fix flashboot, improve verbosity 2020-02-17 19:21:54 +01:00
Florent Kermarrec
6ed0f445b6 soc: increase supporteds address_width/paging 2020-02-17 08:36:40 +01:00
Florent Kermarrec
5b3808cb81 soc_core: expose CSR paging 2020-02-17 08:34:10 +01:00
Florent Kermarrec
0497f3ca71 soc/csr_bus: improve CSR paging genericity 2020-02-17 08:28:56 +01:00
Florent Kermarrec
351896bf57 tools/litex_sim: use new sdram verbosity parameter 2020-02-16 16:09:06 +01:00
Florent Kermarrec
67e8a042f8 integration/soc: add configurable CSR Paging 2020-02-16 12:32:05 +01:00
Florent Kermarrec
6576470179 soc_core: add back identifier 2020-02-15 19:04:47 +01:00
enjoy-digital
8f6114d0cd
Merge pull request #387 from BracketMaster/master 
litex_sim now working on MacOS and Linux
 2020-02-15 17:05:50 +01:00
Yehowshua Immanuel
3da204edd6 update to work with mac 2020-02-15 10:37:39 -05:00
Florent Kermarrec
3574b90924 tools/litex_sim: specify default local/remote-ip addresses. 2020-02-15 14:04:44 +01:00
Florent Kermarrec
aebaea7764 tools/litex_sim: add ethernet local/remote-ip arguments. 2020-02-15 14:01:56 +01:00
Florent Kermarrec
18a9d4ff2f interconnect/stream: cleanup imports/idents 2020-02-14 08:08:19 +01:00
Piotr Binkowski
eff85a99bb tools/litex_sim: add cli options to control SDRAM timing checker 2020-02-13 14:45:15 +01:00
Florent Kermarrec
e4712ff7f3 soc_core: fix cpu_variant renaming regression 2020-02-13 08:34:39 +01:00
Sean Cross
baa29f1b03 doc: fix regression with new irq manager 
Previously, we were accessing the `soc.soc_interrupt_map` property in
order to be able to enumerate the interrupts.  This has been subsumed
into a more general `irq` object that manages the interrupts.

Use `soc.irq.locs` instead of `soc.soc_interrupt_map` as the authority
on interrupts for both doc and export.

This fixes #385.

Signed-off-by: Sean Cross <sean@xobs.io>
 2020-02-13 08:32:44 +08:00
Florent Kermarrec
1620f9c5b0 soc/CSR: show alignment in report and add info when updating. 2020-02-12 21:55:30 +01:00
Florent Kermarrec
5b34f4cd34 soc/add_cpu: use cpu.data_width as CSR alignment, fix regression on Rocket 2020-02-12 21:25:52 +01:00
Florent Kermarrec
2f69f607e3 integration/soc: fix refactoring issues 2020-02-12 18:16:38 +01:00
Florent Kermarrec
1d6ce66bf7 soc/integration/builder: update copyright, align arguments 2020-02-12 16:43:11 +01:00
Xiretza
b56545791c
Unify output directory handling in builder 2020-02-12 15:47:16 +01:00
Florent Kermarrec
e9c665a539 soc_core/soc_sdram: add disclaimer 2020-02-11 18:28:05 +01:00
Florent Kermarrec
5558865cbf soc_core: provide full retro-compatibily when add_wb_slave is called before add_memory_region 2020-02-11 18:21:41 +01:00
Florent Kermarrec
1b5caf56fb soc: fix busword typo 2020-02-11 17:57:05 +01:00
Florent Kermarrec
8b5cc34553 targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC) 2020-02-11 17:44:24 +01:00
enjoy-digital
240a55bace
Merge branch 'master' into new_soc 2020-02-11 17:22:06 +01:00
Florent Kermarrec
d5ad1d56f2 soc/integration: move mem_decoder to soc_core 2020-02-11 17:19:22 +01:00
Florent Kermarrec
0a737cb624 soc/integration/common: simplify get_version 2020-02-11 17:16:24 +01:00
Florent Kermarrec
399b65fa17 soc/add_uart: fix bridge 2020-02-11 16:55:37 +01:00
Florent Kermarrec
160c55d1d4 soc_core/soc_sdram: remove disclaimer (we'll add it later when designs will be adapted) 2020-02-11 16:44:25 +01:00
Florent Kermarrec
b2c66b1efd soc: avoid double definition of main_ram 2020-02-11 16:39:37 +01:00
Florent Kermarrec
5f9946085b soc: improve log colors on error reporting 2020-02-11 16:24:57 +01:00
Florent Kermarrec
b22d2ca02b soc: add linker regions management 2020-02-11 15:28:02 +01:00
Florent Kermarrec
abc31a92c6 soc: improve log presentation/colors 2020-02-11 14:50:16 +01:00
Florent Kermarrec
91e2797bb4 soc: fix cpu_reset_address 2020-02-11 14:17:32 +01:00
Florent Kermarrec
0d7430fc69 tools/litex_sim_new: remove 2020-02-11 14:05:01 +01:00
Florent Kermarrec
21d38701df soc: fix build_time format 2020-02-11 13:23:53 +01:00
Florent Kermarrec
4d761e1afd cores/cpu: remove separators on io_regions (requires python 3.6) 2020-02-11 13:12:54 +01:00
Florent Kermarrec
b43d830fda soc/add_sdram: simplify L2 Cache, use FullMemoryWE on L2 Cache by default (seems better on all devices) 2020-02-11 09:30:45 +01:00
Florent Kermarrec
ea8e745ac2 soc_core/common: move old mem_decoder to soc_core, simplify get_version 2020-02-11 08:44:23 +01:00
Xiretza
e301df7f56
Allow all memory regions to be used as IO with CPUNone 2020-02-10 19:56:36 +01:00
Florent Kermarrec
16d1972bf8 integration/common: fix mem_decoder (shadow base has been deprecated) 2020-02-10 19:40:56 +01:00
Florent Kermarrec
5e11e8391f tools/litex_sim_new: switch to dynamically allocated ethmac origin 2020-02-10 19:37:53 +01:00
Florent Kermarrec
dd0c71d7a1 soc/SoCRegion/Decoder: pass bus to decoder and remove mask on origin 2020-02-10 19:34:18 +01:00
Florent Kermarrec
e8e4537e14 soc/add_sdram: avoid L2 cache when l2_cache_size == 0. 2020-02-10 19:02:44 +01:00
Florent Kermarrec
dcbdb73231 soc: remove unneeded \n 2020-02-10 18:38:59 +01:00
Florent Kermarrec
0f1811fb51 tools/litex_sim_new: use new bus/csr/irq methods 2020-02-10 18:21:41 +01:00
Florent Kermarrec
d320be8ecb soc: use io_regions for alloc_region 2020-02-10 18:19:35 +01:00
Florent Kermarrec
9ac09ddde5 tools: add litex_sim_new based on SoCCore and using add_sdram method 2020-02-10 18:00:46 +01:00
Florent Kermarrec
cbcd953dd7 soc_core: use add_rom 2020-02-10 17:43:29 +01:00
Florent Kermarrec
487ac3da9a soc/add_cpu: simplify CPUNone integration 2020-02-10 17:40:46 +01:00
Florent Kermarrec
f7d4648ca1 soc/SoCBusHandler: add add_adapter method and use it to convert Master/Slave before connecting to the Bus 2020-02-10 17:17:31 +01:00
Florent Kermarrec
379d47a843 soc/add_sdram: add sdram csr 2020-02-10 17:02:20 +01:00
Florent Kermarrec
3921b6345c soc/add_sdram: fix rocket, shorten comments 2020-02-10 16:55:15 +01:00
Florent Kermarrec
14b627b466 soc/add_sdram: improve API 2020-02-10 16:38:20 +01:00
Florent Kermarrec
1faefdc0fa soc: add LiteXSoC class and mode add_identifier/uart/sdram to it 2020-02-10 16:28:11 +01:00
Florent Kermarrec
11dbe19084 soc_core/sdram: cleanup, add disclaimer 2020-02-10 16:21:21 +01:00
Florent Kermarrec
5eb88cd904 soc: add add_sdram 2020-02-10 16:01:19 +01:00
Florent Kermarrec
39011593ac soc: add csr_regions, update copyright 2020-02-10 15:11:37 +01:00
Florent Kermarrec
d2b069516a soc: add cpu rom/sram check 2020-02-10 14:48:46 +01:00
Florent Kermarrec
de100fddf5 soc: add SOCIORegion and manage it 2020-02-10 14:36:53 +01:00
Florent Kermarrec
6b8c425f9b soc: reorder main components/peripherals 2020-02-10 13:07:09 +01:00
Florent Kermarrec
84b5df7871 soc: add add_cpu method 2020-02-09 21:56:32 +01:00
Florent Kermarrec
7ee9ce38a7 .gitmodules/black-parrot: switch to https://github.com/enjoy-digital/black-parrot (without the submodules) 2020-02-09 19:53:04 +01:00
Florent Kermarrec
b676a559fd soc: fix unit-tests 2020-02-09 19:01:03 +01:00
Florent Kermarrec
0a5883901a soc: integrate constants/build 2020-02-08 22:08:37 +01:00
Florent Kermarrec
014d5a56a8 soc: show sorted regions (by origin) / locs 2020-02-08 21:34:26 +01:00
Florent Kermarrec
c69b6b7c12 soc: simplify color theme 2020-02-08 21:30:34 +01:00
enjoy-digital
1dced8183e
Merge pull request #278 from scanakci/blackparrot_litex 
Blackparrot litex
 2020-02-08 10:30:55 +01:00
Florent Kermarrec
3cb90297ac soc: add add_uart method 2020-02-08 10:19:18 +01:00
Florent Kermarrec
e5cacb8bbd soc_core: cleanup imports 2020-02-07 23:16:29 +01:00
Florent Kermarrec
33d498b826 soc_core: get_csr_address no longer used 2020-02-07 23:11:08 +01:00
Florent Kermarrec
1feff1d7d5 soc: integrate CSR master/interconnect/collection and IRQ collection 2020-02-07 19:50:35 +01:00
Florent Kermarrec
3ba7c29ed9 soc: add add_constant/add_config methods 2020-02-07 19:09:54 +01:00
Florent Kermarrec
29bbe4c02a soc: add add_csr_bridge method 2020-02-07 18:49:20 +01:00
Florent Kermarrec
b84c291c34 soc: add add_controller/add_identifier/add_timer methods 2020-02-07 18:31:50 +01:00
Florent Kermarrec
9445c33e9d soc: add add_ram/add_rom methods 2020-02-07 16:06:32 +01:00
Florent Kermarrec
e5a8ac1dab soc: add automatic bus data width convertion to add_master/add_slave 2020-02-07 15:31:59 +01:00
Florent Kermarrec
8f67f1157d soc/soc_core: cleanup, remove some unused attributes 2020-02-07 15:19:02 +01:00
Florent Kermarrec
2c6e5066a7 soc: move SoCController from soc_core to soc 2020-02-07 14:52:53 +01:00
Florent Kermarrec
848fa20d1e soc: create SoCLocHandler and use it to simplify SoCCSRHandler and SoCIRQHandler 2020-02-07 13:25:54 +01:00
Florent Kermarrec
39458c92eb soc: add use_loc_if_exists on SoCIRQ.add to use current location is already defined 2020-02-06 19:50:44 +01:00
Florent Kermarrec
1eff0799a4 soc: add use_loc_if_exists on SoCCSR.add to use current location is already defined 2020-02-06 18:50:17 +01:00
Florent Kermarrec
8bc420679a soc/integration: initial adaptation to new SoC class 2020-02-06 18:21:13 +01:00
Florent Kermarrec
1d70ef6958 soc/cores/spi_opi: cleanup, rename to S7SPIOPI (since 7-Series specific for now) 2020-02-06 17:58:01 +01:00
Florent Kermarrec
62f3537db0 soc/cores: rename spiopi to spi_opi 2020-02-06 17:08:00 +01:00