149ed9630c
platforms/ocp_tap_timecard: Add with_multiboot parameter to enable/disable multiboot images generation.
...
Generating multiboot images is not very fast, disabling it for quick P&R iterations can be useful.
2023-10-03 19:03:42 +02:00
aa853d5a48
platforms/efinix_trion_t20_bga256_dev_kit: CON4 cleanup
2023-10-02 19:19:50 +02:00
bc6f6d869e
platforms/efinix_trion_t20_bga256_dev_kit: CON3 (LVDS RX) / CON4 (LVDS TX)
2023-10-02 18:51:53 +02:00
3d7a1dd152
analog_pocket: +x.
2023-10-02 16:20:09 +02:00
6f0cd56109
update to match zcu102 constraint spec
2023-09-28 11:11:21 +02:00
fd6aee0250
targets/sqrl_acorn: Drive pcie_clkreq_n (Thanks @myftptoyman).
2023-09-27 11:06:50 +02:00
928c1a2539
platforms/sipeed_tang_mega_138k: Fix default_clk_name/period.
2023-09-26 21:07:21 +02:00
29018a8382
Merge pull request #523 from Icenowy/tangmega138k
...
[RFC] sipeed_tang_mega_138k: new board
2023-09-26 19:12:44 +02:00
5f8ac853b1
Resolve High Density bank IOStandard error
...
This resolves the following error during `build` on Vivado 2023.1:
```ERROR: [DRC BIVB-1] Bank IO standard Support: Bank 47 has incompatible IO(s) because: The LVDS I/O standard is not supported for banks of type High Density. Move the following ports or change their properties:
clk125_p```
2023-09-25 12:50:30 +02:00
1fb317840f
platforms/ocp_tap_timecard: Add clk10 and som_led.
2023-09-22 08:33:04 +02:00
c14d66cb6b
analog_pocket: Add Serial (to fix CI) and add to board list.
2023-09-21 10:11:55 +02:00
3df677cfeb
Add initial Analog Pocket platform/target with Clk/SDRAM, able to run a simple SoC with SDRAM over JTAG-UART.
...
$ ./analog_pocket.py --uart-name=jtag_uart --build --load
$ litex_term jtag --jtag-config=openocd_usb_blaster.cfg
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2023 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Sep 21 2023 08:53:57
BIOS CRC passed (1e2b3f44)
LiteX git sha1: 7d738737
--=============== SoC ==================--
CPU: VexRiscv @ 50MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 128.0KiB
SRAM: 8.0KiB
L2: 8.0KiB
SDRAM: 64.0MiB 16-bit @ 50MT/s (CL-2 CWL-2)
MAIN-RAM: 64.0MiB
--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
Write: 0x40000000-0x40200000 2.0MiB
Read: 0x40000000-0x40200000 2.0MiB
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
Write speed: 15.6MiB/s
Read speed: 22.1MiB/s
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex>
2023-09-21 09:19:57 +02:00
531e13dcd6
prog: Remove too specific openocd_max10_blaster/2.cfg.
2023-09-21 09:17:00 +02:00
5064c65dac
targets: Switch to openocd_usb_blaster/2.cfg.
2023-09-21 09:16:24 +02:00
33d1569fb8
prog: Add generic openocd_usb_blaster/2 OpenOCD config files.
2023-09-21 09:15:30 +02:00
a0b7811c54
platforms/ti60_f225: Add n parameter to rgmii_ethernet_qse_ios to allow having multiple adapters.
2023-09-11 10:45:28 +02:00
c26f76e8cb
Fixed misplacement of platform file
2023-09-03 15:49:38 -03:00
632bab937e
Update qmtech_artix7_fgg676.py
2023-09-01 05:03:44 -03:00
d8b006568a
Update qmtech_artix7_fgg676.py
2023-09-01 04:53:07 -03:00
8b0c5b78ee
Added QMTECH RP2040 Daughterboard
...
Added new QMTECH Daughterboard with RP2040, which can be found in [AliExpress](https://www.aliexpress.com/item/1005005094654777.html ).
Documentation can be found [here](https://github.com/ChinaQMTECH/DB_FPGA_with_RP2040 )
2023-09-01 04:47:09 -03:00
b92c96b3a4
colorlight_i9plus: Cosmetic cleanups.
2023-08-30 17:22:11 +02:00
3471617878
Merge pull request #502 from chmousset/add_colorlight_i9plus
...
[init] added colorlight i9+ based on XC7A50 FPGA
2023-08-30 16:54:26 +02:00
c960e85d11
targets/efinix: Now rely in LiteX to automatically exclude Tristate IOs.
2023-08-30 09:59:23 +02:00
4bb064853d
targets/efinix: Update RGMII PHYs (IOs are now directly excluded in PHYs).
2023-08-30 08:56:20 +02:00
347b477b07
sipeed_tang_primer_20k: Fix DDR3 module, SoC reset and remove DDR3 debug code.
...
Now passing memtest with valid reported memory size:
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2023 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS CRC passed (d32a9529)
LiteX git sha1: 85dadb82
--=============== SoC ==================--
CPU: VexRiscv SMP-LINUX @ 48MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 64.0KiB
SRAM: 6.0KiB
L2: 512B
SDRAM: 128.0MiB 16-bit @ 192MT/s (CL-6 CWL-5)
MAIN-RAM: 128.0MiB
--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Read leveling:
m0, b00: |00000000| delays: -
m0, b01: |00000000| delays: -
m0, b02: |01100000| delays: 01+-00
m0, b03: |00000000| delays: -
best: m0, b02 delays: 01+-00
m1, b00: |00000000| delays: -
m1, b01: |00000000| delays: -
m1, b02: |01100000| delays: 01+-00
m1, b03: |00000000| delays: -
best: m1, b02 delays: 01+-00
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
Write: 0x40000000-0x40200000 2.0MiB
Read: 0x40000000-0x40200000 2.0MiB
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
Write speed: 11.7MiB/s
Read speed: 17.4MiB/s
2023-08-29 16:50:17 +02:00
4862d0667c
Merge pull request #515 from josuah/crosslink_nx_openocd
...
Allow use of OpenOCD for the Crosslink-NX
2023-08-28 16:35:20 +02:00
232e829b8f
Merge branch 'master' into crosslink_nx_main_ram
2023-08-28 16:34:27 +02:00
a9ecbffe8f
Merge pull request #520 from josuah/crosslink_nx_prog_flash
...
targets/lattice_crosslink_nx_evn: fix arguments in flash programming
2023-08-28 16:33:23 +02:00
2c3d77b5be
Merge branch 'master' into crosslink_nx_spi_flash
2023-08-28 16:32:37 +02:00
efb76133be
Merge pull request #519 from josuah/fix_crosslink_nx_uartbone
...
Crosslink-NX EVN: fix UARTBone always disabled
2023-08-28 16:31:29 +02:00
5799c35247
platforms/gsd_orangecrab: Set alt point to DFUProg.
2023-08-28 16:28:04 +02:00
a5a6a313cc
targets/lattice_crosslink_nx_evn: add main_ram section for firmware
...
This takes the values from the Antmicro SDI MIPI converter as a model
and is enough to run a Zephyr hello world, but not seemingly enough for
a the Zephyr Shell sample.
Related: https://github.com/litex-hub/zephyr-on-litex-vexriscv/pull/13
2023-08-18 19:56:58 +02:00
ebfb9b8e01
sipeed_tang_mega_138k: new board
...
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2023-08-15 16:33:13 +08:00
2e5c6eb7a7
platforms/crosslink_nx_evn: add SPI flash support
2023-08-11 16:46:52 +02:00
1a46bcce5e
targets/lattice_crosslink_nx_evn: fix arguments in flash programming
2023-08-10 14:39:01 +02:00
3c0b6956cc
platforms/crosslink_nx_evn: Fix 5412d0e always disabling uartbone
...
Also fix a warning about register_mem being deprecated, taking
inspiration from platforms/crosslink_nx_vip
2023-08-09 18:07:13 +02:00
8172a304b3
platforms/crosslink_nx_evn: allow use of OpenOCD
2023-08-08 23:25:41 +02:00
3903cdee92
Merge pull request #517 from bayi/master
...
Digilent CMOD A7 ISSIRAM fix
2023-08-08 19:29:32 +02:00
4362cb23a1
Fix Digilent Cmod A7 ISSIRAM reading
2023-08-05 19:56:32 +02:00
a6b025f7f3
Fix Digilent Cmod A7 ISSIRAM reading
2023-08-05 19:56:15 +02:00
5412d0e0e9
platforms/crosslink_nx_evn: allow use of UARTBone
...
This goes along a small resistor jumper modification and firmware flashing like
it is for the ECP5 board. A warning message is added as the default serial might
be affected (--serial serial by default). The FTDI modification software used
for the ECP5 seems to be requried and matching.
This can be tested this way:
targets/lattice_crosslink_nx_evn.py --csr-csv=csr.csv --toolchain=oxide --programmer=openocd --uart-name crossover+uartbone --build --load
litex_server --uart --uart-port /dev/ttyUSB1
litex_cli --regs
2023-08-04 20:47:32 +02:00
efc15a91a9
global: Use new WaitTimer integrated cast to int.
2023-08-01 14:56:35 +02:00
538399cb3b
lattice_ecp5_evn: update OpenOCD syntax
...
When running `litex_server`, this error appeared:
can't read "_CHIPNAME": no such variable
This is a fix for the specific lattice_ecp5_evn board.
It also refreshes the OpenOCD syntax.
2023-07-31 14:05:34 +02:00
cbcf6df26f
lattice_ecp5_evn: add_jtagbone flag
...
This follows https://github.com/enjoy-digital/litex/pull/1087 which
allows using the built-in JTAG for both the FPGA programming and the
internal core of the FPGA.
2023-07-31 13:53:24 +02:00
2d3b81a532
efinix_trion_t120_bga576: Add Ethernet through RGMII PMOD and switch to it.
...
See https://github.com/enjoy-digital/liteeth/issues/66#issuecomment-859366899 for the PMOD.
2023-07-27 11:52:40 +02:00
c1088befe5
targets/CRG: Add rst signal when missing.
...
Allow properly reseting the PLL from the SoC.
2023-07-26 16:56:27 +02:00
ace789653f
platforms/ti60_f225: Add connector numbering to ease review/schematic comparison.
2023-07-21 09:08:22 +02:00
ce121663ff
targets/uartbone: Update with LiteX change.
2023-07-20 15:42:47 +02:00
72a951081a
xu8_pe3: Fix clk_p/n on pcie_x8.
2023-07-13 18:10:46 +02:00
18a3909a9c
global: Switch to litex.gen.genlib.misc.
2023-07-06 22:11:45 +02:00
67be3ab677
targets: +x on alchitry_cu and vcu128.
2023-07-06 13:29:35 +02:00
e9335cd67a
Fix pins in Alchitry Cu platform, add target for Alchitry Cu
2023-06-27 21:35:55 +05:30
061a768495
Add Alchitry Cu board
2023-06-16 21:36:57 +05:30
c49a50a934
platform/gsd_butterstick: Add mssing USB comment.
2023-06-16 09:10:47 +02:00
28ecb1e9f3
enclustra_mercury_xu8_pe3: Fix pcie_x8 and add GTH banks for pcie_x4/x8.
2023-06-15 17:57:38 +02:00
06e8829eb4
platforms/gsd_butterstick: Add default programmer to avoid breaking older designs.
2023-06-14 16:40:35 +02:00
58805f037c
avnet_aesku40: Expose ethernet/etherbone parameters.
...
To be able to test more easily usrgmii build.
2023-06-13 09:26:07 +02:00
4705a0274e
Support SPI Flash in Colorlight 5A-75x
2023-06-09 13:43:34 -04:00
96175a9986
sitlinv_stlv7325_v2: Add default value to vccio.
2023-06-07 15:00:49 +02:00
765ee1a3ce
sitlinv_stlv7325_v2: VCCIO jumper default factory setting is 3.3V
2023-06-07 10:12:55 +07:00
b01abce7d5
platform/stlv7325-v2: update VCCIO to fix --with-pcie generation
2023-06-01 16:45:33 -04:00
7fc8ca9816
Merge pull request #506 from sensille/rv901t-spiflash
...
Add spiflash definition to linsn_rv901t board
2023-05-30 22:36:14 +02:00
8a263c18f2
sitlinv_stlv7325: Rename to v1 and update VCCIO to fix --with-pcie generation.
2023-05-30 10:39:20 +02:00
4a05e56058
Add spiflash definition to linsn_rv901t board
2023-05-27 16:20:32 +02:00
2ae2dfa6a3
Add vcu128 target ( #497 )
...
Add initial VCU128 support.
2023-05-25 22:25:44 +02:00
9362e589ac
Add initial Enclustra XU8/PE3 platform definition with Clk/I2C/PCIe/DDR4 and FMC connector definition.
2023-05-25 10:01:19 +02:00
e59d75f593
qmtech_xc7k325t: Fix build/CI.
2023-05-12 12:19:16 +02:00
ca6b607255
targets/qmtech: Add missing +x.
2023-05-12 12:09:20 +02:00
550bc0eee5
add QMTech XC7K325T board, add seven segment display to daughterboard
2023-05-08 11:51:51 +07:00
187080228c
add qmtech_xc7l325t
2023-05-08 05:17:35 +07:00
d33cf1a74c
mnt_rkx7: Cosmetic cleanups.
2023-05-05 09:48:06 +02:00
c05c494a82
targets/mnt_rkx7/usb_ohci: Use SoC.bus if SoC does not have a DMA bus.
2023-05-05 09:43:19 +02:00
6144966d24
Merge pull request #501 from mntmn/master
...
mnt_rkx7: RGB and USB fix, add HDMI terminal
2023-05-05 09:37:40 +02:00
9c222454cc
Merge pull request #503 from chmousset/add_colorlight_i5a-907
...
Add colorlight i5a 907
2023-05-03 09:50:26 +02:00
2bff2d4260
target/stlv7325-v2: tune eth phy delay
2023-05-01 09:28:03 -04:00
31c680abf8
[enh] added option for uartbone
2023-04-30 09:42:31 +02:00
874532871f
[enh] taking advantage of pins directly connected
2023-04-30 09:24:49 +02:00
1202c387bf
[init] added colorlight i5a-907 support
2023-04-30 09:24:46 +02:00
fd5511f3fd
[fix] add pmod uart in default config
2023-04-30 09:24:15 +02:00
f5dfdf9abf
[enh] added doc about JTAG and ext. board
2023-04-29 19:39:51 +02:00
322cc5d45b
[init] added colorlight i9+ based on XC7A50 FPGA
2023-04-29 18:36:35 +02:00
1f6e7f36a5
target/stlv7325-v2: fix typo in eth phy delay
2023-04-28 16:56:37 -04:00
1185ff51f1
Initial support for STLV7325 (v2) Kintex-7 board.
...
This is the 2nd (2023) version of the board sold through
https://www.aliexpress.us/item/3256801088848039.html
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2023-04-28 10:24:21 -04:00
a9e3e3c050
Merge branch 'master' of https://github.com/litex-hub/litex-boards
2023-04-25 20:29:11 +02:00
d160a5ad5d
mnt_rkx7: swap RGB red/blue channels
2023-04-25 20:28:16 +02:00
17a5d3c130
mnt_rkx7: add HDMI terminal, default USB to true
2023-04-25 20:27:29 +02:00
68bfb325a5
Fix Memory test failure of Alveo U250
2023-04-24 17:35:58 +09:00
9322869196
Merge pull request #495 from vietthanh85/master
...
Fix Memory initialization of Alveo U200 failed #1606
2023-04-24 08:09:25 +02:00
03913e2e15
Update terasic_de10nano.py
...
Corrected pin number
2023-04-23 22:28:00 -05:00
340da5393c
Fix Memory initialization of Alveo U200 failed #1606
2023-04-17 18:59:50 +07:00
2ed66317c7
efinix_xyloni_dev_kit: fix build error
2023-04-14 22:31:21 +10:00
b8cb2eaa47
Merge pull request #493 from hansfbaier/deca-ddr3
...
make DDR3 memory work on the DECA with the UniPHY
2023-04-11 15:27:02 +02:00
60ac45e80c
make DDR3 memory work on the DECA with the UniPHY
2023-04-11 19:59:49 +07:00
e120b77ef0
enclustra kx2/st1: fix connectors
2023-04-11 10:58:52 +07:00
c7077880b9
copyright notices on enclustra
2023-04-11 10:29:52 +07:00
ed947d1b55
enclustra: add baseboard ST1
2023-04-11 10:29:44 +07:00
be8ee26b2c
enclustra_mercury_kx2: Add ST1 baseboard, part 1
2023-04-11 05:39:11 +07:00
58679262ad
enclustra kx2: add connectors
2023-04-10 14:06:42 +07:00
a8eb0b20c1
Merge pull request #491 from hansfbaier/stlv7325-hdmi
...
STL7325: Add Video, and connectors (FMC, BTB, 2.54mm)
2023-04-07 09:06:55 +02:00
52ca60c2ac
stlv7325: fix HDMI io standard
2023-04-07 09:50:04 +07:00
2f13decc49
stlv7325: make VCCIO configurable
2023-04-07 09:27:03 +07:00
566a753dd3
stlv7325: S7PLL is enough
2023-04-07 08:45:06 +07:00
7c99f0758d
stlv7325: fix video args
2023-04-07 08:35:49 +07:00
66cbd27bbf
stlv7325: fix video PHY
2023-04-07 08:25:59 +07:00
abd639ba9e
stlv7325: add 2.54mm headers
2023-04-07 08:21:17 +07:00
3f85e4ae62
stlv7325: add BTB connectors
2023-04-07 08:09:27 +07:00
b3e44324d1
sitlinv_stlv7325: add FMC connector
2023-04-07 07:56:27 +07:00
5067a2683f
sitlinv_stlv7325: add video HDMI, enable compressed bitstream
2023-04-07 07:31:42 +07:00
43ce24dcb3
add QMTech 5CEFA5 Cyclone V board support
2023-04-06 18:27:51 +07:00
ae3d5d599b
sqrl_fk33: Remove es1 workaround now that recent version of Vivado support it non-es devices.
2023-04-04 18:11:38 +02:00
a4925d14f9
Merge pull request #488 from Icenowy/stlv7325-s7pll
...
sitlinv_stlv7325: use S7PLL instead of S7MMCM for system clock
2023-04-04 08:22:16 +02:00
1b9a74bf08
targets/nexys-video: simplify sata configuration
...
Make nexys-video SATA configuration similar to the way it is supported
on the majority of other SATA-capable targets.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2023-04-03 12:28:12 -04:00
b1107e94d4
sitlinv_stlv7325: use S7PLL instead of S7MMCM for system clock
...
As we do not need fine phase tweaking for the main system clock, use
S7PLL instead of S7MMCM to allow higher VCO frequency and more flexible
sys_clk_freq.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2023-04-03 16:45:13 +08:00
e11d40a249
Merge pull request #487 from ICE-V-Wireless/master
...
Add PMOD registrations to ICE-V Wireless
2023-04-02 11:44:02 +02:00
5de47baa44
Add PMOD registrations to ICE-V Wireless
...
Signed-off-by: Michael Welling <mwelling@ieee.org>
2023-04-02 03:31:55 -05:00
f564f80826
terasic_deca: hdmi i2s uses 1.8V, not 3.3V
2023-04-01 08:14:09 +07:00
74c8569a5c
DDR3 RAM works on 1.5V, not 1.35V
2023-03-27 15:17:42 +07:00
40c8e62b09
use bistream compression on those large devices
2023-03-21 09:25:56 +07:00
0125ae4271
Add support for QMTech Artix7 200T FBG484 board
2023-03-20 08:21:36 +07:00
98ddb97f5e
Support QMTech XC7A75T, XC7A100T core boards
2023-03-20 07:57:58 +07:00
6b8a5d35c0
sipeed_tang_nano_20k: support copackaged SDRAM
...
The copackaged SDRAM of GW2AR-18 QN88 package is 8MB size, 32bit DQ
width.
Add support for it.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2023-03-13 17:11:06 +08:00
291c43b898
sipeed_tang_nano_20k: new board
...
This board uses Gowin GW2AR series chip (which is GW2A with integrated
RAM).
Support for the integrated SDRAM on Tang Nano 20K is still TODO.
Note: currently when the SD card is enabled, block 0 could be correctly
read but block 1 will fail.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2023-03-13 16:45:25 +08:00
28a1aefc21
Update sipeed_tang_nano_9k.py
...
add pin info for _connectors
2023-03-09 17:57:39 +01:00
bf4f688164
targets/pcie: Update Xilinx S7 constraints.
2023-03-06 12:20:34 +01:00
1df46d1571
platforms/sipeed_tang_nano_9k: Review SPI RGB LCD addition.
2023-03-06 09:03:12 +01:00
8d35591f47
Update sipeed_tang_nano_9k.py
...
add SPI-Interface for the 1.14inch LCD
2023-03-04 15:25:59 +01:00
943cf2636f
platforms/sipeed_tang_primer_20k: Add checkme on leds IOstandard.
2023-03-02 12:14:04 +01:00
c9a0f5f50b
targets/sipeed_tang_primer_20: Ethernet/Etherbone working.
...
Test:
./sipeed_tang_primer_20k.py --cpu-type=serv --with-etherbone --build --load
ping 192.168.1.50
2023-03-02 12:02:58 +01:00
4a724d9d2d
targets/sipeed_tang_primer_20k/hdmi: Remove pn_swap on data lines that is no longer required.
2023-03-02 11:44:14 +01:00
9e73ba53ea
platforms/sipeed_tang_primer_20k: Update hdmi pins to official dock version and fix compilation.
...
Test:
./sipeed_tang_primer_20k.py --cpu-type=serv --with-video-terminal --build --load
Working.
2023-03-02 11:39:41 +01:00
47659835b0
platforms: Switch US/USP platforms to XilinxUS/USPPlatform.
...
We were still using Xilinx7SeriesPlatform.
2023-03-01 09:37:55 +01:00
8a6f0bd94f
opalkelly_xem8320: Review and update to recent LiteX changes.
2023-03-01 09:16:51 +01:00
e20391d366
Basic SoC for Opal Kelly XEM8320
2023-02-28 13:19:12 -07:00
f400179b5b
targets: Import all from litex.gen on all targets.
2023-02-23 09:09:33 +01:00
2eb7419678
targets/machdyne: Switch to LiteXModule for consistency with other targets.
2023-02-23 09:07:06 +01:00
33cfe59614
add pullups for kopflos ethernet
2023-02-22 08:00:58 +01:00
bd20b31a5c
add support for machdyne kopflos board
2023-02-21 11:18:22 +01:00
b1df2c0f85
Add initial support for the ICE-V wireless
...
Signed-off-by: Michael Welling <mwelling@ieee.org>
2023-02-19 00:00:07 -06:00
7b716e4899
antmicro_sdi_mipi_video_converter: Cleanup/Update to new LiteX conventions.
2023-02-16 09:02:14 +01:00
fe2be83feb
Merge pull request #473 from antmicro/crosslink-nx-zephyr
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Add support for SDI-MIPI Video Converter
2023-02-16 08:49:04 +01:00
857166e455
xilinx_alveo_u200: Add missing copyrights.
2023-02-16 08:45:34 +01:00
adf8b8c5df
Merge pull request #472 from vietthanh85/xilinx_alveo_u200
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Add support for Xilinx Alveo U200
2023-02-16 08:42:21 +01:00
31d718749a
Add copyrights
2023-02-15 12:37:33 +01:00
70f2fd6368
Fix format
2023-02-15 12:37:33 +01:00
0c774a906d
Add clk12 to platform
2023-02-15 12:37:33 +01:00
01abbc0d50
Replace deprecated register_mem with add_slave
2023-02-15 12:37:33 +01:00
934e031dca
Fix imports
2023-02-15 12:37:33 +01:00
223a69cf91
Add platform and target files for Antmicro's sdi mipi video converter board
...
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
2023-02-15 12:37:33 +01:00
ec7a5c4c0b
Correct DDR4 IO Banks of Xilinx Alveo U200
2023-02-14 06:40:12 +07:00
fdffeb8474
radiona_ulx4m_ld_v2: Do a first review/cleanup path.
2023-02-13 16:11:32 +01:00
8c9ea15d0a
Update radiona_ulx4m_ld_v2.py
2023-02-13 12:08:38 +01:00
404fefaab1
changing filename to radiona
2023-02-13 12:06:04 +01:00
99db2ae60d
Delete ulx4m_ld_v2.py
2023-02-13 11:48:51 +01:00
57c9cff39e
Update radiona_ulx4m_ld_v2.py
2023-02-13 11:45:48 +01:00
9320ae8b74
Fixing platform file
2023-02-13 11:44:59 +01:00
f7822b7dc7
Adding target to files
2023-02-13 11:40:43 +01:00
a3815efccb
Adding radiona ULX4M-LD-V2
2023-02-11 16:57:34 +01:00
a354f04143
avoid undefined clocks by moving the derive*-statements to start of the additional constraints list
2023-02-09 15:58:41 +01:00
b8abdf1b39
targets/digilent_arty: Add arguments for XDAC and DNA.
...
Avoid specific checks for Vivado toolchain (Now handled by user for f4pga toolchain)
and fix linux-on-litex-vexriscv build.
2023-01-23 08:55:10 +01:00
b9874685a5
gadgetfactory_papilio_pro: Cosmetic cleanups.
2023-01-17 15:43:12 +01:00
ec4d203eb6
Merge pull request #471 from Acathla-fr/papilio
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Target/Platform Papilio Pro added (with Arcade MegaWing)
2023-01-17 11:21:27 +01:00
801008f5ad
Merge pull request #469 from hansfbaier/hpcstore-rename
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HPC FPGA Store on AliExpress renamed itself to SITLINV
2023-01-17 11:20:19 +01:00
3b36e576ba
Add support for Xilinx Alveo U200
2023-01-17 06:44:21 +07:00
05ef1ee09e
Target/Platform Papilio Pro added (with Arcade MegaWing)
2023-01-16 13:41:24 +01:00
55fcb4cd47
xilinx_alveo_u2x0: Improve indentation on DRAMs.
2023-01-16 09:34:59 +01:00
be77f82720
platforms/xilinx_alveo_u250: Fix dram numbering.
2023-01-16 09:31:23 +01:00
e02f64a7db
platforms/gsd_butterstick: Fix copyright.
2023-01-16 08:41:10 +01:00
59a897e2dd
gsd_butterstick: Add missing pin defs
2023-01-16 17:32:39 +10:30
c0773ed9b9
HPC FPGA Store on AliExpress renamed itself to SITLINV
2023-01-16 11:31:35 +07:00
36a4100c8b
ocp_timecard: Add DDR3 SDRAM support.
2023-01-13 12:41:34 +01:00
3ca298ba42
ocp_tap_timecard: Add TODO on SMAs.
2023-01-13 11:51:09 +01:00
c753bf7fc1
ocp_tap_timecard: Fix GTPE2 location.
2023-01-13 11:47:52 +01:00
8b0d4787c7
ocp_tap_timecard: Fix CI.
2023-01-13 10:55:07 +01:00
1e35d78512
ocp_tap_timecard: Add initial SMAIOs peripherals to allow using SMA over PCIe DMA or also with direct (and slow) control/visualization with CSR registers.
2023-01-13 10:08:44 +01:00
fc7154a632
ocp_tap_timecard: Add Leds/I2C/PMOD/GPS/SMAs IOs.
2023-01-13 09:14:05 +01:00
a0fd3e7536
Add initial OCP-TAP TimeCard support with PCIe/SPIFlash/Leds/Buttons/DNA/XADC (Compiles but untested).
2023-01-12 18:50:23 +01:00
7a911b8ff6
Allow building digilent_arty using f4pga
...
Only use XADC() and DNA() functions if vivado is the current toolchain.
2023-01-06 16:09:56 -06:00
764f64ff1e
nx_vip: Add missing 'origin' to SRAM SocRegions
...
Signed-off-by: gatecat <gatecat@ds0.me>
2023-01-04 12:02:11 +01:00
f5643e7c78
machdyne: Fix LiteDRAM PHYs imports (QuarterRateGENSDRPHY not already working?/integrated).
2023-01-01 21:35:51 +01:00
563ccbd8cf
Merge pull request #464 from machdyne/master
...
initial support for machdyne konfekt and noir
2023-01-01 16:12:51 +01:00
5de6865cbe
Merge pull request #463 from stone3311/master
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terasic_deca: add SPI SD card support
2023-01-01 16:10:30 +01:00
fec82c59e2
remove konfekt ethernet option
2022-12-30 17:36:52 +01:00
f0dc9a6874
initial support for machdyne konfekt and noir
2022-12-30 17:00:35 +01:00
6cfb56bb07
terasic_deca: add SPI SD card support
2022-12-28 02:13:06 +01:00
57845d1ca4
Correct pinout and IOStandard
...
Correct connector pinout
Correct pinout for ETH
LED IOStandard set to LVCMOS33
BTN[0] IOStandard set to LVCMOS33
Changes are made based on Tang_primer_20K_3690 and Tang_Primer_20K-Dock_3709 schemes.
2022-12-22 18:30:36 +03:00
4e06e5ff9c
targets/xilinx_zybo_z7: adding missing variant parameter to the platform
2022-12-14 07:47:09 +01:00
a92fdffb35
platforms/digilent_zybo_z7: reorder _io_x & _connectors_x, init cleanup
2022-12-12 22:17:39 +01:00
d28894a4b3
Reintroduce original Zybo + HDMI addition ( #461 )
...
* Reintroduce original Zybo support
* Reintroduce original zybo, add HDMI + fixes for Z7
2022-12-12 22:05:47 +01:00
12db52471d
targets/jungle_electronics_fireant: Update SPIFlash (Make it similar to other boards with BIOS in SPIFlash).
2022-12-08 08:37:13 +01:00
c05ce32c8a
Merge pull request #458 from trabucayre/arty_s7_tcl_config
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Arty z7 tcl config
2022-12-08 08:31:22 +01:00
71f1e1976b
Merge pull request #459 from tcal-x/icebitsy-ledchaser
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Add LedChaser to iCEBreaker-bitsy.
2022-12-06 09:05:37 +01:00
25c40ddda7
add gpio to board
2022-12-05 21:38:56 -03:00
6e205be83b
Add LedChaser to iCEBreaker-bitsy.
...
Signed-off-by: Tim Callahan <tcal@google.com>
2022-12-04 17:58:20 -08:00
a889321535
targets/digilent_arty_z7: adding note to load gateware and bios
2022-12-03 16:54:52 +01:00
e71e3ab3ec
platforms,targets/digilent_arty_z7: use a dict for PS config instead of fetching file configuration
2022-12-03 16:54:39 +01:00
d0d90e9eef
Merge branch 'litex-hub:master' into master
2022-11-29 15:25:41 -03:00
b030630237
Merge pull request #453 from cklarhorst/zybo
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Zybo: Fix for Zynq7000 and use ps7 as submodule for Soft-CPUs
2022-11-25 21:48:43 +01:00
53b6bf035a
fixed parser
2022-11-24 16:03:12 +01:00
926ed21f0b
fixed review remarks; added zynq7000 as a submodule for using the ps as a slave
2022-11-23 17:20:25 +01:00
570ea11744
fix(plataform.basys_3): V_sync is pin R19
...
Based in https://github.com/Digilent/digilent-xdc/blob/master/Basys-3-Master.xdc#LL129C34-L129C37
2022-11-23 09:16:50 -03:00
c489347a51
fixed zynq7000 integration; introduced option to add the processing-system as slave to the SoC
2022-11-18 11:19:57 +01:00
6f7716adbb
added config for ps7; introduced different variants for the zybo-board; fixed pins
2022-11-18 11:15:54 +01:00
892bf3546d
isx_im1283: connect CRG reset to PLL
...
This fixes soft reset.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-16 15:12:18 +08:00
e27d8c958e
isx_im1283: add jtagbone support
...
Add necessary script snippets for enabling jtagbone in the command line.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-15 21:07:10 +08:00
ae47172d2a
targets/decklink_mini_4k: Update clock constraints.
2022-11-14 10:21:42 +01:00
6e10df234f
platforms/decklink_mini_4k: Fix data2_n pin (Thanks @rdolbeau).
2022-11-14 10:21:37 +01:00
e9d7013d70
sitlinv_stlv7325: add jtagbone support
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Add necessary script snippets for enabling jtagbone in the command line.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-13 17:28:04 +08:00
c2c59f5e8c
sitlinv_stlv7325: allow to set local/remote ip
...
Port the script snippet from Colorlight i5 for setting the local/remote
IP address to STLV7325.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-13 17:27:58 +08:00
3d8106f84d
stlv7325: fix Ethernet IO voltages
...
The IO voltages of Ethernet pins is set to 2.5V instead of 1.5V.
Fix this in the platform definition.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-13 17:27:23 +08:00
27c3afb8fb
sitlinv_stlv7325: allow dynamic Ethernet IP
...
Currently the sitlinv_stlv7325 target script parses the option that
selects dynamic Ethernet IP; however it's not really passed to LiteETH.
Really pass this option and add an assert that does not allow dynamic
Etherbone IP like other boards.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-13 17:27:23 +08:00
4ba5793822
sitlinv_stlv7325: remove unexistent COL/CRS pins
...
The COL and CRS pins of the Ethernet PHY is not connected on the board
at all, but assigned dummy positions in the platform definition, which
leads to Vivado warning when building.
Remove these pins from the platform definition.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-13 17:27:23 +08:00
1c07fa94ca
sitlinv_stlv7325: fix ident string vendor name
...
As we changed the vendor name to proper Sitlinv in the file name, the
ident string is left untouched.
Fix this too.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-13 17:27:23 +08:00
58489ebebf
targets/BaseSoC: Cleanup parameters.
2022-11-08 12:31:49 +01:00
a8c92cd86f
targets/simple: Switch back to old version for now.
2022-11-08 11:55:06 +01:00
9e7079c4c8
targets: Remove int() on BaseSoC's sys_clk_freq.
2022-11-08 11:54:17 +01:00
b0e6414519
targets: Cleanup arguments and switch --sys-clk-freq to float (avoid conversion in code).
2022-11-08 10:41:35 +01:00
16b9677acd
targets: Switch to soc_core_argdict.
...
The next move was to remove soc_core and only keep soc; so this is probably the right time to do
it in targets to avoid having to handle it later.
2022-11-07 08:43:26 +01:00
f1e24046fd
xilinx_alveo_u250: Fix.
2022-11-06 22:17:28 +01:00
6edfb2ca7a
Merge pull request #448 from trabucayre/fix_alinx_axu2cga_platform
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platforms/alinx_axu2cga: adding missing psu_config at platform level
2022-11-06 22:11:25 +01:00
9a2028a9ba
targets: Remove useless argparse imports.
2022-11-06 22:09:21 +01:00
30723b1bb0
targets: Update targets that were still using argparse.ArgumentParser.
2022-11-06 22:07:17 +01:00
24cd983b8c
platforms/alinx_axu2cga: adding missing psu_config at platform level
2022-11-06 21:52:00 +01:00
33b0400aed
targets: Update LiteXArgumentParser imports.
2022-11-06 21:39:52 +01:00
9960f38d95
targets: replace LiteXSoCArgumentParser by LiteXArgumentParser, remove tasks done LiteXArgumentParser
2022-11-06 11:27:47 +01:00
d7184fb043
stlv7325, a_e115fb: use the proper vendor name Sitlinv
...
The boards are in fact from a vendor called 成都赛特凌威科技有限公司,
and their English registered trademark (used on the banner of their
Taobao store) is Sitlinv, which sounds like 赛特凌威.
Use this vendor name instead of where it's bought.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-10-30 10:51:13 +08:00
4dc8f7223c
Merge pull request #443 from trabucayre/arty_z7_bios
...
targets/digilent_arty_z7: adding software support
2022-10-28 10:42:35 +02:00
3e809c3a1e
targets: Fix some LiteXModule imports.
2022-10-28 10:35:57 +02:00
ab3ed624cc
fpgawars_alhambra2: +x.
2022-10-28 10:31:49 +02:00
5f1b80fac4
targets/digilent_arty_z7: adding software support
2022-10-27 21:47:32 +02:00
548a028730
targets: Switch to LiteXModule to simplify/cleanup code.
2022-10-27 21:21:37 +02:00
6c05ddae1b
Merge pull request #438 from shawnanastasio/nexys4_part_name
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platforms/nexys4*: Update part name
2022-10-27 12:11:07 +02:00
f9d3a39001
chore fix target, args processing
2022-10-26 20:45:53 +02:00
189ee3de39
fix target
2022-10-26 20:36:18 +02:00
54af30a4be
fix: arg cpu-variant
2022-10-26 20:23:14 +02:00
32be05cfb1
chore default CPU variant
2022-10-25 21:14:25 +02:00
125569b2cb
add FPGAWars Alhambra II
2022-10-25 21:12:02 +02:00
bd2f1c2553
targets/isx_im1283: Fix CI.
2022-10-22 16:23:50 +02:00
8e35f15c22
Merge pull request #437 from trabucayre/fix_redpitaya_mem_region
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targets/redpitaya: fix csr & reset region
2022-10-22 16:00:22 +02:00
474dcb5fb3
Merge pull request #436 from Icenowy/isx-im1283
...
Add ISX iM1283 board
2022-10-22 15:56:43 +02:00
d4b2461b5a
platforms/nexys4*: Update part name
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Symbiflow/f4pga don't recognize the part name xc7a100t-CSG324-1, so
change it to xc7a100tcsg324-1 which works with both f4pga and Vivado.
2022-10-21 14:15:27 -05:00
5a8d846a86
targets: Remove add_csr calls (no longer required).
2022-10-21 08:42:24 +02:00
377cda05a3
ti60_f225_dev_kit: Switch 1.2V banks to 1.8V to fix compilation issues with latest Efinity.
...
Will need to be investigated more.
2022-10-20 18:21:52 +02:00
4a5d5318d7
targets/redpitaya: fix csr & reset region
2022-10-20 16:35:57 +02:00
745ebbbfa1
Add ISX iM1283 board
...
ISX iM1283 is a "simple eDP signal generator" which utilizes a XC7A100T
FPGA, and come with a header populated with the FPGA's JTAG.
This commit adds initial reverse engineered IOs including the DDR3 DRAM
(which cannot work reliably @ DDR3-800, so the system clock is defaultly
set to 80MHz now), two LEDs and SD slot.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-10-14 22:50:43 +08:00
cb65099399
Merge pull request #435 from trabucayre/fix_artyz7_build
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targets/digilent_arty_z7: add flash region
2022-10-14 15:49:52 +02:00
23c6acd013
platforms/ti60_f225_dev_kit: Fix IO voltage conflicts between peripherals/banks.
...
Was already reported as a warning on 2021.1.165.2.19 but now an error with 2022.1.226.
Note: To get the build working with 2022.1.226 the following change had to be done to
pt/bin/writer/pinout.py, line 2254:
- table.add_rows(table_rows)
+ for table_row in table_rows:
+ table.add_row(table_row)
This would need to be investigated more to know if related to our local setup/machine.
2022-10-14 10:22:54 +02:00
e44e63f65d
targets/digilent_arty_z7: add flash region
2022-10-13 19:48:41 +02:00
3b339ba9a3
platforms/xilinx_kc705: Fix flash proxy name.
2022-10-13 08:48:33 +02:00
99888c52ce
xilinx_kc705/i2c: Add pullups.
2022-10-11 17:26:06 +02:00
3ec18c3583
Add qmtech Cyclone IV Starter Kit
2022-10-09 16:34:44 +02:00
e6762e228c
targets/mnt_rkx7: Make USB-Host optional and disable by default (for CI).
2022-10-04 09:45:51 +02:00
d0dd009329
targets/mnt_rkx7: Integrate specific eDP video timings in target (Avoid LiteX patch).
2022-10-04 09:29:59 +02:00
c38b8b1d8c
MNT RKX7: update platform and target for D-2 release
2022-10-03 20:09:48 +02:00
cf416d0d66
stlv7325: Adjust DDR3 pins to match reference design
2022-10-01 11:15:47 +02:00
85ba931a3d
targets/litex_acorn_baseboard: fix pn_swap
2022-09-28 21:17:16 +02:00
57eb907210
aliexpress_stlv7325: Fix missing parameter for PULLUP attribute
2022-09-25 23:13:44 +02:00
8c3a5c0608
sipeed_tang_nano_9k: Fix HDMI IOs constraints.
2022-09-23 11:18:30 +02:00
9cd1c1cbd5
targets/digilent_arty: Switch with_buttons to False by default (To fix #426 ).
2022-09-23 10:07:17 +02:00
9dbee62eac
add option to use ecpprog for crosslink-nx eval board
2022-09-15 12:27:08 -07:00
3cef11e04d
platforms/newae_cw305: Add sma_clk_in/out, buttons, switches and expansion header connector.
2022-09-13 14:26:52 +02:00
f1899954e9
Add initial NewAE CW305 board support.
2022-09-13 12:38:30 +02:00
25c28d2c03
fixed issue with default programmer option
2022-09-10 18:16:04 +01:00
6768be7f66
changed use example comment
2022-09-10 17:56:02 +01:00
e8504191e3
cleanup
2022-09-10 17:54:43 +01:00
6d0a4c788e
Added DFU support to Butterstick
2022-09-10 17:45:57 +01:00
756e4f73fc
sipeed_tang_primer_20k: Cleanup CRG.
2022-09-08 17:27:41 +02:00
fadc5619f1
sipeed_tang_primer_20k/ddr3: Add litescope debug.
2022-09-07 17:46:46 +02:00
6c7157f799
sipeed_tang_primer_20k: Disable L2 cache to ease debug and add WIP status.
2022-09-07 17:07:07 +02:00
d39d87b701
sipeed_tang_primer_20k: Switch to PHYPadsReducer and enable the 2 modules.
2022-09-07 12:06:22 +02:00
1663ded641
sipeed_tang_primer_20k: Add initial DDR3 integration (WIP).
2022-09-07 11:53:24 +02:00
c9b8579ea3
sipeed_tang_primer_20k: Drive hdmi hdp to 1.
2022-09-07 11:22:02 +02:00
abd20f560b
sipeed_tang_primer: Minor cleanups (Rename standard dock to standard, reduce margin on hdmi5x).
2022-09-07 10:56:17 +02:00
1d92443604
targets/sipeed_tang_nano_9k: replace VideoHDMIPHY by VideoGowinHDMIPHY
2022-09-06 20:22:32 +02:00
4d72c75f49
platforms/sipeed_tang_primer_20k: use replace _connectors.extend by add_connector
2022-09-06 20:19:37 +02:00
0f242629ab
targets/sipeed_tang_nano_4k: replacing VideoHDMIPHY by VideoGowinHDMIPHY and adding with-video-terminal arg
2022-09-06 19:08:01 +02:00
ce5977bc1a
targets/sipeed_tang_primer_20k: fix CLKDIV (disable reset and calibration)
2022-08-31 13:32:23 +02:00
74d4a72494
radiona/ulx3s: Rename user_button to user_btn (consistency with other boards) and fix ident.
2022-08-26 22:25:54 +02:00
693cce73bd
Merge pull request #417 from Igor542/master
...
radiona_ulx3s: add buttons
2022-08-26 22:24:05 +02:00
0c14bbf0dc
sipeed_tang_primer_20k: adding dock lite support
2022-08-26 08:43:57 +02:00
9ed3b7baae
radiona_ulx3s: add buttons
2022-08-25 22:19:48 -07:00
94d079f469
sipeed_tang_nano_4k: Fix tab/space.
2022-08-24 16:07:18 +02:00
feff243f8f
Merge pull request #416 from shenki/artix-dc-scm
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Add Antmicro Artix DC-SCM board
2022-08-24 15:22:52 +02:00
6314b34dbe
targets/digilent_arty: Cosmetic cleanup.
2022-08-24 15:17:06 +02:00
6548dec149
Merge pull request #415 from lschuermann/dev/arty-button-irq
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digilent_arty: make GPIOs interrupt-capable if SoC has IRQs enabled
2022-08-24 15:15:20 +02:00
6ba6a7e8fa
Merge pull request #414 from lambdaconcept/master
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lambdaconcept_ecpix5: fix HDMI pin
2022-08-24 15:14:11 +02:00
f48ed3d9e7
Add Antmicro Artix DC-SCM board
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Based on commits by:
- Jedrzej Boczar <jboczar@antmicro.com>
- Karol Gugala <kgugala@antmicro.com>
Tested serial and networking on a DC-SCM with mor1k and vexriscv.
2022-08-24 13:03:36 +10:00
94ad22aceb
digilent_arty: make GPIOs interrupt-capable if SoC has IRQs enabled
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Signed-off-by: Leon Schuermann <leon@is.currently.online>
2022-08-17 15:55:39 +02:00
c3e99a8419
lambdaconcept_ecpix5: fix HDMI pin
2022-08-11 18:45:10 +02:00
7487440725
Added Tang Nano 4k Support for GoWin Educational IDE v1.9.8.03
2022-08-05 13:28:22 -03:00
bf458e388e
digilent_arty: Add buttons support.
2022-08-05 15:25:42 +02:00
f143fae2d0
digilent_arty: Add XADC/DNA and do minor cleanups.
2022-08-05 13:00:07 +02:00
6872f7ade6
sipeed_tang_primer_20k: Add LCD pins (untested).
2022-08-05 09:42:38 +02:00
c79d01064e
sipeed_tang_primer_20k: Switch Serial to Dock IOs.
2022-08-05 09:07:20 +02:00
f2cb211432
sipeed_tang_primer_20k: Add buttons and prepare RGB Led.
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Synthesis issue with WS2812/GowinEDA for now.
2022-08-04 16:32:50 +02:00
09b0c975f3
sipeed_tang_primer_20k: Add Ethernet/Etherbone (compiles but not yet working).
2022-07-26 12:53:42 +02:00
abe08a96aa
sipeed_tang_primer_20k: Add Video (Colorbars), compiles but does not seems to be working.
2022-07-26 12:25:10 +02:00
12b8063941
sipeed_tang_primer_20k: Add LedChaser through 204 pin SODIMM connector/Dock.
2022-07-26 11:44:03 +02:00
d49e43801e
sipeed_tang_primer_20k: Add 204 Pins SODIMM Connector.
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Will allow defining Dock peripherals.
2022-07-26 11:30:39 +02:00
99c1e52664
targets/sipeed_tang_primier_20k: Add SPI Flash support (X1).
2022-07-26 10:35:44 +02:00
6677c1d0bd
sipeed_tang_primer_20k: Enable SDCard (SPI and SD modes).
2022-07-26 10:27:19 +02:00
Florent Kermarrec
Gwenhael Goavec-Merou
Liana Koleva
Chandler Klüser
Chandler Klüser
Josuah Demangeon
Icenowy Zheng
Bayi
Mark1626
Ilya Ostrovskiy
Hans Baier
Gabriel Somlo
Arne Jansen
Chen
Charles-Henri Mousset
Lukas F. Hartmann
offNaria
594rk
Do Viet Thanh
Richard Tucker
Michael Welling
Marco
AEW2015
inc
Antoni Pokusinski
Tomasz Michalak
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MV
Fabien
Greg Davill
Luc Lagarde
gatecat
stone3311
jiv4ik
Gwenhael Goavec-Merou
JoyBed
Guilherme Salustiano
Tim Callahan
Guilherme Salustiano
mkuhn99
Chema
Shawn Anastasio
Franck Jullien
Vadzim Dambrouski
slagernate
Adam Zeloof
Igor Safonov
Joel Stanley
Leon Schuermann
Pierre-Olivier Vauboin