d9dcad33a4
build/lattice/prjtrellis: add inout support
2018-10-29 19:23:21 +01:00
091ad799b0
build/lattice/common: add tristate support
2018-10-29 19:22:04 +01:00
23acefb14e
boards/targets/versaecp55g_prjtrellis: simple.py example working, specific target no longer needed
...
simple.py configuration tested:
python3 simple.py --cpu-type=lm32 --gateware-toolchain=prjtrellis litex.boards.platforms.versaecp55g
python3 simple.py --cpu-type=vexriscv --gateware-toolchain=prjtrellis litex.boards.platforms.versaecp55g
2018-10-29 16:02:25 +01:00
1097f82283
build/lattice/prjtrellis: set default toolchain_path to "/opt/prjtrellis"
2018-10-29 15:58:54 +01:00
52917a710e
boards/targets/simple: add gateware-toolchain parameter
2018-10-29 15:56:46 +01:00
d84083f642
boards/platforms/versaecp55g: use ftdi serial pins
2018-10-29 15:39:51 +01:00
c05b9ef2ad
build/lattice/prjtrellis: test and fix iowrapper multi-bit signals support
2018-10-29 13:26:29 +01:00
a8f819fec2
Merge branch 'master' of http://github.com/enjoy-digital/litex
2018-10-29 11:48:10 +01:00
4eb314a252
boards/targets/versaecp55g: use new iowrapper support, basic led blink and ios working :)
2018-10-29 11:46:03 +01:00
27ec2a59e2
build/lattice/prjtrellis: generate iowrapper to set constraints and TRELLIS_IO
...
PrjTrellis does not yet have constraint files support, constraints are set
with signal attributes and specific TRELLIS_IO instances are requested. This
iowrapper does this work for us automatically.
Remove this code and replace with a constraint file generation code when
PrjTrellis will have constraint file support.
2018-10-29 11:44:31 +01:00
c506c9752c
gen/fhdl/verilog: set direction to io signals
2018-10-29 11:41:04 +01:00
1cac079efa
litex/build: Always run Vivado.
...
When using Yosys for synthesis, still need Vivado for place and route.
2018-10-29 02:04:44 -07:00
49dab3b448
build/lattice/prjtrellis: simplify code, remove some workarounds
2018-10-29 09:40:35 +01:00
a73d9d96b1
build/xilinx/vivado: fix merge issue
2018-10-29 08:26:13 +01:00
3e189379f9
boards/targets: add versa ecp55g prjtrellis target (experimental)
2018-10-28 19:34:17 +01:00
a69197d2db
build/lattice: add initial prjtrellis support
2018-10-28 17:51:16 +01:00
397e3c7682
build/lattice/diamond: use bash on linux
2018-10-28 15:40:52 +01:00
d029cd243d
build/lattice: improve special_overrides names (vendor_family)
2018-10-28 15:40:10 +01:00
b200ce9983
Merge branch 'master' into xilinx+yosys
2018-10-28 14:59:03 +01:00
ba0dd5728e
uart: Enable buffering the FIFO.
...
On the iCE40 FPGA, adding buffering allows the SyncFIFO to be placed in
block RAM rather than consuming a large amount of resources.
2018-10-27 16:04:58 -07:00
e3935b481e
build/sim/verilator: don't use THEADS parameters when threads=1
...
Allow using old (non multi-threaded) version of Verilator
2018-10-27 11:06:34 +02:00
a44181e716
soc_sdram: update litedram
2018-10-19 18:37:55 +02:00
ab6a530a24
bios/sdram: s7ddrphy now has bitslip in fabric, show scan for each module/bitslip and remove silent mode
2018-10-18 13:42:51 +02:00
b8be9545cc
build/xilinx/vivado: enable xpm libraries
2018-10-18 09:25:34 +02:00
ab8cf3e345
soc/cores/clock: add margin parameter to create_clkout (default = 1%)
2018-10-16 14:57:37 +02:00
915c2f417a
bios/sdram: improve write/read leveling
...
write_leveling: select last 0 to 1 transition.
read_leveling: do it by module (select best bitslip for each module)
2018-10-10 10:42:56 +02:00
deffa60324
platforms/kc705: add ddram_dual_rank
2018-10-09 15:39:03 +02:00
10624c26da
bios/main: handle all types of carriage return (\r, \n, \r\n or \n\r)
2018-10-09 10:06:51 +02:00
9f083e9bd3
Merge pull request #116 from stffrdhrn/sim-uart
...
sim: serial: Send '\r\n' instead of just '\n'
2018-10-09 07:32:31 +02:00
8877dba7e9
sim: serial: Send '\r\n' instead of just '\n'
...
This fixes an issue when running with the HDMI2USB firmware which
expects \r\n to come from the UART. Since the verilator adapter
is just sending \n commands cannot be executed.
Also, one minor whitespace cleanup. (could remove if needed)
2018-10-09 11:18:11 +09:00
d187921500
cpu_interface: fix select_triple when only one specified
2018-10-08 17:01:04 +02:00
3b27d2ae89
soc/integration/cpu_interface: generate error if unable to find any of the cross compilation toolchains
2018-10-06 21:32:38 +02:00
168b07b9a2
soc_core: add csr range check
2018-10-06 20:55:16 +02:00
ace976242e
build.xilinx: Convert attributes to something Yosys understands.
...
Convert keep, dont_touch and async_reg to something Yosys understands.
Write out an EDIF file with the attributes so that Vivado can use them.
(Requires Yosys with commit
115ca57647
2018-10-05 12:48:30 -07:00
6febb6826c
Merge pull request #112 from cr1901/8k-b-evn
...
build/platforms: Add ice40_hx8k_b_evn from Migen.
2018-10-04 21:12:33 +02:00
ff6de429f0
Fix help for or1k builds
...
The help said cpu-type could be mor1kx, which is correct but you must
pass or1k to get mor1kx. Fix the message to properly represent what
needs to be passed to the commandline.
2018-10-04 23:09:49 +09:00
dafdb8df72
Fix compiler warnings from GCC 8.1
...
Fix these 2 warnings:
litex/build/sim/core/libdylib.c:42:5: warning: 'strncpy' specified bound 2048 equals destination size
[-Wstringop-truncation]
strncpy(last_err, s, ERR_MAX_SIZE);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In function 'set_last_error',
litex/soc/software/libbase/exception.c:28:13: warning: function declaration isn't a prototype [-Wstrict-prototypes]
static char emerg_getc()
2018-10-04 23:07:48 +09:00
2be5205463
build/xilinx/common: update XilinxDDRInputImplS7 and XilinxDDRInputImplKU (from migen)
2018-10-04 08:17:44 +02:00
78414c0588
xilinx/viviado: Allow yosys for synthesis.
2018-10-03 21:58:03 -07:00
d13ac3b3d5
cpu/mor1kx: Adding verilog include directory.
2018-10-03 21:57:24 -07:00
9a44f08a3e
build/platforms: Add ice40_hx8k_b_evn from Migen.
2018-10-03 20:53:33 -04:00
dc7cd75757
build.xilinx: Run `phys_opt_design` and generate timing report.
...
Makes the flow more similar to migen.
2018-10-03 16:02:43 -07:00
948527b0fe
cores/cpu: revert vexriscv (it seems there is a regression in last version)
2018-10-02 12:30:11 +02:00
15bca4535f
targets/sim: fix integrated_main_ram_size when with_sdram
2018-10-02 11:31:08 +02:00
6e327cda26
bios/sdram: rewrite write_leveling (simplify and improve robustness)
2018-10-01 15:38:19 +02:00
975be6686f
platforms/genesys2: add eth clock timing constraint
2018-10-01 15:37:34 +02:00
934a5da559
soc/cores/clock: add expose_drp on S7PLL/S7MMCM
2018-09-28 13:02:10 +02:00
9097573e71
Merge pull request #109 from cr1901/xip-improve
...
Improve XIP Support
2018-09-25 15:32:04 +02:00
082b03016c
targets: use new clock abstraction on all 7-series targets
2018-09-25 09:31:30 +02:00
74e74dc0e7
soc/cores/clock: different clkin_freq_range for pll and mmcm
2018-09-25 09:09:47 +02:00
91d8cc2d6a
soc/cores/clock: different vco_freq_range for pll and mmcm
2018-09-25 09:04:38 +02:00
6cd954940c
soc/core/clock: allow selecting buffer type (None, BUFG, BUFR). (default = BUFG)
2018-09-25 08:36:18 +02:00
912ca3236b
soc/cores/clock: create specific S7IDELAYCTRL module
2018-09-24 23:22:59 +02:00
baec87f530
soc/cores/clock: add S7MMCM support
2018-09-24 23:20:12 +02:00
ef40524924
soc/cores/clocks/S7PLL: add speedgrade support, default to -1 (slowest)
2018-09-24 22:58:23 +02:00
5415b521be
targets/arty: use new clock abstraction module (compile, untested on board)
2018-09-24 22:49:30 +02:00
63fc395006
soc/cores: init clock abstraction module
2018-09-24 22:49:01 +02:00
0ff6d58605
Distinguish crt0 variants more clearly, update BIOS to use CTR variant (as it has no .data section).
2018-09-24 14:48:54 -04:00
8106008184
integration/builder: Create EXECUTE_IN_PLACE Makefile variable to complement COPY_TO_MAIN_RAM.
2018-09-24 12:28:45 -04:00
db90619067
integration/builder: Add LiteX define to generated variables (to distinguish MiSoC and LiteX).
2018-09-24 11:04:57 -04:00
70a32ed86f
sim/verilator: add multithread support (default=1)
2018-09-24 12:43:29 +02:00
7f0d116d88
soc_core: use cpu instead of cpu_or_bridge internally (keep retro-compat for now)
2018-09-24 10:59:32 +02:00
22febe9582
boards/targets: uniformize things between targets
2018-09-24 10:58:10 +02:00
01b025aafd
soc_core/get_mem_data: add endianness support and use it in builder/initialize_rom to avoid duplication
2018-09-24 08:01:32 +02:00
b528a005a0
cores/cpu: add software informations to cpu and simplify cpu_interface
2018-09-24 07:51:41 +02:00
2d785cb0ac
boards/plarforms: fix issues found while testing simple design on all platforms
2018-09-24 02:03:30 +02:00
c88029d330
soc_core: add uart-stub argument
2018-09-24 02:01:15 +02:00
e9ed737037
ease RemoteClient import
2018-09-23 10:23:00 +02:00
6f25a0d8a1
csr: use external csr_readl()/csr_writel() if present
...
If the variable CSR_ACCESSORS_DEFINED is set, then use external
csr_readl() and csr_writel() instead of locally-generated inline
functions.
With this patch, csr.h can be used with etherbone.h and litex_server to
prototype drivers remotely.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-09-22 16:55:09 +02:00
9a252e367c
csr: use readl()/writel() accessors for accessing mmio
...
Instead of directly dereferencing pointers, use variants on readl()/writel().
This way we can replace these functions with others for remote access
when writing drivers and code outside of the litex environment.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-09-22 16:54:46 +02:00
9d4da737ff
libbase/crt0-lm32.S: Add provisions for loading .data from flash.
...
:100644 100644 e0cd7153
2018-09-21 10:23:14 -04:00
15e584d880
targets/sim: generate analyzer.csv
2018-09-20 12:20:48 +02:00
cde72603a1
targets/sim: generate csr.csv
2018-09-20 11:17:18 +02:00
f62df5023f
targets/sim: add rom-init
2018-09-20 01:14:00 +02:00
1dbf591e78
targets/sim: add ram-init param to allow initializing ram from file (faster than tftp)
2018-09-20 01:00:13 +02:00
9893c2460a
integration/soc_core: add get_mem_data function to read memory content from file
2018-09-20 00:46:06 +02:00
a3eb2e403b
soc/intergration/builder: fix when no sdram
2018-09-19 23:59:42 +02:00
934b08ede8
targets/sim: merge in a single class and ease configuration
2018-09-19 23:59:15 +02:00
bd42b18856
Merge branch 'master' of http://github.com/enjoy-digital/litex
2018-09-19 19:21:14 +02:00
3e77ae788f
targets: replace MiniSoC with EthernetSoC
2018-09-19 19:19:50 +02:00
badd992469
targets/sim: add EtherboneSoC target (allow accessing wishbone over in simulation with litex_server)
2018-09-19 19:17:32 +02:00
537b0e9058
Merge pull request #101 from cr1901/icestorm-migen-pull
...
Icestorm Improvements
2018-09-18 08:19:09 +02:00
5c83c88128
Pull in b2740d9 from Migen. nextpnr now default, write out build scripts on dry run.
2018-09-17 21:17:24 -04:00
9c6f76f18c
bios/sdram: mode sdhw()
2018-09-13 06:33:54 +02:00
a44bedd557
bios/sdram: add missing #ifdef
2018-09-13 06:30:37 +02:00
0e68daebf3
targets: self.pll_sys --> pll_sys
2018-09-13 05:31:35 +02:00
1468b9f3ba
bios/sdram: show all read scans when failing.
2018-09-13 05:26:51 +02:00
07e4c183cd
cpu/lm32: re-enable multiplier/divider in minimal variant (does not seem to work correctly on hardware otherwise)
2018-09-12 06:02:23 +02:00
df3f003ecd
soc_sdram: update with litedram
2018-09-09 02:13:00 +02:00
bebc667da6
Merge pull request #99 from cr1901/mk-copy-main-ram
...
Add COPY_TO_MAIN_RAM generated Makefile variable to distinguish systems with/without "main_ram" region.
2018-09-08 03:55:23 +02:00
bd70ba278b
Add COPY_TO_MAIN_RAM generated Makefile variable to distinguish systems with/without main_ram region.
2018-09-07 21:49:24 -04:00
69716852f1
Merge pull request #100 from cr1901/tinyprog-fix
...
lattice/programmer: Use --program-image option with tinyprog if addre…
2018-09-08 03:48:04 +02:00
12a8944711
soc_sdram: revert vivado l2 cache workaround (still seems to cause issues on some cases...)
2018-09-07 11:51:17 +02:00
2b786065b1
targets: pass endianness to LiteEThMAC, tftp working with RISC-V, still need to fix txlen
2018-09-07 10:37:15 +02:00
c812321a93
lattice/programmer: Use --program-image option with tinyprog if address is given.
2018-09-07 04:05:49 -04:00
26963d62fa
libnet/microudp: (WIP) fix endianness issues
2018-09-06 18:43:55 +02:00
22c0131324
fix typo and unused include
2018-09-06 17:07:14 +02:00
fb24ac0ecc
cpu/minerva: add workaround on import until code is released
2018-09-06 16:40:30 +02:00
8f377307d8
add Minerva support
2018-09-05 22:33:04 +02:00
1944289e64
litex_server: update pcie and remove bar_size parameter
2018-09-05 13:01:51 +02:00
c5a2d6f3ec
Merge pull request #96 from cr1901/tinyfpga_bx
...
build/platforms: Add TinyFPGA BX board and programmer.
2018-09-03 20:49:33 -07:00
2949262449
build/platforms: Add TinyFPGA BX board and programmer.
2018-09-03 23:39:40 -04:00
ed507d618d
Add lm32 "lite" variant, remove mult/div from "minimal" and update compiler flags accordingly.
2018-09-03 19:48:19 -04:00
7af89efc70
lattice/icestorm: Add nextpnr pnr as alternate pnr tool.
2018-08-28 05:17:32 -04:00
ff908e404f
Merge pull request #92 from cr1901/l2-gate
...
software/bios: Gate flush_l2_cache() if L2 Cache isn't present.
2018-08-23 13:15:49 +10:00
3146109af3
software/bios: Gate flush_l2_cache() if L2 Cache isn't present.
2018-08-22 23:03:08 -04:00
759e7d4dc3
bios/sdram: improve/simplify read window selection
...
Compute a score for each window and select the best
2018-08-22 23:15:32 +02:00
09776b77e6
sim: run as root only when needed (ethernet module present)
2018-08-22 15:20:28 +02:00
06e835a3f8
builder: change call to get_sdram_phy_c_header and also pass timing_settings
2018-08-22 14:28:37 +02:00
ee26f8c5ae
soc_sdram: cosmetic
2018-08-22 13:40:22 +02:00
2db5424ae6
soc_sdram: vivado is now able to implement the l2_cache correctly (tested with vivado 2017.2 and >)
2018-08-22 13:28:23 +02:00
45e9a42c7e
soc_core: add cpu_endianness
2018-08-21 19:10:22 +02:00
3877d0f111
builder: get_sdram_phy_header renamed to get_sdram_phy_c_header
2018-08-21 18:15:57 +02:00
c64e44ef3f
soc_sdram: use new LiteDRAMWishbone2Native and port.data_width
2018-08-21 14:52:28 +02:00
2eeccc5054
vexriscv: update
2018-08-21 11:04:15 +02:00
eecc6f68ed
soc/integration: move sdram_init to litedram
2018-08-20 15:36:51 +02:00
077f939169
Vexriscv: update csr-defs.h
2018-08-18 14:15:43 +02:00
4225c3b87c
update Vexriscv
2018-08-18 14:14:00 +02:00
9547938527
bios/sdram: changes to ease manual read window selection
2018-08-18 13:45:22 +02:00
a760322fbd
litex_server: allow multiple clients to connect to the same server
2018-08-17 16:09:08 +02:00
8a69a47e7b
cpu/lm32: add minimal variant with no i/d cache, pipelined barrel shifter and multiplier (useful to build SoC on small FPGAs like ice40)
2018-08-17 08:32:32 +02:00
cb5b4ac468
bios/boot: flush all caches before running from ram
2018-08-16 19:47:43 +02:00
650ac18685
sim/verilator: catch ctrl-c on exit and revert default termios settings
2018-08-16 15:13:27 +02:00
0831ad5492
cpu_interace: use riscv64-unknown-elf if available else riscv32-unknown-elf
2018-08-16 10:04:09 +02:00
1610a7f3fb
bios/sdram: fix read_level_scan result
2018-08-14 18:33:36 +02:00
3c7890cdd4
Fix generating csr.csv file
...
Fix generating csr.csv file when no absolute path is given.
2018-08-12 13:37:39 +02:00
9fa234da50
soc/intergration/cpu_interface: typo
2018-08-08 08:53:54 +02:00
22f645adc1
bios/main: use edata instead of erodata
2018-08-07 09:02:09 +02:00
580efecc8c
picorv32: add reset signal
2018-08-07 08:59:34 +02:00
0429ee9f8f
soc/software/bios: add reboot command
2018-08-06 12:23:50 +02:00
da75159814
soc/integration/soc_core: add Controller with reset, scratch and bus_errors registers
2018-08-06 12:23:16 +02:00
8ba5625227
soc/interconnect/wishbone: add Timeout to avoid stalling bus when not responding and generate error.
2018-08-06 12:21:18 +02:00
c0989f65dd
soc/cores/cpu: add reset signal
2018-08-06 12:19:23 +02:00
fb145daced
tools: remove vexriscv_debug
...
This program is no longer needed.
The `openocd_vexriscv` package natively supports `etherbone`, and now
that the vexriscv debug module is available on Wishbone instead of as a
CSR, this module no longer works.
This change simplifies both tooling (because there is one fewer program
to run) and integration (because you don't need to modify your CSRs
anymore, just `register_mem()`.)
Signed-off-by: Sean Cross <sean@xobs.io>
2018-07-27 15:25:33 +08:00
f17b8324d4
vexriscv: reset wishbone bus on CPU reset
...
If the CPU is resetting during a Wishbone transfer, assert the ERR line.
Because the resetOut line is likely multiple cycles long, this should
give Wishbone enough time to finish its transfer, which will cause d.stb
and i.stb to go to 0, which will return d_err and i_err to 0.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-07-27 15:24:43 +08:00
c87ca4f1c3
vexriscv: put debug bus directly on wishbone bus
...
By placing the VexRiscv debug bus on the Wishbone bus, the Etherbone
core can access 32-bit values directly from the core. Additionally,
both reading and writing are supported without the need to do a SYNC
register as before.
Additionally, the address of the Wishbone bus won't move around anymore,
as it's fixed when doing `self.register_mem()`.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-07-27 15:24:43 +08:00
8a311bf4a6
build/generic_platform: use list for sources instead of set
...
Ideally, we want to use an ordered set (to be able to keep compilation order), to avoid using an external package, we use a list.
2018-07-20 10:01:33 +02:00
df7e5dbcf6
bios/sdram: add ERR_DDRPH_BITSLIP constant and some cleanup
2018-07-19 12:52:00 +02:00
1564b440eb
soc/integration/soc_sdram: add assertion on csr_data_width since BIOS only support SDRAM initialization for csr_data_width=8
2018-07-19 12:51:16 +02:00
c314193cc9
boards/plarforms/genesys2: replace user_dip_sw with user_sw
2018-07-18 12:48:44 +02:00
10dd55fd88
boards/platforms/genesys2: add minimum HPC connectors to be able to test SATA, add programmer parameter
2018-07-18 11:51:58 +02:00
85308672d3
software/bios/linker: revert data section since required by RISC-V compiler
2018-07-18 09:30:14 +02:00
55dd58b023
Merge pull request #80 from xobs/fix-vexriscv-csr-read
...
vexriscv_debug: use csr read()/write() accessors
2018-07-17 17:31:48 +02:00
41a9e7d9ae
vexriscv_debug: use csr read()/write() accessors
...
CSR access widths can be different from register widths. 8-bit
registers are common.
The runtime-generated `read()` and `write()` functions handle this
mapping correctly. When direct register accesses are handled, this
mapping is lost.
Use the accessor functions rather than directly accessing the memory
addresses, so that we work on platforms other than 32-bit-wide.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-07-17 18:03:58 +08:00
7ecdcaca4b
soc/integration/sdram_init: use fixed burst_length for each memtype (even in 1:2, use BL8 for DDR3 since BL4 is not efficient)
2018-07-16 18:40:36 +02:00
a4caa8964a
targets/nexys_video: remove read leveling constants (now automatic)
2018-07-16 09:44:15 +02:00
d825004173
targets/nexys4ddr: s7ddrphy now supports ddr2, working
2018-07-16 09:43:09 +02:00
4f1274e6a6
bios/sdram: improve bitslip selection when window can't be optimal (not enough taps for a full window)
2018-07-16 09:42:09 +02:00
7dbd85a842
soc/cores/uart: rename UARTMultiplexer to RS232PHYMultiplexer. UARTMultiplexer now acts on serial signals (tx/rx)
2018-07-10 22:32:51 +02:00
ef1c778446
soc_core: add csr_expose parameter to be able to expose csr bus (useful when design is integrated in another)
2018-07-10 13:29:32 +02:00
f9104b201a
bios/sdram: improve read leveling (artix7 read-leveling is now done automatically at startup)
2018-07-06 19:22:33 +02:00
c84e189d6a
bios/sdram: fix compilation with no write leveling
2018-07-06 16:22:49 +02:00
be8eb5ff84
vexriscv: debug: fix reading DATA register
...
The REFRESH register accepts an 8-bit address and determines which
register to refresh. Since there are only two addresses currently in
use, this register can be either 0x00 or 0x04.
A refactor replaced the compare with one that checked for any 0 bits.
Since both 0x00 and 0x04 have 0 bits, this check always evaluated as
true, causing the logic to always refresh the CORE register.
Replace this check with an explicit check for 0x00.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-07-06 18:22:32 +08:00
6bc9265c2b
setup: add vexriscv_debug to list of entrypoints
...
Add the vexriscv_debug program to the list of scripts created when
installing this module. This program is a simple bridge that allows
openocd to talk to the vexriscv core so it can be debugged.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-07-06 16:22:11 +08:00
45a649be9b
tools: vexriscv_debug: add debug bridge
...
Add a bridge that uses litex_server to go from openocd to wishbone.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-07-06 16:08:06 +08:00
c821a0feab
cores/cpu/vexriscv: create variants: None and "debug", some cleanup
2018-07-05 17:31:23 +02:00
59fa71593d
core/cpu/vexriscv/core: improve indentation
2018-07-05 16:51:40 +02:00
6068f6ce9c
Merge pull request #77 from xobs/debug-vexriscv-enjoy
...
Enable support for vexriscv debugging
2018-07-05 16:46:24 +02:00
11e8491547
platforms/arty_s7: keep up to date with Migen
2018-07-05 12:02:14 +02:00
32d5a751db
soc_core: uart: add a reset line to the UART
...
Enable resetting the UART by adding a ResetInserter to the UART.
The UART must be reset when resetting the softcore.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-07-05 17:25:29 +08:00
1ef127e06d
soc: integration: use the new cpu_debugging flag for vexriscv
...
Allow a new cpu_debugging flag to be passed to the constructor to
enable in-circuit live debugging of the softcore under gdb.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-07-05 17:25:29 +08:00
e7c762c8c3
soc: vexriscv: add cpu debug support
...
Add support for debugging the CPU, and gate it behind a new cpu_debug
parameter. With this enabled, a simple Wishbone interface is provided.
The debug version of the core adds two 32-bit registers to the CPU.
The register at address 0 indicates status, and is used to halt
and reset the core.
The debug register at address 4 is used to inject opcodes into the
core, and read back the result.
A patched version of OpenOCD can be used to attach to this bus via
the Litex Ethernet or UART bridges.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-07-05 17:25:28 +08:00
2024542a3c
vexriscv: verilog: pull debug-enabled verilog
...
The upstream vexriscv repo now generates both the current VexRiscv.v
softcore, as well as VexRiscv-Debug.v. This -Debug varient exposes
their specialized debug bus that allows for attaching a modified version
of openocd.
Sync the litex repo with the upstream version to take advantage of debug
support.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-07-05 17:25:27 +08:00
d35dc5cdea
platforms/arty: merge with Migen
2018-07-05 11:18:49 +02:00
fa0215660b
platforms/kc705: keep up to date with Migen
2018-07-05 10:43:26 +02:00
b9f3b49c63
platforms/de0nano: keep up to date with Migen
2018-07-05 10:42:45 +02:00
df99cc66e8
bios/sdram: also check for last read of scan to choose optimal window
2018-07-02 14:12:27 +02:00
8ce7fcb237
bios/main: add cpu frequency to banner
2018-07-02 13:47:18 +02:00
477d224921
bios/sdram: check for optimal read window before doing read leveling, increment bitslip if not optimal.
2018-07-02 13:46:48 +02:00
9e737d3c57
soc/cores/code_8b10b: update (from misoc)
2018-06-29 14:24:44 +02:00
d58eb4ecb7
bios/sdram: use new phy, improve scan, allow disabling high skew
2018-06-28 18:43:48 +02:00
692cb14245
software/bios: fix picorv32 boot_helper
2018-06-28 11:42:43 +02:00
b5ee110e63
bios/sdram: add write/read leveling scans
2018-06-27 15:31:54 +02:00
34b2bd0c28
boards: add genesys2 (platform with clk/serial/dram/ethernet + target)
2018-06-27 11:27:05 +02:00
8edc659d7d
soc_core: remove assert on interrupt (added to catch design issues, but too restrictive for some usecases)
2018-06-19 11:15:29 +02:00
2c13b701f5
soc/integration/cpu_interface: add shadow_base parameter
2018-06-18 18:01:47 +02:00
7444992999
soc: bios: fix windows build
...
The BIOS builds just fine on Windows, but afterwards tries to run
`chmod`. This command does not exist on Windows, and is unnecessary.
Add a conditional guard to prevent this command from running on Windows.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-06-18 17:13:54 +08:00
18f86881d9
targets: change a7/k7ddrphy imports to s7ddrphy
2018-06-12 15:40:45 +02:00
3e723d152a
soc/cores/cpu: add add_sources static method
...
When creating SoC with multiple sub-SoC already generated, we need an
easy way to add cpu sources.
2018-06-12 10:54:20 +02:00
7353197e21
fix the vexriscv boot helper
2018-05-31 01:24:22 +08:00
34a9303448
Fix for missing connectors for arty boards
2018-05-24 21:55:52 +03:00
e7d1683e34
litex_term: cleanup getkey and revert default settings on KeyboardInterrupt
2018-05-24 08:10:05 +02:00
6854c7f5fc
soc/integration/cpu_interface: use riscv64 toolchain instead of riscv32 (prebuild toolchain for windows can be found at http://gnutoolchains.com/ )
2018-05-09 15:39:25 +02:00
66229c8c05
add VexRiscv support (imported/adapted from misoc)
2018-05-09 15:03:37 +02:00
f60da4a5dc
add VexRiscv submodule
2018-05-09 14:39:31 +02:00
d149f386c9
allow multiple riscv32 softcores (use picorv32 cpu_type instead of riscv32)
2018-05-09 13:26:55 +02:00
c3652935d9
build: use our own fhdl/verilog code (needed to avoid combinatorial loop in simulation)
2018-05-01 12:02:54 +02:00
121eaba722
soc/intergration/soc_core: don't delete uart/timer0 interrupts
2018-05-01 00:46:26 +02:00
39ffa532b0
xilinx/programmer: fix programmer
2018-05-01 00:44:13 +02:00
c001b8eaf6
build/xilinx/vivado: add vivado ip support
2018-04-12 17:55:46 +02:00
43f8c230a7
soc_core: uncomment uart interrupt deletion
2018-04-12 17:23:46 +02:00
d7c7474670
gen/sim: fix import to use litex simulator instead of migen simulator
2018-04-04 15:40:53 +02:00
b7f7c8d159
build/xilinx/common/XilinxDDROutputImplS6: DDR_ALIGNMENT="C0" requires SRTYPE to be "ASYNC"
2018-03-12 09:33:05 +01:00
4324c6f666
bios/sdram: update kuddrphy initialization procedure
2018-03-08 13:54:30 +01:00
90dcd45f0b
soc/software/main: go to new line at startup
2018-03-07 21:39:10 +01:00
6706b24167
software/bios/main: add missing space
2018-03-07 15:24:39 +01:00
2a50a8021a
soc/integration/soc_core: improve error message for missing csrs
2018-03-05 09:59:06 +01:00
5ef34500f7
Improving error message when csr name is not found.
...
Before;
```
"/usr/local/lib/python3.5/dist-packages/litex-0.1-py3.5.egg/litex/soc/integration/soc_core.py",
line 258, in get_csr_dev_address
return self.csr_map[name]
KeyError: 'core'
```
Now;
```
Traceback (most recent call last):
File "XXXX/github/enjoy-digital/litex/litex/soc/integration/soc_core.py", line 259, in get_csr_dev_address
return self.csr_map[name]
KeyError: 'ddrphy'
The above exception was the direct cause of the following exception:
Traceback (most recent call last):
...
File "XXXX/github/enjoy-digital/litex/litex/soc/interconnect/csr_bus.py", line 199, in scan
mapaddr = self.address_map(name, None)
File "XXXX/github/enjoy-digital/litex/litex/soc/integration/soc_core.py", line 269, in get_csr_dev_address
) from e
RuntimeError: Unable to find ddrphy in your SoC's csr address map.
Check BaseSoC.csr_map in XXXX/github/enjoy-digital/litex/litex/boards/targets/arty.py
Found l2_cache, timer0, ddrphy2, buttons, sdram, identifier_mem, uart, uart_phy, leds, crg in the csr_map
```
2018-03-03 16:02:44 -08:00
ab2a3277c3
Merge pull request #67 from cr1901/vivado-paths
...
xilinx/vivado: Provide a fallback mechanism for using the same root f…
2018-03-03 08:29:18 +01:00
db20df49f4
Merge pull request #65 from cr1901/tinyfpga-serial
...
platforms/tinyfpga_b: Move serial peripheral out of default I/O, make it
2018-03-03 08:28:57 +01:00
2b00b7eba4
xilinx/vivado: Provide a fallback mechanism for using the same root for Vivado and ISE toolchains.
2018-03-02 21:48:49 -05:00
fa6b256198
build/xilinx/platform: fix merge
2018-03-03 00:07:50 +01:00
d40c57739c
boards/arty_s7: Fix IOStandard on System Clock.
2018-03-02 13:35:43 -05:00
0332f73a7b
build/xilinx/vivado: revert toolchain_path
2018-02-28 23:45:26 +01:00
2ff50a8882
build: fix merge
2018-02-28 23:10:24 +01:00
64e4e1ce84
build: merge with migen.build 27beffe7
2018-02-28 16:49:12 +01:00
0edfd9b901
boards/kcu105: regroup sfp tx and rx
2018-02-28 14:11:58 +01:00
e71593d67e
platforms/tinyfpga_b: Move serial peripheral out of default I/O, make it
...
optional via `add_extension`.
2018-02-27 18:41:35 -05:00
1925ba176f
replace litex.gen imports with migen imports
2018-02-23 13:38:19 +01:00
43164b9a2c
remove migen fork from litex
2018-02-23 13:37:26 +01:00
688f26cc32
Change AXI interface and tidy code
...
Inspired by parts of https://github.com/peteut/migen-misc/
2018-02-21 00:00:58 +00:00
512ed2b3d6
Preliminary AXI4Lite CSR bridge support
...
This change introduces an AXI4Lite to CSR bridge. Hopefully it will
become extended in the future with full AXI support and more structures
(Wishbone bridge, interconnect, ...). For now this will do.
The bridge has been simulated (and includes an FHDL testbench) and
tested in hardware (on a Zynq 7020).
2018-02-20 21:27:51 +00:00
55fc9d2d6b
Merge pull request #60 from q3k/for-upstream/top-level-module-selection
...
Top module selection (for Verilator and Diamond)
2018-02-19 12:27:25 +01:00
7b5bd4041a
Merge pull request #57 from rohitk-singh/master
...
WIP - BIOS: Flashboot without main ram
2018-02-10 21:37:38 +01:00
c14502807e
board/targets/nexys4ddr: use MT47H64M16
2018-02-06 19:17:54 +01:00
95ebba428c
boards/platforms/nexys4ddr: add user_sw, user_btn, fix ddr3
2018-02-06 19:08:46 +01:00
ee4fa597b4
boards: add nexys4ddr
2018-02-06 14:43:20 +01:00
2ecd1b0666
Merge pull request #61 from PaulSchulz/master
...
platform/arty.py: Move Pmod definitions to 'connectors' section.
2018-01-26 01:58:37 +01:00
4607e5323f
boards/platforms: Add Arty S7 Board.
2018-01-25 18:36:32 -05:00
0ac35300c4
Merge branch 'master' of https://github.com/enjoy-digital/litex into upstream
2018-01-24 13:32:42 +10:30
4f2725809e
software/common: revert PYTHON to python3 (since breaking things)
2018-01-23 10:39:13 +01:00
4e168221d8
bios: fix riscv processor print
2018-01-23 10:33:05 +01:00
d448874879
sim: rename top module to dut and use --top-module parameter (needed for picorv32 simulation)
2018-01-23 10:28:16 +01:00
3ac28ed6f7
platform/arty.py: Move Pmod definitions to 'connectors' section.
2018-01-23 16:11:25 +10:30
ef511e7edc
Specify top-level module in Lattice Diemond build script.
...
When building multi-source files the toolchain gets confused as to which
module is top-level. This ensures that the build_name of the design is
selected.
2018-01-23 01:17:04 +00:00
ef6c517dad
Build top module as 'dut' in Verilator and set it as top-level.
...
When building a design with PicoRV32 we end up with multiple top-level
modules and Verilator becomes confused as to which is the right one.
This change ensures the dut.v generated by the sim build process has
it's top-level name set to 'dut' and that verilator is invoked with this
name.
2018-01-23 01:15:28 +00:00
21bd26dcdd
Allow for multiple synthesis directives in specials.
...
This is needed to specify timing constraints on some Lattice Diamond
library specials, like the EHXPLLL.
To keep backwards compatibility we allow the directive to still be a
single string. If it's not, we assume it's an iterable.
2018-01-23 00:27:49 +00:00
67f8718b26
minor cleanup
2018-01-23 00:35:20 +01:00
6daf3eabc5
Implement IRQ software support for RISC-V.
...
Well, at least PicoRV32-specific. Turns out there is no RISC-V
specification for simple microcontroller-like interrupts, so PicoRV32
implements its' own based on custom opcodes.
It's somewhat esoteric, and for example doesn't offer a global interrupt
enable/disable. For this we implement a thin wrapper in assembly and
then expose it via a few helpers in irq.h.
2018-01-22 18:50:26 +00:00
2108c97b9b
Import PicoRV32-specific instruction macros.
...
These come from the PicoRV32 repo and are released under the public
domain [1].
[1] - 70f3c33ac8/firmware/custom_ops.S
2018-01-22 18:50:26 +00:00
cf74c781f4
Write init files that respect CPU's endianness.
...
This is required for PicoRV32 support. We also drive-by enable
explicit specification of run= in Builder.build() by callers.
2018-01-22 18:50:26 +00:00
7176492231
Set the MABI and MArch of the riscv target.
...
Again, this should be tunable, and synchronized with the core settings.
2018-01-22 18:50:26 +00:00
7ea5a26734
Enable hardware multiplier and divider in PicoRV32
...
This should become tunable later once we can configure whether we link
in the soft mul library or not.
2018-01-22 18:50:26 +00:00
75e230aae7
Replace __riscv__ macros with __riscv.
...
The __riscv__ form is deprecated [1].
[1] - https://github.com/riscv/riscv-toolchain-conventions#cc-preprocessor-definitions
2018-01-22 18:50:26 +00:00
20ed23443b
Export trap signal from PicoRV32.
...
This is useful for handling crashes from hardware.
2018-01-22 18:50:26 +00:00
b0be563012
Bump PicoRV32 version.
2018-01-22 18:50:26 +00:00
75e7f9505a
BIOS: Flashboot without main ram
...
Modified flashboot() to skip copy to main ram if there is no main
ram, and instead execute in place out of SPI flash. (For this to
work the linker .ld will also need to redirect references to be
inside the SPI flash mapping.)
2018-01-20 15:05:47 +11:00
3a5f93db5d
software/bios: add litex logo
2018-01-19 18:41:13 +01:00
c553fe2bf3
Add mimasv2 platform (pulled from litex-buildenv).
2018-01-19 06:16:04 -05:00
ead88ed66d
Support forcing colorama colors on.
...
This is needed if you want colors but are using pipes and similar.
2018-01-18 14:41:45 +11:00
fcc22350fb
Merge pull request #52 from ewen-naos-nz/tftp-alt-port
...
BIOS: Support alternate TFTP server port
2018-01-18 13:40:28 +11:00
5ce8ca8e9b
BIOS: TFTP: try UDP/69 if specified port fails
2018-01-18 13:10:28 +11:00
cb31266500
BIOS: set TFTP_SERVER_PORT from enviroment
2018-01-18 13:09:34 +11:00
97f381baa6
BIOS: allow BIOS to specify TFTP server port
...
Swaps hard coded PORT_OUT in tftp.c for parameter on the tftp_get()
and tftp_put() functions. Allow TFTP_SERVER_PORT used by BIOS to be
set at compile time from compiler defines.
2018-01-18 12:03:35 +11:00
e06bb3724b
Merge pull request #51 from felixheld/liteeth-untangling
...
Include the ethernet related header files conditionally
2018-01-16 21:37:24 +01:00
21ad435def
Include the ethernet related header files conditionally
...
Only including those header files in the litex firmware is the first step to
move the firmware parts of liteeth to the liteeth tree.
2018-01-16 14:33:49 +11:00
3d40ad0a82
soc_core: Don't fail if name is the same.
...
Otherwise you can't override the UART with another UART, you get an
error like;
```
File "/home/tansell/github/timvideos/HDMI2USB-litex-firmware/third_party/litex/litex/soc/integration/soc_core.py", line 176, in __init__
interrupt, mod_name, interrupt_rmap[interrupt]))
AssertionError: Interrupt vector conflict for IRQ 2, user defined uart conflicts with SoC inbuilt uart
```
2018-01-13 19:10:57 +11:00
bebaef1e25
Merge pull request #48 from mithro/fix-constants
...
cpu_interface: Fix indenting on constant generation.
2018-01-13 19:07:04 +11:00
f6f73cf13c
cpu_interface: Fix indenting on constant generation.
...
This was preventing constants from getting added to the csr.h header
file.
2018-01-13 19:05:26 +11:00
6318a2b29a
Fix all remaining indentation issues in python code
...
I ran a script that shouldn't have missed any tab in the python source files.
2018-01-13 13:19:36 +11:00
782711e5a9
bios/sdram: make read leveling robust for KUS SDRAM
...
Increases the initial delay step into the valid read window as
with the original delay I was not getting out of the noisy
transition window, as evidenced by seeing read delay windows
of only 8 LSB ~10% of the time, leading to failing memory
tests
2018-01-12 19:23:08 +01:00
5c95c8ead0
Merge pull request #44 from felixheld/nexys_video-dram-fix
...
Fix DDR3 on nexys_video
2018-01-12 14:08:03 +11:00
9eb1beea04
fix DDR3 on arty
2018-01-12 13:54:10 +11:00
4a3454107a
fix DDR3 on nexys_video
2018-01-12 13:33:13 +11:00
23585385c0
fix the unsupported programmer case for kc705 and minispartan6
2018-01-11 18:15:11 +11:00
10000eb607
build/xilinx/vivado: only generate constraints that are not empty
2018-01-08 17:03:19 +01:00
5681a3c1a9
bios/sdram: revert capability to do manual read leveling since still needed with some targets
2018-01-08 12:04:33 +01:00
03eb137449
bios/sdram: fix data error reporting
2018-01-08 11:43:49 +01:00
22ff745027
bump year
2018-01-08 11:43:13 +01:00
ee6b33e9d3
build: add Inverted property to IOs to ease inverting signals and propagate property to cores
2018-01-06 01:33:02 +01:00
621aaf6988
soc/integration/soc_core: avoid removing uart interrupts (break some designs)
2017-12-30 18:41:49 +01:00
377af99678
Merge pull request #40 from mithro/or1k-linux
...
cpu: Adding "variant" support.
2017-12-30 11:19:12 +01:00
f8a07c5d3c
Merge pull request #41 from cr1901/python-3.6
...
fhdl/tracer: Import Python 3.5/3.6 version guards from Migen.
2017-12-30 11:17:41 +01:00
ff0ad9a622
fhdl/tracer: Import Python 3.5/3.6 version guards from Migen.
2017-12-29 19:56:52 -05:00
44650dffd8
cpu: Adding "variant" support.
...
It is useful to support slightly different variants of the CPU
configurations. This adds a "cpu_variant" option.
For the mor1k we now have the default mor1k configuration and the
"linux" variant which enables the features needed for Linux support on
the mor1k.
Currently there are no variants for the lm32, but we will likely add a
"tiny" variant for usage on the iCE40.
2017-12-30 01:18:51 +01:00
bbd15ca567
Wait longer before giving up on the 2nd tftp block.
...
Previously we would wait the same number of iterations as it took us to
receive the first data block after sending the request. When using the
build in tftp server in qemu, the first wait loop succeeds (and thus
breaks when 'i' is still 0.
Since the counter was never reset between the first and second data
block, under qemu the tftp_get call would fail before ever checking if
we have received the second block of data.
Now that we initialise 'i' to 12M, we ensure that we wait the same
amount of time for the second data block as it previously did for the
third (and subsequent) blocks.
2017-12-29 23:56:32 +01:00
0a2d38ecd2
bios/sdram: use same initialization procedure for artix7 than kintex7 excepting write leveling that is not done
2017-12-29 17:13:58 +01:00
b78a4760bb
soc/integration/builder: don't build bios is user is providing rom data
2017-12-28 22:42:58 +01:00
5d98a60e6e
Merge pull request #38 from cr1901/mercury
...
Add Mercury baseboard support from Migen, import fixes.
2017-12-27 17:52:37 +01:00
282f22f09e
Add tracelength report generation by default to help with board layout
2017-12-27 22:40:39 +08:00
b463b2169b
boards/platforms/tinyfpga_b: add defaut serial pins
2017-12-27 00:26:30 +01:00
fe2564e921
build/lattice/icestorm: fix missing toolchain_path
2017-12-27 00:26:07 +01:00
5a2c92ba80
Add TinyFPGA platform based on Migen.
2017-12-27 00:00:05 +01:00
f096030fc8
Import Icestorm backend improvements from Migen.
2017-12-26 23:57:13 +01:00
e7015e4191
soc/integration/soc_core: add uart_name parameters (allow selecting uart without modifications in platform file)
2017-12-26 18:11:47 +01:00
a3390bb403
build/xilinx/programmer: fix settings in run_vivado (update)
2017-12-19 10:29:29 +01:00
dd6ca87561
Add Mercury baseboard support from Migen, import fixes.
2017-12-18 19:30:25 -05:00
4c82eb549f
build/xilinx: add support for edif/ngc files
2017-12-16 13:20:45 +01:00
b31d0f37db
cpu/picorv32: adapt to current version, some cleanup
2017-12-10 03:01:53 +01:00
4239aff68a
cpu: cleanup wrappers
2017-12-10 02:52:01 +01:00
43429560d4
soc/integration/soc_core: add integrated_rom_init to allow initializing rom with custom code
2017-12-08 10:18:01 +01:00
27d37fa95d
targets/sim: fix
2017-12-06 22:22:05 +01:00
284b16e2c1
soc/integration/soc_core: make nmi interrupt optional
2017-12-03 23:07:41 +01:00
c1eba9a6cc
soc/integration: add integrated_main_ram_init parameter to allow using main_ram with pre-initialized firmware
2017-11-24 13:16:58 +01:00
831b489fd3
soc/interconnect/stream: fix specific cases for last/first signal in UpConverter
2017-11-23 17:58:02 +01:00
c3d902ef42
soc/software/bios/sdram: add Kintex Ultrascale support
2017-11-08 12:59:38 +01:00
2665a83288
soc/interconnect/stream: expose depth on SyncFIFO
2017-10-30 22:56:09 +01:00
56ef229029
Make the interrupt dicts read only.
2017-10-29 19:45:52 -07:00
295e78ee9e
Make it harder to have conflicting interrupts.
2017-10-29 19:45:52 -07:00
ff72757b87
Bump the IRQ for liteeth based targets.
2017-10-29 19:45:52 -07:00
73e0036b99
Change the default IRQs.
...
* Reserve IRQ 0 to be used as a "non-maskable interrupt" (NMI) in the
future.
* Use IRQ 2 for the LiteX. This matches the standard mor1k config which
connects the UART to IRQ 2.
This change is needed for Linux running on LiteX as it gets grumpy with
using IRQ 0 for anything other other than an NMI.
2017-10-29 19:45:52 -07:00
e07bd71b16
build/xilinx: Fixing settings finding.
...
* Better error messages.
* Search correct directories;
- XXX/Vivado/<version>
- XXX/<version>/ISE_DS/
2017-10-16 18:25:51 +11:00
db6c88bbef
soc/interconnect/stream: don't use reset less on last and first signals (not reseting these signals can cause troubles in some specific cases)
2017-10-12 11:30:56 +02:00
2c013948b1
Output better error message for flash_proxy.
2017-10-07 12:14:00 +11:00
279ec488e3
bios: Print location jumping too.
...
Makes it easier to understand what is happening (and that the BIOS is
jumping to the right place).
2017-10-06 20:38:44 +11:00
8152673d18
common: Compile with debugging symbols on.
...
Debugging symbols are useful when using GDB :-)
2017-10-06 20:38:44 +11:00
b1b6a74170
or1k: Use EXCEPTION_STACK_SIZE of 256bytes.
...
or1k defines a 128 byte "red zone" after the stack that can not be
touched by the exception handler.
We also need 128 bytes to store the 32 registers.
2017-10-06 20:38:44 +11:00
07a9df3586
bios: Declare dependency on linked in .a files.
2017-10-06 20:38:44 +11:00
e558473119
Add iCEStick board. Tested with litescope.
2017-10-04 01:59:53 -04:00
c3383f47ba
Port IceStorm backend from Migen.
2017-10-03 22:48:44 -04:00
ba1bf20f37
soc/cores: add cordic
2017-09-29 12:07:43 +02:00
878380abba
Merge pull request #28 from enjoy-digital/eb-docs-2
...
More docs for etherbone packet fields.
2017-09-26 12:33:57 +02:00
e42ab27f30
gen/fhdl/verilog: revert _printcomb_simulation and _printcomb_regular (needed for icarus simulation) and add Finish command
2017-09-13 13:47:25 +02:00
2a8f6edded
soc/integration/soc_core: add ident_version parameter to allow adding soc version to identifier
2017-09-06 15:39:54 +02:00
3a656c61d9
More docs for etherbone packet fields.
...
Info comes from http://www.ohwr.org/attachments/1669/spec.pdf dated 24 July 2012
2017-09-01 23:57:34 +10:00
c125ea6440
Adding a little docs to field descriptions.
2017-09-01 23:27:58 +10:00
8f3dcf90ab
soc/software/bios/sdram: add optional memtest debug traces
2017-08-18 09:42:27 +02:00
c02de1632b
soc/cores: fix vivado issue with SPIRegister (at least with Vivado 2017.x+, mosi was not generated correctly), create cs_n signal if pads does not exists
2017-07-27 18:22:01 +02:00
04646b24ed
soc/interconnect/stream: fix make_m2s for reset_less
2017-07-24 18:18:35 +02:00
9509d9e361
gen/genlib/cdc/gearbox: fix possible pointers overlap by removing AsyncResetSynchronizers.
...
read/write clocks don't have the same frequencies, using AsyncResetSynchronizers cause differents delay when releasing reset and can cause pointers overlap.
2017-07-24 13:39:08 +02:00
f25e46c428
Merge pull request #26 from q3k/diamond-linux-support
...
Add Diamond toolchain support for Linux.
2017-07-20 14:41:05 +02:00
503df5e93e
Add Diamond toolchain support for Linux.
...
This tries to replicate the same setup as in the Windows buildsystem. We
also remove the Jedecgen step, as it doesn't seem to be supported nor
necessary in newer versions of Diamond.
2017-07-20 13:21:10 +01:00
756554371a
soc/tools/remote/litex_server: allow multiple instance of server
2017-07-19 21:18:12 +02:00
0b6d38abe9
build/xilinx/programmer: add multi jtag devices support to VivadoProgrammer
2017-07-19 14:54:19 +02:00
d05d170b75
soc/integration/cpu_interface: do not generate constant access functions when with_access_functions is set to False
2017-07-19 12:18:35 +02:00
20c859d45c
soc/tools/remote/etherbone: speed optimization (~20/30%)
2017-07-17 00:25:58 +02:00
bdea4152e3
soc/core/uart: add UartStub to enable fast simulation with cpu
2017-07-06 19:19:10 +02:00
1885e50d54
Add Versa ECP5-5G Platform.
2017-07-05 15:01:07 +01:00
0894f9e6f7
targets: cleanup arty/nexys_video/kc705 and use better ddr3 timings on arty/nexys_video (found using the new bitslip/delay finder tool)
2017-07-04 09:01:29 +02:00
fe535db5ab
merge migen ee0e709 changes
2017-07-04 08:15:40 +02:00
c6f6d7b491
soc/interconnect/wishbonebridge: reset_less optimizations
2017-06-30 19:41:14 +02:00
7fcdd94cd4
soc/interconnect/stream_packet: reset_less optimizations
2017-06-30 19:40:54 +02:00
227b14c3f3
soc/interconnect/stream: improve reset_less support for streams
2017-06-30 19:40:17 +02:00
f5a971a8d8
soc/interconnect/stream: use reset_less attr of signal for payload and param
2017-06-28 23:10:45 +02:00
bd876d4cd6
merge migen 9a6fdea3 changes
2017-06-28 22:47:13 +02:00
4d664730fe
soc/software/libbase: fix get_ident
2017-06-28 18:10:56 +02:00
e61d9eabc6
board/targets/sim: add identifier
2017-06-28 18:08:37 +02:00
4433e2449a
litex/build/sim: cleanup modules
2017-06-28 18:01:04 +02:00
c3710ec139
build/sim: cleanup serial2console and fix terminal mode
2017-06-28 17:38:09 +02:00
5ece895fd3
litex/build/sim: add README
2017-06-28 16:55:32 +02:00
4a0a431119
litex/build/sim: rename c functions from lambdasim to litex_sim (since integrated in litex)
2017-06-28 16:28:45 +02:00
ab6f4de521
litex/build/sim: small cleanup
2017-06-28 16:25:56 +02:00
1d8298af94
litex/build/sim: add tapcfg submodule for ethernet
2017-06-28 16:18:15 +02:00
8510b12e93
litex/build/sim: introduce new simulator with modules support (thanks lambdaconcept)
2017-06-28 16:14:13 +02:00
6631aa5385
boards/platforms/arty: add pmods
2017-06-23 10:50:37 +02:00
1364ac3657
soc/cores/identifier: append 0 to contents to indicate end of string
2017-06-22 17:53:19 +02:00
f720ef5631
soc/tools: simplify litex_server usage and integrage udp, pcie
2017-06-22 11:30:33 +02:00
41a91829eb
soc/tools: syntax fix on comm_pcie, import in __init__.py
2017-06-22 11:29:57 +02:00
c82c1d103f
soc/tools: fix debug prints of comm_pcie
2017-06-22 10:33:08 +02:00
684ae45dbe
soc/tools: remove csr builder from comm_udp (we should use litex_server)
2017-06-22 10:32:39 +02:00
4ea7026747
gen/fhdl/specials: revert migen's commit d98502c6 (specials/Memory: homogenize read-only port syntax) since causing a regression with litepcie
2017-06-10 21:53:53 +02:00
c44a4b051f
soc/interconnect/stream: add first signal to streams (avoid over-complicated code in some cases)
2017-06-09 19:35:48 +02:00
c19c4b711b
soc/cores/identifier: remove additionnal first character
2017-06-08 14:15:27 +02:00
77732fca95
soc/cores/uart: add uart multiplexer
2017-06-05 19:36:30 +02:00
157c2b17bc
boards/platforms/nexys_video: rename hpa to hdp_en on nexy_video hdmi_in port
2017-06-05 15:13:21 +02:00
a36986a501
gen/fhdl/verilog: list available clock domains on keyerror
2017-06-05 14:33:46 +02:00
931ea5ac75
gen/genlib/cdc/gearbox: remove TODO since code is already a good compromise
...
latency can't be reduced that much and reducing ressource usage (already low) would introduce unneeded complexity.
2017-06-01 19:00:22 +02:00
85aea62d74
soc/core: add frequency meter
2017-06-01 00:39:19 +02:00
ff2a9c2176
gen/genlib/cdc/gearbox: add more margin on pointers (for cases where clocks are not perfectly aligned)
2017-05-31 13:23:31 +02:00
4bc6cf6165
soc/cores: dna/xadc: add missing copyright
2017-05-16 21:18:32 +02:00
9350a7b5e6
soc/cores: add dna and xadc (for 7-series, add support for others fpgas?)
2017-05-16 21:02:33 +02:00
5f9ff09c08
vivado: Fix segfault with or1k.
...
The or1k doesn't have any verilog include paths added. This means the
code use to generate;
```tcl
synth_design -top top -part xc7a50t-csg325-2 -include_dirs {}
```
which causes Vivado to segfault with the following error;
```
Command: synth_design -top top -part xc7a50t-csg325-2 -include_dirs {}
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a50t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a50t'
Abnormal program termination (11)
Please check 'build/netv2_base_or1k/gateware/hs_err_pid76959.log' for details
Traceback (most recent call last):
File "./make.py", line 82, in <module>
```
2017-04-29 16:44:18 +10:00
bedd428d9d
soc/integration/builder: remove error when compile_software=False and integrated ROM: when using compile_software=False user knows what he's doing.
2017-04-26 13:49:16 +02:00
bb582619eb
gen/genlib/cdc: cleanup lcm computation, fix timeout on BusSynchronizer
2017-04-25 15:13:47 +02:00
0daeff8689
gen/sim/core: do not use reset_less clock_domains for the one that are created (logic may need to access reset signal)
2017-04-25 10:56:19 +02:00
456cce3ec6
gen/genlib/cdc: import gcd from math and not fractions (deprecated)
2017-04-25 10:55:13 +02:00
4c7d460475
litex/gen/util/misc: import gcd from math and not fractions (deprecated)
2017-04-24 19:25:24 +02:00
c0800d25a6
soc/integration/builder.py: don't take care of ROM when compile_software is forced to False
2017-04-24 19:12:30 +02:00
b34f74397a
soc/cores: add code_8b10b from misoc
2017-04-19 11:05:21 +02:00
9cfc594280
soc/cores: move flash cores to cores directory
2017-04-19 10:58:15 +02:00
e1319924aa
soc: move uart to a single file
2017-04-19 10:37:59 +02:00
1acca39397
soc/cores: add new spi master, remove obsolete one
2017-04-19 10:22:35 +02:00
f73eb5fe71
gen/genlib/misc: add BitSlip
2017-04-19 09:55:19 +02:00
b708b9cfba
gen/genlib/cdc: add gearbox
2017-04-19 09:54:51 +02:00
e27bc936ef
boards/platforms: add vadj, change user_sw, user_btn IOStandard to LVCMOS25
2017-04-03 17:36:45 +02:00
5efd6a8412
soc/interconnect/stream_packet.py: make error payload optional on Packetizer
2017-03-28 12:21:54 +02:00
d173d946b7
boards/platforms/papilio_pro: fix imports
2017-03-27 10:40:29 +02:00
b6bc040142
boards/platforms/arty: add spi pins
2017-03-20 16:11:00 +01:00
4ee7019852
soc_core: Add CPU_RESET_ADDR as a constant.
...
So we can do a "soft reset" by jumping to this address.
2017-03-12 22:49:36 +11:00
c69012d713
boards/platforms/kcu105: add user_sma_gpio
2017-03-08 16:52:31 +01:00
36bb0f4f3a
Allow using gcc for or1k.
...
* Using CLANG can set by using CLANG=1 or CLANG=0 in the environment.
* or1k continues to default to CLANG if environment is not net.
2017-03-05 19:01:03 +11:00
4dea714ec7
Add Mercury development board (port from MiSoC)
2017-02-21 05:06:51 -05:00
187d9577ab
boards/platforms: fix IOStandard on sfp_tx_disable_n pins
2017-02-20 18:34:49 +01:00
1cda83f11b
build/xilinx/programmer: add target parameter to load_bitstream to select jtag programmer
2017-02-20 17:37:03 +01:00
d8c7702be8
boards/platforms/kcu105: add sma/sfp ios
2017-02-20 15:55:41 +01:00
9774cbd20e
boards/platforms/kc705: add sma/sfp/xadc ios
2017-02-20 12:22:23 +01:00
60f7e9c14f
build/lattice/diamond: add jedec file generation
2017-02-18 17:33:50 +01:00
384f4f428e
build/xilinx/vivado: set_property library only supported for vhdl
2017-02-17 11:42:55 +01:00
ac70083453
boards/plaforms: add FMC LPC connector to nexys_video
2017-02-16 19:16:07 +01:00
afd0a0c7f3
boards/targets: add dram to arty and nexys_video
2017-02-16 18:52:27 +01:00
5fde6d6d3d
build/lattice/diamond: remove use of tools.mkdir_noerror
2017-02-16 11:48:22 +01:00
3711ae0615
boards/targets: remove build and load parameters on arty and nexys_video (consistency with others targets)
2017-02-10 12:32:33 +01:00
c98a90520e
boards/kc705: store bios in flash as it's done for others litex targets (we could use flash in custom designs)
2017-02-10 09:30:10 +01:00
a3ef0fd53d
boards/platforms/kcu105: add ddr4 dram pinout
2017-02-09 15:26:22 +01:00
892f019871
boards/platforms/nexys_video: fix IOStandards on hdmi_in
2017-02-06 18:18:36 +01:00
be4fbdcaeb
boards/platforms/kcu105: add DP4 to DP7 to HPC connector
2017-02-02 18:44:12 +01:00
4177023a20
build/xilinx/programmer: remove open_hw_target parameters on VivadoProgrammer (now works for ultrascale)
2017-02-01 14:33:26 +01:00
790020de9f
soc/cores/flash/spi_flash: remove bitbanging comment (no longer supported)
2017-02-01 12:21:56 +01:00
7b6f06cc07
boards/platforms/kcu105: fix GBTCLK0_M2C/GBTCLK1_M2C pins
2017-02-01 11:58:41 +01:00
0b86295c6d
boards/platforms/kcu105: add user_sma_clock_p/n
2017-02-01 10:36:57 +01:00
df464aeaf3
boards/platforms/kcu105: add user_btns, user_dip_btns, clk300, i2c, spi_flash, rotary hdmi, pcie
2017-01-31 09:57:36 +01:00
194cf6c959
boards/platforms/kcu105: add LPC connector
2017-01-31 09:28:22 +01:00
c2dd7b1235
boards/platforms/kcu105: add user sma clock and HPC connector
2017-01-30 18:47:22 +01:00
f0020a6490
boards/platforms: add minimal kcu105 platform
2017-01-30 17:33:19 +01:00
de336a86e5
soc/integration/soc_core: use cpu_reset_address = self.mem_map["rom"] when using integrated_rom
2017-01-30 14:10:57 +01:00
67645ce7dd
boards/platform/arty: add spiflash_4x/spiflash_1x to test SpiFlashDualQuad and SpiFlashSingle
2017-01-26 13:28:19 +01:00
4b77b850ce
add SpiFlashSingle and rename SpiFlash to SpiFlashDualQuad
2017-01-26 13:28:18 +01:00
2444c090ab
Adding paths for vivado.
2017-01-20 10:30:34 +11:00
6d0096a18e
Merge pull request #14 from mithro/spiflash2
...
spi_flash: fix bitbang with spi_width=1
2017-01-17 04:41:05 +01:00
455cb3ebe3
soc/software/main: fix double serialboot (merge issue)
2017-01-17 04:37:18 +01:00
bd0eb48357
Fixing missing csr_constant/config support.
...
Missed as part of misoc merge at ff31959aea
2017-01-14 19:24:04 +11:00
9c0e978556
Fixing accidental revert in merge commit.
2017-01-14 00:13:53 +11:00
ff31959aea
merge most of misoc 54e1ef82 and migen e93d0601 changes
2017-01-13 03:55:00 +01:00
2507eff890
Merge pull request #15 from joeladdison/master
...
Add strcasecmp function to lib
2017-01-12 04:24:28 +01:00
f0202db90f
gen/genlib/cdc: add GrayDecoder from misoc
2017-01-12 04:15:33 +01:00
31dbd35c2e
Add strcasecmp function to lib
2017-01-12 14:00:05 +11:00
ab5b9389b7
soc/tools/litex_term.py: fix reader for c = b"\r" case
2017-01-11 01:56:31 +01:00
30f7dd69bd
soc/interconnect/stream/: add busy signal to PipelinedActor
2017-01-10 02:18:21 +01:00
e39c470bbc
spi_flash: fix bitbang with spi_width=1
2016-12-26 14:11:49 +01:00
b81839bf1a
Raise AttributeError.
...
Makes hasattr work correctly.
2016-12-23 11:14:18 +01:00
284c94f1d3
Fix Makefile dependency inclusion for other software.
2016-12-19 14:29:33 +01:00
ffc342f49c
Merge pull request #11 from mithro/file-dont-change
...
Only require rebuild on actual changes
2016-12-17 14:43:34 +01:00
1f6dc446d2
Allow CSRElement objects to be autocompleted.
2016-12-17 14:14:53 +01:00
722edfe9e8
Provide csr_data_width via the constants.
2016-12-17 14:14:53 +01:00
8bccd2d988
bios: Include dependency rebuild info.
2016-12-17 14:14:14 +01:00
46bbec5494
main.o is not a phony target.
2016-12-15 19:56:58 +01:00
4522157ddd
Use write_to_file helper.
2016-12-15 19:51:36 +01:00
8179a9ea2e
Don't modify file if contents hasn't changed.
2016-12-15 19:14:12 +01:00
9d716def9d
Make the csv directory if it doesn't exist.
2016-12-15 17:19:51 +01:00
8b5166f294
litex/boards: add machxo3 starter kit platform
2016-12-02 17:28:32 +01:00
873e50430e
litex/build: move xcf_template to platform (xcf is specific to platform)
2016-12-02 17:23:40 +01:00
daa9473809
soc/software/bios/main: revision command becomes ident
2016-11-30 15:45:06 +01:00
0f57451f30
soc/software/bios: remove dataflow
2016-11-30 15:44:30 +01:00
460185fa8e
litex_term: nicer progress bar
2016-11-30 15:36:13 +01:00
4f3ce6db2b
build/xilinx/vivado: fix settings source on linux
2016-11-30 15:28:38 +01:00
7bb2be41e8
Merge pull request #9 from mithro/vprintf-fix
...
libbase: Adding missing vprintf function.
2016-10-30 09:43:43 +01:00
548fd33d20
libbase: Adding missing vprintf function.
...
Fixes #8 .
```
int vprintf(const char *format, va_list ap);
The functions vprintf(), vfprintf(), vsprintf(), vsnprintf() are equivalent to
the functions printf(), fprintf(), sprintf(), snprintf(), respectively, except
that they are called with a va_list instead of a variable number of
arguments.
```
2016-10-30 16:25:06 +11:00
35ba9cf735
soc/software/Makefile: Fix Makefile depend generation.
...
Previously the flags were not actually set and the *.d files were never
actually generated.
2016-10-28 01:25:47 +11:00
7a9cf57cfe
boards/targets/sim: fix
2016-10-14 17:49:04 +02:00
677243bd8c
ElasticBuffer: infer reset
2016-10-14 09:43:09 +02:00
4362e5c528
gen/genlib/cdc: add ElasticBuffer
2016-10-13 17:04:39 +02:00
b74132f563
boards/platforms: add papilio_pro
2016-09-01 16:27:49 +02:00
99f2e31b2e
soc/tools/remote: allow direct use of comm_udp and some fixes
2016-07-18 17:04:58 +02:00
d59757eb4a
build/xilinx/ise: remove debug print
2016-06-29 23:32:43 +02:00
9499147bd4
build/xilinx/ise: fix top name
2016-06-29 23:22:57 +02:00
3bb2bc35e2
boards/targets/sim: desactivate refresh for simulation
2016-06-20 16:00:19 +02:00
f193873bb8
soc/tools/remove/comm_uart: limit write bursts to 8 32bits words
2016-05-30 16:16:05 +02:00
6a35337a09
gen/sim/vcd: allow continous update of vcd file and dynamic signals
...
With continous update, VCD header needs to be writen at the beginning of the simulation.
When a new signal is created, we rewrite the header and the content.
2016-05-28 10:25:48 +02:00
fa7ac6c9a2
build/sim/dut_tb: add bottom line on surface to show frame count
2016-05-23 10:20:05 +02:00
65f74959b3
gen/sim/core: add Display support
2016-05-18 15:47:10 +02:00
6fe3e1237d
gen/fhdl/structure: fix Display
2016-05-18 12:41:29 +02:00
36fd466324
build/sim/dut_tb: rename needs to wait
2016-05-12 15:39:51 +02:00
e890a566a9
buid/sim: add vga framebuffer with SDL
2016-05-04 20:17:02 +02:00
55c9c653e0
adapt to litedram changes
2016-05-04 00:59:02 +02:00
7a7b9420e6
soc/integration/soc_dram: sync with litedram
2016-05-03 19:44:33 +02:00
dca8b3c92e
boards/targets/sim: update litedram
2016-05-01 10:26:21 +02:00
69f0035315
gen/fhdl: add Display for debug in simulation
2016-04-29 23:03:43 +02:00
e79b2e3fef
boards/targets: SDRAM modules are now litedram.modules
2016-04-29 19:05:23 +02:00
3d71ba6e66
targets: remove sdram_controller_type parameter (minicon removed)
2016-04-29 17:51:16 +02:00
8c7332e75e
soc/integration/soc_sdram: use new LiteDRAM names
2016-04-29 17:40:55 +02:00
dc52d33fba
soc_sdram: remove minicon support (we will make lasmicon more configurable to reduce ressource usage)
2016-04-29 16:24:24 +02:00
44d766c09f
software/sdram: cleanup artix7 init
2016-04-29 15:55:10 +02:00
66362b1280
move sdram code to litedram ( https://github.com/enjoy-digital/litedram )
2016-04-29 07:45:15 +02:00
42767286ca
gen/fhdl/verilog: add do in reserved_keywords
2016-04-27 17:43:25 +02:00
80d673e502
soc/integration/soc_sdram: always generate L2_SIZE constant
2016-04-27 12:34:18 +02:00
4e451a78d6
soc/software/bios/sdram: add sdrlevel_artix7 (bitslip and delays have to be found manually)
2016-04-27 12:33:44 +02:00
ab8569916b
boards/platforms/arty: use 1.5V and the 16bits instead of only 8bits
2016-04-26 23:29:35 +02:00
e6681bbb9c
soc/interconnect/wishbone: add FlipFlop (should be removed)
2016-04-25 19:14:20 +02:00
b6d8999471
platforms/arty: add missing address pins, was not going to work :(
2016-04-25 16:56:23 +02:00
f6e1c45d57
gen/genlib/record: fix connect
2016-04-21 19:05:01 +02:00
e80cfedd7f
gen/genlib/record: fix connect
2016-04-21 12:16:26 +02:00
9ae16c2f40
boards/platforms/nexys_video: use TDMS_33 on hdmi
2016-04-21 11:13:29 +02:00
3d98be0997
use new Record.connect omit parameter (replace leave_out)
2016-04-21 09:39:21 +02:00
c330e7be49
gen/genlib/record: rename leave_out by omit and add keep parameter to Record.connect
2016-04-21 09:39:12 +02:00
ee378b2557
boards/plaforms/nexys_video: fix hdmi_out pinout
2016-04-19 19:04:05 +02:00
849434c1bd
soc/software/bios: show cpu on first banner line
2016-04-19 09:19:37 +02:00
76bb0ef456
Merge pull request #2 from mithro/master
...
More fixes.
2016-04-19 09:07:23 +02:00
1b9ab2f1fc
soc/integration/cpu_interface: fix clang detection
2016-04-19 08:06:56 +02:00
d9b598368f
Make verilator build output error messages.
2016-04-19 16:02:26 +10:00
8998ae5c92
bios: Print CPU architecture on boot.
2016-04-19 16:02:26 +10:00
e0e56e3655
Merge pull request #1 from mithro/master
...
Bunch of small fixes
2016-04-19 07:49:24 +02:00
514496d744
libcompiler_rt: Fixing Makefile for CPU endianness.
2016-04-19 14:55:01 +10:00
5ba03160ed
soc/cores: fix spi
2016-04-19 06:49:23 +02:00
7b7f1dd68c
Merge branch 'master' of https://github.com/enjoy-digital/litex
2016-04-19 06:05:22 +02:00
e7f3c585b7
Allow using gcc for or1k.
...
* Using CLANG can set by using CLANG=1 or CLANG=0 in the environment.
* or1k continues to default to CLANG if environment is not net.
2016-04-19 14:03:24 +10:00
2f834d0aa2
bios: Use single characters for boot modes.
...
* The function keys never really worked properly.
* Also add commands for the ROM/Flash/etc.
2016-04-19 13:42:56 +10:00
429f533bd0
soc/cores/sdram/settings: simplify modules and fix timing margins computation
2016-04-18 18:22:53 +02:00
41f6408d56
Merge branch 'master' of https://github.com/enjoy-digital/litex
2016-04-15 08:09:42 +02:00
7b3699839e
build/xilinx/ise: use Tim's fix on add_period_constraint and add_false_path_constraint
2016-04-14 21:48:52 +02:00
3d222d9e63
soc/interconnect/dma_lasmi: change endpoint names
2016-04-13 18:28:52 +02:00
fcd8d792a1
Merge branch 'master' of https://github.com/enjoy-digital/litex
2016-04-13 01:19:21 +02:00
6e0045e6be
soc/integration/soc_sdram: allow passing controller settings in register_sdram
2016-04-12 20:16:47 +02:00
40eb779e67
software/include/base: fix system.h for or1k
2016-04-10 17:21:54 +02:00
238d69f186
software/common: use -std=gnu99 for GCC
2016-04-10 17:21:17 +02:00
b2eaf412c1
soc/interconnect/stream/PipelinedActor: add latency attribute
2016-04-07 12:10:32 +02:00
9fa9bdcf68
build/sim: adapt verilator simulation to new stream signals
2016-04-07 08:56:53 +02:00
8ced064160
soc/software/libcompiler_rt: fix mulsi3 compilation
2016-04-07 08:28:38 +02:00
80d78698e3
soc/software/libnet/microudp: fix debug flag
2016-04-07 08:28:38 +02:00
454d5d13e2
soc/software: fix libcompiler_rt mulsi3.c compile
2016-04-04 08:36:23 +02:00
17f6cb1f17
initial RISC-V support (with picorv32), still some software to do (manage IRQ, L2 cache flush)
2016-04-01 00:09:17 +02:00
7e62cdf601
soc/software/bios: update default ip addresses (local: 192.168.1.50 / remote: 192.168.1.100)
2016-03-31 10:55:11 +02:00
1d4f44e7db
soc/interconnect/stream_sim: add more genericity to PacketStreamer/PacketLogger to use them for all cores
2016-03-31 00:02:22 +02:00
b8d89535fd
soc/cores/sdram/phy: fix S6QuarterRateDDRPHY
2016-03-29 14:59:30 +02:00
f512971d9e
gen/sim: hack to update vcd output file during simulation (allow visualizing progress directly and having a vcd file even when simulation fails or doesn't stop)
2016-03-25 13:22:26 +01:00
0ef1d44c44
gen/sim, fhdl: remove port.we_granularity limitation on simulations
...
We have to find a way to eliminate all replaced memory ports from specials,
here we use a workaround and remove remaining _MemPorts before simulating.
If possible, proper way would be to remove replaced ports from specials.
Another solution can to remove all ports that are no longer associated with
a Memory.
2016-03-23 09:46:54 +01:00
9517b9b870
soc/interconnect/stream_sim: use passive generators and some cleanup
2016-03-23 01:04:33 +01:00
5e16516706
gen: add missing sim files
2016-03-21 23:52:52 +01:00
dd2397b57c
gen: remove vpi (no longer used)
2016-03-21 20:07:03 +01:00
cf29ee0b91
soc/interconnect/stream_sim: adapt to new simulator
2016-03-21 19:56:43 +01:00
703b30e078
gen/build: merge with migen 0575c749e35a7180f0dca408e426af8eef22b568 and reintegrate migen simulator
...
* fhdl/visit: determinism
* structure/Case/makedefault: fix corner cases
* fhdl/tools: apply lowerer to specials in deterministic order
* fhdl/verilog: fix variable name conflict
* fhdl/verilog: simpler names for IOs. Closes #40
* fhdl/namer: deterministic naming of signals with name_override
* use https url for m-labs.hk
* pipistrello: make PMOD an extension header
* vivado: find clock nets by get_nets, not get_ports
* build: support platform-independent false path designation
* sim: add more signals to VCD (#36 )
* build/xilinx: fix error message when Xilinx toolchain directory exists but does not contain a ISE version directory. Closes #39
* kc705: make xadc an extension header
* kc705: add xadc/ams gpios
* Merge branch 'master' of github.com:m-labs/migen
* conda: fix for conda-build > 1.19
* platforms/kc705: enable on-die termination for user_sma_clock
* README: update
* Revert "conda: use BUILDNUMBER from environment."
This reverts commit b2eedfd2e24f0b83c2fb118a3f98cf349b256e91.
* conda: use BUILDNUMBER from environment.
* typo
* Exception now has helpful string.
* README: remove outdated build badge
* sim: run MemoryToArray before lowering specials
* fhdl/simplify/MemoryToArray: remove spurious memory ports from specials
* sim: make unlowered specials an error
* sim: lower specials, closes #34
* sim: support evaluating Replicate()
* Revert "README.md->rst"
* Prevent backslashes in (Windows) paths from being escaped by OpenOCD's TCL implementation.
* Revert "conda: run tests as a part of package build."
* Revert "setuptools: include examples as migen.examples."
* Revert "test: also look for examples in [.../dist-packages]/migen/examples/."
* conda: use source from the current checkout.
* travis: disable (superseded by our buildbot).
* test: also look for examples in [.../dist-packages]/migen/examples/.
* setuptools: include examples as migen.examples.
* conda: run tests as a part of package build.
* build: return to current working directory after building
* sim/vcd: support signals not appearing in FHDL
* sim: deterministic clock iteration
* sim: add support for passive generators
* fhdl/structure: fix last test in _Value.__bool__ (a instead of b)
2016-03-21 19:15:40 +01:00
71a719be44
soc/interconnect/stream: use valid/ready/last signals instead of stb/ack/eop (similar to AXI)
2016-03-16 20:13:47 +01:00
9032665750
soc/interconnect/wishbonebridge: fix import
2016-03-16 19:34:50 +01:00
d7112efdba
soc/interconnect/stream_packet: remove Buffer (we will use simple fifo for now)
2016-03-16 19:33:29 +01:00
39aacf2df4
soc/interconnect/stream: remove busy signal, BufferizeEndpoints refactoring
2016-03-16 19:33:00 +01:00
e0e2427795
soc: replace all Sink/Source with stream.Endpoint
2016-03-16 18:05:57 +01:00
c860581b86
soc/interconnect/stream: use new Converter/StrideConverter
2016-03-16 17:00:58 +01:00
8c272c1f6f
soc/interconnect/stream: fix missing param
2016-03-16 16:21:32 +01:00
cb47373383
soc/interconnect/stream: remove packetized parameter and use of sop
2016-03-16 11:54:28 +01:00
44a5b95281
soc/interconnect/stream: set packetized to True by default (we are going to remove this parameter)
2016-03-15 15:52:57 +01:00
a016ededa0
soc/integration/builder: remove use of symlinks (simply use make -C dst_dir -f src_dir/Makefile, thanks robert)
2016-03-04 20:56:05 +01:00
042c36ee1b
soc/tools/litex_term: continue cleanup
2016-02-19 17:44:25 +01:00
2fa848c15f
soc/tools/litex_term: continue cleanup
2016-02-19 14:35:18 +01:00
247ecc5d8a
soc/tools/litex_term: continue cleanup
2016-02-19 13:38:34 +01:00
ed2e623994
soc/tools/litex_term: remove write_exact, use more bytes
2016-02-19 00:20:10 +01:00
4bdefbdfba
soc/tools/litex_term: remove character function
2016-02-19 00:02:38 +01:00
5b8566d20f
soc/tools/litex_term: replace get_file_data with f.read()
2016-02-18 23:55:41 +01:00
68c2d3b7a0
soc/tools/remove: fix import
2016-02-18 12:55:18 +01:00
fd2997bf4a
build/xilinx: cleanup Vivado/ISE special_overrides
2016-02-18 00:36:53 +01:00
8ee3874088
soc/integration/soc_core: instanciate wishbone/csr/interrupts only if we have at least a wishbone master
2016-02-18 00:11:25 +01:00
34b45e3618
gen/build: use verilog 2001-style synthesis attributes for vivado (will need rework)
2016-02-11 22:54:26 +01:00
2218ece98a
soc/interconnect/stream: fix merge issue (missing params connect)
2016-02-01 00:08:27 +01:00
6c71811138
soc/tools/litex_term: also rename inside file
2016-01-16 21:26:33 +01:00
601c91a3e2
soc/tools: rename to litex_term, litex_server, litex_client
2016-01-16 21:22:21 +01:00
162900144a
soc/tools/remove_server: cleanup
2016-01-16 21:12:19 +01:00
b856b54720
soc/tools/flterm: get rid of serial.tools.miniterm import and fix echo on linux
2016-01-16 21:05:03 +01:00
002508a69a
soc/integration: return vns with soc and builder
2016-01-14 17:15:39 +01:00
2c32791a28
soc/software/bios/main: add capability to configure TEST_USER_ABORT_DELAY
2016-01-14 16:53:04 +01:00
492f276247
soc/software/bios/main: give priority to romboot over serialboot/netboot
2016-01-14 16:46:42 +01:00
9913da5ac9
boards/targets: change mode (add +x)
2016-01-01 18:37:20 +01:00
7b879b36c6
soc/tools/remove/server: avoid closing server when client closes connection
2015-12-27 22:33:08 +01:00
0498a31818
some cleanup
...
- remove Sink/Source connect specialization.
- remove use of Record.connect
- use sink/source on Buffer
2015-12-27 13:09:58 +01:00
219fbef26c
soc/tools/remove/client: set socket timeout to 5s
2015-12-27 11:26:58 +01:00
6ea65f957c
soc/interconnect/stream: expose Endpoint
2015-12-19 21:49:45 +01:00
6a4e3bb5c0
build/xilinx/vivado: use build_name as top in synth_design
2015-12-09 11:40:27 +01:00
3191533889
soc/software/libnet: add debug defines on microudp
2015-12-07 12:03:36 +01:00
4fed1cc7a7
soc/integration/builder: move csr_csv generation outside of generate include
...
we mostly use csr_csv for designs without CPU
2015-12-03 15:16:22 +01:00
90f03133ef
build/sim/verilator: add toolchain_path parameter
2015-12-02 15:35:55 +01:00
e8262ed447
build: pass build_name to get_verilog (same name for top module and top level file)
2015-12-02 14:18:09 +01:00
b7a1888a36
gen/fhdl/verilog: add regular comb parameter to allow implementation of simulation code (for icarus)
...
We will remove that when we will be using new migen simulator
2015-12-02 14:16:23 +01:00
646d3b19b4
boards/nexys_video: use ethernet constraints similar to kc705
2015-12-01 11:50:05 +01:00
ca6b9aa6e3
boards/targets: add default rom/ram configuration for arty
2015-12-01 10:20:16 +01:00
e5d35ccb6d
boards/targets: add nexys_video
2015-12-01 10:19:41 +01:00
4bfd1fdce6
boards/plaforms: fix IOStandard of eth_rst_n
2015-11-30 22:27:40 +01:00
b6a6b5d540
boards/platforms: add cpu_reset to nexys_video and some fixes around DDR3
2015-11-30 21:53:01 +01:00
5694dca0fc
boards/platforms: add hdmi_in/hdmi_out/ethernet/dram to nexys_video
2015-11-30 20:46:57 +01:00
7e1df951ba
boards/platforms: add nexys_video (basic)
2015-11-30 20:25:00 +01:00
a716c562f0
gen/build: use name_override for all IOs defined in Platform file (avoid random naming of IOs)
2015-11-30 18:26:33 +01:00
53c86e34f4
build: ensure we return to working directory after building
2015-11-30 13:33:39 +01:00
f6aeb6e41a
soc/interconnect/stream: improve Pipeline to allow passing endpoints
2015-11-28 18:31:47 +01:00
d85d2b7b9b
soc/interconnect/stream_packet: add check of field's width vs signal's width in Header.get_field
2015-11-27 20:14:01 +01:00
c0539fff3e
boards: add new digilent arty
2015-11-27 00:29:30 +01:00
c24727ab4c
soc/integration: allow using builder with soc.cpu_type == None
2015-11-26 17:44:50 +01:00
7298fff1e6
soc/interconnect/stream_packet: fix Counter removing
2015-11-24 20:30:53 +01:00
8ebffc563a
soc/tools/remote/csr_builder: manage memory regions and some fixes on CSRRegister
2015-11-23 19:13:37 +01:00
254504e73f
soc/integration/builder: export constants and memory_regions with csr_csv
2015-11-23 19:12:58 +01:00
f6a2d5847a
soc/tools/remote/client: make csr_csv parameter optional and default value to None
2015-11-23 18:39:28 +01:00
6f4dd14ffa
soc/software/boot: add #ifndef on LOCALIP and REMOTEIP to allow definition in the SoC with add_constant
2015-11-23 11:08:04 +01:00
cb22a207f1
build/generic_platform: add support for int parameter for Pins (useful for core generation)
2015-11-19 14:57:09 +01:00
8056653004
soc/tools/remote/server: add --debug parameter
2015-11-17 15:43:10 +01:00
6870707620
soc/tools/remoter/server: fix exit on KeyboardInterrupt
2015-11-17 15:31:23 +01:00
8ff31557c6
soc/tools/remoter/server: add some printfs
2015-11-17 15:18:46 +01:00
1a92489555
soc/tools/remote: add comm_pcie and comm_udp (to be tested)
2015-11-17 15:07:00 +01:00
d6fdd76930
soc/tools/remote: small cleanup and remove csr_data_width from server side
2015-11-17 11:35:22 +01:00
71483b8935
soc/tools: initialize wishbone remote control (for now only uart)
2015-11-17 01:05:52 +01:00
1cde84dccf
soc/cores/uart remove software (will be re-written and will move to soc/tools)
2015-11-16 17:07:22 +01:00
1f80bb9561
soc/interconnect/stream_packet: remove Counter
2015-11-16 16:53:23 +01:00
ec35290c45
soc/interconnect/wishbonebridge: remove Counter
2015-11-16 16:48:37 +01:00
6fd0b73817
build: remove edif support
2015-11-16 16:26:38 +01:00
e407a1cdda
gen/fhdl/verilog: remove asic_syntax and expose reg_initialization, dummy_signal and blocking_assign
2015-11-16 16:18:09 +01:00
2f52d364af
soc/interconnect/stream/SyncFIFO: expose fifo level
2015-11-16 16:11:31 +01:00
7ed2576ce1
soc/integration/cpu_interface: add bases, constants and memories output to csv files
2015-11-15 00:04:44 +01:00
af909b43d5
soc/cores/uart: add UARTWishboneBridgeDriver software
2015-11-14 21:23:20 +01:00
3a2e6117f4
soc/interconnect/stream: add Cast and others small fixes
2015-11-14 12:17:09 +01:00
041483dbe1
soc/integration/builder: only copy Makefiles when not using symlinks
2015-11-14 03:36:46 +01:00
a2aa5726bf
soc/cores: remove liteeth_mini and use liteeth
2015-11-14 03:22:43 +01:00
16ba646b1b
add TODOs
2015-11-14 03:15:10 +01:00
cf4c7da2e7
fix soc/integration/soc_core.py
2015-11-14 02:44:12 +01:00
032f5a9620
soc/interconnect: add stream_sim
2015-11-14 00:43:49 +01:00
ba959c832d
soc/interconnect: rename packet to stream_packet
2015-11-14 00:42:58 +01:00
fc3ffe87ac
for now use our fork of migen (to be able to simulate our designs)
2015-11-13 18:31:46 +01:00
ae3d54499a
litex/gen: reintegrate migen with modifications to be able to simulate with vpi until all missing features of the new simulator are implemented
2015-11-13 14:44:16 +01:00
7d6cee6751
soc/interconnect/stream: add BufferizeEndpoints
2015-11-12 18:54:15 +01:00
83427c87cd
soc/interconnect/stream: add Pipeline
2015-11-12 01:41:23 +01:00
81c6facca2
soc/interconnect/stream: reintroduce params
2015-11-12 01:12:15 +01:00
f6b30fcae2
soc/interconnect: add packet
2015-11-12 00:54:40 +01:00
525da89c7d
soc/interconnect: add wishbonebridge and uart bridge
2015-11-12 00:52:36 +01:00
89b189ce4a
soc/interconnect/stream: reintroduce PipelinedActor/Buffer
2015-11-12 00:51:32 +01:00
194e6137ae
soc/integration/soc_core: add support for SoCs without CPU
2015-11-12 00:50:23 +01:00
c076c2cbd6
boards/targets: remove papilio_pro/pipistrello
2015-11-11 17:38:03 +01:00
352cb91688
soc/integration/builder: add use_symlinks parameter and desactivate symlinks by default
...
On windows machines, console need to be run as Administrator to create symlinks which is bit painful.
2015-11-11 17:37:28 +01:00
1cec0f8086
boards/targets/sim: add ethernet support
2015-11-11 14:23:39 +01:00
1f6983da2c
soc/cores/liteeth_mini: add phy model for verilator simulation
2015-11-11 14:22:27 +01:00
481163b233
soc/cores: reintroduce liteeth_mini (until we switch to liteeth)
2015-11-11 14:01:48 +01:00
714a3d88e2
add LICENSE, update copyrights, add Migen install instructions
2015-11-11 13:22:39 +01:00
bda196fbc8
soc/software/bios/sdram: split memtest and allow external #define of memtest sizes
2015-11-11 13:10:03 +01:00
619cd8e695
avoid forking migen, we will add custom modules in litex/gen but will use upstream migen for common modules
2015-11-11 12:10:55 +01:00
3f43a49382
soc: merge with misoc 3fcc4f116c3292020cb811d179e45ae45990101b
...
changes:
-software/bios: remove dataflow
-cores/identifier: replace with user-defined string
-interconnect/CSRBankArray: support read-only mappings
-targets: Added Numato Mimas V2 target
-Our libunwind changes were merged upstream.
-wishbone: update TODO
-replace Counter in Converters
-Fix CSRBankArray
-flterm: properly exit on ^C.
2015-11-10 16:51:51 +01:00
3297210e48
boards/targets/sim: get SDRAM working in simulation with sdram/model
2015-11-10 12:57:23 +01:00
4afe4a07e4
soc/software: remove memtest (should be re-written)
2015-11-10 12:22:08 +01:00
6764c06b62
soc/sofware: remove libdyld
2015-11-10 12:21:23 +01:00
f72e172ac3
soc/software: remove libunwind
2015-11-10 12:16:34 +01:00
85e6716b6b
litex/build/xilinx/programmer: remove UrJTAG and Adept
2015-11-10 12:01:25 +01:00
a775672314
litex: get verilator simulation working and add sim target as example
2015-11-07 23:51:37 +01:00
6a0f85dc42
litex: reorganize things, first work working version
2015-11-07 17:48:55 +01:00
637634f312
import migen in litex/gen
2015-11-07 12:22:32 +01:00
b028569784
import misoc in litex/soc
2015-11-07 12:19:30 +01:00
Florent Kermarrec
Tim 'mithro' Ansell
Stafford Horne
William D. Jones
Sean Cross
Jean-François Nguyen
Jean-François Nguyen
Jean-François Nguyen
Peter Gielda
bunnie
Deano Calver
Dolu1990
Sergiusz Bazanski
Paul Schulz
Ewen McNeill
Felix Held
Chris Ballance
Tim 'mithro' Ansell
Greg Darke
Pierre-Olivier Vauboin
Joel Addison
Sebastien Bourdeauducq
whitequark
Robert Jordens