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2266 commits 9 branches 14 tags 12 MiB
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1331 commits

Author SHA1 Message Date
Sylvain Munaut
b3caabcca3 di_adrv2crr_fmc: Bump PCIe to 8 lanes 
There used to be an issue with 8 lanes litepcie USP for that board
when it was first added, but it's been solved now, so might as well
use all the available lanes

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2024-02-05 11:43:02 +01:00
Sylvain Munaut
2264df8a0a adi_adrv2crr_fmc: Speedgrade of the PLL is -2 
Speedgrade of the chip was updated in a previous commit, but
I forgot to update the PLL too

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2024-02-05 11:42:14 +01:00
Ruurd Keizer
66152390ba Add support for QMTech Kintex 7 Development board 2024-02-01 16:16:01 +01:00
John Simons
741082e5ee
Merge branch 'litex-hub:master' into axau15_update 2024-01-27 03:28:28 +01:00
John Simons
721fa0b4b3 axau15: added more FMC+ pins and made some corrrections 2024-01-27 03:27:48 +01:00
Florent Kermarrec
39dc0b36a4 sipeed_tang_mega_138k: Fix build with ethernet and local/remote ip indent. 2024-01-22 13:20:07 +01:00
Florent Kermarrec
261c61cf62 targets/sipeed_tang_nano_4k: Remove commited spiflash.o. 2024-01-14 11:24:18 +01:00
Florent Kermarrec
926d54cb41 sipeed_tang_nano_4k: Switch to LiteX's UART and expose hyperram parameter. 2024-01-11 13:54:44 +01:00
Florent Kermarrec
688a020f35 sipeed_tang_meta_138k: Add gowin_ae350 CPU initial support. 
./sipeed_tang_mega_138k.py --cpu-type=gowin_ae350  --build --flash
        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2024 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Jan 11 2024 12:37:50
 BIOS CRC passed (0efaefbe)

 LiteX git sha1: e689aab1

--=============== SoC ==================--
CPU:		Gowin AE350 @ 800MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		128.0KiB
SRAM:		8.0KiB


--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex> ident
Ident: LiteX SoC on Tang Mega 138K 2024-01-11 12:37:47
 2024-01-11 13:17:05 +01:00
enjoy-digital
52f9f0f107
Merge pull request #555 from machdyne/master 
add support for minze board
 2024-01-07 08:10:51 +01:00
Florent Kermarrec
52aeec00d7 sipeed_tang_nano_4k: Remove note since openFPGALoader regression has been fixed. 2024-01-04 18:29:31 +01:00
Florent Kermarrec
c0a98a6b9d targets/sipeed_tang_nano_4k: Directly integrate flashing of EMCU flash. 
Ex to build/flash bitstream + firmware with EMCU:
./sipeed_tang_nano_4k.py --cpu-type=gowin_emcu --build --flash
 2024-01-03 13:07:44 +01:00
Florent Kermarrec
55ade3b2df sipeed_tang_nano_4k: Minor cleanup/add comments. 2024-01-02 13:42:56 +01:00
inc
fd59d954ba add support for minze board 2023-12-29 06:01:59 +01:00
Florent Kermarrec
982038508e alinx_axau15/PCIe: Switch to Gen3/128-bit for now (configuration used on others Ultrascale+ Gen3 X4 boards). 2023-12-28 19:56:52 +01:00
Florent Kermarrec
e229d1a0b6 alinx_axau15: First review/cleanup pass and fix missing INTERNAL_VREF on bank 66. 2023-12-28 19:48:50 +01:00
enjoy-digital
b340d9e5e7
Merge pull request #550 from Johnsel/master 
alinx_axau15: Added new Alinx Artix US+ board
 2023-12-28 19:24:14 +01:00
inc
754b6d2427 add support for mozart ml1 2023-12-19 22:18:21 +01:00
Gwenhael Goavec-Merou
e8bc9fa81d targets/sipeed_tang_nano_4k: adding description to write Gowin EMCU firmware 2023-12-14 13:24:57 +01:00
John Simons
2c2b3e318a Fixed pinout and first steps adding PCIe support 2023-12-12 15:44:51 +01:00
John Simons
ab60d91138 alinx_axau15: Fixed minor clock and sdcard reference issues 2023-12-05 21:14:57 +01:00
John Simons
7be052911b alinx_axau15: Added new Alinx Artix US+ board 2023-12-05 20:45:57 +01:00
Florent Kermarrec
6333fbe724 targets/siglent_sds1104xe: Update with new LiteX Ethernet/Etherbone integration. 2023-11-13 09:02:09 +01:00
Florent Kermarrec
1969b4f6d3 siglent_sds1104xe: Update Ethernet/Etherbone integration. 2023-11-10 18:58:42 +01:00
Gwenhael Goavec-Merou
fd36608438 sipeed_tang_mega_138k: fix pins DRIVE, remove a[15], fix memory model 2023-11-10 07:39:19 +01:00
enjoy-digital
17a0152ef9
Merge pull request #547 from trabucayre/tangMega138k 
Tang mega138k
 2023-11-09 11:56:58 +01:00
Gwenhael Goavec-Merou
4ff1362e5b targets,platforms/sipeed_tang_mega_138k: fix copyright 2023-11-09 11:55:35 +01:00
Florent Kermarrec
8e3dc21ce5 aliexpress_xc7k70t: Review/Cleanup. 
- Cosmetic cleanups in platform.
- Add clk50 constraint.
- Remove JTAGBone specific support since now directly handled by LiteX.
 2023-11-09 08:26:06 +01:00
Hans Baier
69ee48d421 Add AliExpress Kintex XC7K70T board 2023-11-09 10:34:18 +07:00
Gwenhael Goavec-Merou
2c52ce0c47 targets/sipeed_tang_mega_138k: fix SDRAM (requires Mister XSDS v3.0 extension) 2023-11-08 07:13:28 +01:00
Gwenhael Goavec-Merou
e9f53685fe targets/sipeed_tang_mega_138k: DDR3 support (not working) 2023-11-08 07:00:24 +01:00
Florent Kermarrec
bc74eeca78 targets/digilent_nexys_video: Use reset_buf on sys_clk's create_clkout to improve timings and demonstrate use. 2023-11-07 13:22:30 +01:00
Florent Kermarrec
c7ad9adacb terasic_de2_115: Cosmetic cleanup. 2023-11-06 19:21:53 +01:00
enjoy-digital
d8228c2c0f
Merge pull request #544 from madprogrammer/master 
Improve terasic_de2_115 target support
 2023-11-06 19:17:54 +01:00
Gwenhael Goavec-Merou
e23ac0251a targets/sipeed_tang_mega_138k: HDMI support 2023-11-05 16:36:59 +01:00
Florent Kermarrec
8792dd8e53 target/analog_pocket: Remove debug (Will be investigated externally). 2023-10-27 15:32:36 +02:00
Sergey Anufrienko
ce951589d1 improve terasic_de2_115 target support 2023-10-23 21:15:00 +03:00
Florent Kermarrec
0d560bc240 targets/siglent_sds1104xe: Review. 2023-10-23 19:25:12 +02:00
enjoy-digital
71d8b17fff
Merge pull request #543 from trabucayre/siglent_sds1104xe_etherbone 
targets/siglent_sds1104xe: simplify etherbone by using new etherbone's params to specify hybrid mode
 2023-10-23 19:20:32 +02:00
Gwenhael Goavec-Merou
26d112b094 targets/siglent_sds1104xe: simplify etherbone by using new etherbone's params to specify hybrid mode 2023-10-23 19:07:37 +02:00
Gwenhael Goavec-Merou
afbf9eb8c9 target/xxx: remove with-uartbone, add_uartbone and deal with case where uartbone is required inconditionnally 2023-10-23 17:43:13 +02:00
Gwenhael Goavec-Merou
a6f3c5276e target/xxx: remove with-jtagbone, add_jtagbone and deal with case where jtagbone is required inconditionnally 2023-10-23 17:16:57 +02:00
Gwenhael Goavec-Merou
a4fc45bba6 targets/efinix_titanium_ti60_f225_dev_kit: adding jtagbone support (litex_server --jtag --jtag-config openocd_titanium_ft4232.cfg) 2023-10-18 09:11:54 +02:00
Florent Kermarrec
eae62a60ac target/analog_pocket: Fix. 2023-10-17 21:40:46 +02:00
Florent Kermarrec
cc19078650 targets/analog_pocket: Disable debug for CI. 2023-10-17 15:23:58 +02:00
Florent Kermarrec
f86ba2dea0 targets/analog_pocket: Add debug code for framebuffer (wip). 2023-10-17 13:18:07 +02:00
Gwenhael Goavec-Merou
9ae224a2a7 sipeed_tang_primer_25k: new board 2023-10-17 07:45:40 +02:00
enjoy-digital
3a75f6cf79
Merge pull request #537 from rniwase/master 
xilinx_zcu102: Add pin definitions for DDR4 SDRAM and FMC connectors, add litedram to the target.
 2023-10-14 20:14:53 +02:00
rniwase
9fb388407a targets/xilinx_zcu102: Add litedram to the target. 2023-10-14 00:00:26 +09:00
darryln
e0e8600db4 fix help text 2023-10-12 11:21:20 -04:00
Florent Kermarrec
ec2f9480b8 targets/analog_pocket: Fix indent on videophy/cores. 2023-10-09 11:59:32 +02:00
Florent Kermarrec
6386f290e9 targets/analog_pocket: Add --video-colorbars/video-terminal/video-framebuffer arguments. 2023-10-09 10:59:15 +02:00
Florent Kermarrec
dec25b7ce9 targets/analog_pocket: Add initial Video support. 
From https://github.com/tpwrules/pocket_linux.
 2023-10-09 10:14:00 +02:00
Florent Kermarrec
7359a331eb analog_pocket: Add 1:2 (HalfRate) SDRAM support. 2023-10-06 19:25:42 +02:00
Florent Kermarrec
d00810c983 sds1104xe: Fix typo. 2023-10-06 19:25:22 +02:00
Florent Kermarrec
3d7a1dd152 analog_pocket: +x. 2023-10-02 16:20:09 +02:00
Florent Kermarrec
fd6aee0250 targets/sqrl_acorn: Drive pcie_clkreq_n (Thanks @myftptoyman). 2023-09-27 11:06:50 +02:00
enjoy-digital
29018a8382
Merge pull request #523 from Icenowy/tangmega138k 
[RFC] sipeed_tang_mega_138k: new board
 2023-09-26 19:12:44 +02:00
Florent Kermarrec
3df677cfeb Add initial Analog Pocket platform/target with Clk/SDRAM, able to run a simple SoC with SDRAM over JTAG-UART. 
$ ./analog_pocket.py --uart-name=jtag_uart --build --load
$ litex_term jtag --jtag-config=openocd_usb_blaster.cfg

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2023 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Sep 21 2023 08:53:57
 BIOS CRC passed (1e2b3f44)

 LiteX git sha1: 7d738737

--=============== SoC ==================--
CPU:		VexRiscv @ 50MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		128.0KiB
SRAM:		8.0KiB
L2:		8.0KiB
SDRAM:		64.0MiB 16-bit @ 50MT/s (CL-2 CWL-2)
MAIN-RAM:	64.0MiB

--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
  Write: 0x40000000-0x40200000 2.0MiB
   Read: 0x40000000-0x40200000 2.0MiB
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
  Write speed: 15.6MiB/s
   Read speed: 22.1MiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex>
 2023-09-21 09:19:57 +02:00
Florent Kermarrec
5064c65dac targets: Switch to openocd_usb_blaster/2.cfg. 2023-09-21 09:16:24 +02:00
Florent Kermarrec
b92c96b3a4 colorlight_i9plus: Cosmetic cleanups. 2023-08-30 17:22:11 +02:00
enjoy-digital
3471617878
Merge pull request #502 from chmousset/add_colorlight_i9plus 
[init] added colorlight i9+ based on XC7A50 FPGA
 2023-08-30 16:54:26 +02:00
Florent Kermarrec
c960e85d11 targets/efinix: Now rely in LiteX to automatically exclude Tristate IOs. 2023-08-30 09:59:23 +02:00
Florent Kermarrec
4bb064853d targets/efinix: Update RGMII PHYs (IOs are now directly excluded in PHYs). 2023-08-30 08:56:20 +02:00
Florent Kermarrec
347b477b07 sipeed_tang_primer_20k: Fix DDR3 module, SoC reset and remove DDR3 debug code. 
Now passing memtest with valid reported memory size:

       __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2023 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS CRC passed (d32a9529)

 LiteX git sha1: 85dadb82

--=============== SoC ==================--
CPU:		VexRiscv SMP-LINUX @ 48MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		64.0KiB
SRAM:		6.0KiB
L2:		512B
SDRAM:		128.0MiB 16-bit @ 192MT/s (CL-6 CWL-5)
MAIN-RAM:	128.0MiB

--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Read leveling:
  m0, b00: |00000000| delays: -
  m0, b01: |00000000| delays: -
  m0, b02: |01100000| delays: 01+-00
  m0, b03: |00000000| delays: -
  best: m0, b02 delays: 01+-00
  m1, b00: |00000000| delays: -
  m1, b01: |00000000| delays: -
  m1, b02: |01100000| delays: 01+-00
  m1, b03: |00000000| delays: -
  best: m1, b02 delays: 01+-00
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
  Write: 0x40000000-0x40200000 2.0MiB
   Read: 0x40000000-0x40200000 2.0MiB
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
  Write speed: 11.7MiB/s
   Read speed: 17.4MiB/s
 2023-08-29 16:50:17 +02:00
enjoy-digital
4862d0667c
Merge pull request #515 from josuah/crosslink_nx_openocd 
Allow use of OpenOCD for the Crosslink-NX
 2023-08-28 16:35:20 +02:00
enjoy-digital
232e829b8f
Merge branch 'master' into crosslink_nx_main_ram 2023-08-28 16:34:27 +02:00
enjoy-digital
a9ecbffe8f
Merge pull request #520 from josuah/crosslink_nx_prog_flash 
targets/lattice_crosslink_nx_evn: fix arguments in flash programming
 2023-08-28 16:33:23 +02:00
enjoy-digital
2c3d77b5be
Merge branch 'master' into crosslink_nx_spi_flash 2023-08-28 16:32:37 +02:00
Josuah Demangeon
a5a6a313cc targets/lattice_crosslink_nx_evn: add main_ram section for firmware 
This takes the values from the Antmicro SDI MIPI converter as a model
and is enough to run a Zephyr hello world, but not seemingly enough for
a the Zephyr Shell sample.

Related: https://github.com/litex-hub/zephyr-on-litex-vexriscv/pull/13
 2023-08-18 19:56:58 +02:00
Icenowy Zheng
ebfb9b8e01 sipeed_tang_mega_138k: new board 
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2023-08-15 16:33:13 +08:00
Josuah Demangeon
2e5c6eb7a7 platforms/crosslink_nx_evn: add SPI flash support 2023-08-11 16:46:52 +02:00
Josuah Demangeon
1a46bcce5e targets/lattice_crosslink_nx_evn: fix arguments in flash programming 2023-08-10 14:39:01 +02:00
Josuah Demangeon
3c0b6956cc platforms/crosslink_nx_evn: Fix 5412d0e always disabling uartbone 
Also fix a warning about register_mem being deprecated, taking
inspiration from platforms/crosslink_nx_vip
 2023-08-09 18:07:13 +02:00
Josuah Demangeon
8172a304b3 platforms/crosslink_nx_evn: allow use of OpenOCD 2023-08-08 23:25:41 +02:00
enjoy-digital
3903cdee92
Merge pull request #517 from bayi/master 
Digilent CMOD A7 ISSIRAM fix
 2023-08-08 19:29:32 +02:00
Bayi
4362cb23a1
Fix Digilent Cmod A7 ISSIRAM reading 2023-08-05 19:56:32 +02:00
Bayi
a6b025f7f3
Fix Digilent Cmod A7 ISSIRAM reading 2023-08-05 19:56:15 +02:00
Josuah Demangeon
5412d0e0e9 platforms/crosslink_nx_evn: allow use of UARTBone 
This goes along a small resistor jumper modification and firmware flashing like
it is for the ECP5 board. A warning message is added as the default serial might
be affected (--serial serial by default). The FTDI modification software used
for the ECP5 seems to be requried and matching.

This can be tested this way:
targets/lattice_crosslink_nx_evn.py --csr-csv=csr.csv --toolchain=oxide --programmer=openocd --uart-name crossover+uartbone --build --load
litex_server --uart --uart-port /dev/ttyUSB1
litex_cli --regs
 2023-08-04 20:47:32 +02:00
Florent Kermarrec
efc15a91a9 global: Use new WaitTimer integrated cast to int. 2023-08-01 14:56:35 +02:00
Josuah Demangeon
cbcf6df26f lattice_ecp5_evn: add_jtagbone flag 
This follows https://github.com/enjoy-digital/litex/pull/1087 which
allows using the built-in JTAG for both the FPGA programming and the
internal core of the FPGA.
 2023-07-31 13:53:24 +02:00
Florent Kermarrec
2d3b81a532 efinix_trion_t120_bga576: Add Ethernet through RGMII PMOD and switch to it. 
See https://github.com/enjoy-digital/liteeth/issues/66#issuecomment-859366899 for the PMOD.
 2023-07-27 11:52:40 +02:00
Florent Kermarrec
c1088befe5 targets/CRG: Add rst signal when missing. 
Allow properly reseting the PLL from the SoC.
 2023-07-26 16:56:27 +02:00
Florent Kermarrec
ce121663ff targets/uartbone: Update with LiteX change. 2023-07-20 15:42:47 +02:00
Florent Kermarrec
18a3909a9c global: Switch to litex.gen.genlib.misc. 2023-07-06 22:11:45 +02:00
Florent Kermarrec
67be3ab677 targets: +x on alchitry_cu and vcu128. 2023-07-06 13:29:35 +02:00
Mark1626
e9335cd67a
Fix pins in Alchitry Cu platform, add target for Alchitry Cu 2023-06-27 21:35:55 +05:30
Florent Kermarrec
58805f037c avnet_aesku40: Expose ethernet/etherbone parameters. 
To be able to test more easily usrgmii build.
 2023-06-13 09:26:07 +02:00
Ilya Ostrovskiy
4705a0274e
Support SPI Flash in Colorlight 5A-75x 2023-06-09 13:43:34 -04:00
Hans Baier
765ee1a3ce sitlinv_stlv7325_v2: VCCIO jumper default factory setting is 3.3V 2023-06-07 10:12:55 +07:00
Florent Kermarrec
8a263c18f2 sitlinv_stlv7325: Rename to v1 and update VCCIO to fix --with-pcie generation. 2023-05-30 10:39:20 +02:00
Chen
2ae2dfa6a3
Add vcu128 target (#497) 
Add initial VCU128 support.
 2023-05-25 22:25:44 +02:00
Florent Kermarrec
e59d75f593 qmtech_xc7k325t: Fix build/CI. 2023-05-12 12:19:16 +02:00
Florent Kermarrec
ca6b607255 targets/qmtech: Add missing +x. 2023-05-12 12:09:20 +02:00
Hans Baier
550bc0eee5 add QMTech XC7K325T board, add seven segment display to daughterboard 2023-05-08 11:51:51 +07:00
Hans Baier
187080228c add qmtech_xc7l325t 2023-05-08 05:17:35 +07:00
Florent Kermarrec
d33cf1a74c mnt_rkx7: Cosmetic cleanups. 2023-05-05 09:48:06 +02:00
Florent Kermarrec
c05c494a82 targets/mnt_rkx7/usb_ohci: Use SoC.bus if SoC does not have a DMA bus. 2023-05-05 09:43:19 +02:00
enjoy-digital
6144966d24
Merge pull request #501 from mntmn/master 
mnt_rkx7: RGB and USB fix, add HDMI terminal
 2023-05-05 09:37:40 +02:00
enjoy-digital
9c222454cc
Merge pull request #503 from chmousset/add_colorlight_i5a-907 
Add colorlight i5a 907
 2023-05-03 09:50:26 +02:00
Gabriel Somlo
2bff2d4260 target/stlv7325-v2: tune eth phy delay 2023-05-01 09:28:03 -04:00
Charles-Henri Mousset
31c680abf8
[enh] added option for uartbone 2023-04-30 09:42:31 +02:00
Charles-Henri Mousset
874532871f
[enh] taking advantage of pins directly connected 2023-04-30 09:24:49 +02:00
Charles-Henri Mousset
1202c387bf
[init] added colorlight i5a-907 support 2023-04-30 09:24:46 +02:00
Charles-Henri Mousset
fd5511f3fd
[fix] add pmod uart in default config 2023-04-30 09:24:15 +02:00
Charles-Henri Mousset
f5dfdf9abf
[enh] added doc about JTAG and ext. board 2023-04-29 19:39:51 +02:00
Charles-Henri Mousset
322cc5d45b
[init] added colorlight i9+ based on XC7A50 FPGA 2023-04-29 18:36:35 +02:00
Gabriel Somlo
1f6e7f36a5 target/stlv7325-v2: fix typo in eth phy delay 2023-04-28 16:56:37 -04:00
Gabriel Somlo
1185ff51f1 Initial support for STLV7325 (v2) Kintex-7 board. 
This is the 2nd (2023) version of the board sold through
https://www.aliexpress.us/item/3256801088848039.html

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2023-04-28 10:24:21 -04:00
Lukas F. Hartmann
a9e3e3c050 Merge branch 'master' of https://github.com/litex-hub/litex-boards 2023-04-25 20:29:11 +02:00
Lukas F. Hartmann
17a5d3c130 mnt_rkx7: add HDMI terminal, default USB to true 2023-04-25 20:27:29 +02:00
offNaria
68bfb325a5
Fix Memory test failure of Alveo U250 2023-04-24 17:35:58 +09:00
Do Viet Thanh
340da5393c Fix Memory initialization of Alveo U200 failed #1606 2023-04-17 18:59:50 +07:00
Richard Tucker
2ed66317c7 efinix_xyloni_dev_kit: fix build error 2023-04-14 22:31:21 +10:00
Hans Baier
c7077880b9 copyright notices on enclustra 2023-04-11 10:29:52 +07:00
Hans Baier
ed947d1b55 enclustra: add baseboard ST1 2023-04-11 10:29:44 +07:00
enjoy-digital
a8eb0b20c1
Merge pull request #491 from hansfbaier/stlv7325-hdmi 
STL7325: Add Video, and connectors (FMC, BTB, 2.54mm)
 2023-04-07 09:06:55 +02:00
Hans Baier
2f13decc49 stlv7325: make VCCIO configurable 2023-04-07 09:27:03 +07:00
Hans Baier
566a753dd3 stlv7325: S7PLL is enough 2023-04-07 08:45:06 +07:00
Hans Baier
7c99f0758d stlv7325: fix video args 2023-04-07 08:35:49 +07:00
Hans Baier
66cbd27bbf stlv7325: fix video PHY 2023-04-07 08:25:59 +07:00
Hans Baier
5067a2683f sitlinv_stlv7325: add video HDMI, enable compressed bitstream 2023-04-07 07:31:42 +07:00
Hans Baier
43ce24dcb3 add QMTech 5CEFA5 Cyclone V board support 2023-04-06 18:27:51 +07:00
enjoy-digital
a4925d14f9
Merge pull request #488 from Icenowy/stlv7325-s7pll 
sitlinv_stlv7325: use S7PLL instead of S7MMCM for system clock
 2023-04-04 08:22:16 +02:00
Gabriel Somlo
1b9a74bf08 targets/nexys-video: simplify sata configuration 
Make nexys-video SATA configuration similar to the way it is supported
on the majority of other SATA-capable targets.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2023-04-03 12:28:12 -04:00
Icenowy Zheng
b1107e94d4 sitlinv_stlv7325: use S7PLL instead of S7MMCM for system clock 
As we do not need fine phase tweaking for the main system clock, use
S7PLL instead of S7MMCM to allow higher VCO frequency and more flexible
sys_clk_freq.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2023-04-03 16:45:13 +08:00
Hans Baier
0125ae4271 Add support for QMTech Artix7 200T FBG484 board 2023-03-20 08:21:36 +07:00
Hans Baier
98ddb97f5e Support QMTech XC7A75T, XC7A100T core boards 2023-03-20 07:57:58 +07:00
Icenowy Zheng
6b8a5d35c0 sipeed_tang_nano_20k: support copackaged SDRAM 
The copackaged SDRAM of GW2AR-18 QN88 package is 8MB size, 32bit DQ
width.

Add support for it.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2023-03-13 17:11:06 +08:00
Icenowy Zheng
291c43b898 sipeed_tang_nano_20k: new board 
This board uses Gowin GW2AR series chip (which is GW2A with integrated
RAM).

Support for the integrated SDRAM on Tang Nano 20K is still TODO.

Note: currently when the SD card is enabled, block 0 could be correctly
read but block 1 will fail.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2023-03-13 16:45:25 +08:00
Florent Kermarrec
bf4f688164 targets/pcie: Update Xilinx S7 constraints. 2023-03-06 12:20:34 +01:00
Florent Kermarrec
c9a0f5f50b targets/sipeed_tang_primer_20: Ethernet/Etherbone working. 
Test:
./sipeed_tang_primer_20k.py --cpu-type=serv --with-etherbone --build --load

ping 192.168.1.50
 2023-03-02 12:02:58 +01:00
Florent Kermarrec
4a724d9d2d targets/sipeed_tang_primer_20k/hdmi: Remove pn_swap on data lines that is no longer required. 2023-03-02 11:44:14 +01:00
Florent Kermarrec
9e73ba53ea platforms/sipeed_tang_primer_20k: Update hdmi pins to official dock version and fix compilation. 
Test:
./sipeed_tang_primer_20k.py --cpu-type=serv --with-video-terminal --build --load

Working.
 2023-03-02 11:39:41 +01:00
Florent Kermarrec
8a6f0bd94f opalkelly_xem8320: Review and update to recent LiteX changes. 2023-03-01 09:16:51 +01:00
AEW2015
e20391d366 Basic SoC for Opal Kelly XEM8320 2023-02-28 13:19:12 -07:00
Florent Kermarrec
f400179b5b targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
Florent Kermarrec
2eb7419678 targets/machdyne: Switch to LiteXModule for consistency with other targets. 2023-02-23 09:07:06 +01:00
inc
33cfe59614 add pullups for kopflos ethernet 2023-02-22 08:00:58 +01:00
inc
bd20b31a5c add support for machdyne kopflos board 2023-02-21 11:18:22 +01:00
Michael Welling
b1df2c0f85 Add initial support for the ICE-V wireless 
Signed-off-by: Michael Welling <mwelling@ieee.org>
 2023-02-19 00:00:07 -06:00
Florent Kermarrec
7b716e4899 antmicro_sdi_mipi_video_converter: Cleanup/Update to new LiteX conventions. 2023-02-16 09:02:14 +01:00
enjoy-digital
fe2be83feb
Merge pull request #473 from antmicro/crosslink-nx-zephyr 
Add support for SDI-MIPI Video Converter
 2023-02-16 08:49:04 +01:00
Florent Kermarrec
857166e455 xilinx_alveo_u200: Add missing copyrights. 2023-02-16 08:45:34 +01:00
enjoy-digital
adf8b8c5df
Merge pull request #472 from vietthanh85/xilinx_alveo_u200 
Add support for Xilinx Alveo U200
 2023-02-16 08:42:21 +01:00
Antoni Pokusinski
70f2fd6368 Fix format 2023-02-15 12:37:33 +01:00
Antoni Pokusinski
01abbc0d50 Replace deprecated register_mem with add_slave 2023-02-15 12:37:33 +01:00
Antoni Pokusinski
934e031dca Fix imports 2023-02-15 12:37:33 +01:00
Tomasz Michalak
223a69cf91 Add platform and target files for Antmicro's sdi mipi video converter board 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2023-02-15 12:37:33 +01:00
Florent Kermarrec
fdffeb8474 radiona_ulx4m_ld_v2: Do a first review/cleanup path. 2023-02-13 16:11:32 +01:00
Goran Mahovlic
8c9ea15d0a
Update radiona_ulx4m_ld_v2.py 2023-02-13 12:08:38 +01:00
Goran Mahovlic
404fefaab1
changing filename to radiona 2023-02-13 12:06:04 +01:00
Goran Mahovlic
f7822b7dc7
Adding target to files 2023-02-13 11:40:43 +01:00
Florent Kermarrec
b8abdf1b39 targets/digilent_arty: Add arguments for XDAC and DNA. 
Avoid specific checks for Vivado toolchain (Now handled by user for f4pga toolchain)
and fix linux-on-litex-vexriscv build.
 2023-01-23 08:55:10 +01:00
Florent Kermarrec
b9874685a5 gadgetfactory_papilio_pro: Cosmetic cleanups. 2023-01-17 15:43:12 +01:00
enjoy-digital
ec4d203eb6
Merge pull request #471 from Acathla-fr/papilio 
Target/Platform Papilio Pro added (with Arcade MegaWing)
 2023-01-17 11:21:27 +01:00
enjoy-digital
801008f5ad
Merge pull request #469 from hansfbaier/hpcstore-rename 
HPC FPGA Store on AliExpress renamed itself to SITLINV
 2023-01-17 11:20:19 +01:00
Do Viet Thanh
3b36e576ba Add support for Xilinx Alveo U200 2023-01-17 06:44:21 +07:00
Fabien
05ef1ee09e Target/Platform Papilio Pro added (with Arcade MegaWing) 2023-01-16 13:41:24 +01:00
Hans Baier
c0773ed9b9 HPC FPGA Store on AliExpress renamed itself to SITLINV 2023-01-16 11:31:35 +07:00
Florent Kermarrec
36a4100c8b ocp_timecard: Add DDR3 SDRAM support. 2023-01-13 12:41:34 +01:00
Florent Kermarrec
3ca298ba42 ocp_tap_timecard: Add TODO on SMAs. 2023-01-13 11:51:09 +01:00
Florent Kermarrec
c753bf7fc1 ocp_tap_timecard: Fix GTPE2 location. 2023-01-13 11:47:52 +01:00
Florent Kermarrec
8b0d4787c7 ocp_tap_timecard: Fix CI. 2023-01-13 10:55:07 +01:00
Florent Kermarrec
1e35d78512 ocp_tap_timecard: Add initial SMAIOs peripherals to allow using SMA over PCIe DMA or also with direct (and slow) control/visualization with CSR registers. 2023-01-13 10:08:44 +01:00
Florent Kermarrec
a0fd3e7536 Add initial OCP-TAP TimeCard support with PCIe/SPIFlash/Leds/Buttons/DNA/XADC (Compiles but untested). 2023-01-12 18:50:23 +01:00
Luc Lagarde
7a911b8ff6
Allow building digilent_arty using f4pga 
Only use XADC() and DNA() functions if vivado is the current toolchain.
 2023-01-06 16:09:56 -06:00
gatecat
764f64ff1e nx_vip: Add missing 'origin' to SRAM SocRegions 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-01-04 12:02:11 +01:00
Florent Kermarrec
f5643e7c78 machdyne: Fix LiteDRAM PHYs imports (QuarterRateGENSDRPHY not already working?/integrated). 2023-01-01 21:35:51 +01:00
enjoy-digital
563ccbd8cf
Merge pull request #464 from machdyne/master 
initial support for machdyne konfekt and noir
 2023-01-01 16:12:51 +01:00
inc
fec82c59e2 remove konfekt ethernet option 2022-12-30 17:36:52 +01:00
inc
f0dc9a6874 initial support for machdyne konfekt and noir 2022-12-30 17:00:35 +01:00
stone3311
6cfb56bb07 terasic_deca: add SPI SD card support 2022-12-28 02:13:06 +01:00
Gwenhael Goavec-Merou
4e06e5ff9c targets/xilinx_zybo_z7: adding missing variant parameter to the platform 2022-12-14 07:47:09 +01:00
JoyBed
d28894a4b3
Reintroduce original Zybo + HDMI addition (#461) 
* Reintroduce original Zybo support

* Reintroduce original zybo, add HDMI + fixes for Z7
 2022-12-12 22:05:47 +01:00
Florent Kermarrec
12db52471d targets/jungle_electronics_fireant: Update SPIFlash (Make it similar to other boards with BIOS in SPIFlash). 2022-12-08 08:37:13 +01:00
enjoy-digital
c05ce32c8a
Merge pull request #458 from trabucayre/arty_s7_tcl_config 
Arty z7 tcl config
 2022-12-08 08:31:22 +01:00
Tim Callahan
6e205be83b Add LedChaser to iCEBreaker-bitsy. 
Signed-off-by: Tim Callahan <tcal@google.com>
 2022-12-04 17:58:20 -08:00
Gwenhael Goavec-Merou
a889321535 targets/digilent_arty_z7: adding note to load gateware and bios 2022-12-03 16:54:52 +01:00
Gwenhael Goavec-Merou
e71e3ab3ec platforms,targets/digilent_arty_z7: use a dict for PS config instead of fetching file configuration 2022-12-03 16:54:39 +01:00
Gwenhael Goavec-Merou
b030630237
Merge pull request #453 from cklarhorst/zybo 
Zybo: Fix for Zynq7000 and use ps7 as submodule for Soft-CPUs
 2022-11-25 21:48:43 +01:00
mkuhn99
53b6bf035a fixed parser 2022-11-24 16:03:12 +01:00
mkuhn99
926ed21f0b fixed review remarks; added zynq7000 as a submodule for using the ps as a slave 2022-11-23 17:20:25 +01:00
mkuhn99
c489347a51 fixed zynq7000 integration; introduced option to add the processing-system as slave to the SoC 2022-11-18 11:19:57 +01:00
Icenowy Zheng
892bf3546d isx_im1283: connect CRG reset to PLL 
This fixes soft reset.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2022-11-16 15:12:18 +08:00
Icenowy Zheng
e27d8c958e isx_im1283: add jtagbone support 
Add necessary script snippets for enabling jtagbone in the command line.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2022-11-15 21:07:10 +08:00
Florent Kermarrec
ae47172d2a targets/decklink_mini_4k: Update clock constraints. 2022-11-14 10:21:42 +01:00
Icenowy Zheng
e9d7013d70 sitlinv_stlv7325: add jtagbone support 
Add necessary script snippets for enabling jtagbone in the command line.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2022-11-13 17:28:04 +08:00
Icenowy Zheng
c2c59f5e8c sitlinv_stlv7325: allow to set local/remote ip 
Port the script snippet from Colorlight i5 for setting the local/remote
IP address to STLV7325.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2022-11-13 17:27:58 +08:00
Icenowy Zheng
27c3afb8fb sitlinv_stlv7325: allow dynamic Ethernet IP 
Currently the sitlinv_stlv7325 target script parses the option that
selects dynamic Ethernet IP; however it's not really passed to LiteETH.

Really pass this option and add an assert that does not allow dynamic
Etherbone IP like other boards.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2022-11-13 17:27:23 +08:00
Icenowy Zheng
1c07fa94ca sitlinv_stlv7325: fix ident string vendor name 
As we changed the vendor name to proper Sitlinv in the file name, the
ident string is left untouched.

Fix this too.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2022-11-13 17:27:23 +08:00
Florent Kermarrec
58489ebebf targets/BaseSoC: Cleanup parameters. 2022-11-08 12:31:49 +01:00
Florent Kermarrec
a8c92cd86f targets/simple: Switch back to old version for now. 2022-11-08 11:55:06 +01:00
Florent Kermarrec
9e7079c4c8 targets: Remove int() on BaseSoC's sys_clk_freq. 2022-11-08 11:54:17 +01:00
Florent Kermarrec
b0e6414519 targets: Cleanup arguments and switch --sys-clk-freq to float (avoid conversion in code). 2022-11-08 10:41:35 +01:00
Florent Kermarrec
16b9677acd targets: Switch to soc_core_argdict. 
The next move was to remove soc_core and only keep soc; so this is probably the right time to do
it in targets to avoid having to handle it later.
 2022-11-07 08:43:26 +01:00
Florent Kermarrec
f1e24046fd xilinx_alveo_u250: Fix. 2022-11-06 22:17:28 +01:00
Florent Kermarrec
9a2028a9ba targets: Remove useless argparse imports. 2022-11-06 22:09:21 +01:00
Florent Kermarrec
30723b1bb0 targets: Update targets that were still using argparse.ArgumentParser. 2022-11-06 22:07:17 +01:00
Florent Kermarrec
33b0400aed targets: Update LiteXArgumentParser imports. 2022-11-06 21:39:52 +01:00