29b468529f
bus: replace simple bus module with new bidirectional Record
2013-04-01 21:54:21 +02:00
6a3c413717
New bidirectional-capable Record API
2013-04-01 21:53:33 +02:00
c4f4143591
New CSR API
2013-03-30 17:28:41 +01:00
633e5e6747
fhdl/module/finalize: pass additional args to do_finalize
2013-03-30 11:29:46 +01:00
574becc1fc
fhdl/specials: clean up clock domain handling
2013-03-26 11:58:34 +01:00
77a0f0a3bb
actorlib/structuring/Cast: support inversion
2013-03-25 15:54:09 +01:00
c4c4765a4e
bank/csrgen/BankArray: retain name information
2013-03-25 14:44:15 +01:00
53edc3557e
bank/description/Register: add get_size
2013-03-25 14:43:44 +01:00
3da98ea04d
genlib/record: use getattr instead of __dict__
2013-03-24 00:51:01 +01:00
1897b74f97
genlib/record: add eq
2013-03-24 00:50:33 +01:00
9d7c679b8c
genlib/fifo: simple synchronous FIFO
2013-03-22 18:18:38 +01:00
ca431fc7c2
fhdl/module: support clock domain remapping of submodules
2013-03-22 18:17:54 +01:00
a94bf3b2c5
genlib/cdc/MultiReg: output clock domain defaults to sys
2013-03-21 10:40:02 +01:00
17f2b17654
fhdl/verilog: optionally disable clock domain creation
2013-03-18 18:45:19 +01:00
7a06e9457c
Lowering of Special expressions + support ClockSignal/ResetSignal
2013-03-18 18:36:50 +01:00
dc55289323
fhdl/tools/_ArrayLowerer: complete support for arrays as targets
2013-03-18 14:38:01 +01:00
e95d2f4779
fhdl/tools/value_bits_sign: support not
2013-03-18 09:52:43 +01:00
b6fe3ace05
fhdl/structure: style fix
2013-03-17 15:33:38 +01:00
2a4cc3875c
Merge pull request #6 from larsclausen/master
...
Minor improvements
2013-03-17 07:33:14 -07:00
2f522bdd9f
genlib/cdc/MultiReg: implement rename_clock_domain + get_clock_domains
2013-03-15 19:50:24 +01:00
e2d156ef64
genlib/cdc/MultiReg: remove idomain
2013-03-15 19:49:24 +01:00
7b49fd9386
fhdl/specials: fix rename_clock_domain declarations
2013-03-15 19:47:01 +01:00
51bec340ab
sim: remove PureSimulable (superseded by Module)
2013-03-15 19:41:30 +01:00
dd0f3311cd
structure: remove Fragment.call_sim
2013-03-15 19:15:48 +01:00
9b9bd77d00
sim: compatibility with new ClockDomain API
2013-03-15 19:15:28 +01:00
bd8bbd9305
Make ClockDomains part of fragments
2013-03-15 18:17:33 +01:00
5adab17efa
flow/actor/filter_endpoints: deterministic order
2013-03-14 12:20:18 +01:00
fc883198ae
bank/csrgen/BankArray: create banks in sorted order
2013-03-13 23:07:44 +01:00
52d13959f2
bank/description: modify reg/mem in-place
2013-03-13 19:46:34 +01:00
dea4674922
Allow SimActors to produce/consume a constant stream of tokens
...
Currently a SimActor requires one clock period to recover from consuming or
producing a token. ack/stb are deasserted in the cycle where the token is
consumed/produced and only re-asserted in the next cycle. This patch updates the
code to keep the control signals asserted if the actor is able to produce or
consume a token in the next cycle.
The patch also sets 'initialize' attribute on the simulation method, this will
make sure that the control and data signals will be ready right on the first
clock cycle.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2013-03-12 23:10:51 +01:00
72579a6129
Add support for negative slice indices
...
In python a negative indices usually mean start counting from the right side.
I.e. if the index is negative is acutal index used is len(l) + i. E.g. l[-2]
equals l[len(l)-2].
Being able to specify an index this way also comes in handy for migen slices in
some cases. E.g. the following snippet can be implement to shift an abitrary
length register n bits to the right:
reg.eq(Cat(Replicate(0, n), reg[-n:])
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2013-03-12 21:56:01 +01:00
69dbf84e54
sim/generic: support implicit get_fragment
2013-03-12 16:54:01 +01:00
ecfe1646ec
fhdl/verilog: implicit get_fragment
2013-03-12 16:16:06 +01:00
4ada2ead05
fhdl/specials/Memory: automatic name#
2013-03-12 15:58:39 +01:00
04df076fba
bank: automatic register naming
2013-03-12 15:45:24 +01:00
7e2581bf17
fhdl/tracer: recognize CALL_FUNCTION_VAR opcode
2013-03-12 13:48:09 +01:00
12158ceadf
fhdl/tracer: recognize LOAD_DEREF opcode
2013-03-12 10:31:56 +01:00
3c75121783
fhdl/tracer: remove leading underscores from names
2013-03-11 22:21:58 +01:00
80970b203c
bus/asmibus: use implicit finalization
2013-03-11 17:11:59 +01:00
b042757187
Fix Register name conflict between Pytholite and Bank
2013-03-10 19:47:21 +01:00
f93695f60e
bank/eventmanager: use module and autoreg
2013-03-10 19:29:05 +01:00
174e8cb8d6
bus/asmibus: use fhdl.module API
2013-03-10 19:28:22 +01:00
17e0dfe120
fhdl/module: replace autofragment
2013-03-10 19:27:55 +01:00
cddbc1157d
bank/description/AutoReg: check that get_memories and get_registers are callable
2013-03-10 18:11:29 +01:00
68fe4c269c
bank/csrgen: BankArray
2013-03-10 00:45:16 +01:00
f1474420df
bank/description: AutoReg
2013-03-10 00:43:16 +01:00
d0676e2dd1
migen/fhdl/autofragment: factorize
2013-03-09 23:23:24 +01:00
d0d2df3c4b
fhdl/autofragment: remove legacy functions
2013-03-09 23:05:45 +01:00
72fb6fd6bd
fhdl/tools/flat_iteration: generalize
2013-03-09 23:03:15 +01:00
f53acb92e7
fhdl/autofragment: fix submodules
2013-03-09 21:15:38 +01:00
6da8eb906f
fhdl/autofragment: empty build_fragment by default
2013-03-09 19:10:47 +01:00
2b8dc52c13
Use common definition for FinalizeError
2013-03-09 19:03:13 +01:00
b75fb7f97c
csr/SRAM: support for writes with memory widths larger than bus words
2013-03-09 00:50:57 +01:00
6fa30053bf
fhdl/verilog: tristate outputs are always wire
2013-03-06 11:30:52 +01:00
9b4ca987e0
bus/csr: support memories with larger word width than the bus (read only)
2013-03-03 19:27:13 +01:00
bb5ee8d3bd
fhdl/autofragment: bugfixes + add auto_attr
2013-03-03 17:53:06 +01:00
cc8118d35c
fhdl/autofragment: FModule
2013-03-02 23:30:54 +01:00
d2491828a4
csr/SRAM: prefix page register with memory name
2013-03-01 12:06:12 +01:00
c10622f5e2
fhdl/verilog: insert reset before listing signals
2013-02-27 18:10:04 +01:00
d2cbc70190
bank/description: memprefix
2013-02-25 23:14:15 +01:00
a81781f589
fhdl/specials: allow setting memory name
2013-02-25 23:14:03 +01:00
425de02f42
uio/ioo: fix specials
2013-02-25 23:13:38 +01:00
55ab01f928
fhdl/specials/Instance: _printintbool -> verilog_printexpr
2013-02-24 13:08:01 +01:00
a878db1e3c
genlib: clock domain crossing elements
2013-02-23 19:03:35 +01:00
7c4e6c35e5
fhdl/verilog: support special lowering and overrides
2013-02-23 19:03:16 +01:00
f9acee4e68
corelogic -> genlib
2013-02-22 23:19:37 +01:00
38664d6e16
fhdl: inline synthesis directive support
2013-02-22 19:10:02 +01:00
49cfba50fa
New 'specials' API
2013-02-22 17:56:35 +01:00
1b18194b1d
fhdl: TSTriple
2013-02-19 17:26:02 +01:00
dc93a231c6
fhdl: tristate support
2013-02-15 00:17:24 +01:00
63d399b6ad
fhdl/autofragment: from_attributes
2013-02-11 18:34:01 +01:00
92b67df41c
sim: default runner to Icarus Verilog
2013-02-09 17:04:53 +01:00
bd6856ba7a
flow/perftools: finish removing ActorNode
2013-02-09 17:03:48 +01:00
473fd20f8c
fhdl/structure: store clock domain name
2013-01-24 13:49:49 +01:00
3201554f76
fhdl/verilog: fix spurious clock/reset signals on multiple calls to convert()
2013-01-23 15:13:06 +01:00
314a6c7743
corelogic: complex arithmetic support
2013-01-05 14:18:36 +01:00
badba89686
fhdl: support nested statement lists
2013-01-05 14:18:15 +01:00
47f5fc70e4
pytholite: fix bug with constant assignment to register
2012-12-19 16:21:57 +01:00
9c65402fda
pytholite: prune unused registers
2012-12-19 16:03:05 +01:00
3fae6c8f03
Do not use super()
2012-12-18 14:54:33 +01:00
b06fbdedd6
fhdl/tools: bitreverse
2012-12-14 23:56:16 +01:00
1f350adf14
actorlib/sim/SimActor: do not drive busy low when generator yields None
2012-12-14 23:56:03 +01:00
a67f483f0f
Token: support idle_wait
2012-12-14 19:16:22 +01:00
6f99241585
Move Token to migen.flow.transactions
2012-12-14 15:55:38 +01:00
28b4d99d31
replace some forgotten is_abstract()
2012-12-12 22:36:45 +01:00
a7227d7d2b
Remove ActorNode
2012-12-12 22:20:48 +01:00
8163ed4828
Merge branch 'master' of github.com:milkymist/migen
2012-12-06 20:57:30 +01:00
483b821342
fhdl/structure: do not create Signal in Instance when parameter is int
2012-12-06 20:56:46 +01:00
280a87ea69
elsewhere: do not create interface in default param
2012-12-06 17:34:48 +01:00
62187aa23d
migen/bank: do not create interface in default param
2012-12-06 17:28:28 +01:00
c3fdf42825
bus/csr: add SRAM
2012-12-06 17:16:17 +01:00
e89c66bf14
bank/csrgen: interface -> bus
2012-12-06 17:15:34 +01:00
273d9d285b
bank/description: define reset value of read signal
2012-12-05 16:40:44 +01:00
34ce934809
actorlib/sim: drive busy high until generator is finished
2012-12-05 16:40:12 +01:00
4bcb39699b
bus/wishbone/sram: accept memories < 32 bits
2012-12-01 13:04:22 +01:00
523816982a
bus/wishbone: add SRAM
2012-12-01 12:59:09 +01:00
adb1565d7a
pytholite: fix bit width of selection signal
2012-11-30 17:07:32 +01:00
cfb23c442f
pytholite: support signed registers
2012-11-30 17:07:12 +01:00
7093939309
corelogic/roundrobin: fix request width (again)
2012-11-29 23:47:51 +01:00
31c722f993
corelogic/roundrobin: fix request width
2012-11-29 23:47:08 +01:00
70e97e0456
Fix various errors from new bitwidth/signedness system conversion
2012-11-29 23:36:55 +01:00
261166d92b
fhdl/verilog: make signal behave as integers in arithmetic (MyHDL style)
...
See http://jandecaluwe.com/hdldesign/counting.html
2012-11-29 22:59:54 +01:00
55d143a454
fhdl/structure: add unary minus
2012-11-29 22:52:57 +01:00
d8e478efee
Replace Signal(bits_for(... with Signal(max=...
2012-11-29 21:53:36 +01:00
50ed73c937
New specification for width and signedness
2012-11-29 21:22:38 +01:00
6eebfce44a
Refactor Case
2012-11-29 01:11:15 +01:00
070652cc39
pytholite/reg: use source id in dictionary
2012-11-29 00:09:35 +01:00
fee22a4631
Remove Constant
2012-11-28 23:18:43 +01:00
59831e0485
fhdl/structure: improved bits_for function
2012-11-28 18:39:44 +01:00
11b1e53224
visit/NodeTransformer: copy most nodes
2012-11-28 17:50:55 +01:00
a2bcbfdf8f
fhdl/tools: use NodeTransformer to lower arrays
2012-11-28 17:46:15 +01:00
3bc15024ac
fhdl/tools: use NodeVisitor
2012-11-26 21:40:23 +01:00
e3a983d731
Remove unroll
2012-11-26 20:07:48 +01:00
1460f069f6
fhdl/structure: remove deprecated MemoryPort
2012-11-26 19:36:43 +01:00
5183774ec8
bus/wishbone2asmi: do not use MemoryPort
2012-11-26 19:14:59 +01:00
fc85ca53ad
actorlib/spi: do not use MemoryPort
2012-11-26 18:27:59 +01:00
dac0d11e52
actorlib/sim: Dumper
2012-11-24 00:00:07 +01:00
27d87c9412
fhdl/structure: disable we_granularity when larger than width
2012-11-23 23:08:12 +01:00
d2c61e6a90
sim/generic/multiread: do not return spurious items
2012-11-23 23:07:25 +01:00
74721b206f
pytholite: fix import of _Slice
2012-11-23 21:20:18 +01:00
95122bb778
pytholite/io: support memory
2012-11-23 20:36:09 +01:00
f42683b71e
fhdl/structure/Memory: fix we width
2012-11-23 19:21:52 +01:00
0f6215a13a
fhdl/structure: add Memory.get_port API
2012-11-23 19:17:49 +01:00
9d3e218863
fhdl: use object creation counter (HUID) as hash. This finally makes the generated code textually the same across runs.
2012-11-23 18:38:03 +01:00
3971600917
fhdl/structure: use sets for memories and instance collections
2012-11-23 17:20:08 +01:00
f3efd74dfd
uio: support memories
2012-11-23 16:23:24 +01:00
ab31b4d99c
bus: memory initiator
2012-11-23 16:22:50 +01:00
0b7dd7bdce
pytholite/io: fix Wishbone writes + support sel attribute
2012-11-23 13:40:46 +01:00
4c216d8f11
pytholite/io: support Wishbone reads
2012-11-23 13:09:55 +01:00
0b24a2ff36
pytholite/io: support Wishbone writes
2012-11-23 12:41:50 +01:00
f098c5c695
pytholite/compiler: pass keyword arguments to gen_io
2012-11-23 12:40:57 +01:00
51e2e6ecd0
fhdl/verilog: remove empty cases
2012-11-18 16:32:51 +01:00
89643bc434
sim/ipc/Message: convert values
2012-11-17 23:19:40 +01:00
e92af9de59
pytholite/transel: use python3-compatible comparison methods
2012-11-17 23:16:07 +01:00
b6b4c5d70e
uio/ioo: fix UnifiedIOSimulation
2012-11-17 22:25:42 +01:00
1cabcb3c3f
uio: support generator trampolining in simulation
2012-11-17 19:59:22 +01:00
be68ecfc72
uio: add simulation I/O object
2012-11-17 19:55:33 +01:00
7add4c6f3c
uio: unified I/O object
2012-11-17 19:54:50 +01:00
d10df1a8ab
actorlib/sim: swap TokenExchanger parameters
2012-11-17 19:46:28 +01:00
d4baac6c0f
bus/csr: allow specifying existing interface
2012-11-17 19:44:25 +01:00
86090e1cbd
bus/asmibus: swap port position to be consistent with wishbone API
2012-11-17 19:42:39 +01:00
ece786d6aa
bus/wishbone: allow specifying existing interface
2012-11-17 19:42:06 +01:00
d0d4c48098
bus/transactions: add busname parameter
2012-11-17 19:36:08 +01:00
897a2e3f9c
actorlib/sim: split TokenExchanger
2012-11-17 14:15:51 +01:00
eb156af20c
pytholite/io: support token pull
2012-11-16 23:48:41 +01:00
dd9a102a78
pytholite/io: support token push
2012-11-16 19:24:45 +01:00
bf5ce8dc20
pytholite: move expression and register handling to separate modules
2012-11-11 23:48:23 +01:00
f59fd69e34
pytholite/compiler: recognize composite I/O pattern
2012-11-11 18:03:16 +01:00
0b5652bb79
pytholite/compiler: visit_assign_special
2012-11-11 15:52:06 +01:00
687d18a150
pytholite: move FSM management to separate module
2012-11-11 14:30:25 +01:00
409a5570e4
pytholite/compiler: refactor visit_block
2012-11-11 14:17:52 +01:00
fb63698ef4
pytholite/compiler: clean up visit_statement
2012-11-10 23:30:14 +01:00
6ebd1e4503
pytholite: forward 'yield call' statements to io module
2012-11-10 22:59:14 +01:00
48acb1bcfd
pytholite: introduce io module
2012-11-10 21:51:19 +01:00
6776f06a42
pytholite/compiler: support bitslice
2012-11-10 18:04:05 +01:00
37f113c3ea
pytholite/compiler: support range(constants) in for loops
2012-11-10 15:26:13 +01:00
370bab1190
pytholite/compiler: cleanup print statements
2012-11-10 15:10:57 +01:00
39c7dc7d63
pytholite/compiler: support for loops (iterating on lists only)
2012-11-10 15:02:55 +01:00
93db3edd00
pytholite/compiler: support while loops
2012-11-10 14:37:33 +01:00
a901ef46ab
Revert "pytholite/compiler: SymbolStack"
...
This reverts commit f57da497b2
2012-11-10 12:09:45 +01:00
f57da497b2
pytholite/compiler: SymbolStack
2012-11-09 23:02:16 +01:00
5750c7c07e
pytholite/compiler: improve naming of selection signals
2012-11-09 20:19:22 +01:00
4921a34616
pytholite/compiler: fix handling of constants
2012-11-09 20:17:57 +01:00
26cf1b8840
fhdl: make constants hashable
2012-11-09 20:17:43 +01:00
c1b8492b61
pytholite/compiler: go to next state
2012-11-09 20:12:15 +01:00
e1075a962c
pytholite/compiler: support if statements
2012-11-09 19:37:52 +01:00
92ff5095da
pytholite/compiler: support comparisons in expressions
2012-11-09 18:41:32 +01:00
a645e0b24e
pytholite/compiler: create FSM
2012-11-09 17:37:42 +01:00
7744655ef2
fhdl/visit: add missing self
2012-11-09 17:37:24 +01:00
13af0ce556
fhdl: visit module (untested)
2012-11-09 16:00:11 +01:00
9c182c47d1
pytholith: add register muxes
2012-11-08 21:49:20 +01:00
18758d87f6
pytholite: do not use ast.NodeVisitor
2012-11-06 13:52:19 +01:00
56d4cdeb48
fhdl/structure: make all values hashable
2012-11-06 13:51:51 +01:00
3042f047fe
pytholite: visit AST and list registers
2012-10-31 15:59:12 +01:00
b171b3b3c2
pytholite: transformable elements
2012-10-29 18:13:03 +01:00
31cdb02eff
bank/description: regprefix
2012-10-15 21:21:59 +02:00
7a1a781f49
actorlib/spi: typo
2012-10-15 21:21:42 +02:00
daee4fb58c
transform/unroll_sync: autodetect in/out
2012-10-15 20:32:07 +02:00
fecab5518b
transform/unroll_sync: support generator function
2012-10-15 19:42:30 +02:00
9efc581bee
transform/unroll: support empty dictionaries
2012-10-12 21:54:48 +02:00
eacba52fba
transform/unroll: support for variables
2012-10-12 19:54:03 +02:00
e5fc9cc675
transform: unroll
2012-10-12 13:16:39 +02:00
d329d40fe9
actorlib/spi: SingleGenerator
2012-10-09 21:11:15 +02:00
c473718a12
actorlib/spi/collector: atomic update for write_count
2012-10-09 19:08:09 +02:00
85081793cf
bank: remove RE signal for field registers
2012-10-09 19:07:53 +02:00
e410973352
bank: support for atomic writes
2012-10-08 18:43:18 +02:00
24877f271b
actorlib/spi: fix memory port we/wd
2012-10-04 20:10:24 +02:00
035870703f
flow/actorlib: Simple Processor Interface (WIP)
2012-10-04 18:22:22 +02:00
8101b68965
fhdl: fix instance get_io
2012-09-28 18:02:03 +02:00
c273866b08
fhdl: support expressions in instance ports
2012-09-22 20:51:10 +02:00
2fc9cae88a
fhdl: support inverted clock ports in instances
2012-09-22 20:50:49 +02:00
2e14569b5c
fhdl/verilog: sort clock domains by name
2012-09-11 10:00:03 +02:00
9a18a9df3f
fhdl: list signals in execution order
2012-09-11 09:59:37 +02:00
e16353a281
Multi-clock design support + new instance API
2012-09-10 23:45:02 +02:00
6490785b6c
Merge pull request #3 from brandonhamilton/upstream
...
Optionally accept iverilog simulator options
2012-09-09 10:52:52 -07:00
b45c9546eb
fhdl/namer: better handling of indices
2012-09-09 19:33:55 +02:00
589251fffd
fhdl/tracer: support BUILD_LIST opcode
2012-09-09 18:53:24 +02:00
910c350021
fhdl/namer: use execution order indices for variable names as well
2012-09-09 17:31:35 +02:00
f3e3a3eec7
fhdl/namer: number objects according to execution order
2012-09-09 12:27:32 +02:00
51f9a2a963
fhdl/namer: simplify + more relevant names
2012-09-09 01:26:33 +02:00
4164fb4ac9
bus/csr: configurable data width
2012-08-26 21:19:34 +02:00
5bf19c155f
sim: ensure clean IPC shutdown
2012-08-05 00:16:11 +02:00
47c341ecdf
flow/isd: add freeze register
2012-08-04 23:39:52 +02:00
6de517f59c
flow/network: remove print
2012-08-03 18:50:57 +02:00
25cb25a8ae
flow/network: option to add debugger
2012-08-03 18:49:35 +02:00
fd0e281dfc
flow: in-system debugger module
2012-08-03 18:49:04 +02:00
adacdadd58
flow/hooks/DFGHook: add iterator on hooks
2012-08-03 18:48:35 +02:00
37fe6d64c3
flow: EndpointHook -> EndpointSimHook
2012-08-03 12:58:41 +02:00
30f1e77c18
corelogic/ReorderBuffer: do not touch empty count when issuing and reading at the same time
2012-07-13 20:21:04 +02:00
8de192dfbd
x.bv.width -> len(x)
2012-07-13 18:32:54 +02:00
9cdc88eadf
fhdl: len() for Constant
2012-07-13 18:16:50 +02:00
8c169a99df
corelogic/misc: remove multimux
2012-07-13 18:05:57 +02:00
599ed8d470
fhdl: fix value_bv for operators
2012-07-13 17:40:49 +02:00
b4613d913f
bus/wishbone: remove use of deprecated multimux
2012-07-13 17:17:20 +02:00
7f47a2568a
fhdl: remove _StatementList
2012-07-13 17:07:56 +02:00
8062e48697
bus/asmibus: fix per-port tag generation
2012-07-12 19:37:50 +02:00
c543edf6f3
actorlib/dma_asmi: out-of-order reader and class factory
2012-07-12 18:34:13 +02:00
43653dbe1a
corelogic: reorder buffer (untested)
2012-07-12 18:33:28 +02:00
eed8fa374d
fhdl/arrays: use correct BV for intermediate signals
2012-07-11 12:06:32 +02:00
ed27783a53
fhdl: arrays (TODO: use correct BV for intermediate signals)
2012-07-09 15:16:38 +02:00
c82a468506
bus: CSR initiator
2012-07-07 22:36:15 +02:00
0b19112f8f
actorlib/misc/IntSequence: add offset feature
2012-07-07 00:10:23 +02:00
518501c493
flow/perftools: refactor to use hooks
2012-07-06 23:36:23 +02:00
6cf38bfcba
flow: hooks
2012-07-06 23:36:10 +02:00
a49dcb328a
actorlib/structuring/Cast: rawbits parameter
2012-06-29 16:10:50 +02:00
fa5a9915c3
doc: actor network
2012-06-25 16:07:45 +02:00
920aa5dc60
actorlib: merge composer into ala + derive ComposableSource from ActorNode
2012-06-25 11:34:58 +02:00
bbfa120e2f
doc: arithmetic and logic actors
2012-06-24 19:56:31 +02:00
fd233d5b3c
Move arithmetic actors to actorlib
2012-06-24 19:13:49 +02:00
1edaec0d75
control.For -> misc.IntSequence
2012-06-22 15:01:47 +02:00
4785ca526b
flow/perftool: fix cpt equation
2012-06-21 00:41:22 +02:00
cbc387f69e
actorlib/sim/SimActor: remove dead time between transactions
2012-06-20 22:39:52 +02:00
6aff41a883
actorlib/structuring/Pack: drive busy signal
2012-06-20 22:39:03 +02:00
34d8ae3c11
flow: perftools
2012-06-20 21:59:17 +02:00
6fac3f027f
examples/dataflow: structuring test
2012-06-20 18:25:01 +02:00
7d0e179a03
actorlib: structuring (untested)
2012-06-20 16:35:01 +02:00
1576cb0950
actorlib/control: simplify + fix
2012-06-17 21:19:47 +02:00
66ac62d0bb
flow/network: fix handling of edges with subrecords at both ends
2012-06-17 18:31:45 +02:00
75d569a12c
actorlib/control: use numbers of bits instead of maxima
2012-06-17 18:29:57 +02:00
4873cfe1a7
flow/plumbing: Combinator/Splitter should not inherit CombinatorialActor
2012-06-17 13:45:18 +02:00
98c9da95d1
flow/network: handle default endpoints correctly in _infer_plumbing_layout
2012-06-16 22:41:15 +02:00
9af87367eb
flow/network: require ActorNode be passed to add_connection
2012-06-16 22:40:26 +02:00
b0b0380ea7
flow/network: fix ActorNode default params
2012-06-16 22:39:31 +02:00
1a576e5c83
flow/actor: fix busy signal generation for pipelined actors
2012-06-16 22:38:45 +02:00
9228e8a96d
flow/actor: add single_sink/single_source retrieval methods
2012-06-16 22:38:16 +02:00
c1450daa93
flow: insert splitters
2012-06-16 21:23:42 +02:00
bde8361e19
flow: insert combinators and infer plumbing layout
2012-06-16 17:30:54 +02:00
da522cd58d
Abstract actor graphs
2012-06-15 17:52:19 +02:00
b14be4c8a3
actorlib: ASMI sequential reader
2012-06-12 21:04:47 +02:00
ce9e35b8ef
fix SimActor get_fragment
2012-06-12 17:52:08 +02:00
8a23451237
PureSimulable
2012-06-12 17:08:56 +02:00
a591510189
ASMI simulation models
2012-06-12 16:57:00 +02:00
b7a84b3750
wishbone: base TargetModel class
2012-06-10 17:05:10 +02:00
ec501e7797
bus/wishbone: target model
2012-06-10 16:40:33 +02:00
f061b25a24
bus/wishbone/Tap: remove ack feature
2012-06-10 12:46:24 +02:00
009f26bb9d
flow/network: refactor graph
2012-06-08 22:49:49 +02:00
de408b2cba
flow/ala: fix typo
2012-06-08 22:48:47 +02:00
356051e8a8
actorlib: WB reader simulation OK
2012-06-08 21:31:05 +02:00
11674242c4
Use super() instead of calling parent constructors directly
2012-06-08 18:06:12 +02:00
152a7e282e
actorlib/sim: use set instead of list to represent active transactions
2012-06-08 17:56:52 +02:00
910c7806cf
actorlib: generator-based generic simulation actor
2012-06-08 17:54:03 +02:00
b145f9e5e2
sim: multiread/multiwrite
2012-06-08 17:52:32 +02:00
f38ef626de
corelogic/record: better repr
2012-06-08 17:49:31 +02:00
1c0f636c8d
flow: generic parameter passing to Actor from sequential/pipelined
2012-06-07 18:24:33 +02:00
a1fc86af8f
flow: fix actor repr
2012-06-07 15:48:35 +02:00
680a34465d
flow: refactor scheduling models
2012-06-07 14:44:43 +02:00
493b181af1
bank/description: pad unaligned multi-word registers at the top
2012-05-21 22:55:23 +02:00
9449bbea0a
Add LICENSE file
2012-05-21 19:56:23 +02:00
68cd445662
bus/wishbone2asmi: fix cache tag size
2012-05-15 15:18:03 +02:00
0bea1e2589
asmi: dat_wm high to disable data write
2012-05-15 14:41:54 +02:00
f2c20e4af0
bus/asmibus/hub: hack to prevent comb loops
2012-04-30 17:11:42 -05:00
398ece8fe2
fhdl/verilog: add option to display which comb blocks are run
...
This is a debug hack to help find combinatorial loops in designs.
2012-04-30 16:38:40 -05:00
0b62e573ae
sim: pass extra keyword arguments to Verilog converter
2012-04-30 16:38:17 -05:00
6a52e44d09
fhdl: support len() on signals
2012-04-08 18:06:22 +02:00
b9c533be51
bank/csrgen: allow specifying existing CSR interface
2012-04-06 14:59:09 +02:00
49b58a03a0
Optionally accept iverilog simulator options
2012-04-03 12:58:19 +02:00
2a4e49e381
fhdl: phase out pads
2012-04-02 19:21:43 +02:00
623e8e436a
fhdl/verilog: do not attempt to initialize instance and mem output signals
2012-04-02 12:59:42 +02:00
6e3b25ebb6
bus/dfi: reset active low signals to 1
2012-04-01 17:43:24 +02:00
d3c6b8d16f
sim/proxy: support lists
2012-04-01 17:19:53 +02:00
f3ae22f488
fhdl/verilog: initialize internal read-only signals with their reset values
2012-04-01 16:39:11 +02:00
0dfc215fe8
corelogic/roundrobin: handle correctly special case with 1 request source
2012-03-31 18:01:40 +02:00
94b02aa8ed
bus/asmicon: initiator
2012-03-30 22:16:31 +02:00
bb864c65dc
sim: proxy
2012-03-30 16:40:26 +02:00
081b658e2d
Update copyright notices
2012-03-23 16:41:30 +01:00
d47b564fad
corelogic/fsm: typo
2012-03-18 22:12:46 +01:00
5f28103769
corelogic/fsm: delayed enters
2012-03-18 00:09:40 +01:00
a4294762d0
corelogic/roundrobin: CE switching
2012-03-16 16:54:47 +01:00
e969b9afc3
corelogic: convert timeline to function and move to misc
2012-03-15 20:25:44 +01:00
1665f293a6
bus/asmibus/hub: require finalization before get_slots
2012-03-14 16:19:29 +01:00
5c0cc6292c
fhdl: export log2_int
2012-03-14 12:19:42 +01:00
bfcd4e636b
fhdl: handle negative constants correctly
2012-03-08 20:49:24 +01:00
ab800fa2ed
bus: generic transaction model
2012-03-08 18:14:06 +01:00
678a89d572
sim: fix zero encoding
2012-03-08 15:34:08 +01:00
decbd069fa
sim: fix message debug formatting
2012-03-08 15:27:35 +01:00
98e96b3952
sim: make initialization cycle optional (selectable by function attribute)
2012-03-06 19:43:59 +01:00
8160ced2e9
sim: memory access
2012-03-06 19:29:39 +01:00
db8f8bf2e3
fhdl: register memory objects with namespace
2012-03-06 18:33:44 +01:00
6f829c7afc
sim: support for signed numbers
2012-03-06 16:46:18 +01:00
90184b22d2
fhdl/verilog: fix signed constant conversion
2012-03-06 16:45:44 +01:00
9da512dbf5
sim: VCD generation
2012-03-06 15:26:04 +01:00
22b3c11b93
sim: clean startup/shutdown
2012-03-06 15:00:02 +01:00
06de17b16c
sim: remove temporary files and socket
2012-03-06 14:20:26 +01:00
7230508e7c
fhdl/namer: do not reference objects with __del__ methods to avoid uncollectable cycles
2012-03-06 14:18:22 +01:00
2c375e900f
sim: remove default sockaddr
2012-03-06 13:58:49 +01:00
8d16fde48c
fhdl: add simulation functions in fragment
2012-03-06 13:58:22 +01:00
aac9752558
sim: basic functionality working
2012-03-05 20:31:41 +01:00
29859acc34
sim: two way IPC working
2012-03-04 19:17:03 +01:00
8586daf2dd
sim: IPC module (lacks str/int encoding)
2012-03-03 18:55:38 +01:00
1b8cb5b46c
bus/dfi: fix multiphase naming
2012-02-19 17:57:04 +01:00
d8d4e81b6e
bank/csrgen: fix RE generation
2012-02-18 18:56:18 +01:00
55a265d967
bank: add RE signal for registers made of fields
2012-02-17 23:52:06 +01:00
92dfbb92dd
bus: add interconnect statements function
2012-02-17 23:51:32 +01:00
f995e8b92e
fhdl: check we pass BV to signals
2012-02-17 23:50:54 +01:00
a1ad30faab
fhdl/verilog: properly connect instance inouts
2012-02-17 11:08:41 +01:00
ca7056b07f
fhdl: support forwarding of bidirectional signals from instance ports
2012-02-16 18:34:32 +01:00
c08687b9c6
bus/dfi: filter signals by direction
2012-02-15 21:48:05 +01:00
ef7aea0f31
bank: omit device write register when access_bus==READ_ONLY and access_dev==WRITE_ONLY
2012-02-15 18:23:31 +01:00
fa9cf3e466
bus: add DFI
2012-02-15 18:09:14 +01:00
91e279ee04
bank/csrgen: use new bus API
2012-02-15 16:42:17 +01:00
af5230c8ee
bus: fix simple interconnect
2012-02-15 16:42:05 +01:00
0493212124
bus: simplify and cleanup
...
Unify slave and master interfaces
Remove signal direction suffixes
Generic simple interconnect
Wishbone point-to-point interconnect
Description filter (get_name)
Misc cleanups
2012-02-15 16:30:16 +01:00
46b1f74e98
bus/asmibus/hub: forward data and tag_call
2012-02-14 14:00:17 +01:00
0c214b484e
Use double quotes for all strings
2012-02-14 13:12:43 +01:00
e11d9b9322
bus/wishbone2asmi: cache hits working
2012-02-13 23:11:16 +01:00
1662e1b3bc
corelogic: support reverse in displacer/chooser
2012-02-13 23:10:27 +01:00
264be80f2d
Fix syntax errors and other stupid problems
2012-02-13 22:28:02 +01:00
8a61d9d121
bus/csr: Rename a->adr d->dat to be consistent with the other buses
2012-02-13 21:46:39 +01:00
060426cb59
bus/wishbone2asmi: set WM, and send 0 when inactive
2012-02-13 16:49:43 +01:00
cad9d3b960
bus: Wishbone to ASMI caching bridge (untested)
2012-02-13 16:29:38 +01:00
244bf17db7
corelogic/misc: displacer + chooser
2012-02-11 20:57:08 +01:00
e10e4360f3
corelogic/misc/multimux: less confusing variable name
2012-02-11 20:56:51 +01:00
7894411418
bus/asmibus: fix typo
2012-02-11 20:56:01 +01:00
28b0c340af
corelogic/record: add to_signal convenience function
2012-02-11 20:55:23 +01:00
e62ac1d3a1
corelogic/misc: contiguous split
2012-02-11 11:52:15 +01:00
ef436a1ec9
bus/asmibus: add get_slots, fix get_fragment
2012-02-10 17:49:06 +01:00
945d655d45
bus: ASMI hub (untested)
2012-02-10 15:21:04 +01:00
47883675db
bus/wishbone2csr: truncate WB data
2012-02-06 18:43:34 +01:00
1eb348c573
fhdl: do not attempt slicing non-array signals to keep Verilog happy
2012-02-06 18:07:02 +01:00
fcd6583cbb
bank: event manager
2012-02-06 17:39:32 +01:00
3a2a0c4dd8
bank: support registers larger than the bus word width
2012-02-06 16:15:27 +01:00
f3ddfffc47
bank: refactoring
2012-02-06 13:55:50 +01:00
1a86f26a66
bank/csrgen: use enumerate
2012-02-06 11:18:30 +01:00
629e771fc0
fhdl/structure: binary constant builder
2012-02-05 19:32:11 +01:00
8380318e84
Use enumerate(x) instead of zip(range(x), x)
...
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2012-02-02 21:28:00 +01:00
2b3f00cbc1
fhdl/namer: Add support for STORE_DEREF opcode
...
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2012-02-02 21:15:10 +01:00
6a9b59786b
fhdl/namer: extract variable names with bytecode inspection
2012-01-28 23:17:44 +01:00
5c2df45577
fhdl: do not prefix instance signal names
2012-01-28 11:39:28 +01:00
a99c2acfa8
Remove explicit bus names and rely on the new automatic namer
2012-01-27 22:20:57 +01:00
685b5eb08f
fhdl: support memory read enable
2012-01-27 21:39:23 +01:00
0cc7e2ac1e
fhdl: make WRITE_FIRST default
2012-01-27 21:35:58 +01:00
5405a83ff9
fhdl: memories working
2012-01-27 20:22:17 +01:00
a5bd111370
fhdl/verilog: clean up signal classification and support memory descriptions
2012-01-27 16:54:48 +01:00
6b1d775e9f
fhdl/structure: memory description
2012-01-27 16:53:34 +01:00
1966117e17
flow/ala: fix typo for And (thanks Lars)
2012-01-22 00:32:02 +01:00
076c171c7b
Use meaningful class names
2012-01-20 23:07:32 +01:00
d3d5b481fe
Include fragment pads in pre-naming dictionary
2012-01-20 22:59:40 +01:00
039c6d8eb4
namer/trace_back: behave on None code_context
2012-01-20 22:52:50 +01:00
e9be3241f6
Fix instance support
2012-01-20 22:36:17 +01:00
e4f531a739
Include unused I/Os in pre-naming dictionary and register signals with name_override
2012-01-20 22:20:32 +01:00
904d14d4cf
Remove NoContext
2012-01-20 22:15:44 +01:00
05b20d4987
Only include context prefix when necessary
2012-01-19 19:25:04 +01:00
fc473e31eb
Fix disjoint namespace test
2012-01-19 19:24:43 +01:00
00d3eb7989
Always include last step in names
2012-01-19 18:42:43 +01:00
4eac60d181
New naming system: second attempt
2012-01-19 18:25:25 +01:00
4c85d921b3
corelogic/record: empty default name
2012-01-16 19:38:14 +01:00
bdde97f5fd
New naming system beginning to work
2012-01-16 18:42:55 +01:00
ab8e08a2ed
fhdl: new naming system (broken)
2012-01-16 18:09:52 +01:00
e6bfad498d
actorlib/control: 'for' generator
2012-01-15 22:08:33 +01:00
c3d7b98b43
dma_wishbone: small syntax simplification thanks to None statements
2012-01-15 17:46:15 +01:00
aa8b8da684
fhdl: allow None statements
2012-01-15 17:45:54 +01:00
85491efc68
wishbone_dma: convert to new endpoint API and fix some bugs
2012-01-15 16:41:15 +01:00
77b3c8e3bb
bus: list signals
2012-01-15 15:48:51 +01:00
3c7161cc34
flow: saner endpoint management
2012-01-15 15:09:44 +01:00
20425703fa
Wishbone: omit fixed LSBs
2012-01-13 17:29:05 +01:00
077fd9fdbc
actorlib: Wishbone DMA read master (WIP)
2012-01-10 17:10:18 +01:00
c93eb5f482
record: return offset
2012-01-10 17:10:03 +01:00
a6e5f3e766
flow: simplify actor fragment interface
2012-01-10 15:54:51 +01:00
683e6b4a6c
record: support aligned flattening
2012-01-09 19:16:11 +01:00
b06e70d849
corelogic: FSM
2012-01-09 16:28:48 +01:00
47ae303846
record: cleanup
2012-01-09 15:20:09 +01:00
cef1c5d3af
record: better exception code
2012-01-09 15:17:24 +01:00
89bf704b2b
record: preserve order
2012-01-09 15:14:42 +01:00
bdcaeb159b
flow: draw network graph
2012-01-09 14:21:54 +01:00
d26ded93d8
flow: actor busy signal
2012-01-09 14:21:45 +01:00
d2d55372d8
Composer (WIP)
2012-01-08 13:56:11 +01:00
34c69db14a
endpoint: add _i/_o suffix on signal names
2012-01-07 21:21:46 +01:00
cdd9977a40
fhdl: better signal naming heuristic
2012-01-07 15:30:14 +01:00
b6763c28ea
constant: equality
2012-01-07 12:29:47 +01:00
7b395b565e
verilog: split comb block, use assign statements
2012-01-07 12:19:06 +01:00
f209bf6b33
convtools -> tools
2012-01-07 00:39:28 +01:00
0b195a244d
flow: network
2012-01-07 00:33:28 +01:00
3c1dada9cf
record: compatibility check
2012-01-06 23:00:23 +01:00
588f1a259e
flow: plumbing
2012-01-06 17:24:05 +01:00
8f1bf508ca
actor: simplified automatic control
2012-01-06 15:35:17 +01:00
a3bf877802
ALA: use records for tokens
2012-01-06 14:32:00 +01:00
038992e7d2
corelogic: record
2012-01-06 11:20:44 +01:00
d7a3bed44c
Signal repr
2012-01-06 11:20:33 +01:00
9366a226bb
Convert -> convert
2012-01-05 19:27:33 +01:00
edf90870c2
flow: sum and division actors
2011-12-23 00:35:53 +01:00
76db20cd9f
fhdl: encapsulate replicated constants
2011-12-23 00:35:13 +01:00
f0aac4b50f
flow: actor class
2011-12-22 19:37:16 +01:00
566295dea3
csr: use optree
2011-12-22 19:36:56 +01:00
ba40f58491
corelogic: operator tree
2011-12-22 15:46:19 +01:00
8a394f9159
verilog: comb reset
2011-12-22 00:04:53 +01:00
4d6be55e9f
verilog: break down Convert function
2011-12-21 23:08:50 +01:00
26e0b817e8
verilog: ignore variable property in combinatorial block
2011-12-21 23:00:36 +01:00
7456195775
Consistent names
2011-12-21 22:57:07 +01:00
94c5fba067
corelogic: fix signal exports
2011-12-18 21:54:28 +01:00
4f4d809a4e
fhdl: better matching of assignment
2011-12-18 21:49:48 +01:00
107f03fd4b
Remove uses of declare_signal
2011-12-18 21:47:48 +01:00
dd42b2daff
fhdl: also take into account object attributes in _make_signal_name. Get rid of declare_signal
2011-12-18 21:47:29 +01:00
41e2430e2b
fhdl: automatic signal name from assignment
2011-12-18 21:26:51 +01:00
135a2eb868
bank: support raw registers
2011-12-18 00:28:04 +01:00
d21e095397
fhdl: fix series of if/elif/else
2011-12-17 20:31:42 +01:00
1a845d4553
32-device, 8-bit CSR bus
2011-12-17 15:54:49 +01:00
6f8a6db40a
verilog: get the simulator to run the combinatorial process at the beginning
2011-12-17 15:20:22 +01:00
ec47394012
verilog: support for float parameters in instances
2011-12-17 14:59:27 +01:00
ee6ca729a2
verilog: user-definable reset and clock
2011-12-16 22:25:05 +01:00
c7b9dfc203
fhdl: simpler syntax
2011-12-16 21:30:14 +01:00
39b7190334
Pay a bit more attention to PEP8
2011-12-16 16:02:55 +01:00
929cc98070
wishbone2csr: wait for WB deack
2011-12-13 17:38:59 +01:00
22d03b4943
timeline: only trigger in rest state
2011-12-13 15:25:46 +01:00
c840848dba
verilog: use blocking assignment in combinatorial process
2011-12-13 14:09:12 +01:00
92f24b784d
wishbone: decoder: fix slave cyc generation in registered mode
2011-12-13 14:08:39 +01:00
0ea7a9b2e6
wishbone2csr: fix double-write bug
2011-12-13 00:25:46 +01:00
923fc52e68
wishbone: only send ack to the active master in arbiter
2011-12-13 00:25:25 +01:00
a72faaecdd
fhdl: allow a namespace to be specified for Verilog conversion
2011-12-13 00:24:40 +01:00
eee6980a36
fhdl: support Constant parameters for Verilog conversion
2011-12-11 20:17:51 +01:00
dafef5d744
fhdl: fix list references (thanks Lars)
2011-12-11 20:17:29 +01:00
16a6029a1b
bus: fix CSR interconnect data readback
2011-12-11 20:17:12 +01:00
dad9120653
bus: 14-bit CSR addresses
2011-12-11 20:16:50 +01:00
7582b76406
bank: fix csrgen address decoder
2011-12-11 20:15:30 +01:00
05d91c7104
bus: Wishbone to CSR bridge
2011-12-11 15:04:34 +01:00
af74a89b8a
corelogic: timeline module
2011-12-11 01:11:13 +01:00
019ef16db4
fhdl: remove broken fragment iadd
2011-12-11 01:10:59 +01:00
b00581616e
convtools: insert reset on variables
2011-12-11 01:10:37 +01:00
d3127fd5d8
autofragment: remove debug
2011-12-10 20:48:23 +01:00
44f44b8a05
fhdl: autofragment
2011-12-10 20:47:21 +01:00
4b15a84505
fhdl: fix += for empty fragment
2011-12-10 20:47:06 +01:00
a49ecc4331
fhdl: pad support in fragments
2011-12-10 20:25:24 +01:00
4d1a960308
wishbone: decoder + shared bus interconnect
2011-12-09 13:11:52 +01:00
fa63cc1ec8
fhdl: replication support
2011-12-09 13:11:34 +01:00
5c7131dc86
wishbone: arbiter
2011-12-08 23:21:25 +01:00
c1041b9a5f
simplebus: export GetSigName function
2011-12-08 23:06:04 +01:00
b2bc5ad4f4
corelogic: multimux module
2011-12-08 23:04:34 +01:00
b0c5b74c22
verilog: handle default in case statements
2011-12-08 23:04:20 +01:00
512655c108
fhdl: improve automatic signal naming
2011-12-08 21:28:20 +01:00
5034af3038
Corelogic conversion example
2011-12-08 21:25:05 +01:00
62f70a54f0
corelogic: MC divider module
2011-12-08 21:19:40 +01:00
Sebastien Bourdeauducq
Lars-Peter Clausen
Brandon Hamilton