Florent Kermarrec
52d7f59af5
software/liblitedram: remove DDRPHY_CMD_DELAY support (no longer useful).
2020-06-25 09:01:33 +02:00
Florent Kermarrec
07f145fdaf
software/liblitedram/sdram: remove SRAM hack.
...
We now have memtest bios functions to test memories and testing SRAM while used by the BIOS is probably not a good idea.
2020-06-25 08:58:01 +02:00
Florent Kermarrec
e2f9a82529
software/libbase/memtest: reorder functions.
2020-06-25 08:47:57 +02:00
Jędrzej Boczar
3b084b284a
bios: move memtest from liblitedram to libbase
2020-06-24 14:53:18 +02:00
Florent Kermarrec
3a5aec6933
software/liblitesdcard: simplify, switch to DMAs, remove clocking/test functions.
2020-06-24 12:25:37 +02:00
Florent Kermarrec
fd4765e159
integration/soc: replace SDDataReader/SDDataWriter with DMAs.
2020-06-24 12:23:35 +02:00
Florent Kermarrec
bc64e35480
soc/cores: add simple DMA with WishboneDMAReader/WishboneDMAWriter.
2020-06-24 12:22:44 +02:00
Florent Kermarrec
d7cc7d2ac6
platforms/genesys2: add usb_fifo.
2020-06-23 18:01:51 +02:00
Florent Kermarrec
309eda4246
litex_term: keep and reduce inter-frame delay to 1e-5.
...
Removing it completely would require revisiting the gateware/firmware code of the
UART. Since this is use for test purpose only and already allow > 600KB/s upload
speed, keeping it is acceptable.
2020-06-23 17:20:12 +02:00
Florent Kermarrec
64589cfd2b
soc/cores/uart/FT245: only use Asynchronous FIFO (Synchronous FIFO requires a software configuration).
2020-06-23 16:53:17 +02:00
Florent Kermarrec
0780b629a9
soc/cores/usb_fifo: cleanup and reduce fifo_depth (provide similar throughput when used as UART).
2020-06-23 16:51:24 +02:00
Florent Kermarrec
d59cec5acc
software: use a single crt0 (deprecate crt0-ctr/crt0-xip) and avoid unnecessary defines.
...
Since https://github.com/enjoy-digital/litex/issues/566 , crt0-ctr and crt0-xip are now similiar
so we can get back to a single crt0 and remove the defines that were generated to distinguish
the different cases.
Since LiteX/MiSoC have diverged and are no longer compatible, we also no longer need to generate
the LiteX flag.
2020-06-23 12:41:48 +02:00
Florent Kermarrec
384646c6be
platforms/genesys2: use openocd_genesys2.cfg.
2020-06-23 11:58:36 +02:00
Florent Kermarrec
e92efc1ac5
platforms/kcu105: add sdcard/spisdcard.
2020-06-23 11:54:33 +02:00
Florent Kermarrec
35b04658a6
genesys2: add sdcard/spisdcard.
2020-06-23 11:54:16 +02:00
Florent Kermarrec
d53a51c550
platforms/netv2: add spisdcard.
2020-06-23 11:54:05 +02:00
Florent Kermarrec
c895586461
platforms/k705: rename mmc to sdcard and make it similar to other boards.
2020-06-23 10:57:43 +02:00
Florent Kermarrec
02908c51b3
cpu/lm32: fix config include paths.
...
Was broken since the switch to python data modules.
2020-06-23 09:47:04 +02:00
Florent Kermarrec
b1fe3140d7
bios/main: enable sdcardboot in boot_sequence with litesdcard.
2020-06-22 21:57:00 +02:00
Florent Kermarrec
847a5fcff4
software/liblitesdcard/sdcard: boot with FatFs working (hacky).
...
Tested with Linux-on-LiteX-Vexriscv on Trellisboard with 10MHz clock.
2020-06-22 21:33:17 +02:00
Florent Kermarrec
5b2f9c244d
cores/cpu/microwatt: revert setup stack and fix missing subi %r1,%r1,0x100 (thanks ozbenh).
...
Tested with powerpc64le-buildroot-linux-gnu-gcc.br_real (Buildroot 2020.02-00011-g7ea8a52) 8.4.0.
2020-06-22 17:09:55 +02:00
Florent Kermarrec
0c0689f444
wishbone/DownConverter: fix read datapath when access is skipped because sel = 0.
...
We also need to shift dat_r when acess is skipped.
2020-06-22 13:37:14 +02:00
Florent Kermarrec
84617b585b
cores/cpu/microwatt: temporary revert crt0.S/setup stack.
...
lxsim --cpu-type=microwatt --cpu-variant=standard+ghdl no longer working otherwise.
2020-06-22 11:36:19 +02:00
Benjamin Herrenschmidt
28ea4b3f4c
software/microwatt: Fix copying data to RAM and clearing BSS
...
This also makes us use the "small" memory model to avoid having to
use more complex constructs and adds the TOC to the linker script
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-06-21 19:35:04 +10:00
Florent Kermarrec
13e0852af4
tools/litex_server: set socket option flags separately (required for Mac OS X).
2020-06-20 22:20:29 +02:00
Florent Kermarrec
efa41fd6bb
litex_sim: simplify a bit ethernet+etherbone.
2020-06-20 09:15:56 +02:00
Florent Kermarrec
b0b37b4cb9
soc/cores/spi: make cs/loopback CSR optional.
...
Useful for API retro-compatibility.
2020-06-19 14:17:30 +02:00
Florent Kermarrec
05cb5f96a1
bios/boot: rewrite ROM boot description.
2020-06-18 12:56:29 +02:00
enjoy-digital
bdcccb9216
Merge pull request #569 from gsomlo/gls-mor1kx-data-init
...
cpu/mor1kx: fix .data initialization (follow-up to PR #567 )
2020-06-18 08:43:20 +02:00
Gabriel Somlo
9ad45a6932
liblitesdcard/[spi]sdcard: avoid redundant (re-)initialization
2020-06-17 17:21:33 -04:00
Gabriel Somlo
e96cfbbc83
cpu/mor1kx: fix .data initialization (follow-up to PR #567 )
2020-06-16 20:28:57 -04:00
enjoy-digital
aa0cd21378
Merge pull request #565 from gsomlo/gls-cosmetic-spi-fat
...
post-FatFs cleanup
2020-06-16 21:49:15 +02:00
enjoy-digital
05d4756eff
Merge pull request #567 from zyp/fix_data_segment
...
bios/linker: Place .data in sram with initial copy in rom.
2020-06-16 21:45:17 +02:00
Florent Kermarrec
b0f7611258
platforms/arty: move sdcard_pmod_io to JD.
2020-06-16 20:17:15 +02:00
Ilia Sergachev
3610b066c2
build/sim/core/modules: fix compilation warnings
2020-06-16 01:06:11 +02:00
Gabriel Somlo
5d9d99c0c2
liblitesdcard/sdcard: streamline initialization (cosmetic)
...
Also, s/spisdcardstatus/sdcardstatus/g (this is *not* the SPI version).
2020-06-15 15:31:41 -04:00
Gabriel Somlo
c05d0f1966
liblitesdcard/spisdcard: streamline initialization (cosmetic).
2020-06-15 15:24:40 -04:00
Vegard Storheil Eriksen
27fcddb209
soc_core: Increase sram size default to 8k.
2020-06-15 21:18:26 +02:00
Vegard Storheil Eriksen
9c68d71503
bios/linker: Place .data in sram with initial copy in rom.
2020-06-15 16:24:53 +02:00
Vegard Storheil Eriksen
336896603f
bios/linker: Place .got in .rodata.
2020-06-15 16:04:02 +02:00
Gabriel Somlo
7d5ca3f926
bios/boot: addresses should use 'unsigned long'
2020-06-13 21:31:49 -04:00
Florent Kermarrec
5ddf350c2d
software/spisdcard: reduce SPISDCARD_CLK_FREQ to 16MHz.
...
25MHz does not seem to work on all boards/configurations, needs to be investigated.
2020-06-11 19:18:32 +02:00
Florent Kermarrec
d6f92d1ffd
build: add DFUProg.
2020-06-11 14:45:50 +02:00
Florent Kermarrec
653edd17ca
bios/boot: simplify flashboot (remove specific linux boot).
...
Storage in SPI Flash is generally limited and booting Linux from it is no longer very useful
since boot from SDCard is now supported. This is in the continuity of the SDCard/Ethernet
simplications to have an easier and more flexible boot scheme.
2020-06-11 13:38:38 +02:00
Florent Kermarrec
7b65a93ca5
bios/boot: add separators, update copyrights.
2020-06-11 13:19:37 +02:00
Florent Kermarrec
f4abdd3f2c
bios/boot: make Ethernet boot mode flexible (now also using boot.json similarly to SDCard boot).
...
Example of boot.json:
{
"Image": "0x40000000",
"rootfs.cpio": "0x40800000",
"rv32.dtb": "0x41000000",
"emulator.bin": "0x41100000"
}
2020-06-11 13:12:58 +02:00
Florent Kermarrec
c2ae22eeb6
bios/boot: make SDCard boot more flexible using a boot.json file on the SDCard.
...
The BIOS now reads the boot.json file to know which files need to be copied to RAM and where.
It will fallback to boot.bin is no boot.json is found and boot will fail if neither is found.
Example of boot.json file used to boot Linux-On-LiteX-Vexriscv:
{
"Image": "0x40000000",
"rootfs.cpio": "0x40800000",
"rv32.dtb": "0x41000000",
"emulator.bin": "0x41100000"
}
2020-06-11 11:26:10 +02:00
Florent Kermarrec
d918c0bb99
software/bios/boot/sdcardboot: let FatFs do the SDCard initialization with disk_initialize.
2020-06-11 08:33:56 +02:00
Florent Kermarrec
5197600812
software/bios/boot: add sdcardboot support for VexRiscv SMP.
2020-06-10 17:39:09 +02:00
Florent Kermarrec
72026d44f7
software/bios/main: clarify address space with @ instead of -.
2020-06-10 15:19:44 +02:00
enjoy-digital
a086237a07
Merge pull request #564 from shenki/microwatt-updates
...
Microwatt updates
2020-06-10 14:53:09 +02:00
enjoy-digital
ace81c83ee
Merge pull request #562 from gsomlo/gls-crlf
...
liblitesdcard: maintain unix newline convention across all source files
2020-06-10 14:40:28 +02:00
Florent Kermarrec
08bef5fc4c
software/liblitesdcard/ffconf: enable FF_FS_MINIMIZE and FF_FS_TINY.
2020-06-10 11:46:59 +02:00
Florent Kermarrec
75225e5e33
software/bios/boot: move f_mount to copy_image_from_sdcard_to_ram and force mount.
2020-06-10 11:46:18 +02:00
Florent Kermarrec
59a048b666
software/libliteeth/tftp: switch to progress bar.
2020-06-10 10:00:05 +02:00
Florent Kermarrec
f7e06a7e3f
bios/boot/copy_image_from_flash_to_ram: add missing init_progression_bar.
2020-06-10 09:59:38 +02:00
Florent Kermarrec
df9146fb78
soc/spisdcard: use 32-bit SPIMaster and do 32-bit xfers in spisdcardreceive_block to optimize speed.
2020-06-10 09:50:30 +02:00
Florent Kermarrec
d45cfc1e15
software/libbase/progress: avoid \t in progress bar, reduce HASHES_PER_LINE.
2020-06-10 09:16:06 +02:00
Florent Kermarrec
5beba178f2
software/libsdcard/spisdcard: add and use busy_wait_us to optimize speed.
2020-06-10 09:15:12 +02:00
Florent Kermarrec
dae15511a4
bios/boot/copy_image_from_sdcard_to_ram: use chunks of 32KB to increase speed.
2020-06-10 08:21:54 +02:00
Florent Kermarrec
d294e0f1de
bios/boot: add progress bar to copy_image_from_flash_to_ram, use uint32_t in flash/sdcard functions.
2020-06-10 08:12:12 +02:00
Florent Kermarrec
99f40fecaa
libase/progress: move __div64_32, do_div to div64.h/c as it was in Barebox.
2020-06-10 07:47:21 +02:00
Florent Kermarrec
96fc96eccd
software/liblitesdcard: remove read_block prototype, minor cleanup.
2020-06-10 07:40:08 +02:00
Joel Stanley
748dcc1c26
microwatt: Add mmu.vhdl
2020-06-10 12:30:52 +09:30
Joel Stanley
b57fc8702a
microwatt: Update IRQ signal in wrapper
2020-06-10 12:30:52 +09:30
Joel Stanley
68d2aa45fa
microwatt: Add icache flush
2020-06-10 12:30:49 +09:30
Joel Stanley
e6909e2978
microwatt: Implement boot helper
2020-06-10 11:23:22 +09:30
Gabriel Somlo
5575a921d0
liblitesdcard: maintain unix newline convention across all source files
2020-06-09 14:09:35 -04:00
Florent Kermarrec
fe9b42facf
bios/boot: use progress bar in copy_image_from_sdcard_to_ram.
2020-06-09 20:00:32 +02:00
Florent Kermarrec
21b9239dc0
libbase: add progress bar (from Barebox).
2020-06-09 20:00:05 +02:00
Florent Kermarrec
32ebbc7761
software/liblitesdcard: add retries when setting card to Idle.
2020-06-09 19:59:38 +02:00
Florent Kermarrec
04d0ba6187
software/liblitesdcard/sdcard: add FatFs disk functions.
2020-06-09 17:58:43 +02:00
Florent Kermarrec
e27ed657e9
software/liblitesdcard/spisdcard: rename #defines and allow external definition.
2020-06-09 13:50:28 +02:00
Florent Kermarrec
a9e8860e49
software/liblitesdcard: create fat directory for FatFs files.
2020-06-09 13:44:26 +02:00
Florent Kermarrec
f1aba7e45c
sofware/liblitesdcard: enable Long Filename (LFN).
2020-06-09 13:35:14 +02:00
Florent Kermarrec
fb282d1a72
software/libsdcard: rewrite/simplify SPISDCard/FatFs support and only keep SDCard ver2.00+ compatibility.
2020-06-09 12:50:56 +02:00
Gabriel Somlo
78e3f25157
liblitesdcard: convert all sources to unix style newlines (cosmetic)
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-06-06 13:24:29 -04:00
Florent Kermarrec
c1806eba11
software/liblitesdcard: remove unsused functions with FF_FS_READONLY.
2020-06-05 23:25:54 +02:00
Florent Kermarrec
f9b43c81cc
software/liblitesdcard: switch to FatFs for sdcardboot.
2020-06-05 21:20:19 +02:00
Florent Kermarrec
f972c8e45e
software/liblitesdcard: base it on FatFs generic example code + LiteX's SPIMaster specific functions.
2020-06-05 16:27:38 +02:00
Florent Kermarrec
5b908983a2
software/liblitesdcard: add FatFs files.
...
To avoid maintaining our own code and support all Fat filesystems, let's just use FatFs library.
2020-06-05 16:26:58 +02:00
Florent Kermarrec
7d141258be
software/liblitesdcard/spisdcard: simplify/rewrite for consistency with the others parts of the project.
...
- Improve code readability, remove un-needed or duplicate comments.
- Only use a spi_xfer function for both write/read.
- Set the SDCard to low clk freq before init and increase it when initialized.
2020-06-05 12:46:23 +02:00
Florent Kermarrec
860ac1e212
software/liblitesdcard: add copyrights to spisdcard/fat16.
2020-06-04 12:14:54 +02:00
Florent Kermarrec
0ec50881f0
software/liblitesdcard/sdcard: simplify readSector.
2020-06-04 11:55:25 +02:00
Florent Kermarrec
8c6f74d483
software/liblitesdcard: fat16 boot working with both SPI and SD modes.
2020-06-04 11:40:42 +02:00
Florent Kermarrec
bdaf6ff2dd
software/liblitesdcard: move fat16 code to separate file to avoid duplication.
2020-06-03 23:16:13 +02:00
Florent Kermarrec
4b3c5203ed
software/bios/libsdcard: add initial boot from sdcard with litescard, rename spisdcardboot command to sdcardboot.
2020-06-03 20:03:18 +02:00
Florent Kermarrec
b30e3353b5
soc/add_sdcard: use SDClockerS7 for 7-Series and SDClockerGen for others devices.
2020-06-03 18:37:08 +02:00
Jan Kowalewski
eceee7e4c4
litex/soc/software/liblitespi: fix names associated with PHY CSRs
2020-06-03 15:37:06 +02:00
Florent Kermarrec
fb4b6c35a3
boards/ulx3s: add sdcard pins and initial LiteSDCard integration.
2020-06-03 14:36:33 +02:00
Florent Kermarrec
997a17b933
soc/add_sdcard: add minimal SDClockerECP5 on ECP5.
2020-06-03 14:34:59 +02:00
Florent Kermarrec
9a026c09f9
soc/add_sdcard: remove limitation to 7-Series but only add clocker for it.
2020-06-03 13:47:39 +02:00
Florent Kermarrec
c311f98cfa
soc/add_sdcard: emulator clocking moved to litesdcard.
2020-06-03 13:43:44 +02:00
Florent Kermarrec
382f239e74
software/libsdcard: keep SDCARD_DEBUG enabled for now, fix typos.
2020-06-03 13:38:34 +02:00
Florent Kermarrec
20bbdaaf6b
soc/add_sdcard: remove Timer (unused).
2020-06-03 13:13:07 +02:00
Florent Kermarrec
ab447df922
software/liblitesdcard: review/simplify (code is over-complicated, revert part of the old code and write a minimal test for now).
2020-06-03 13:12:45 +02:00
Florent Kermarrec
ee4056cfec
software/liblitesdcard: remove sdtimer functions (unused).
...
sdtimer was used to evaluate performance but is no longer used.
2020-06-03 11:11:45 +02:00
Mariusz Glebocki
635a61e306
targets/arty: use sys_clk_freq = 60MHz for Symbiflow toolchain
2020-06-02 16:23:08 +02:00
Mariusz Glebocki
5071ef3ef7
build/xilinx/symbiflow: remap part name
2020-06-02 16:23:08 +02:00
Florent Kermarrec
55723f138b
software/liblitedram: revert sdrsw() in sdrlevel: this is still required for sdrlevel command.
2020-06-02 16:14:53 +02:00
enjoy-digital
ddcf68c062
Merge pull request #553 from ozbenh/sim-autoinit
...
sdram: Unconditionally switch to SW control before inits
2020-06-02 15:49:00 +02:00
Mateusz Holenko
f1e7d73e48
bios: boot: Boot linux on mor1kx with external device tree and rootfs
2020-06-02 14:57:48 +02:00
Florent Kermarrec
5d202ddb97
test: update.
2020-06-02 13:51:48 +02:00
Florent Kermarrec
01f7947b56
targets: rename gateware-toolchain parameter to toolchain.
2020-06-02 13:44:23 +02:00
Florent Kermarrec
245985d6c5
targets/arty: integrate symbiflow changes to avoid duplication.
2020-06-02 13:37:19 +02:00
Florent Kermarrec
89106873db
build/generic_platform: add default_clk constraints only when used.
2020-06-02 13:34:09 +02:00
Florent Kermarrec
0cd613ccb8
build/xilinx/symbiflow: reuse .xdc generation from Vivado to avoid duplication, fix copyright.
2020-06-02 13:21:12 +02:00
Florent Kermarrec
80ec5eca76
boards/arty: remove specific arty_symbiflow platform and adapt target to use standard platform.
2020-06-02 12:18:12 +02:00
Florent Kermarrec
af928b2626
xilinx/simbiflow: add simple symbiflow_device re-mapping.
2020-06-02 12:15:38 +02:00
enjoy-digital
5104d07a13
Merge pull request #551 from antmicro/mglb/symbiflow-toolchain-xilinx-7-support
...
Add Symbiflow toolchain support for Xilinx 7-series
2020-06-02 11:55:33 +02:00
Tim Ansell
77139289f8
Merge pull request #552 from ozbenh/memspeed-long
...
sdram: Use unsigned long for memory test
2020-06-01 15:23:03 -07:00
Benjamin Herrenschmidt
6239eac130
sdram: Use unsigned long for memory test
...
This makes it twice as fast on 64-bit CPUs when using a 64-bit bus :-)
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-06-02 08:08:42 +10:00
Mariusz Glebocki
ae121aacdf
targets: add arty_symbiflow
...
Signed-off-by: Mariusz Glebocki <mglebocki@antmicro.com>
2020-06-01 21:41:56 +02:00
Mariusz Glebocki
2bb2fbdbea
platforms: add arty_symbiflow
...
Signed-off-by: Mariusz Glebocki <mglebocki@antmicro.com>
2020-06-01 21:41:17 +02:00
Mariusz Glebocki
bd702397d1
build/xilinx: add Symbiflow toolchain support
...
Signed-off-by: Mariusz Glebocki <mglebocki@antmicro.com>
2020-06-01 21:36:28 +02:00
enjoy-digital
a116578c82
Merge pull request #550 from antmicro/jboc/spd-read
...
bios/litedram: Add command to verify SPD contents with the one used during generation
2020-06-01 21:17:40 +02:00
Benjamin Herrenschmidt
4a6256a50d
sdram: Unconditionally switch to SW control before inits
...
This will allow the controller to default to HW control which means
the sim model can be used without specific initializations
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-06-01 23:44:09 +10:00
Mariusz Glebocki
a4e8323485
build/xilinx: do not assume build name is "top"
2020-06-01 13:28:54 +02:00
enjoy-digital
5cc7a98845
Merge pull request #547 from gsomlo/gls-fix-sdcard-status
...
soc/software/litesdcard: update for response register back to 128 bits
2020-06-01 11:37:05 +02:00
Florent Kermarrec
395af900fd
interconnect/wishbone/DownConverter: skip accesses on slave when sel==0 and simplify.
...
Improve efficiency for 64-bit CPU accessing only the 32-bit LSBs/MSBs.
2020-06-01 11:06:23 +02:00
Florent Kermarrec
511832a911
soc/interconnect/axi: generate wishbone.sel for reads.
2020-06-01 10:58:45 +02:00
Florent Kermarrec
4f82a36afd
soc/software: only keep 32-bit CSR alignment support.
...
64-bit support was added for 64-bit CPU because of limitation of the hardware
on CSR accesses. Now that the Wihhbone2CSR bus handles wishbone.sel, this is no
longer required.
2020-06-01 10:01:14 +02:00
Gabriel Somlo
28290efd00
soc/software/litesdcard: update for response register back to 128 bits
...
The additional (17th) byte returned via the response register was
ignored by software (bios and kernel), so LiteSDCard was updated
to only return the (original, useful) 128 bits.
This patch updates the LiteSDCard code in the LiteX bios to only
expect those 128 bits, and to do so in a manner that's portable
across CSR data widths and alignments.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-05-30 18:12:51 -04:00
Florent Kermarrec
759367752c
wishbone/wishbone2csr: use wishbone.sel on CSR write.
...
CSR write is only done if wishbone.sel != 0. This should avoid the need for 64-bit
CSR alignment on 64-bit CPUs since a 64-bit Wishbone write access targeting only the
32-bit LSB or MSB will be splitted in 2x32-bit accesses: one with sel=0xf, one with sel=0.
2020-05-30 15:22:02 +02:00
Florent Kermarrec
b1ec092e88
soc/software/litesdcard: use new send register to send command and remove CSR8_CMD_FIX.
2020-05-29 20:15:02 +02:00
Florent Kermarrec
efcba14b1b
platforms/nexys_video: add spisdcard pins.
2020-05-29 19:36:33 +02:00
Florent Kermarrec
119ce56f6c
targets/nexys_video: add spi-sdcard and sdcard support.
2020-05-29 19:26:29 +02:00
Florent Kermarrec
cc5950178d
plaforms/nexys_video: keep up to date with litex-boards.
2020-05-29 19:26:03 +02:00
Florent Kermarrec
5cc564fb8f
targets: simplify Ethernet/Etherbone integration on targets with both.
2020-05-29 19:22:35 +02:00
Florent Kermarrec
55c7461e7b
bios/cmds/cmd_litesdcard: rewrite comments/descriptions.
2020-05-29 18:51:24 +02:00
Florent Kermarrec
6cb03963f3
bios/main: replace / with -.
2020-05-29 18:40:54 +02:00
enjoy-digital
5dd5f97b88
Merge pull request #545 from gsomlo/gls-fix-mmptr
...
csr: fix simple accessor alignment
2020-05-29 18:32:30 +02:00
Gabriel Somlo
3e1b17d459
csr: fix simple accessor alignment
...
MMPTR should always follow CSR alignment, NOT CSR data width.
(the latter merely indicates how many bits within a MMPTR are
actually populated).
Fixup for commit #4a5072a.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-05-29 12:03:05 -04:00
Florent Kermarrec
6c1e2d8413
software/liblitesdcard: replace hexdump with dump_bytes already available in the BIOS.
2020-05-29 17:15:20 +02:00
Florent Kermarrec
9e068a7494
soc/add_sdcard: add with_emulator parameter to use SDCard emulator (from Google Project Vault) and integrate it in litex_sim.
2020-05-29 16:07:40 +02:00
Jędrzej Boczar
a433c837e0
bios/litedram: add option to verify SPD EEPROM memory contents
2020-05-29 15:14:54 +02:00
Jędrzej Boczar
1692dfbf61
build/sim/spdeeprom: use hex format when loading from file
2020-05-29 14:56:56 +02:00
enjoy-digital
62d939e85f
Merge pull request #543 from antmicro/jboc/eeprom-sim
...
litex/build/sim: add module for simulating SPD EEPROM
2020-05-28 16:46:34 +02:00
Florent Kermarrec
c4f96318ec
targets/nexys4ddr: fix sdcard assert.
2020-05-28 15:31:33 +02:00
Florent Kermarrec
76cc112ecf
bios: add main bus and csr bus infos, use KiB/GiB.
2020-05-28 15:05:24 +02:00
Jędrzej Boczar
a0ce4ce56b
litex/build/sim: add module for simulating SPD EEPROM
2020-05-28 12:10:25 +02:00
Florent Kermarrec
02072deab1
integration/soc/add_sdcard: always use 32-bit/512bytes memories (not sure this will change?) and allocate sdwrite/sdread regions dynamically.
2020-05-27 23:47:07 +02:00
Florent Kermarrec
4b3afa75a7
integration/soc: add add_sdcard method with integration code from nexys4ddr.
...
Even if not cleaned up yet, having it there will avoid duplications in targets.
2020-05-27 23:18:15 +02:00
Benjamin Herrenschmidt
c78caeb998
csr: Fix definition(s) of CSR_BASE in generated headers
...
CSR_BASE is currently defined twice. Once in mem.h as the base
of the CSR region in the SoC address space, and once in csr.h
as the base address for all CSRs.
This fixes two issues with those definitions:
- The mem.h one is unconditional which prevents an external
redefinition (which is useful under some circumstances such as
when using an address decoder outside of LiteX with a standalone
core).
- The csr.h one is actually the origin of the first CSR region
rather than the origin of the CSR region in the SoC space. They
are usually the same ... unless you don't have CSR bank 0 in
which case the csr.h one becomes different. This causes conflicts
with the mem.h definition and breaks projects using a standalone
cores.
The first one is fixed by adding the #ifndef/#endif around the
definition of the memory regions, the second one by passing the
csr_base to use to get_csr_header()
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-27 21:48:00 +02:00
Benjamin Herrenschmidt
f8bb500a43
liblitedram/sdram: Add option to disable cdelay()
...
When running in sim, those delays can take a *long* time, which
isn't always necessary with the simulated litedram PHY.
This allows system.h to optionally set CONFIG_SIM_DISABLE_DELAYS
which causes cdelay to do nothing.
This is especially useful when using a verilated litedram inside
a bigger/slower simulated design as to not spend a huge amount
of time going through the initializations.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-27 21:39:28 +02:00
Florent Kermarrec
6d72ef28a8
cpu/serv: add variants.
2020-05-27 20:00:10 +02:00
Florent Kermarrec
fd7ec50e43
soc/integration/export: add optional csr_base parameter.
2020-05-27 19:59:54 +02:00
Florent Kermarrec
795ff08a20
build/sim/verilator: add regular_comb parameter (that defaults to False) and pass it to get_verilog.
2020-05-27 19:54:52 +02:00
enjoy-digital
25d2e7c92f
Merge pull request #542 from gsomlo/gls-sdcard-followup
...
software/bios: fixup sdclk command
2020-05-27 19:04:18 +02:00
enjoy-digital
3fd6ecd86e
Merge pull request #541 from antmicro/jboc/spd-read
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Add support for I2C to read SPD EEPROM
2020-05-27 19:03:50 +02:00
Florent Kermarrec
ab80606036
soc/core/uart: move WishboneStreamingBridge in it and rename to Stream2Wishbone.
2020-05-27 18:40:45 +02:00
Gabriel Somlo
6da98ca14d
software/bios: fixup sdclk command
2020-05-27 12:38:59 -04:00
Florent Kermarrec
0a3d649ad8
interconnect/wishbone: integrate Wishbone2CSR.
2020-05-27 18:15:05 +02:00
Florent Kermarrec
b5b88d27b5
interconnect/csr_bus: add separators.
2020-05-27 18:13:57 +02:00
Florent Kermarrec
86952a6e06
interconnect/wishbone: remove CSRBank (probably not used by anyone).
2020-05-27 18:04:08 +02:00
Florent Kermarrec
e404608cf4
interconnect/wishbone: add separators and move SDRAM/Cache.
2020-05-27 17:59:33 +02:00
Florent Kermarrec
1fddd0e3d3
interconnect/wishbone: simplify DownConverter.
2020-05-27 17:34:11 +02:00
Jędrzej Boczar
1172c10afb
bios: move I2C from liblitedram to libbase
2020-05-27 15:37:19 +02:00
Florent Kermarrec
e0d2682055
interconnect/wishbone: remove UpConverter (probably not used by anyone and would need to be rewritten).
...
We'll provide a better implementation if this is useful.
2020-05-27 15:27:33 +02:00
Florent Kermarrec
696b31ed18
tools/litex_sim: switch to SoCCore/add_sdram instead of SoCSDRAM.
2020-05-27 15:16:30 +02:00
Florent Kermarrec
2efcf87925
targets/nexys4ddr: update add_sdcard method.
...
Tested with:
sdinit
sdtestwrite 0x10 foobar
sdtestread 0x10
2020-05-27 14:09:05 +02:00
Jędrzej Boczar
472bf9ac71
bios/sdram: expose I2C functions
2020-05-27 11:56:59 +02:00
Florent Kermarrec
3b47d4a479
tools/litex_jtag_uart: add openocd config and telnet port parameters.
2020-05-27 08:59:12 +02:00
Florent Kermarrec
67cf67034c
cpus: remove common cpu variants/extensions definition and simplify variant check.
...
Having common cpu variants/extensions has no real additional value since we are supporting
very various CPUs where minimal/standard/full have different meanings. Checking against
common variants/extensions has also cause more issues recently when adding new CPUs than
the additional value it was supported to provide.
So let's just simplify things: a CPU provide the supported variants and we just check
against that.
2020-05-26 09:36:44 +02:00
Florent Kermarrec
062ff67e12
cpu/microwatt: add standard+ghdl variant that uses GHDL Yosys plugin.
2020-05-26 08:51:33 +02:00
Florent Kermarrec
24687cbd9f
tools/litex_client/RemoteClient: add base_address parameter.
...
Useful when address translation is done in the SoC.
2020-05-25 14:11:14 +02:00
Florent Kermarrec
78a9579e09
cores/uart/RS232PHYTX: fix startbit duration by pre-loading phase_accumulator_tx to tuning_word.
2020-05-25 10:46:53 +02:00
enjoy-digital
370e46529d
Merge pull request #539 from dayjaby/pr-fix_uart_startbit
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Fix UART startbit: 1 cycle later
2020-05-25 10:33:58 +02:00
Florent Kermarrec
c75cf45ab4
tools: add litex_jtag_uart to create a virtual uart for the jtag uart.
2020-05-25 10:21:06 +02:00
Florent Kermarrec
2cf83b9f69
tools: rename litex_crossover poc to litex_crossover_uart, remove from setup for now.
2020-05-25 10:19:16 +02:00
David Jablonski
e853ad4b61
fix uart startbit: 1 cycle later
2020-05-24 16:12:07 +02:00
Florent Kermarrec
bed5aafd6c
tools: add litex_crossover to be able to use lxterm (and serialboot) over a crossover UART (bridged over UART/Ethernet/PCIe/USB, etc...).
...
This is still a proof of concept but can be used/tested with:
lxsim --with-etherbone --uart-name=crossover --csr-csv=csr.csv
lxserver --udp --udp-ip=192.168.1.51
lxcrossover (will indicate the virtual_tty)
lxterm virtual_tty
2020-05-24 10:55:25 +02:00
Florent Kermarrec
3833bc3ec3
litex_sim: override uart_name to sim only for serial.
...
Using uart_name=crossover is useful to simulate crossover mode.
2020-05-24 09:52:56 +02:00
Florent Kermarrec
2fb52e66b1
integration/soc: remove TODO in header.
2020-05-23 18:54:04 +02:00
Florent Kermarrec
b65f18c357
cpu/cv32e40p: fix copyright year.
2020-05-23 18:53:03 +02:00
Florent Kermarrec
30f3517041
cpu/cv32e40p: add copyright and improve indentation.
2020-05-22 15:55:35 +02:00
enjoy-digital
4c4cd335de
Merge pull request #535 from antmicro/arty-cv32e40p
...
Add support for the CV32E40P RISC-V CPU
2020-05-22 13:44:10 +02:00
Mateusz Hołenko
9d16b0fc82
libbase: Include missing uart header
...
This fixes compilation on mor1kx.
2020-05-22 11:43:18 +02:00
Jędrzej Boczar
bdc7eb5c48
litex_sim: load SPD data from files in hexdump format as printed in BIOS
2020-05-21 16:20:06 +02:00
Jędrzej Boczar
a42dc97401
bios/sdram: add BIOS command for reading SPD
2020-05-21 14:32:31 +02:00
Jędrzej Boczar
8fd3e74ec9
bios/sdram: add firmware for reading SPD EEPROM
2020-05-21 14:07:42 +02:00
Florent Kermarrec
42350f6d83
platforms/targets: keep in sync with litex-boards.
...
- LedChaser.
- use of soc.build_name in load/flash bitstream.
2020-05-21 09:14:33 +02:00
Florent Kermarrec
2eea786436
build/sim: rename dut to sim (for consistency with other builds).
2020-05-21 09:06:29 +02:00
Florent Kermarrec
a6cbbc9d69
integration/soc: set build_name to platform.name when not specified.
2020-05-21 09:05:45 +02:00
Florent Kermarrec
16417cb8f1
software/liblitespi: fix #endif location.
2020-05-20 23:20:45 +02:00
enjoy-digital
9bdb063b3e
Merge pull request #516 from antmicro/i2s_support_arty
...
Add I2S support to Arty
2020-05-20 19:49:42 +02:00
Franck Jullien
7c5f56c207
litex/sim: fix compiler warnings
2020-05-20 15:34:19 +02:00
Pawel Sagan
ce49990084
Extend I2S capabilities
...
This commit:
* adds the support for I2S standard mode,
* extends I2S left justified mode,
* allows to configure sample size for tx/rx in 1-32 bits range,
* implements I2S master mode,
* allows to concatenate channels or used the padded mode.
This required to rework the FSM.
2020-05-20 14:31:51 +02:00
Piotr Binkowski
2d6ee5aaf2
cores/cpu: add cv32e40p
2020-05-20 13:46:37 +02:00
Piotr Binkowski
ca8cb83424
software/bios/isr: add support for cv32e40p
2020-05-20 13:46:37 +02:00
Jan Kowalewski
ab41e27e4c
software/liblitespi/spiflash: fix dummy bits setup function name
2020-05-20 11:47:40 +02:00
Florent Kermarrec
bd0f21ba85
targets/netv2: remove LiteSPI integration (not mature enough to be directly integrated on targets).
...
The LiteSPI integration can be prototype in the LiteSPI example designs. Once mature and
fully tested, we could integrate it to the targets.
2020-05-20 11:18:59 +02:00
Florent Kermarrec
80eca3000b
software/liblitespi/spiflash: review/simplify/update and test on arty.
2020-05-20 11:16:39 +02:00
Florent Kermarrec
4a1756208d
build/xilinx: simplify LITEX_ENV_ISE/VIVADO handling.
2020-05-20 10:00:39 +02:00
Florent Kermarrec
e91c317139
software/bios: cleanup includes and specify the lib in the include.
...
This ease understanding from which lib the file is included and also allow
having simple filenames in the libs.
2020-05-20 09:55:19 +02:00
Florent Kermarrec
c3a03d0d99
software: create liblitespi and mode litespi code to it (with some parts commented out for now).
2020-05-20 09:32:45 +02:00
Jan Kowalewski
61238beeae
soc/software/bios: add autoconfiguration functionality for LiteSPI core
2020-05-20 09:16:07 +02:00
Gabriel Somlo
c5524dbf20
software/bios: fix link order to avoid undefined symbol errors
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-05-19 16:20:58 -04:00
Florent Kermarrec
b4267a7901
build/xilinx: source settings64.sh automatically just before build if LITEX_ENV_ISE/LITEX_ENV_VIVADO environment variables are set.
2020-05-19 16:21:52 +02:00
Florent Kermarrec
de7e0ee9ff
integration/soc_core: avoid cpu_variant check if custom cpu_cls is passed.
2020-05-19 16:01:57 +02:00
Florent Kermarrec
6f8f0d2346
litex_setup: add litehyperbus and remove hyperbus core/test.
2020-05-19 15:49:25 +02:00
Florent Kermarrec
109fd2674a
integration/builder: simplify default output_dir to "build/platform".
...
All SoC are now based on the same base class and naming was too complicated.
2020-05-19 13:59:56 +02:00
Florent Kermarrec
7192397ab4
software/libbase: remove linker-sdram (unused).
2020-05-18 23:35:48 +02:00
Florent Kermarrec
b4b84def3c
software/bios: mode spisdcard code to liblitesdcard.
2020-05-18 23:33:34 +02:00
Florent Kermarrec
21e2a34c3f
software/bios: rename commands to cmds and update with libs' names.
2020-05-18 23:26:51 +02:00
Florent Kermarrec
33f6ce7431
software/bios: move hw flags definitions to respective libs, remove hw/flags.h.
2020-05-18 23:09:31 +02:00
Florent Kermarrec
403355a8ed
software: create liblitescard and move sdcard init/test code to it.
2020-05-18 22:49:12 +02:00
Florent Kermarrec
920d0ee536
software: create liblitedram and move sdram init/test code to it.
2020-05-18 22:42:23 +02:00
Florent Kermarrec
c95084e5c6
bios/software: rename cmd_dram/cmd_sdcard/cmd_spi_flash to cmd_litedram/cmd_litesdcard/cmd_spiflash.
2020-05-18 22:24:24 +02:00
Florent Kermarrec
573a881529
software/bios/commands: rename cmd_mdio to cmd_liteeth.
2020-05-18 22:16:20 +02:00
Florent Kermarrec
ff8d9e61bf
software/bios: move mdio to libliteeth.
2020-05-18 21:09:41 +02:00
Florent Kermarrec
70a67ce7ed
software/bios: rename libnet to libliteeth and move all ethernet files to it.
2020-05-18 21:04:54 +02:00
Florent Kermarrec
56b8723b72
software/bios: rename cmd_mem_access to cmd_mem.
2020-05-18 19:59:28 +02:00
Florent Kermarrec
a02077d547
cpu/microwatt/add_sources: add use_ghdl_yosys_synth parameter to convert microwatt to verilog using GHDL-Yosys-plugin and use converted verilog for build.
2020-05-18 17:30:42 +02:00
Florent Kermarrec
b5352f403c
cpu/microwatt: update microwatt_wraper.vhdl
2020-05-18 16:38:08 +02:00
Florent Kermarrec
be25500e91
uptime: rework and integrate it in Timer to ease software support.
2020-05-17 11:05:14 +02:00
Florent Kermarrec
d6549ff8f1
bios: add uptime command and rewrite cmd_bios comments.
2020-05-16 10:02:31 +02:00
Florent Kermarrec
fc0e55be32
soc: improve uptime comments.
2020-05-16 10:01:39 +02:00
enjoy-digital
840679add6
Merge pull request #526 from rprinz08/master
...
Make booting from SD-Card to behave same as from SPI flash
2020-05-15 16:03:37 +02:00
Florent Kermarrec
82364de57f
soc/SoCController: add uptime since start (disabled by default) and allow features to be enabled/disabled.
2020-05-15 15:00:04 +02:00
rprinz08
3f649077b1
Make booting from SD-Card to behave same as from SPI flash
2020-05-15 12:07:52 +02:00
Florent Kermarrec
3391398a5f
bios/sdram: always show bitslip on two digits to keep scan aligned.
2020-05-14 15:20:52 +02:00
Benjamin Herrenschmidt
1e35b0e705
csr: Rework accessors
...
Have all the new compound accessors be written in terms of the simple
ones and fix how CSR_ACCCESORS_DEFINED can be used to override the
simple ones but keep the definitions of the other ones around.
This *should* also also fix incorrect multiple accesses done
by 64-bit CPUs to 32-bit CSR busses, and make the accessors not
depend on CONFIG_CSR_ALIGNMENT being the same as sizeof(unsigned long)*8
In addition, the generated csr.h now will include system.h
always when with_access_functions is True. This guarantees that the
higher level accessors are defined. The extern prototypes for the
simple accessors when CSR_ACCCESORS_DEFINED are removed and system.h
is responsible for providing them. It is also added to hw/common.h
This allows system.h to set CSR_ACCCESORS_DEFINED when necessary, in
which case it's responsible for both declaring and defining the simple
accessors. That way, it can make them inline rather than forcing them
to be extern which at least on microwatt saves spaces.
One can continue to use -DCSR_ACCCESORS_DEFINED but in that case a system.h
will have to be provided with at least the extern definitions.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-14 21:38:19 +10:00
enjoy-digital
a51c7a7bac
Merge pull request #518 from enjoy-digital/csr_base
...
export: add define of CSR_BASE if not already defined and use it for …
2020-05-14 08:02:37 +02:00
Arnaud Durand
9d9e7d54cd
Update litex_term help
...
Specify the use of kernel address with flash flag.
2020-05-13 22:50:09 +02:00
Florent Kermarrec
2e59dc329d
platforms/nexys4ddr: add card detect pin to sdcard.
2020-05-13 19:11:46 +02:00
Florent Kermarrec
51742be2bb
integration/soc: review/simplify interconnect and add logger.info.
2020-05-13 18:29:12 +02:00
Benjamin Herrenschmidt
1ed6869110
soc: Revive generation of a PointToPoint interconnect
...
When there's only one master, one slave, and that slave is at 0
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-14 00:06:53 +10:00
Florent Kermarrec
748ef1add3
export: add define of CSR_BASE if not already defined and use it for CSRs definitions/accesses.
...
This will allow more flexibility when integrating standalone cores.
2020-05-13 15:56:20 +02:00
Florent Kermarrec
9d1443c1a8
cpu/soc_core: automatically set csr mapping to 0x00000000 when using CPUNone, remove csr_base parameter that was used for that.
2020-05-13 09:31:20 +02:00
Florent Kermarrec
5ea3bae036
bios/boot: review/fix #503 .
...
- copy_image_from_flash_to_ram is now used by all CPUs.
- copy_image_from_flash_to_ram already show the flash address, no need to duplicate it.
2020-05-13 08:44:17 +02:00
enjoy-digital
bf7857f553
Merge pull request #503 from rprinz08/master
...
BIOS boot firmware from SPI with address offset
2020-05-13 08:36:43 +02:00
Dave Marples
d2d82dacf2
Bios linker edits to prevent inappropriate optimisation
2020-05-12 23:32:49 +01:00
rprinz08
1f55fcf449
fixed bug in BIOS spi flash "fw" command
2020-05-12 16:58:42 +02:00
rprinz08
f062c0c44b
removed FLASH_BOOT_OFFSET, replaced memcyp with copy_image_from_flash_to_ram
2020-05-12 16:57:21 +02:00
Florent Kermarrec
3fb99b7d33
cores/spi_flash: add back old SpiFlashDualQuad and rename new one as SpiFlashQuadReadWrite.
2020-05-12 16:51:47 +02:00
enjoy-digital
2a5a7536b8
Merge pull request #478 from antmicro/extended_spi_flash
...
Extended SPI flash support
2020-05-12 16:42:01 +02:00
enjoy-digital
7d79da8eda
Merge pull request #510 from mubes/colorlight_usb
...
Colorlight usb
2020-05-12 16:35:29 +02:00
Florent Kermarrec
3a6dd95d6f
integration/soc: review/simplify changes for standalone cores.
...
- do the CSR alignment update only if CPU is not CPUNone.
- revert PointToPoint interconnect when 1 master and 1 slave since this will
break others use cases and will prevent mapping slave to a specific location.
It's probably better to let the synthesis tools optimize the 1:1 mapping directly.
- add with_soc_interconnect parameter to add_sdram that defaults to True. When
set to False, only the LiteDRAMCore will be instantiated and interconnect with
the SoC will not be added.
2020-05-12 16:18:26 +02:00
Dave Marples
8499733289
Fix dumb missing line
2020-05-12 14:40:11 +01:00
enjoy-digital
0d5eb13359
Merge pull request #511 from ozbenh/standalone-cores
...
Improve standalone cores
2020-05-12 14:55:44 +02:00
Florent Kermarrec
873d95e517
interconnect/wishbonebridge: refresh/simplify.
...
This should also improve Wishbone timings.
Tested on iCEBreaker:
./icebreaker.py --cpu-type=None --uart-name=uartbone --csr-csv=csr.csv --build --flash
With the following script:
#!/usr/bin/env python3
import sys
from litex import RemoteClient
wb = RemoteClient()
wb.open()
# # #
print("scratch: 0x{:08x}".format(wb.regs.ctrl_scratch.read()))
errors = 0
for i in range(2):
for j in range(32):
wb.write(wb.mems.sram.base + 4*j, i + j)
for j in range(32):
if wb.read(wb.mems.sram.base + 4*j) != (i + j):
errors += 1
print("sram errors: {:d}".format(errors))
# # #
wb.close()
2020-05-12 13:40:28 +02:00
Benjamin Herrenschmidt
f628ff6b47
WB2CSR: Use CSR address_width for the wishbone bus
...
Currently, we create a wishbone interface with the default address
width (30 bits) for the bridge. Instead, create an interface that
has the same number of address bits as the CSR bus.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-12 21:37:36 +10:00
Benjamin Herrenschmidt
520c17e96d
soc_core: Add option to override CSR base
...
When creating standalone IP cores such as standalone LiteDRAM without
a CPU, the CSR are presented externally via a wishbone with just enough
address bits to access individual CSRs (14), and no address decoding
otherwise. It is expected that the design using such core will have
its own address decoder gating cyc/stb.
However, such a design might still need to use LiteX code such as
the sdram init code, which relies on the generated csr.h. Thus we
want to be able to control the CSR base address used by that generated
csr.h.
This could be handled instead by having the "host" code provide
modified csr_{read,write}_simple() that include the necessary base
address. However, such an approach would make things complicated
if the design includes multiple such standalone cores with separate
CSR busses (such as LiteDRAM and LiteEth).
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-12 21:35:12 +10:00
Benjamin Herrenschmidt
ecbd40284a
soc: Don't update CSR alignment when there is no CPU
...
The alignment specified by the standalone core config should
be honored.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-12 21:31:23 +10:00
Benjamin Herrenschmidt
f28f247130
soc: Don't create a wishbone slave to LiteDRAM with no CPU
...
When creating a standalone LiteDRAM core with no CPU, there is
no need to create a wishbone slave to LiteDRAM interface.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-12 21:30:19 +10:00
Dave Marples
33e202edd4
Bring into line with master
2020-05-12 12:28:09 +01:00
Benjamin Herrenschmidt
dcc881db92
soc: Don't create a share intercon with only one master and one slave
...
This creates a lot of useless churn in the resulting verilog. Instead
use a point to point interconnect in that case.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-12 20:58:19 +10:00
enjoy-digital
c136113a9b
Merge pull request #506 from scanakci/blackparrot_litex
...
Update README and core.py for Blackparrot and change vivado command for systemverilog
2020-05-12 11:41:25 +02:00
Dave Marples
dc1d452008
Addition of boot address parameter for trellis builds
2020-05-12 09:41:37 +01:00
Kamil Rakoczy
0db3506997
Update Litex bios to handle updated litesdcard.
2020-05-12 10:07:16 +02:00
sadullah
aed1d514ab
Update README.md and core.py for BlackParrot
2020-05-12 03:06:38 -04:00
sadullah
5e4a436089
Vivado Command Update for Systemverilog
...
Add BlackParrot to LiteX setup file
2020-05-12 03:05:41 -04:00
enjoy-digital
3ce9010083
Merge pull request #505 from DurandA/patch-3
...
Enable 1x mode on SPI flash
2020-05-11 22:53:31 +02:00
Florent Kermarrec
e2176cefc2
soc: remove with_wishbone (a SoC always always has a Bus) and expose more bus parameters.
2020-05-11 22:39:17 +02:00
Arnaud Durand
2c40967b5a
Enable 1x mode on SPI flash
2020-05-11 22:12:40 +02:00
Florent Kermarrec
1e610600f6
build/lattice/diamond/clock_constraints: review and improve similarities with the others build backends.
2020-05-11 10:52:39 +02:00
enjoy-digital
ebcf67c10f
Merge pull request #502 from shuffle2/master
...
diamond: project generation improvements
2020-05-11 09:55:52 +02:00
enjoy-digital
13db89ebd2
Merge branch 'master' into rdimm_bside_init
2020-05-11 09:42:35 +02:00
Florent Kermarrec
c9e36d7fdd
lattice/icestorm: add ignoreloops/seed support (similar to trellis) and icestorm_args.
2020-05-11 09:33:26 +02:00
Florent Kermarrec
ea7fe383a3
lattice/trellis: simplify seed support and add it to trellis_args.
2020-05-11 09:26:12 +02:00
enjoy-digital
5ee01c9460
Merge pull request #484 from ilya-epifanov/lattice-trellis-toolchain-seed
...
Can now pass `--seed` to `nextpnr-ecp5` via `TrellisToolchain` `kwargs`
2020-05-11 09:13:26 +02:00
enjoy-digital
c5f74a5aa7
Merge branch 'master' into cpu-imac-config-for-vexriscv
2020-05-11 08:58:20 +02:00
Florent Kermarrec
59d88a880c
integration/soc/add_adapter: rename is_master to direction.
2020-05-11 08:47:50 +02:00
Ilia Sergachev
e4fa4bbcf7
integration/soc: fix add_adapter for slaves
2020-05-10 11:32:34 +02:00
Benjamin Herrenschmidt
2d70220b80
bios: Fix warning on 64-bit
...
This fixes an incorrect printf format specifier
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-09 19:44:43 +02:00
rprinz08
ea232fc53a
BIOS boot firmware from SPI with address offset
2020-05-09 19:20:32 +02:00
Shawn Hoffman
eeee179dd8
diamond: close project when done
...
Avoids ".recovery file is present" prompt.
2020-05-09 02:28:00 -07:00
Shawn Hoffman
9b782bd7da
diamond: clock constraint improvements
...
Specify NET or PORT for freq constraints
Add equivalent timing closure check that diamond ui uses,
and default to asserting check has passed
2020-05-09 02:28:00 -07:00
Florent Kermarrec
fbbbdf03b5
core/led: simplify LedChaser (to have the same user interface than GPIOOut).
2020-05-08 22:13:47 +02:00
Florent Kermarrec
05869beb72
cores/led: add LedChaser (now that LiteX is running on FPGA mining boards let's use fancy led blinks :))
2020-05-08 13:18:12 +02:00
Florent Kermarrec
90c485fcc8
integration/soc: add clock_domain parameter to add_etherbone.
...
To allow using a sys_clk < 125MHz with a 1Gbps link.
2020-05-08 13:16:26 +02:00
Florent Kermarrec
f1a50a2138
integration/soc: add add_uartbone method (to add a UARTBone aka UART Wishbone bridge).
2020-05-08 11:54:51 +02:00
Florent Kermarrec
79ee135f56
bios/sdram: fix lfsr typo.
2020-05-07 12:11:59 +02:00
enjoy-digital
162d32603d
Merge pull request #500 from mubes/fixups
...
Fixups
2020-05-07 11:55:58 +02:00
Florent Kermarrec
d74f8fc93d
build/xilinx: add disable_constraints parameter to Platform.add_ip.
...
When integrate .xci, we don't necessarily want to apply the default timing/loc
constrants generated by Vivado but our custom ones. Setting disable_constraints
to True allow disabling .xdc generated by the IP.
2020-05-07 11:34:26 +02:00
Dave Marples
2a37b97d9f
Merge branch 'master' of https://github.com/enjoy-digital/litex into fixups
2020-05-07 09:36:41 +01:00
Dave Marples
967e38bb57
Small fixups to address compiler warnings etc.
2020-05-07 09:26:46 +01:00
Florent Kermarrec
84841e1d58
bios/sdram: fix merge typo in lfsr (thanks Benjamin Herrenschmidt).
2020-05-07 08:21:57 +02:00
Benjamin Herrenschmidt
99c5b0fca1
bios/sdram: Use an LFSR to speed up pseudo-random number generation
...
This speeds up the memory test by an order of magnitude, esp. on
cores without a hardware multiplier by getting rid of the
multiplication in the loop.
The LFSR implementation comes from microwatt's simple_random test
project.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-06 21:56:10 +02:00
Florent Kermarrec
8b9aa16d2e
boards/platforms: update xilinx programmers.
2020-05-06 16:16:41 +02:00
Florent Kermarrec
3c34039b73
build/xilinx/vivado: ensure Vivado process our .xdc early.
...
When generating the LitePCIe PHY wrappers from the .xci, Vivado is locking the
PCIe lanes to default locations that do not necessarily match the ones used in
the design.
Processing our constraints earlier makes Vivado use our constraints and not the
ones from the generated wrapper.
2020-05-06 13:13:01 +02:00
Florent Kermarrec
b057858071
gen/fhdl/verilog: explicitly define input/output/inout wires.
...
When integrating designs which set `default_nettype none, the top also needs
to explicitly define the type of the signals.
2020-05-05 16:58:33 +02:00
Florent Kermarrec
0aa3c339cc
targets/genesys2: set cmd_latency to 1.
2020-05-05 16:33:14 +02:00
Florent Kermarrec
95b57899cd
bios: remove usddrphy debug (we'll use a specific debug firmware to fix the usddrphy corner cases).
2020-05-05 16:27:21 +02:00
Florent Kermarrec
98d1b45157
platforms/targets: fix CI.
2020-05-05 15:55:09 +02:00
Florent Kermarrec
22bcbec03a
boards: keep in sync with LiteX-Boards, integrate improvements.
...
- create_programmer on all platforms.
- input clocks automatically constrainted.
- build/load parameters.
2020-05-05 15:27:56 +02:00
Florent Kermarrec
28f85c7403
build/lattice/programmer: add UJProg (for ULX3S).
2020-05-05 13:31:58 +02:00
Florent Kermarrec
85ac5ef133
build/lattice/programmer: make OpenOCDJTAGProgrammer closer to OpenOCD programmer.
2020-05-05 12:17:12 +02:00
Florent Kermarrec
9a7f9cb87b
build/generic_programmer: catch 404 not found when downloading config/proxy.
2020-05-05 12:16:29 +02:00
Florent Kermarrec
d0b8daa005
build/platform: allow doing a loose lookup_request (return None instead of ConstraintError) and allow subname in lookup_request.
...
In the platforms, insead of doing:
self.lookup_request("eth_clocks").rx
we can now do:
self.lookup_request("eth_clocks:rx")
This allows some try/except simplifications on constraints.
2020-05-05 11:23:46 +02:00
Florent Kermarrec
b8f9f83a8f
build/openocd: add find_config method to allow using local config file or download it if not available locally.
2020-05-05 09:56:13 +02:00
Florent Kermarrec
9bef218ad6
cpu/microwatt: fix integration/crt0.S (thanks Benjamin Herrenschmidt).
...
Tested on Arty A7:
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2020 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on May 4 2020 17:15:13
BIOS CRC passed (0adc4193)
Migen git sha1: 5b5e4fd
LiteX git sha1: 6f24d46d
2020-05-04 17:30:50 +02:00
Gabriel Somlo
edfed4f068
software/*/Makefile: no need to copy .S files from CPU directory
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-05-04 09:16:52 -04:00
shuffle2
ee413527ac
diamond: quiet warning about missing clkin freq for EHXPLLL
...
FREQUENCY_PIN_CLKI should be given in mhz
2020-05-04 01:10:09 -07:00
Florent Kermarrec
2112703181
cpu/microwatt: add powerpc64le-linux-gnu to gcc_triple.
...
It seems to be what most distros cross-comiplers are using.
2020-05-04 08:51:38 +02:00
Florent Kermarrec
c06a127909
cpu/microwatt: add pythondata and fix build with it.
2020-05-04 08:46:25 +02:00
Florent Kermarrec
45377d9faa
cpus: use a common definition of gcc_triple for the RISC-V CPUs, reorganize CPU by ISA/Data-Width.
2020-05-03 21:29:54 +02:00
Florent Kermarrec
7c69a6dbba
bios/cmd_mdio.c: fix missing <base/mdio.h> import.
2020-05-03 10:54:35 +02:00
Florent Kermarrec
b02053357c
cpu/vexriscv: fix flush_cpu_icache, remove workaround on boot.c.
2020-05-02 20:07:52 +02:00
Florent Kermarrec
97e534d0b6
cpus: add nop instruction and use it to simplify the BIOS.
2020-05-02 12:52:25 +02:00
Florent Kermarrec
4efc783534
cpus: add human_name attribute and use it to simplify the BIOS.
2020-05-02 11:52:58 +02:00
Florent Kermarrec
d81f171c8a
software/libbase/system.c: remove unused includes.
2020-05-02 11:27:22 +02:00
enjoy-digital
999b93af0a
Merge branch 'master' into blackparrot_litex
2020-05-02 11:16:33 +02:00
enjoy-digital
705d388745
Merge pull request #474 from fjullien/term_hist_auto_compl
...
Terminal: add history and auto completion
2020-05-02 10:45:12 +02:00
Sadullah Canakci
0c770e0683
Update README.md
2020-05-02 02:51:41 -04:00
sadullah
19bb1b9b8c
update to comply with python-data layout
2020-05-01 23:44:20 -04:00
sadullah
3eb9efd64f
BP fpga recent version
2020-05-01 16:27:30 -04:00
sadullah
bf864d335b
Fix memory transducer bug, --with-sdram for BIOS works, memspeed works
2020-05-01 16:27:27 -04:00
sadullah
cf01ea65f3
rebased, minor changes in core.py
2020-05-01 16:25:01 -04:00
sadullah
b7b9a1f0fb
Linux works, LiteDRAM works (need cleaning, temporary push)
2020-05-01 16:24:58 -04:00
Sadullah Canakci
74140587c8
Create GETTING STARTED
...
Rename GETTING STARTED to GETTING STARTED.md
Update GETTING STARTED.md
Update GETTING STARTED.md
Update GETTING STARTED.md
2020-05-01 16:20:35 -04:00
enjoy-digital
e853cac6b6
Merge pull request #483 from ilya-epifanov/lattice-openocd-jtag-programmer-erase-flag-and-quiet-output
...
Lattice OpenOCD JTAG programmer: removed erase flag and made progress output less noisy
2020-05-01 21:18:09 +02:00
enjoy-digital
a6779b9d61
Merge pull request #491 from gsomlo/gls-spisd-clusters
...
software: spisdcard: cosmetic: avoid filling screen with cluster numbers
2020-05-01 21:17:38 +02:00
Florent Kermarrec
bd8a410047
cpu/minerva: add pythondata and use it to compile the sources.
2020-05-01 20:12:02 +02:00
Gabriel Somlo
c8e3bba4b7
software: spisdcard: cosmetic: avoid filling screen with cluster numbers
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-05-01 09:49:16 -04:00
Florent Kermarrec
3c70c83f9b
cpu/software: move flush_cpu_icache/flush_cpu_dcache functions to CPUs.
2020-05-01 12:41:14 +02:00
Franck Jullien
74dc444b02
bios: add auto completion for commands
2020-05-01 12:12:35 +02:00
Franck Jullien
fc2b8226c5
bios: switch command handler to a modular format
...
Command are now described with a structure. A pointer to this
structure is placed in a dedicated linker section.
2020-05-01 12:12:35 +02:00
Franck Jullien
86cab3d362
bios: move helper functions to their own file
2020-05-01 12:12:35 +02:00
Franck Jullien
bc5a1986e2
bios: add terminal history
...
Terminal history and characters parsing is done in readline.c.
Passing TERM_NO_HIST disable terminal history.
Passing TERM_MINI use a simple terminal implementation in order to save
more space.
2020-05-01 12:12:07 +02:00
Franck Jullien
e764eabda1
builder: add a parameter to pass options to BIOS Makefile
2020-05-01 12:10:50 +02:00
Florent Kermarrec
bb70a2325a
cpu/software: move CPU specific software from the BIOS to the CPU directories.
...
This simplifies the integration of the CPUs' software, avoid complex switches in the code,
and is a first step to make CPUs fully pluggable.
The CPU name is no longer present in the crt0 files (for example crt0-vexriscv-ctr.o
becomes crt0-ctr.o) so users building firmwares externally will have to update their
Makefiles to remove the $(CPU) from crt0-$(CPU)-ctr.o.
2020-05-01 11:04:54 +02:00
Florent Kermarrec
0abc7d4f0b
cpu/Minerva: Clone the repository locally for now, we need to create a pythondata repository.
2020-05-01 11:03:07 +02:00
Florent Kermarrec
b82b3b7ecf
integration/soc: rename usb_cdc to usb_acm.
...
As discussed on Discord recently.
2020-04-30 21:45:53 +02:00
Florent Kermarrec
0a1afbf66f
litex/__init__.py: remove retro-compat > 6 months old.
2020-04-30 21:31:58 +02:00
Florent Kermarrec
3531a64173
soc: allow passing custom CPU class to SoC.
...
Useful to experiment with custom CPU wrappers and a first step to make CPUs plugable.
2020-04-29 20:12:23 +02:00
David Shah
64b505156e
Add RDIMM side-B inversion support
...
Signed-off-by: David Shah <dave@ds0.me>
2020-04-29 12:28:53 +01:00
Ilya Epifanov
83f4dcb2c6
Added imac config for CPUs which implements the most basic working riscv32imac feature set, implemented for VexRiscv
2020-04-28 22:27:35 +02:00
Ilya Epifanov
ac1e968351
Can now pass --seed to nextpnr-ecp5 via TrellisToolchain kwargs
2020-04-28 22:25:57 +02:00
Ilya Epifanov
a11f1c39b7
Removed erase flag and made progress output less noisy
2020-04-28 22:22:33 +02:00
bunnie
17b766546b
propose patch to not break litex for python 3.5
2020-04-29 00:34:19 +08:00
Jakub Cebulski
00f973ea35
spi_flash: extend non-bitbanged flash support
...
This commit adds support for memory mapped writes
in the same configuration as memory mapped reads
are currently supported.
It also adds support for accessing registers
and erasing sectors in non-bitbanged single SPI
mode.
2020-04-28 15:02:55 +02:00
Florent Kermarrec
6d0896de1d
cpu/serv: switch to pythondata package instead of local git clone.
2020-04-28 10:34:39 +02:00
enjoy-digital
4d86ab9ded
Merge pull request #399 from mithro/litex-sm2py
...
Converting LiteX to use Python modules.
2020-04-28 08:34:19 +02:00
Florent Kermarrec
5ef869b9eb
soc/cpu: add memory_buses to cpus and use them in add_sdram.
...
This allows the CPU to have direct buses to the memory and replace the Rocket specific code.
2020-04-27 23:53:52 +02:00
Florent Kermarrec
467fee3e23
soc/cpu: rename cpu.buses to cpu.periph_buses.
2020-04-27 23:08:15 +02:00
enjoy-digital
317ea7edd1
Merge branch 'master' into litex-sm2py
2020-04-27 22:24:10 +02:00
shuffle2
f71014b9fb
diamond: fix include paths
...
include paths given via tcl script need semicolon separators and forward slash as directory separator (even on windows)
2020-04-27 11:14:18 -07:00
Florent Kermarrec
4dece4ce24
soc/cpu: simplify integration of CPU without interrupts (and automatically use UART_POLLING mode in this case).
2020-04-27 19:06:16 +02:00
enjoy-digital
c5ef9c7356
Merge pull request #473 from fjullien/memusage
...
bios: print memory usage
2020-04-27 18:24:43 +02:00
Franck Jullien
3892d7a90a
bios: print memory usage
...
Print memory usage during the compilation of bios.elf.
2020-04-27 16:33:34 +02:00
Florent Kermarrec
9460e048ec
tools/litex_sim: use similar analyzer configuration than wiki.
2020-04-27 16:10:41 +02:00
enjoy-digital
443cc72d0a
Merge pull request #476 from enjoy-digital/serv
...
Add SERV support (The SErial RISC-V CPU)
2020-04-27 13:59:28 +02:00
Florent Kermarrec
1d1a4ecd28
software/irq: cleanup and make explicit that irqs are not supported with Microwatt and SERV, fix compilation warning.
2020-04-27 13:47:13 +02:00
Florent Kermarrec
fb9e369a19
serv: connect reset.
2020-04-27 13:26:45 +02:00
Florent Kermarrec
c4c891dec5
build/icestorm: add verilog_read -defer option to yosys script (changes similar the ones applied to trellis).
2020-04-27 13:17:53 +02:00
Greg Davill
642c4b3036
build/trellis: add verilog_read -defer option to yosys script
2020-04-27 20:10:25 +09:30
Florent Kermarrec
71778ad226
serv: update copyrights (Greg Davill found the typos/issues).
2020-04-27 10:27:44 +02:00
Florent Kermarrec
1f9db583fd
serv/cores: fix verilog top level (use serv_rf_top instead of serv_top), working :).
2020-04-26 21:05:47 +02:00
Florent Kermarrec
2efd939d06
serv: fix ibus/dbus byte/word addressing inconsistency, add missing ibus.sel (thanks @GregDavill).
2020-04-26 16:26:57 +02:00
Florent Kermarrec
96e7e6e89a
bios/sdram: reduce number of scan loops during cdly scan to speed it up.
2020-04-25 12:51:33 +02:00
Florent Kermarrec
43e1a5d67d
targets/kcu105: use cmd_latency=1.
2020-04-25 12:12:27 +02:00
Florent Kermarrec
85a059bf77
bios/sdram: add some margin on cdly ideal_delay, do the read_leveling even if write_leveling is not optimal.
...
We need to provide enough information to ease support and understand the issue. The write leveling/read leveling
are doing there best to calibrate the DRAM correctly and memtest gives the final result.
2020-04-25 12:11:10 +02:00
Florent Kermarrec
038e1bc048
targets/kc705: manual DDRPHY_CMD_DELAY no longer needed.
2020-04-25 11:03:04 +02:00
Florent Kermarrec
aaed4b9475
bios/sdram: review/cleanup Command/Clock calibration, set window at the start instead of middle.
...
Working on KC705 that previously required manual adjustment.
2020-04-25 11:00:21 +02:00
enjoy-digital
33c7b2ce6b
Merge pull request #472 from antmicro/jboc/sdram-calibration
...
bios/sdram: add automatic cdly calibration during write leveling
2020-04-25 09:59:08 +02:00
enjoy-digital
4608bd1864
Merge pull request #470 from antmicro/jboc/sdram-eeprom-timings
...
litex_sim: add option to create SDRAM module from SPD data
2020-04-25 08:27:00 +02:00
Jakub Cebulski
a344e20b5e
spi_flash: fix building without bitbang
2020-04-24 17:45:17 +02:00
Jędrzej Boczar
ab92e81e31
bios/sdram: add automatic cdly calibration during write leveling
2020-04-24 14:00:42 +02:00
Florent Kermarrec
22c3923644
initial SERV integration.
2020-04-23 08:18:41 +02:00
Florent Kermarrec
0b3c4b50fa
soc/cores/spi: add optional aligned mode.
...
In aligned mode, MOSI and MISO bits are located on the LSBs and first transmitted MOSI bit is length - 1 bit.
2020-04-22 13:15:51 +02:00
Florent Kermarrec
6bb22dfe6b
cores/spi: simplify.
2020-04-22 12:20:23 +02:00
Florent Kermarrec
fc434af949
build/lattice/common: add specific LatticeiCE40SDROutputImpl/LatticeiCE40SDRTristateImpl (thanks @tnt).
2020-04-22 12:01:23 +02:00
Florent Kermarrec
1457c32052
xilinx/common: use a common SDRTristate implementation for Spartan6, 7-Series and Ultrascale.
2020-04-22 10:42:06 +02:00
Florent Kermarrec
69462e6669
build/xilinx/common: add 7-Series/Ultrascale SDROutput/Input.
2020-04-22 10:33:22 +02:00
Florent Kermarrec
65e6ddc6cd
lattice/common: add LatticeECP5DDRInput.
2020-04-22 10:13:28 +02:00
Florent Kermarrec
2031f28057
lattice/common: cleanup instances, simplify tritates.
2020-04-22 09:07:38 +02:00
Florent Kermarrec
2d25bcb09c
lattice/common: add LatticeiCE40DDRInput, LatticeiCE40SDROutput and LatticeiCE40SDRInput.
2020-04-22 09:07:33 +02:00
Florent Kermarrec
56e1528455
platforms/de0nano: swap serial tx/rx to ease use of cheap FT232 based cables.
2020-04-18 11:38:24 +02:00
Florent Kermarrec
08e4dc02ec
tools/remote/etherbone: update import.
2020-04-17 21:30:33 +02:00
Jędrzej Boczar
b0f8ee9876
litex_sim: add option to create SDRAM module from SPD data
2020-04-17 14:52:53 +02:00
Florent Kermarrec
19f983c420
targets: manual define of the SDRAM PHY no longer needed.
2020-04-16 11:26:59 +02:00
Florent Kermarrec
c0f3710d66
bios/sdram: update/simplify with new exported LiteDRAM parameters.
2020-04-16 10:42:01 +02:00
Florent Kermarrec
3915ed9760
litex_sim: add phytype to PhySettings.
2020-04-16 10:22:43 +02:00
Florent Kermarrec
c0c5ae558a
build/generic_programmer: move requests import to do it only when needed.
2020-04-16 08:44:36 +02:00
Florent Kermarrec
c9ab593989
bios/sdram/ECP5: set ERR_DDRPHY_BITSLIP to 4.
...
Bitslip software control is now used on ECP5 to move dqs_read.
2020-04-15 19:30:28 +02:00
Florent Kermarrec
5e149ceda2
build/generic_programmer: add automatic search/download of flash_proxy in repositories if not available locally.
2020-04-15 08:59:03 +02:00
Mateusz Holenko
77a05b78e8
soc_core: Fix region type generation
...
Include information about being a linker region.
2020-04-14 21:45:32 +02:00
Florent Kermarrec
d44fe18bd9
stream/AsyncFIFO: add default depth (useful when used for CDC).
2020-04-14 17:35:19 +02:00
Florent Kermarrec
ded10c89dc
build/sim/core/Makefile: add -p to mkdir modules.
2020-04-14 12:38:02 +02:00
enjoy-digital
c323e94c83
Merge pull request #464 from mithro/litex-sim-fixes
...
Improve the litex_sim Makefiles
2020-04-14 12:16:21 +02:00
Tim 'mithro' Ansell
97d0c525ee
Remove trailing whitespace.
2020-04-12 10:29:13 -07:00
Florent Kermarrec
4fe31f0760
cores: add External Memory Interface (EMIF) Wishbone bridge.
...
Useful to interface Processors/DSPs with LiteX. EMIF is generally used on Texas Instrument DSPs.
2020-04-12 16:34:33 +02:00
Rangel Ivanov
c57e438df6
boards/targets/ulx3s.py: Update --device option help message
...
Signed-off-by: Rangel Ivanov <rangelivanov88@gmail.com>
2020-04-12 12:01:31 +03:00
Rangel Ivanov
f4b345ecd7
build/lattice/trellis.py: Add 12k device
...
nextpnr adds the --12k option which is the same like
the --25k but with the correct idcode for the 12k devices
Signed-off-by: Rangel Ivanov <rangelivanov88@gmail.com>
2020-04-12 11:46:44 +03:00
Tim 'mithro' Ansell
1f35669508
litex_sim: Find tapcfg from pythondata module.
2020-04-11 18:38:15 -07:00
Tim 'mithro' Ansell
ebcb2a4406
Rename litex-data-XXX-YYY to pythondata-XXX-YYY
2020-04-11 18:37:06 -07:00
Tim 'mithro' Ansell
e618d41ffb
Fixing mor1kx data finding.
2020-04-11 18:37:06 -07:00
Tim 'mithro' Ansell
2e3b7f20c7
Fix typo in error message.
2020-04-11 18:37:06 -07:00
Tim 'mithro' Ansell
83b2581331
Fix the libcompiler_rt path.
2020-04-11 18:37:06 -07:00
Tim 'mithro' Ansell
1c1c5bcbda
Remove submodules.
2020-04-11 18:37:06 -07:00
Tim 'mithro' Ansell
c96d1e6672
Fix import for data.
2020-04-11 18:37:06 -07:00
Tim 'mithro' Ansell
69367f8d4e
Make litex a namespace.
2020-04-11 18:37:06 -07:00
Tim 'mithro' Ansell
d5a21a7522
Converting litex to use Python modules.
2020-04-11 18:37:06 -07:00
Tim 'mithro' Ansell
5a0bb6ee01
litex_sim: Rework Makefiles to put output files in gateware directory.
2020-04-11 18:37:03 -07:00
Tim 'mithro' Ansell
a0658421cc
litex_sim: Better error messages on failure to load module.
2020-04-11 18:35:39 -07:00
Florent Kermarrec
b95e0a19b1
altera/common: add DDROutput, DDRInput, SDROutput, SDRInput.
2020-04-10 15:50:35 +02:00
Florent Kermarrec
40f43efcf6
targets: use DDROutput on sdram_clock and similar configuration for all SDRAM targets.
2020-04-10 14:41:01 +02:00
Florent Kermarrec
292d6b75b6
build/xilinx/common: add Spartan6 specialized DDRInput, SDROutput, SDRInput and SDRTristate.
2020-04-10 14:38:22 +02:00
Florent Kermarrec
88dc5158c1
build/io: add SDR Tristate (with infered version) and remove multi-bits support on SDRIO.
2020-04-10 14:37:29 +02:00
Florent Kermarrec
fdadbd868b
build/lattice/common: remove multi-bits support on SDRInput/Output.
2020-04-10 14:36:13 +02:00
Florent Kermarrec
8159b65bee
litex/build/io: also import CRG (since using DifferentialInput).
2020-04-10 10:25:21 +02:00
Florent Kermarrec
79913e8614
litex.build: update from migen.genlib.io litex.build.io.
2020-04-10 09:49:45 +02:00
Florent Kermarrec
8e014f76da
litex/build: move io.py from litex/gen and re-import DifferentialInput/Output, DDRInput/Output contributed to Migen.
...
This will make things easier and more consistent, all special IO primitives are now in LiteX.
2020-04-10 08:47:07 +02:00
Florent Kermarrec
2e270cf28c
platforms/versa_ecp5: remove Lattice Programmer (no longer used since we can now use OpenOCD).
2020-04-09 23:08:59 +02:00
Florent Kermarrec
deebc49ab0
boards/platforms: cosmetic cleanups.
2020-04-09 23:04:29 +02:00
Florent Kermarrec
3c0ba8ae62
boards/plarforms/ulx3s: cleanup, fix user_leds, add spisdcard, add PULLMODE/DRIVE on SDRAM pins.
2020-04-09 18:55:01 +02:00
Florent Kermarrec
6c429c9995
build/lattice: add ECP5 implementation for SDRInput/SDROutput.
2020-04-09 16:24:05 +02:00
Florent Kermarrec
72c8d590fa
litex/gen: add io with SDRInput/SDROutput (if not overrided, register is supposed to be infered).
2020-04-09 16:23:27 +02:00
Florent Kermarrec
8f57321f30
tools/litex_sim: remove LiteSPI support for now since breaking Travis-CI of others sub-projects.
...
LiteSPI is not mature enough to be integrated in LiteX sim directly. (will case trouble is things are refactored).
This could be re-introduced later when more mature. For now simulation with LiteX Sim
could be tested directly in LiteSPI with a custom simulation.
2020-04-09 11:14:19 +02:00
Florent Kermarrec
9afd017a3a
tools/litex_term: increase workaround delay for usb_fifo. (validated on Minispartan6 and MimasA7).
...
Still needs to be fixed properly.
2020-04-09 10:52:15 +02:00
David Sawatzke
d69b4443b3
Add riscv64-none-elf triple
2020-04-09 05:36:10 +02:00
Florent Kermarrec
14bf8b8190
soc/cores/clock: add Max10PLL.
2020-04-08 08:54:12 +02:00
Florent Kermarrec
2470ef5096
soc/cores/clock: add Cyclone10LPPLL.
2020-04-08 08:33:57 +02:00
Florent Kermarrec
f8d6d0fda8
soc/cores/clock/CycloneVPLL: fix typos.
2020-04-08 08:25:46 +02:00
Florent Kermarrec
970c8de4c2
soc/cores/clock: rename Altera to Intel.
2020-04-08 08:16:37 +02:00
Florent Kermarrec
383fcd36d6
soc/cores/clock: add CycloneVPLL.
2020-04-07 17:24:12 +02:00
Florent Kermarrec
ab4906ea3b
targets/de0nano: use CycloneIVPLL, remove 50MHz limitation.
2020-04-07 17:00:45 +02:00
Florent Kermarrec
0f17547c5b
soc/cores/clock: add initial AlteraClocking/CycloneIV support.
2020-04-07 16:59:53 +02:00
Florent Kermarrec
0f352cd648
soc/cores: use reset_less on datapath/configuration CSRStorages.
2020-04-06 13:17:14 +02:00
Florent Kermarrec
a67ab41835
interconnect/csr: add reset_less parameter.
...
In cases CSRStorage can be considered as a datapath/configuration register and does not need to be reseted.
2020-04-06 13:15:08 +02:00
Florent Kermarrec
05b1b7787b
interconnect/csr, wishbone: use reset_less on datapath signals.
2020-04-06 13:11:50 +02:00
Florent Kermarrec
b95965de73
cores/code_8b10b: set reset_less to True on datapath signals.
...
Reset is only required on control signals.
2020-04-06 11:35:18 +02:00
Florent Kermarrec
a35df4f7d1
stream: set reset_less to True on datapath signals.
...
Reset is only required on control signals.
2020-04-06 11:33:49 +02:00
kessam
fb532f5e92
Fix timing constraints
2020-04-05 17:56:29 +02:00
Florent Kermarrec
6043108376
soc/cores/clock/ECP5PLL: add CLKI_DIV support.
2020-04-03 11:14:57 +02:00
enjoy-digital
27f00851d0
Merge pull request #447 from antmicro/spi-xip
...
Add initial support for the new LiteSPI core
2020-04-01 16:51:29 +02:00
Piotr Binkowski
81be74a7b1
targets: netv2: add LiteSPI
2020-04-01 16:20:36 +02:00
Piotr Binkowski
946cb16429
platform: netv2: update SPI flash pinout
2020-04-01 16:20:36 +02:00
Piotr Binkowski
31fceb0a10
litex_sim: add LiteSPI
2020-04-01 16:20:36 +02:00
Florent Kermarrec
91981b960c
soc/cores/uart: use reset_less on accumulator, reg, bitcount to reduce.
...
This reduces logic a bit. It does not make large difference on usual design with
only 1 UART, but is interesting on designs with hundreds of UARTs used to "document"
FPGA boards :) (similar to https://github.com/enjoy-digital/camlink_4k/blob/master/ios_stream.py )
2020-03-31 16:54:38 +02:00
Florent Kermarrec
87160059d3
soc/cores/spi_flash: add ECP5SPIFlash (non-memory-mapped).
2020-03-31 16:17:12 +02:00
enjoy-digital
e3445f6cd9
Merge pull request #444 from ilya-epifanov/openocd-jtag-programmer
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Added openocd jtagspi programmer, to be used with ECP5-EVN board
2020-03-28 12:58:08 +01:00
Ilya Epifanov
351551a041
Added openocd jtagspi programmer, to be used with ECP5-EVN board
2020-03-28 11:20:30 +01:00
Gabriel Somlo
8473ed567a
software/bios: add spisdcardboot() to boot_sequence()
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-27 15:24:09 -04:00
Gabriel Somlo
e9054ef65a
software/libbase/spisdcard: add delay to goidle loop
...
In `spi_sdcard_goidle()`, insert a `busy_wait()` into the CMD55+ACMD41
loop to avoid exhausting the retry counter before the card has a chance
to be ready (required on the trellisboard, also tested OK on nexys4ddr).
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-27 15:24:09 -04:00
Gabriel Somlo
c6b6dee2e7
software/bios: factor out busy_wait() function
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-27 15:24:09 -04:00
Gabriel Somlo
540218b2d8
software/libbase/spisdcard: fix width of address parameter
...
Host address parameter types should match CPU word width, so
use `unsigned long` to be correct on both 32 and 64 bit CPUs.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-27 15:24:09 -04:00
Florent Kermarrec
2e48ab568b
soc/cores/spi: make dynamic clk divider optional (can be enabled with add_clk_divider method) and only use it in add_spi_sdcard.
2020-03-27 18:44:48 +01:00
Florent Kermarrec
4abb3715d9
targets/add_constant: avoid specifying value when value is None (=default).
2020-03-26 09:45:19 +01:00
Florent Kermarrec
73b4347587
software/libbase/spisdcard: add USE_SPISDCARD_RECLOCKING define to easily disable reclocking.
2020-03-26 07:46:32 +01:00
Florent Kermarrec
b509df8bb6
integration/soc/add_uart: add USB CDC support (with ValentyUSB core).
2020-03-25 19:07:06 +01:00
Florent Kermarrec
76872a7afb
tools/litex_sim: simplify using uart_name=sim.
2020-03-25 19:06:37 +01:00
Florent Kermarrec
09a3ce0ee5
integration/soc/add_uart: add Model/Sim.
2020-03-25 18:56:58 +01:00
Florent Kermarrec
3f43c6a223
integration/soc/add_uart: cleanup.
2020-03-25 18:54:29 +01:00
Florent Kermarrec
5bcf730c77
build/tools: add replace_in_file function.
2020-03-25 16:36:53 +01:00
Florent Kermarrec
ffe83ef0f3
tools/litex_term: use 64 bytes as default payload_lengh (work for all confniguration) and add small delay between frames for FT245 FIFO.
...
The delay still need to be investigated.
2020-03-25 09:31:51 +01:00
Florent Kermarrec
8f2e36927d
bios/boot: update comments.
2020-03-25 09:21:28 +01:00
enjoy-digital
1746b57a1b
Merge pull request #437 from feliks-montez/bugfix/fix-serialboot-frames
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flush rx buffer when bad crc and fix frame payload length
2020-03-25 09:18:31 +01:00
Florent Kermarrec
8d999081e3
boards/targets: update SDRAM to use new GENSDRPHY and new ECP5PLL phase support.
2020-03-24 20:04:18 +01:00
Florent Kermarrec
3eb08c7dd8
boards/platforms: remove versa_ecp3 (ECP3 no longer supported).
2020-03-24 20:02:57 +01:00
Florent Kermarrec
eb64169521
build/lattice/diamond: remove ECP3 support. (ECP3 is not used and no longer interesting now that ECP5 has an open-source toolchain).
2020-03-24 19:36:57 +01:00
Florent Kermarrec
bba5f1828b
cores/clock/ECP5PLL: add phase support.
2020-03-24 19:09:05 +01:00
Florent Kermarrec
0123ccc893
build/lattice/common: change LatticeECPXDDROutputImpl from ECP3 to ECP5.
2020-03-24 19:08:38 +01:00
bunnie
5a402264d0
Fix off-by-one error on almost full condition for prefetch
...
This causes a DRC error on the Xilinx tools when the prefetch
lines setting is 1. Don't know why this wasn't caught earlier,
but it just popped up in CI.
2020-03-24 08:04:35 +01:00
Feliks
ebdc38fc91
flush rx buffer when bad crc and fix frame payload length
2020-03-23 23:04:36 -04:00
Florent Kermarrec
d62ef38c4b
soc/doc/csr: allow CSRField.reset to be a Migen Constant.
2020-03-23 18:47:41 +01:00
Florent Kermarrec
4adac90d88
cpu/vexriscv/mem_map_linux: move main_ram to allow up to 1GB.
2020-03-23 15:35:33 +01:00
Florent Kermarrec
63ab2ba40c
software/bios/boot/linux: move emulator.bin to main_ram and allow defining custom ram offsets.
2020-03-23 15:06:32 +01:00
Florent Kermarrec
d998475498
targets: remove Etherbone imports.
2020-03-21 21:39:34 +01:00
Florent Kermarrec
3b04efbcae
targets: switch to add_etherbone method.
2020-03-21 19:55:00 +01:00
Florent Kermarrec
5ad7a3b7df
integration/soc: add add_etherbone method.
2020-03-21 19:54:36 +01:00
Florent Kermarrec
d6b0819e4c
integration/soc/add_ethernet: add name parameter (defaults to ethmac).
2020-03-21 19:36:31 +01:00
Florent Kermarrec
930679efd7
targets: always use sys_clk_freq on SDRAM modules.
2020-03-21 19:36:06 +01:00
Florent Kermarrec
ae6ef923af
targets: fix typos in previous changes.
2020-03-21 18:26:58 +01:00
enjoy-digital
c547b2cc29
Merge pull request #436 from rob-ng15/master
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Reclock spi sdcard access after initialisation
2020-03-21 09:26:25 +01:00
enjoy-digital
011773af8d
Merge pull request #435 from enjoy-digital/spi_master_clk_divider
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soc/core/spi: add Clk Divider CSR (defaults to sys_clk_freq/spi_clk_f…
2020-03-21 09:25:37 +01:00
rob-ng15
2bf31a31da
Reclock spi sdcard access after initialisation
...
Depends upon https://github.com/enjoy-digital/litex/pull/435
After initialising the card, reclock the card, aiming for ~16MHz (divider is rounded up, as slower speed is safer), but a maximum of half of the processor speed.
Tested with the card being clocked to 12.5MHz on de10nano
2020-03-21 07:37:21 +00:00
Florent Kermarrec
f03d862c06
targets: switch to add_ethernet method instead of EthernetSoC.
2020-03-20 23:46:15 +01:00
Florent Kermarrec
4e9a8ffe9c
targets: switch to SoCCore/add_sdram instead of SoCSDRAM.
2020-03-20 22:02:36 +01:00
Florent Kermarrec
61c9e54a90
soc/core/spi: add Clk Divider CSR (defaults to sys_clk_freq/spi_clk_freq).
2020-03-20 19:49:42 +01:00
Florent Kermarrec
dd7718b4fe
targets/arty: use new ISERDESE2 MEMORY mode.
2020-03-20 18:58:31 +01:00
Florent Kermarrec
fca52d110d
Merge branch 'master' of http://github.com/enjoy-digital/litex
2020-03-20 18:54:51 +01:00
rob-ng15
f3c233776e
Use <stdint.h> to provide structure sizes
2020-03-20 11:35:05 +00:00
rob-ng15
c2ebbcbf6c
Use <stdint.h> for structure sizes
2020-03-20 11:34:24 +00:00
Florent Kermarrec
ccf7363932
integration/soc: add add_spi_flash method to add SPI Flash support to the SoC.
2020-03-20 10:24:31 +01:00
Florent Kermarrec
ec3e068669
targets/nexys4ddr: use LiteXSoC's add_spi_sdcard method.
2020-03-20 09:58:09 +01:00
Florent Kermarrec
d276036f24
integration/soc: add add_spi_sdcard method to add SPI mode SDCard support to the SoC.
2020-03-20 09:57:37 +01:00
enjoy-digital
6044570928
Merge pull request #433 from gsomlo/gls-rocket-spisdcard
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Support SPI-mode SDCard booting on Litex+Rocket (64bit) configuration
2020-03-20 09:41:56 +01:00
Gabriel Somlo
b960d7c574
targets/nexys4ddr: add '--with-spi-sdcard' build option
2020-03-19 21:51:44 -04:00
Gabriel Somlo
7a7b8905b7
platforms/nexys4ddr: add spisdcard pins.
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Synchronize with litex-boards commit #57bcadb.
2020-03-19 21:51:44 -04:00
Gabriel Somlo
af4de03fad
targets/nexys4ddr: make sdcard reset conditional
2020-03-19 21:51:44 -04:00
Gabriel Somlo
a33916bc6b
software/libbase/spisdcard: fix 4-byte FAT fields on 64-bit CPUs
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On 64-bit architectures (e.g., Rocket), 'unsigned long' means
eight (not four) bytes. Use 'unsigned int' wherever a FAT data
structure requires a four-byte field!
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-19 21:51:44 -04:00
Piotr Esden-Tempski
279886721b
Don't let python convert lane number to float.
...
While at it also:
* Don't multilane for reg >= 8 bit width.
* Only check if we should switch to multilane after finding min field width.
2020-03-19 18:12:41 -07:00
Gabriel Somlo
1f90abea8e
bios: make SPI SDCard boot configs other than linux-on-litex-vexriscv
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When NOT on linux-on-litex-vexriscv, we load 'boot.bin' to MAIN_RAM_BASE,
and jump to it.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-19 19:37:47 -04:00
Gabriel Somlo
c2938dc973
bios/boot.c: cosmetic: re-indent spisdcardboot() for consistency
2020-03-19 19:37:47 -04:00
enjoy-digital
dd07a0ad2f
Merge pull request #431 from antmicro/hybrid-mac
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litex_sim: add support for hybrid mac
2020-03-19 22:10:33 +01:00
Florent Kermarrec
37f25ed37a
software/libbase/bios: rename spi.c/h to spisdcard.h, also rename functions.
2020-03-19 11:02:15 +01:00
Florent Kermarrec
939256340f
software/bios/main: revert USDDRPHY_DEBUG (merge issue with SPI SD CARD PR).
2020-03-19 10:47:28 +01:00
enjoy-digital
8fe9e72f7b
Merge pull request #429 from rob-ng15/master
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SPI hardware bitbanging from SD CARD
2020-03-19 10:41:09 +01:00
Piotr Binkowski
96a265a408
litex_sim: add support for hybrid mac
2020-03-19 10:04:08 +01:00
Gabriel Somlo
b2103f4ad8
bios/sdcard: provide sdclk_set_clk() stub for clocker-less targets
...
Targets which lack an adjustable clocker will not expose the required
registers. Provide a stub sdclk_set_clk() routine for those situations.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-18 15:11:23 -04:00
Florent Kermarrec
e865162904
platforms/kcu105: fix pcie tx0 p/n swap.
2020-03-18 19:05:54 +01:00
rob-ng15
27720409ce
SPI hardware bitbanging from SD CARD
2020-03-17 09:51:11 +00:00
rob-ng15
d45dda731a
SPI hardware bitbanging from SD CARD
2020-03-17 09:50:45 +00:00
rob-ng15
50b6db6a6b
SPI hardware bitbanging from SD CARD
2020-03-17 09:50:16 +00:00
Florent Kermarrec
2c4b89639f
soc/cores/clock: make sure specific clkoutn_divide_range is only used as a fallback solution.
2020-03-16 11:44:39 +01:00
Piotr Esden-Tempski
57576fa8fc
Add bit more logic to decide when to switch to multilane CSR documentation.
...
Now we only generate multilane bitfield documentation when the CSR has
fields, and the smallest field is less than 8bit long. As this is when
we start running into space problems with the field names.
2020-03-13 14:48:56 -07:00
Piotr Esden-Tempski
dda7a8c5f3
Split CSR documentation diagrams with more than 8 bits into multiple lanes.
...
In cases when each CSR bit has a name and we use CSR with more than 8
bits, the register diagram quickly becomes crowded and hard to read.
With this patch we split the register into multiple lanes of 8 bits
each.
2020-03-13 14:48:23 -07:00
Florent Kermarrec
aec1bfbeb4
cores/clock: simplify Fractional Divide support on S7MMCM.
...
Specific clkoutn_divide_range can now be provided by specialized XilinxClocking classes.
When provided, the specific range will be used. Floats are also now supported in the
range definition/iteration.
2020-03-13 15:56:39 +01:00
enjoy-digital
f34593a17d
Merge pull request #421 from betrusted-io/clk0_fractional
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add fractional division options to clk0 config on PLL
2020-03-13 14:15:24 +01:00
Florent Kermarrec
eb9f54b2bc
test: add initial (minimal) test for clock abstraction modules.
...
Also fix divclk_divide_range on S6DCM.
2020-03-13 12:38:23 +01:00
Florent Kermarrec
c304c4db27
targets/icebreaker: add description of the board, link to crowdsupply campagin and to the more complete example.
2020-03-13 09:37:42 +01:00
Piotr Esden-Tempski
d063acb767
Updating the vendored wavedrom js files.
2020-03-12 22:35:04 -07:00
Florent Kermarrec
a27385a79c
soc/intergration: rename mr_memory_x parameter to memory_x.
2020-03-12 12:20:48 +01:00
Piotr Esden-Tempski
4d02263223
Add --mr-memory-x parameter to generate memory regions memory.x file.
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This file is used by rust embedded target pacs.
2020-03-11 18:12:18 -07:00
Florent Kermarrec
e9f0ff68ce
Merge branch 'master' of http://github.com/enjoy-digital/litex
2020-03-11 12:57:29 +01:00
Florent Kermarrec
979f98ea31
software: revert LTO changes (Disable it).
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It seems LTO is not yet fully working with all configurations, so it's better
reverting the changes for now.
- cause issues with LM32 available compilers.
- seems to cause issues with min/lite variant of VexRiscv.
- seems to cause issues with some litex-buildenv configurations. (see https://github.com/enjoy-digital/litex/issues/417 ).
2020-03-11 12:57:00 +01:00
Sean Cross
01b6969375
Merge pull request #422 from xobs/core-doc-fixes
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Core doc fixes
2020-03-11 19:38:42 +08:00
enjoy-digital
4ccf62afc1
Merge pull request #423 from gsomlo/gls-ethmac-fixes
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integration/soc: add_ethernet: honor self.map["ethmac"], if present
2020-03-11 12:33:50 +01:00
Florent Kermarrec
bb8905fa5d
cores/gpio: add CSR descriptions.
2020-03-11 12:06:15 +01:00
Florent Kermarrec
4dabc5a625
cores/icap: add CSR descriptions.
2020-03-11 11:04:42 +01:00
Florent Kermarrec
77132a48b0
cores/spi: add CSR descriptions.
2020-03-11 10:58:32 +01:00
Florent Kermarrec
6d861c6e57
cores/pwm: add CSR descriptions.
2020-03-11 10:38:28 +01:00
Florent Kermarrec
cbc1f5949d
cores/xadc: add CSR descriptions.
2020-03-11 10:05:14 +01:00
Gabriel Somlo
a904034811
integration/soc: add_ethernet: honor self.map["ethmac"], if present
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Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-10 19:49:34 -04:00
Florent Kermarrec
846a2720b7
targets/kcu105: move cd_pll4x.
2020-03-10 17:02:28 +01:00
Florent Kermarrec
c97fabb285
targets/kcu105: simplify CRG using USIDELAYCTRL.
2020-03-10 16:48:07 +01:00
Florent Kermarrec
3c0b97eec8
cores/clock/USIDELAYCTRL: use separate reset/ready counters and set cd_sys.rst internally.
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This is the behaviour that was duplicated in each target. Integrating it here
will allow simplifying the targets.
2020-03-10 16:46:54 +01:00
Sean Cross
a2f61b4e80
soc/cores/spi_opi: documentation fixes
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The ModuleDoc-generated documentation for the spi_opi module produced
slightly invalid output due to ambiguities in how rst assigns headers.
As a result, sections from the spi_opi document would appear as full
sections.
This cleans up these errors so that it parses properly under sphinx.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-03-10 20:40:04 +08:00
Sean Cross
d2f6139dc7
soc/cores/i2s: fix rst parsing errors
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The ModuleDoc-generated documentation for the i2s module produced
slightly invalid output due to ambiguities in how rst assigns headers.
As a result, sections from the i2s document would appear as full
sections.
This cleans up these errors so that it parses properly under sphinx.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-03-10 20:37:55 +08:00
Florent Kermarrec
bcbf558b6b
bios: add more Ultrascale SDRAM debug with sdram_cdly command to set clk/cmd delay.
2020-03-10 13:08:49 +01:00
bunnie
5b92bf2d57
add fractional division options to clk0 config on PLL
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S7 MMCMs allow fractional divider on clock 0. Add a fallback
to try fractional values on clock 0 if a solution can't be found.
This is necessary for e.g. generating both a 100MHz and 48MHz
clock from a 12MHz source with margin=0
2020-03-10 18:48:30 +08:00
enjoy-digital
c4ce6da6c8
Merge pull request #419 from gsomlo/gls-ultra-sdram-fixup
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software/bios: fixup for Ultrascale SDRAM debug
2020-03-10 11:43:23 +01:00
Florent Kermarrec
b509068790
cores/clock: add logging to visualize clkin/clkouts and computed config.
2020-03-10 11:13:16 +01:00
Florent Kermarrec
04b8a91255
integration/soc: add FPGA device and System clock to logs.
2020-03-10 11:10:23 +01:00
Florent Kermarrec
02cba41d64
targets/icebreaker: create CRG after SoC.
2020-03-10 11:09:56 +01:00
Gabriel Somlo
4d15e1f7f8
software/bios: fixup for Ultrascale SDRAM debug
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Keep CSR accesses independent of csr_data_width and csr_alignment.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-09 15:32:08 -04:00
Florent Kermarrec
ba2f31d43d
integration/soc: set use_rom when cpu_reset_address is defined in a rom region.
2020-03-09 19:36:47 +01:00
Florent Kermarrec
8808c884c5
boards/platforms/icebreaker: cleanup a bit.
2020-03-09 19:16:02 +01:00
Florent Kermarrec
4656b1b2ad
software/common: fix LTO checks.
2020-03-09 19:08:27 +01:00
Florent Kermarrec
2a91deadcb
soc/cores/clock/iCE40PLL: add SB_PLL40_PAD support.
2020-03-09 19:03:05 +01:00
Florent Kermarrec
38d7f8a6e6
build/lattice/icestorm: add timingstrict parameter and default to False. (similar behavior than others backends)
2020-03-09 19:02:23 +01:00
Florent Kermarrec
1e9aa64387
targets/icebreaker: simplify, use standard VexRiscv, add iCE40PLL and run BIOS from SPI Flash.
2020-03-09 19:01:16 +01:00
Florent Kermarrec
197bdcb026
lattice/icestorm: enable DSP inference with Yosys and avoid setting SPI Flash in deep sleep mode after configuration which prevent running ROM CPU code from SPI Flash.
2020-03-09 16:51:18 +01:00
Florent Kermarrec
37869e38b8
boards: add initial icebreaker platform/target from litex-boards.
2020-03-09 11:56:55 +01:00
Florent Kermarrec
72af1b39eb
software/bios: add Ultrascale SDRAM debug functions.
2020-03-09 10:55:31 +01:00
Florent Kermarrec
6480d1803e
boards/platforms/kcu105: avoid unnecessary {{}} on INTERNAL_VREF.
2020-03-09 09:37:31 +01:00
Florent Kermarrec
b02c23391a
integration/soc/SoCRegion: add size_pow2 and use this internally for checks since decoder is using rounded size to next power or 2.
2020-03-08 19:17:31 +01:00
Florent Kermarrec
e801dc0261
soc: allow creating SoC without BIOS.
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By default the behaviour is unchanged and the SoC will provide a ROM:
./arty.py
Bus Regions: (4)
rom : Origin: 0x00000000, Size: 0x00008000, Mode: R, Cached: True Linker: False
sram : Origin: 0x01000000, Size: 0x00001000, Mode: RW, Cached: True Linker: False
main_ram : Origin: 0x40000000, Size: 0x10000000, Mode: RW, Cached: True Linker: False
csr : Origin: 0x82000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False
The integrated rom can be disabled with:
./arty.py --integrated-rom-size=0
but the SoC builder will check for a user provided rom, and if not provided will complains:
ERROR:SoC:CPU needs rom Region to be defined as Bus or Linker Region.
When a rom is provided, the CPU will use the rom base address as cpu_reset_address.
If the user just wants the CPU to start at a specified address without providing a rom,
the cpu_reset_address parameter can be used:
./arty.py --integrated-rom-size=0 --cpu-reset-address=0x01000000
If the provided reset address is not located in any defined Region, an error will
be produced:
ERROR:SoC:CPU needs reset address 0x00000000 to be in a defined Region.
When no rom is provided, the builder will not build the BIOS.
2020-03-06 20:05:27 +01:00
Florent Kermarrec
ecca3d801d
integration/builder: rename software methods to _prepare_rom_software/_generate_rom_software/_initialize_rom_software.
2020-03-06 14:53:59 +01:00
Florent Kermarrec
69ffafd81d
integration/builder: generate csr maps before compiling software.
2020-03-06 14:20:32 +01:00
Florent Kermarrec
e2dab06386
Add SVD export capability to Builder (csr_svd parameter) and targets (--csr-svd argument) and fix svd regression.
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This allows generating SVD export files during the build as we are already doing for .csv or .json.
Use with Builder:
builder = Builder(soc, csr_svd="csr.svd")
Use with target:
./arty.py --csr-svd=csr.svd
2020-03-06 14:12:58 +01:00
Florent Kermarrec
e124aed9a2
software/common.mak: fix LTO refactoring issue.
2020-03-05 23:42:36 +01:00
Karol Gugala
da580e31fd
Fix copyrights
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Signed-off-by: Karol Gugala <kgugala@antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
2020-03-05 17:44:10 +01:00
Gabriel Somlo
020bef4197
targets/nexys4ddr: fix sdcard clocker initialization
2020-03-05 09:02:29 -05:00
enjoy-digital
9249fc90cf
Merge pull request #410 from antmicro/netv2-edid
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platform/netv2: add proper I2C pins for HDMI IN0
2020-03-05 11:43:02 +01:00
Piotr Binkowski
72f63243cd
platform/netv2: add proper I2C pins for HDMI IN0
2020-03-05 11:27:47 +01:00
Florent Kermarrec
ad11ff39ad
targets/ecp5: make sure all BaseSoC/EthernetSoc default to trellis.
2020-03-05 11:19:29 +01:00
