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595 commits

Author SHA1 Message Date
Dolu1990
281d61bbe1 regression fix hex << dec #46 2018-12-09 16:37:16 +01:00
Dolu1990
1fbb81a4d9 regression fix delete [] #46 2018-12-09 15:40:02 +01:00
Dolu1990
f121ce1ed5 add sanity asserts in regression #46 2018-12-08 14:10:18 +01:00
Dolu1990
9330945623 fix regression makefile 2018-12-07 23:50:13 +01:00
Dolu1990
52419fd7ad Regression remove dplus stuff #46 2018-12-07 23:47:49 +01:00
Dolu1990
68fdbe60cc verilator regression fix missing fclose #46 2018-12-07 23:43:19 +01:00
Dolu1990
eca54585b0 Fix hardware breakpoint 2018-12-04 16:57:24 +01:00
Dolu1990
ac1ed40b80 Move things into SpinalHDL lib 2018-12-01 18:25:18 +01:00
Dolu1990
3d71045159 DebugPlugin doesn't require memory/writeback stage anymore 2018-12-01 18:24:33 +01:00
Dolu1990
58d7a4784d move HexTools into SpinalHDL lib 2018-11-30 17:39:33 +01:00
Dolu1990
b1b7da4f10 Rename SimpleBus into PipelinedMemoryBus 
Move PipelinedMemoryBus into SpinalHDL lib
 2018-11-30 17:37:17 +01:00
Dolu1990
2f6a2dfccc Add configs setup in SimpleBusInterconnect 2018-11-29 16:14:45 +01:00
Dolu1990
7075e08d9f Hazarplugin tell to branch plugin if the RS are hazardous in the execute stage 2018-11-24 13:38:54 +01:00
Dolu1990
c2b9544794 Allow iBusCached plugin to be used when no memory stage is present 2018-11-24 13:37:53 +01:00
Dolu1990
0086de9e36 Fix CsrPlugin catch illegalAccess 
Add dhrystone optimized divider
cleaning
 2018-11-20 19:39:17 +01:00
Dolu1990
75d4d049d7 Add shadow regfile 
various cleaning
 2018-11-16 17:06:11 +01:00
Dolu1990
cc48fc7403 add fenceiGenAsANop 2018-11-13 15:17:35 +01:00
Dolu1990
0d92a5e5cd Add many little options to reduce area 2018-11-12 14:14:34 +01:00
Dolu1990
fb9ea11a5e Allow VexRiscv to suppress the memory and the writeback stage, allowing to go downto a 2 stage CPU (FETCH_DECODE, EXECUTE) 2018-11-09 05:41:43 +01:00
Dolu1990
b12e15b112 branch/csr/muldiv minor improvments 2018-11-07 19:27:49 +01:00
Dolu1990
b7f3ee5e06 Fix CsrPlugin pipelined option 2018-11-05 16:22:41 +01:00
Dolu1990
662d76e3aa csrPlugin : avoid using ALU to get SRC1 (which was useless) 2018-11-03 11:29:30 +01:00
Dolu1990
978232fd63 Optimise div iterative plugin done signal 2018-11-03 11:12:37 +01:00
Dolu1990
c8ac214097 Optimize CSR 2018-10-28 02:18:27 +02:00
Dolu1990
51de2b5820 SimpleBusInterconnect now adapte address width 2018-10-28 02:18:08 +02:00
Dolu1990
00bf84b7f8 Add SimpleBusInterconnect 2018-10-25 23:47:05 +02:00
Dolu1990
4ed4af6a3e SrcPlugin add decodeAddSub option 2018-10-24 01:28:37 +02:00
Dolu1990
372063582c Improve CsrPlugin CombinatorialPaths 2018-10-23 19:07:08 +02:00
Dolu1990
7096c63d50 Add more SimpleBus utilies 2018-10-23 17:46:31 +02:00
Dolu1990
7c0f2dc713 Add SimpleBus object 2018-10-20 12:39:30 +02:00
Morard Dany
85e696b286 CsrPlugin : Add mtvecModeGen 2018-10-16 14:53:41 +02:00
Dolu1990
905abd5aaa Add wfiGenAsWait and wfiGenAsNop 
CsrPlugin cleaning
Much cleaning in general
Zephyr is running
 2018-10-16 13:07:30 +02:00
Dolu1990
f903df4b66 sync 2018-10-12 17:13:54 +02:00
Dolu1990
2b29690010 Clean branch plugin lsb bit calculation 
BranchPlugin doesn't try anymore to catch exception when RVC is on
 2018-10-12 12:24:52 +02:00
Dolu1990
eea92154ae fetcher force PC LSB to be zero 2018-10-12 12:02:52 +02:00
Dolu1990
0b8f6f6ed4 Fix broken C.LWSP reference_output 2018-10-12 12:02:02 +02:00
Dolu1990
594f7a8bf2 Seem to pass all risc-v compliance tests, excepted the C.LWSP which is a broken test 2018-10-11 22:19:17 +02:00
Dolu1990
8c25e73b9d Fix DIV negative values divided by zero 2018-10-11 22:18:21 +02:00
Dolu1990
c26b7e15cf BranchPlugin exceptions are now risc-v compliance alligned 2018-10-11 17:56:49 +02:00
Dolu1990
8b1a4a2717 Add RISCV compliance regression test, need to fix I-MISALIGN_JMP-01 mtval 2018-10-11 00:25:39 +02:00
Dolu1990
40d85b8c70 Add fenceiGenAsAJump into BranchPlugin 2018-10-10 21:13:21 +02:00
Dolu1990
68f1ff3222 Add CsrPlugin ebreak support 2018-10-10 19:23:04 +02:00
Dolu1990
0662cc2797 Add GenMicro experiment to reduce ice40 area usage. 
IBusSimplePlugin now require cmdFork parameters to be set (no default)
 2018-10-03 22:08:57 +02:00
Dolu1990
48bff80653 rework fetchPc to optionaly share the pcReg with the stage(1) 
IBusSimplePlugin now implement cmdForkPersistence option
 2018-10-03 16:24:10 +02:00
Dolu1990
c61f17aea3 Fetcher/IBusSimplePlugin wip 2018-10-03 01:02:22 +02:00
Dolu1990
0ada869b2d regression golden ref regfile is now sync with trl boot's random values 
wip
 2018-10-01 16:14:21 +02:00
Dolu1990
65a8d84d30 Introduce HAS_SIDE_EFFECT Stageable to solve sensitive instruction squeduling 
(uncached DBus TODO)
 2018-10-01 12:13:05 +02:00
Dolu1990
7770eefa3b wip 2018-09-30 12:57:08 +02:00
Dolu1990
39c6bc11d6 Pass basic regression again 2018-09-29 19:04:20 +02:00
Dolu1990
5ad7c39f47 wip 2018-09-29 12:04:58 +02:00
Dolu1990
37a1970ad6 wip 2018-09-28 16:02:33 +02:00
Dolu1990
9a3510f63d Map all supervisor registers 2018-09-27 19:03:57 +02:00
Dolu1990
acd1ca422a wip 2018-09-27 18:24:40 +02:00
Dolu1990
6dde73f97c Murax demo with XIP is now fully defined in SpinalHDL 2018-09-27 00:55:30 +02:00
Dolu1990
aff436ddcf Sync with SpinalHDL head 
Add mmu test into the dhrystone regression command
 2018-09-24 18:31:33 +02:00
Dolu1990
1e3b75ef1d xip typo 2018-09-23 22:06:21 +02:00
Dolu1990
86efb75f6a rework fetcher 2018-09-23 22:05:53 +02:00
Dolu1990
56fd73fbbc Add missing bin files 2018-09-23 19:26:11 +02:00
Dolu1990
bdc3246f5a Fix xip gitignore 2018-09-23 19:23:43 +02:00
Dolu1990
5024cc5616 Hardware breakpoint feature added 
Murax XIP debugging passed tests
 2018-09-20 13:11:20 +02:00
Dolu1990
ff1d1072a7 XIP is physicaly working on murax 2018-09-19 00:09:14 +02:00
Dolu1990
b51ac03a5e murax xip flash integration wip 2018-09-18 16:53:26 +02:00
Dolu1990
3e17461cc7 Add optional XIP to Murax 2018-09-16 11:00:56 +02:00
Dolu1990
d7cba38ec2 move to SpinalHDL 1.1.7, add more default value for plugins parameters 2018-09-11 16:08:28 +02:00
Dolu1990
791608f655 Move swing stuff into main test package 2018-08-29 14:55:25 +02:00
Dolu1990
0255f51cc5 Add unpipelined Wishbone support for uncached version 2018-08-24 16:41:34 +02:00
Dolu1990
7ed6835e97 Add C++ VexRiscv model to cross check the hardware simulation 2018-08-22 02:08:55 +02:00
Dolu1990
38af5dbdd5 riscv emulator WIP (RVC missing) 2018-08-21 01:03:51 +02:00
Dolu1990
dca1e5f438 revert RVC from murax 2018-08-17 23:12:45 +02:00
Dolu1990
8ebb3af4fc Merge remote-tracking branch 'origin/master' into reworkFetcher 
Conflicts:
	README.md
	src/main/scala/vexriscv/TestsWorkspace.scala
	src/test/scala/vexriscv/Play.scala
 2018-08-17 20:56:51 +02:00
Dolu1990
9c7e089329 Fix ExternalInterruptArrayPlugin CSR ids 2018-08-17 20:38:33 +02:00
Dolu1990
1d3ac7830b restore tests without CSR catch all 2018-08-17 19:33:41 +02:00
Dolu1990
330ee14a23 final fetchRework commit ? 2018-08-17 19:13:23 +02:00
Dolu1990
91773ec7d5 Sync, Seem to pass all except dynamic_o0 which is probably a freertos test setup issue 2018-08-14 11:51:53 +02:00
Tom Verbeure
ae85698a2b MulSimple 2018-08-09 22:15:26 -07:00
Dolu1990
32fe1dcbd4 Add google cloud VM regressions scripts 2018-07-07 21:47:09 +02:00
Dolu1990
3ea4f28354 wip 2018-07-07 11:39:42 +02:00
Dolu1990
9c1a8ea219 Fix EPC 
Fix Freertos binaries
wip
 2018-07-03 23:17:32 +02:00
Dolu1990
ffe5fa23f0 wip 2018-06-25 09:36:07 +02:00
Dolu1990
d73aa9ce00 rework csr exception/interrupt handeling wip 2018-06-24 00:14:55 +02:00
Dolu1990
dd47db9ad0 wip 2018-06-20 12:35:12 +02:00
Dolu1990
8886f7e6d4 test wip 2018-06-19 16:15:42 +02:00
Dolu1990
1090111a6f TestIndividual is now fully random 2018-06-15 13:00:59 +02:00
Dolu1990
b2cd8c5314 Fix exception pipelining 2018-06-15 13:00:26 +02:00
Dolu1990
83864710a3 Fix IBusCached single cycle interaction with mmu bus 
Add random test configs
 2018-06-09 08:40:19 +02:00
Dolu1990
08a1212fca Add DBus simple/cached regressions 2018-06-07 02:31:18 +02:00
Dolu1990
6bc5431fcd Add iBusCached regressions 2018-06-07 00:57:26 +02:00
Dolu1990
5e7dd02bf7 Fix relaxedPc/DYNAMIC_TARGET interaction 2018-06-06 18:30:30 +02:00
Dolu1990
dc968020c4 Fix relaxedBusCmdValid pendingCmd overflow 2018-06-06 15:20:37 +02:00
Dolu1990
7768f065e4 Add many cpu configs on regressions tests (some config are broken) 2018-06-06 02:23:07 +02:00
Dolu1990
8729530a8d Fix Dynamicfetch/!rvc config 2018-06-05 02:33:18 +02:00
Dolu1990
930563291c Allow RVC/dynamic_target/fetch bus latency > 1 all together 
Fix freeretos rvc regressions
 2018-06-05 02:21:05 +02:00
Dolu1990
702db29edd Fix dynamic prediction RVC allignement 2018-06-04 20:03:08 +02:00
Dolu1990
fc835f370e Fix DynamicPrediction with RVC missprediction between ret instruction and first instruction of the next function 2018-06-04 19:45:15 +02:00
Tom Verbeure
52f1cdbca7 Fix some missing Barriel -> barriel fixes 2018-06-03 21:46:40 -07:00
Dolu1990
9f0387350b Add Freertos RVC binaries regression 2018-06-03 17:10:58 +02:00
Tom Verbeure
e9bbbb3965 BarrielShifter -> BarrelShifter 2018-06-03 07:40:11 +00:00
Dolu1990
7375855e58 DYNAMIC_PREDICTION used with RVC pass tests (1 cycle fetch) 2018-06-03 00:50:18 +02:00
Dolu1990
98b68093f4 dynamic_prediction + RVC => instruction fetch stopped midair 2018-05-28 21:28:39 +02:00
Dolu1990
863ac3f34d dynamic prediction now use history from first aligned word of the instruction instead of the last one. 2018-05-28 11:03:13 +02:00
Dolu1990
8a0c238bf3 dynamic prediction ok with rvc, todo dynamic_target with rvc 2018-05-28 10:59:22 +02:00
Tom Verbeure
0335543309 More Unrolls 2018-05-28 07:20:26 +00:00
Tom Verbeure
1613191779 Unrool -> Unroll 2018-05-28 07:18:13 +00:00
Dolu1990
7493e70265 Merge remote-tracking branch 'origin/master' into reworkFetcher 2018-05-28 09:02:30 +02:00
Dolu1990
5943ee727e Fill travis, DhrystoneBench is now a Unit test 2018-05-28 09:02:01 +02:00
Dolu1990
1752b5f184 Give name to inter stages registers 2018-05-27 23:39:49 +02:00
Dolu1990
5704f22739 wip 2018-05-27 23:33:57 +02:00
Dolu1990
346338f084 Better HexTools 2018-05-26 11:51:42 +02:00
Dolu1990
6142b04603 Move HexTools into Spinal 2018-05-26 11:43:16 +02:00
Dolu1990
c8677cca9b Better HexTools 2018-05-26 11:32:36 +02:00
Dolu1990
b0777bc646 Merge remote-tracking branch 'origin/master' into reworkFetcher 2018-05-24 14:05:35 +02:00
Dolu1990
6004dcc365 Fix typo 2018-05-24 14:04:50 +02:00
Dolu1990
9815763b7f Merge remote-tracking branch 'origin/master' into reworkFetcher 
Conflicts:
	src/main/scala/vexriscv/plugin/PcManagerSimplePlugin.scala
	src/test/cpp/regression/main.cpp
 2018-05-24 14:04:01 +02:00
Dolu1990
c4f33b30e2 Update SynthesisBench murax 2018-05-24 14:03:28 +02:00
Dolu1990
485f35a1b5 IBusCachedPlugin default is two cycle cache with single cycle ram. 2018-05-24 13:46:31 +02:00
Dolu1990
2f8ccc55b6 Fix branch plugin decode prediction exception by using the instruction decoder 2018-05-24 12:52:00 +02:00
Dolu1990
a53f8fdc35 Clean configs 2018-05-23 16:57:32 +02:00
Dolu1990
eb5bc4a791 Fix RVC decompressor (ALU immediats) 2018-05-22 17:23:20 +02:00
Dolu1990
ff760a0bf0 DYNAMIC_TARGET branch prediction back for not compressed ISA (PASS) 2018-05-21 13:45:08 +02:00
Dolu1990
7ffbfab312 Reintroduce MMU feature (pass tests) 2018-05-16 20:32:12 +02:00
Dolu1990
c8cec59f1d Update IBusCachedPlugin parameters 2018-05-16 12:11:53 +02:00
Dolu1990
3b54ecf303 Restore two cycle instruction cache features 2018-05-15 23:03:33 +02:00
Dolu1990
4e7152ae5a IcestormFlow add ultraplus support 2018-05-14 20:18:53 +02:00
Dolu1990
df3d9ccb13 rework IBusSimplePlugin parameters 2018-05-14 10:31:40 +02:00
Dolu1990
c0271d382f More assertion (csrPlugin) 2018-05-14 10:13:44 +02:00
Dolu1990
9caa7163ae IBusSimplePlugin add relaxedBusCmdValid feature 2018-05-14 10:04:19 +02:00
Dolu1990
610bd01f3b remove rspStageGen 2018-05-14 09:21:28 +02:00
Dolu1990
7b37669a0f Add exception catch to iBusSimplePLugin (pass) 2018-05-09 18:43:48 +02:00
Dolu1990
acccbf40e2 RVC debug pass tets 2018-05-09 00:28:14 +02:00
Dolu1990
0056da1342 DebugPlugin work 2018-05-08 02:01:34 +02:00
Dolu1990
e65757e34c wip before moving the fetchHalt 2018-05-06 16:38:00 +02:00
Dolu1990
294293cb70 Reintroduce debug plugin (instruction injector need optimisations) 2018-05-05 23:05:32 +02:00
Dolu1990
a50fbf0d7a Fix IBusCachedPlugin Pass all dhrystone tests 2018-04-30 13:35:17 +02:00
Dolu1990
558af595a1 Add ice40 synthesis results 2018-04-26 13:14:37 +02:00
Dolu1990
bdcf3f6234 Add HexTools and add a Briey main which load the ram 2018-04-26 10:27:39 +02:00
Dolu1990
cfc324aa0f Allow csr mtvec to not have reset values 2018-04-24 23:33:48 +02:00
Dolu1990
a9cbc48eb2 PcManagerPlugin is can now handle an external reset vector signal 2018-04-24 23:11:11 +02:00
Dolu1990
978eb9b6b2 DBusCachedPlugin add CSR info 2018-04-22 11:46:01 +02:00
Dolu1990
74f2a4194a Add ExternalInterruptArrayPlugin 2018-04-20 17:56:21 +02:00
Dolu1990
6598e82920 wishbone => word address, not byte address 2018-04-19 11:22:06 +02:00
Dolu1990
455607b6b4 Fix dBus IO access 2018-04-18 14:11:59 +02:00
Dolu1990
6e59ddcc73 Cached wishbone demo is passing regression tests 2018-04-18 13:51:33 +02:00
Dolu1990
b37fc3fcc8 Add VexRiscv Wishbone demo for sim (generation ok) 2018-04-18 12:54:20 +02:00
Dolu1990
a66efcb35b Add wishbone support for i$ / d$ (not tested) 2018-04-17 23:56:44 +02:00
Dolu1990
4440047fb6 ICache compressed is working 2018-04-16 10:34:18 +02:00
Dolu1990
76352b44fa wip 2018-04-13 12:51:27 +02:00
Dolu1990
19d5d1ecf1 wip 2018-04-09 09:18:08 +02:00
Dolu1990
4dd2997ad5 wip 2018-04-09 09:12:30 +02:00
Dolu1990
e00c0750eb wip 2018-04-03 18:37:05 +02:00
Dolu1990
d9f2e03753 statuc prediction is fully funcitonnal 2018-04-02 17:43:58 +02:00
Dolu1990
76ca852478 Static prediction is fully functionnal 2018-04-02 17:43:06 +02:00
Dolu1990
0919308a8f IBusSimplePlugin add relaxedPcCalculation 2018-03-23 22:49:32 +01:00
Dolu1990
c48c7170e8 Added many pipelining option into IBusSimplePlugin 2018-03-23 19:07:03 +01:00
Dolu1990
351ad10925 RVC Add dhrystone regressions (PASS) 2018-03-21 23:36:57 +01:00
Dolu1990
0c7c2a1fba IBusPlugin add support of bus error when using compressed instruction 2018-03-21 22:34:54 +01:00
Dolu1990
31a464ffdc VexRiscv now pass Riscv-test compressed stuff 2018-03-21 20:50:07 +01:00
Dolu1990
af638e7bde RV32IC is passing some of the compressed Riscv-test tests 2018-03-21 20:30:09 +01:00
Dolu1990
f872d599e2 Add decodePcGen 2018-03-20 18:34:36 +01:00
Dolu1990
1fb138de1f IBusSimplePlugin fully functional Need to restore branch prediction 2018-03-20 00:01:28 +01:00
Dolu1990
ac74fb9ce8 iBusSimplePlugin done, DebugPlugin need minor rework 2018-03-18 13:21:21 +01:00
Dolu1990
64022557bf Add synthesis attribut to the PcManagerSimplePlugin to optimize the pc calculation for vhdl 2018-03-15 18:56:25 +01:00
Dolu1990
63c1b738ff Add synthesis attribut to the PcManagerSimplePlugin to optimize the pc calculation inferation timings 2018-03-14 00:56:23 +01:00
Dolu1990
d9b7426cde undo InOutWrapper from Murax 2018-03-14 00:47:23 +01:00
Dolu1990
91031f8d75 DivPlugin is now based MulDivIterativePlugin (Smaller) 2018-03-10 13:31:35 +01:00
Dolu1990
e437a1d44e Add division support in the MulDivInterativePlugin 2018-03-09 22:41:47 +01:00
Dolu1990
36438bd306 iterative mul improvments 2018-03-09 20:00:50 +01:00
Dolu1990
674ab2c594 experimental iterative mul/div combo 2018-03-09 19:07:26 +01:00
Dolu1990
5228a53293 MuraxSim improve simulation Speed 2018-03-06 12:20:39 +01:00
Dolu1990
9b2cd7b234 MuraxSim add switch 2018-03-06 12:17:15 +01:00
Dolu1990
53970dd284 SpinalHDL 1.1.4 
Now the CsrPlugin is waiting that the memory/writeback stages are empty before reading/writing things
 2018-03-05 14:34:59 +01:00
Dolu1990
ccad64def5 Pipeline CSR isWrite 2018-02-26 10:19:33 +01:00
Dolu1990
2b6185b063 Decoding logic : Add primes duplication removal 2018-02-25 08:57:31 +01:00
Dolu1990
2b6f43cef8 Fix Murax memory mapping range 2018-02-25 08:57:31 +01:00
Dolu1990
5260ad5c35 Decoding lib cleaning 2018-02-25 08:57:31 +01:00
Dolu1990
137b1ee32c Briey testbench, fix io_coreInterrupt to zero to avoid external interrupt set by random boots values 2018-02-22 22:36:13 +01:00
Dolu1990
d957934949 Fix ICache exception priority over miss reload 2018-02-19 22:44:46 +01:00
Dolu1990
d0e963559a Update readme with the new ICache implementation 2018-02-18 23:48:11 +01:00
Dolu1990
93110d3b95 Add jump priority managment in PcPlugins 2018-02-16 14:27:20 +01:00
Dolu1990
506e0e3f60 New faster/smaller/multi way instruction cache design. 
Single or dual stage
 2018-02-16 02:21:08 +01:00
Dolu1990
3853e0313b SynthesisBench cleaning/experiments 2018-02-11 14:53:42 +01:00
Dolu1990
0e6ae682b1 Add architecture section describing plugins in the readme 2018-02-09 00:44:27 +01:00
Dolu1990
57ebfee2e6 Add more axi bridges 2018-02-08 21:39:22 +01:00
Dolu1990
3ee111e100 Update readme (gcc stuff) 2018-02-05 16:34:10 +01:00
Dolu1990
d4b05ea365 Remap Briey/Murax onChipRam to 0x80000000 to avoid having memory at the null pointer location 
Commit missing file
Update dhrystone hex to use GP. 1.44 DMIPS/Mhz
 2018-02-05 16:16:27 +01:00
Dolu1990
4729e46763 Add DummyFencePlugin 2018-02-03 12:28:53 +01:00
Dolu1990
f13dba847c Add custom csr gpio example 2018-02-02 11:14:55 +01:00
Dolu1990
b7d8ed8a81 Add onWrite/onRead/isWriting/isReading on the CsrPlugin 2018-02-01 21:28:28 +01:00
Dolu1990
4ee2482cbf Fix custom_csr regression against random ibus stall 2018-01-31 18:33:21 +01:00
Dolu1990
d2e5755df4 revert removed code by mistake 2018-01-31 18:29:30 +01:00
Dolu1990
30b05eaf96 Add CsrInterface to allow custom CSR addition 
Add CustomCsrDemoPlugin as a show case
 2018-01-31 18:13:42 +01:00
Dolu1990
bdbf6ecf17 BranchPrediction DYNAMIC_TARGET add source PC tag to only consume entries on branch instructions 2018-01-29 14:52:31 +01:00
Dolu1990
0d318ab6b9 Add DYNAMIC_TARGET branch prediction (1.41 DMIPS/Mhz) 
Add longer timeouts in the regressions tests
 2018-01-29 13:17:11 +01:00
Dolu1990
307c0b6bfa Now mret and ebreak are only allowed in CSR machine mode 2018-01-28 16:34:55 +01:00
Dolu1990
93da5d29bc Fix dhrystone referance log 2018-01-28 16:34:55 +01:00
Dolu1990
26732942e5 Update DMIPS/Mhz 
Add cached config with maximal performance settings
FullBarrielShifterPlugin can now be configured to do everything in the execute stage
 2018-01-25 01:11:57 +01:00
Dolu1990
3b3bbd48b9 SpinalHDL 1.1.3 => Now Verilog rom are emited into separated bin files 2018-01-20 18:29:33 +01:00
Dolu1990
6a521a8d13 Better MuraxSim gui 
Add MuraxSim in the readme
 2018-01-09 08:59:17 +01:00
Dolu1990
9a89573942 SpinalHDL 1.1.2 
Add Murax setup with Mul Div Barriel
 2018-01-06 22:09:42 +01:00
Dolu1990
43d3ffd685 CsrPlugin : Now wait that the whole pipeline (including writeback) is empty before executing interruptions. This make the separation between context switching clear and avoid on atomic instructions failure 2018-01-04 17:37:23 +01:00
Dolu1990
2b7465e5df Add more atomic tests (PASS) 2018-01-04 16:16:22 +01:00
Dolu1990
611f2f487f Fix DataCache atomic integration into DBusCachedPlugin 
Atomic is passing basic tests
 2018-01-04 15:24:00 +01:00
Dolu1990
4637e6cb48 Fix DecodingSimplePlugin model building when reinvocation is done one a preexisting opcode. 
add Atomic test flow
 2018-01-04 14:43:30 +01:00
Dolu1990
468dd3841e Add Atomic LR SC support to the DBusCachedPlugin via reservation entries buffer 2018-01-04 13:16:40 +01:00
Dolu1990
4ed19f2cc5 SpinalHDL 1.1.1 2017-12-30 03:36:57 +01:00
Dolu1990
0d39e38906 SpinalHDL 1.1.0 2017-12-28 13:49:39 +01:00
Dolu1990
3c0588eb4b remove MuraxSim fixed path 2017-12-19 22:33:46 +01:00
Dolu1990
7f2b2181c1 SpinalHDL 1.0.3 2017-12-19 21:21:16 +01:00
Dolu1990
37849b7a66 Spinal 1.0.2 sim update 2017-12-19 00:40:52 +01:00
Dolu1990
ebda7526b5 MuraxSim 1.0.0 2017-12-17 17:57:09 +01:00
Dolu1990
dda5372a6c Fix typo 2017-12-14 01:05:06 +01:00
Dolu1990
d6e0761065 Fix led gui refresh rate 2017-12-14 01:04:31 +01:00
Dolu1990
2259c9cb0f Add SpinalHDL sim (1.0.0) 2017-12-14 00:57:12 +01:00
Dolu1990
e1b86ea511 SpinalHDL 0.11.4 update 2017-12-01 11:19:23 +01:00
Dolu1990
586d3ed286 Update formal VexRiscv to halt on missaligned dbus 2017-11-26 15:30:48 +01:00
Dolu1990
4de0aac469 Merge branch 'formal' 2017-11-24 14:03:25 +01:00
Dolu1990
b7f4f09814 Update verilator makefiles to support the last SpinalHDL changes (process merges) 2017-11-21 23:56:46 +01:00
Dolu1990
9b9bbaa4ad Add missing full config for the iBus 2017-11-21 00:09:02 +01:00
Dolu1990
ce6fd6d0aa Add VexRiscvAxi4 demo 2017-11-20 23:57:37 +01:00
Dolu1990
7c19288648 Update Synthesis bench 
Update some synthesis results
 2017-11-17 20:10:46 +01:00
Tony Kao
290dbc106e Fixes GPIO width mismatch 
Adds explicit type to apbDecoder.slave to suppress IDE errors
 2017-11-16 15:02:13 -05:00
Dolu1990
6c3fed3505 SpinalHDL 0.11.1 2017-11-15 16:44:42 +01:00
Dolu1990
be3d301eaf Merge remote-tracking branch 'origin/spinalhdl_reworkDev' 2017-11-12 13:08:05 +01:00
Dolu1990
838c13d68b spinal.core.internals literals import 2017-11-10 13:14:30 +01:00
Dolu1990
3060296b94 unsetRegIfNoAssignement -> allowUnsetRegToAvoidLatch 2017-11-10 11:33:04 +01:00
Dolu1990
c3a7f4e58c CSR unsetRegIfNoAssignement fix 
BranchPlugin doesn't emit the prediction cache when the STATIC setup is used
 2017-11-10 00:59:31 +01:00
Dolu1990
d6777ae8ec usetRegIfNoAssign upgrade 2017-11-09 20:10:56 +01:00
Dolu1990
a72c7fd0d1 Clean Murax toplevel by extracting integrated Area into dedicated components located in MuraxUtiles.scala 2017-11-07 22:19:33 +01:00
Dolu1990
714d44d248 Add fixed bug into the FormalPlugin comments 2017-11-07 13:54:07 +01:00
Dolu1990
200a73bea0 Fix FormalPlugin to pass liveness again. 2017-11-06 23:04:33 +01:00
Dolu1990
8098a03a9b with no bus stall, pass all tests except uniqueness 2017-11-06 20:26:45 +01:00
Dolu1990
e2a432eb5e add HaltOnExceptionPlugin 
wip
 2017-11-05 20:13:27 +01:00
Dolu1990
276f7895e7 Add FormalPlugin 
Add FormalSimple CPU configuration
 2017-11-04 00:55:32 +01:00
Dolu1990
ba42f71813 pass VexRiscv regressions 2017-10-30 14:29:25 +01:00
Ubuntu
008a5b7309 updated main.cpp 
added missing using namespace std
 2017-10-17 22:09:08 +00:00
Dolu1990
2bf7ca24f2 Add VexRiscvAvalonWithIntegratedJtag 2017-10-16 11:52:17 +02:00
Dolu1990
aa859aae6b Update framework.h 
Add missing using namespace std;
 2017-10-05 10:08:09 +02:00
Dolu1990
09ba7c28da Change some xx.input(REGFILE_WRITE_DATA) for xx.output(REGFILE_WRITE_DATA) 2017-08-27 15:21:44 +02:00
Dolu1990
8168c9bf3a Update simd_add makefile 2017-08-27 14:49:36 +02:00
Charles Papon
2c6889e688 Murax mainBus now handle unmapped memory access allowing the debug to access unmapped area without locking the CPU 
Murax add dhrystone config
 2017-08-10 22:48:00 +02:00
Charles Papon
aa477b2b1c DebugPlugin now prevent the CPU catching exception when debug instruction are pushed 
Fix DataCache locking when loading mem read rsp  transaction has the flag set
Briey : Now the debug module reset the whole AXI system instead of only the CPU
Now in debug, you can access unmapped memory without crashing the CPU
 2017-08-10 20:56:54 +02:00
Charles Papon
1653548140 Better readme about custum instruction testing 2017-08-08 18:36:23 +02:00
Charles Papon
54b06e6438 Add SIMD_ADD regression and config (show case) 2017-08-08 18:19:02 +02:00
Charles Papon
3307d6c3b5 Briey move CPU and UART generics from to toplevel to the toplevel configuration object 2017-08-06 15:42:37 +02:00
Charles Papon
671aa5050e Move CPU and UART configs into the murax configuration object (in place of toplevel hardcoding) 
Add MuraxConfig.fast
 2017-08-04 14:55:54 +02:00
Charles Papon
ac59eebb8d Add Murax configuration which integrate a boot programme : 
Will blink led and echo UART RX to UART TX   (in the verilator sim, type some text and press enter to send UART frame to the Murax RX pin)
 2017-08-03 21:58:23 +02:00
Dolu1990
58981c0e8e Add Murax fast in synthesis bench 2017-08-01 21:14:09 +02:00
Charles Papon
f44b345132 Add console TX in the Murax verilator 2017-07-31 21:04:41 +02:00
Charles Papon
0c9a39d3ce Connect the UART interruption to the CPU 2017-07-31 17:20:47 +02:00
Charles Papon
c16a53c388 Refractoring of some arbitration signals 
Add UART into Murax
 2017-07-31 13:34:25 +02:00
Dolu1990
8708d2482f Add more information about dependencies 2017-07-30 11:37:22 +02:00