litex

mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00

Author	SHA1	Message	Date
developandplay	9fd9eaea07	Move patch script to python-data	2021-06-27 01:31:05 +02:00
developandplay	ac217d818f	Set environmental variables in python	2021-06-27 01:07:27 +02:00
developandplay	e3f6d8349b	Use os methods to expand env vars	2021-06-26 16:30:54 +02:00
developandplay	b787ee4411	Move systemverilog files to python-data	2021-06-26 15:45:48 +02:00
developandplay	16b3e08c17	Copy config loader in python	2021-06-26 15:37:17 +02:00
enjoy-digital	23afca3de8	Merge pull request #953 from developandplay/blackparrot-32bit-csr Blackparrot 32bit csr	2021-06-23 19:20:51 +02:00
Florent Kermarrec	edc4c85615	build/lattice/common: Add ECP5 Differential Output support.	2021-06-23 11:55:22 +02:00
developandplay	adb71bde8c	Adjust wishbone adapter for 32bits	2021-06-22 23:37:24 +02:00
developandplay	b795f848a2	Fixup blackparrot	2021-06-22 18:43:17 +02:00
Florent Kermarrec	c395a8068a	cores/prbs: Minor Cleanup and make sure to generate errors when RX is Idle.	2021-06-22 16:57:00 +02:00
Florent Kermarrec	2cd6224acf	clock/lattice_ecp5/ECP5PLL: Add expose_dpa method (Dynamic Phase Adjustment) and move code to it.	2021-06-22 12:07:39 +02:00
enjoy-digital	09a3ca6fd0	Merge pull request #949 from zyp/ecp5_dynamic_pll cores/clock/ecp5: Add dynamic phase adjustment signals.	2021-06-22 12:04:20 +02:00
enjoy-digital	26df3fa2c4	Merge pull request #952 from smunaut/dfu build/DFUProg: Allow to specify alt interface and to not reboot	2021-06-22 12:03:43 +02:00
Florent Kermarrec	3d81c9a437	build/lattice/LatticeProgrammer: pgrcmd always seems to return a non-zero value so disable check.	2021-06-22 11:59:42 +02:00
Florent Kermarrec	f381cdcd1a	build/GenericProgrammer: Add check parameter to make check optional.	2021-06-22 11:59:38 +02:00
Sylvain Munaut	38e46bb3d3	build/DFUProg: Allow to specify alt interface and to not reboot Some targets have multiple alt settings for DFU for different zone of the flash. Allowing to specify which one to flash and not rebooting immediately allows to flash several of them at once. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>	2021-06-21 16:12:55 +02:00
Florent Kermarrec	d6f24f2f68	cores/uart/RS232ClkPhaseAccum: Avoid reset on phase signal, improve timings/resources on iCE40.	2021-06-20 14:33:25 +02:00
Florent Kermarrec	4c8184fbb6	cores/uart: Fix refactoring typo (tick is a 1-bit Signal), thanks @tnt.	2021-06-20 08:58:45 +02:00
Vegard Storheil Eriksen	b58c416a24	cores/clock/ecp5: Add dynamic phase adjustment signals.	2021-06-19 11:24:08 +02:00
developandplay	7d2e19ac26	Enable non-interactive mode	2021-06-18 12:35:42 +02:00
enjoy-digital	fdb278838c	Merge pull request #881 from developandplay/patch-1 Add --non-interactive option to simulation	2021-06-18 10:40:19 +02:00
Florent Kermarrec	5205356d24	tools/litex_json2dts: Simplify Switches interrupt support (and make it similar to other interrupts).	2021-06-18 10:36:33 +02:00
enjoy-digital	291374e66f	Merge pull request #854 from mczerski/gpio_dts_irq dts: gpio: interrupt controller definition for switches	2021-06-18 10:29:30 +02:00
Florent Kermarrec	98676162a3	VexRiscv-SMP: Review/Cleanup #906 .	2021-06-18 10:19:27 +02:00
enjoy-digital	58c533668c	Merge pull request #906 from rdolbeau/extra_config_and_dts Configurable [ID]TLB for VexRiscv & improved DTS	2021-06-18 10:09:28 +02:00
Florent Kermarrec	8ce7c583e6	cores/spi: Add Manual CS Mode (to allow doing Bulk Xfers without external changes), also cleanup/simplify a bit CSR descriptions.	2021-06-18 10:07:01 +02:00
Florent Kermarrec	a4be067d91	tools: Add litex_contributors.py script to easily update CONTRIBUTORS file.	2021-06-17 23:04:28 +02:00
Florent Kermarrec	7179d88e8c	ram/lattice_nx: Add init parameter and rename method to add_init. When init is not empty, call add_init automatically (similar to Memory).	2021-06-16 18:33:00 +02:00
enjoy-digital	869b5c24a8	Merge pull request #941 from danc86/nxlram-initval soc/cores/ram: allow populating initial values in Nexus LRAM	2021-06-16 18:31:00 +02:00
enjoy-digital	b0e6851150	Merge pull request #942 from zyp/external_software_packages Allow external software packages to be linked into the BIOS	2021-06-16 18:21:55 +02:00
enjoy-digital	aad64bbf9b	Merge pull request #943 from JosephBushagour/jbushagour_getargspec_fix Replace deprecated inspect.getargspec with inspect.getfullargspec.	2021-06-16 14:59:39 +02:00
Tim Callahan	e59530ab50	Force SymbiFlow 'make' to be non-parallel. Signed-off-by: Tim Callahan <tcal@google.com>	2021-06-15 14:49:28 -07:00
Florent Kermarrec	8a644c9086	soc/add_video_xy: Allow passing phy or phy's Endpoint.	2021-06-15 18:10:24 +02:00
Joey Bushagour	62ea48940a	Replace deprecated inspect.getargspec with inspect.getfullargspec.	2021-06-15 08:03:11 -05:00
Vegard Storheil Eriksen	8d527a1f3f	soc/software/bios: Allow registering init functions.	2021-06-13 14:04:34 +02:00
Vegard Storheil Eriksen	61636f1248	soc/integration/builder: Allow linking in external software packages.	2021-06-13 14:04:34 +02:00
Dan Callaghan	be4c7cfb34	soc/cores/ram: allow populating initial values in Nexus LRAM On designs which use Nexus parts without any external memory, it can be difficult to fit an embedded ROM program larger than a few KiB. Radiant cannot infer LRAM, and refuses to infer EBRAM under many circumstances too, so large memories tend to just consume a huge number of LUTs. This patch makes it possible to explicitly wire up an LRAM as a ROM, populate its initial values with a program, and execute directly from it. That lets us embed programs up to 64KiB.	2021-06-11 16:41:10 +10:00
bunnie	311b633a11	breakout the keyclearb pin for integration elsewhere	2021-06-11 04:44:39 +08:00
enjoy-digital	0a932be491	Merge pull request #936 from developandplay/patch-4 Sync ROM_BOOT_ADDRESS with main_ram location	2021-06-09 12:11:24 +02:00
enjoy-digital	d5cfe09f4c	Merge pull request #931 from madscientist159/add-1920-1200-mode Add 1920x1200@60 RBv2 to LiteX video modes	2021-06-09 09:03:57 +02:00
enjoy-digital	8cdb0b8db3	Merge pull request #932 from developandplay/patch-3 Fix base_address for LiteDRAMWishbone2Native	2021-06-09 08:58:28 +02:00
Florent Kermarrec	5061a368da	cores/video: Regroup VGA/DVI Phy in VideoGenericPHY and support variations (positive/negative hsync/vsync, etc...)	2021-06-09 08:49:29 +02:00
developandplay	e0352a1f0f	Sync ROM_BOOT_ADDRESS with main_ram location Rocket and Blackparrot main_ram starts at 0x80000000 Vexriscv main_ram starts at 0x40000000	2021-06-09 03:36:32 +02:00
Florent Kermarrec	25ead1ad69	interconnect/stream: Add Gate.	2021-06-08 18:58:08 +02:00
developandplay	f2caeaf83a	Fix base_address for LiteDRAMWishbone2Native Fixes `origin == None` due to https://github.com/litex-hub/litex-boards/commit/ba01776	2021-06-08 00:51:11 +02:00
Raptor Engineering Development Team	47c19933fa	Add 1920x1200@60 RBv2 to LiteX video modes Tested on Raptor Sparrowhawk	2021-06-07 14:49:33 -05:00
Florent Kermarrec	a064e9d048	soc/interconnect/wishbone: Fix SEL propagation on UpConverter (thanks @Dolu1990).	2021-06-02 10:46:53 +02:00
Florent Kermarrec	0b329c3dce	tools/litex_json2dts: Add initial USB OHCI support.	2021-06-01 10:41:35 +02:00
Florent Kermarrec	a17ded2ce6	soc/cores: Add initial USB OHCI core wrapper.	2021-06-01 10:28:30 +02:00
Florent Kermarrec	6c8e839cef	soc/cores/freqmeter: Minor simplification.	2021-06-01 10:26:27 +02:00
Florent Kermarrec	26db10701a	integration/soc/add_video_terminal: Connect UART to TX FIFO instead of Source. Allow UART to be displayed on terminal with Auto TX flush.	2021-05-28 11:11:49 +02:00
Florent Kermarrec	ad1fe143cc	cores/uart: Cleanup code and add optional automatic TX Flush. In some SoCs where UART's PHY is managed externally (ex through a Bridge) we don't necessarily want the UART TX to wait for the PHY to be ready (and then stall the CPU) but just want to let the CPU print the UART and will just connect when useful and handle backpressure when connected. This is now possible by calling add_auto_tx_flush method, ex in the SoC: self.uart.add_auto_tx_flush(sys_clk_freq)	2021-05-28 11:03:23 +02:00
Florent Kermarrec	d11dc0b503	libbase/memtest: Print size with 1 digit after the decimal point.	2021-05-27 19:33:29 +02:00
enjoy-digital	9b85769499	Merge pull request #923 from gsomlo/gls-fix-gcc-warn software/lib*: address gcc warnings	2021-05-27 18:50:24 +02:00
enjoy-digital	d7f4293743	Merge pull request #924 from developandplay/patch-2 Use add_etherbone in simulation	2021-05-27 18:49:45 +02:00
Florent Kermarrec	34df454157	cores/timer/uart: Use edge="rising on Timer/UART's EventSourceProcess. Make code easier to understand.	2021-05-27 18:47:40 +02:00
Gabriel Somlo	9a24034d1d	software/lib*: address gcc warnings Fix gcc warnings: use 'unsigned long' to represent memory addresses, and remove 'static' from the definition of 'cdelay()', as it is called from multiple C files.	2021-05-27 08:47:29 -04:00
developandplay	c17421bccb	Use add_etherbone in simulation Fixes not working analyzer example from wiki	2021-05-26 23:18:22 +02:00
Florent Kermarrec	5fd215fe3a	soc/interconnect/stream/Pipeline: Improve comments.	2021-05-26 18:34:22 +02:00
Florent Kermarrec	b1d8fe61f8	cores/cpu: Add initial FemtoRV support. FemtoRV is a minimalist RISC-V CPU with design process documented and available at https://github.com/BrunoLevy/learn-fpga. This CPU is a very nice way to discover/learn RISC-V and this LiteX support can be useful to learn how to integrate a custom CPU with LiteX. With this support, FemtoRV is now directly usable with LiteX Sim: $litex_sim --cpu-type=femtorv This should also enable its use on all boards (> 50) available in LiteX-Boards repository (but hasn't been tested yet), ex: $python3 -m litex_boards.targets.digilent_arty --cpu-type=femtorv --build	2021-05-26 09:08:41 +02:00
Florent Kermarrec	d3560e5772	liblitedram/sdram.c: Update sdram_write_read_check_test_pattern with SDRAM_PHY_ECP5DDRPHY. The return value has been changed and also required to be update for SDRAM_PHY_ECP5DDRPHY.	2021-05-25 10:28:56 +02:00
enjoy-digital	8085cc3c97	Merge pull request #915 from zyp/liblitespi_remove_mode software/liblitespi: Remove manual mode control.	2021-05-25 08:41:13 +02:00
Romain Dolbeau	c06bd2c77d	Make the [ID]TLB size configurable from Litex ; expand the DTS to include cache/TLB/topology in CPUs & generate the required information for VexRiscv	2021-05-23 03:15:02 -04:00
Florent Kermarrec	55344b4c14	cores/clock/xilinx: Add power down support.	2021-05-19 22:31:35 +02:00
Florent Kermarrec	cbb75b852e	cores/clock/xilinx: Cosmetic cleanup on Instances.	2021-05-19 22:20:04 +02:00
Florent Kermarrec	12b27f961c	software/liblitedram: Fix compilation on designs without SDRAM.	2021-05-19 11:07:03 +02:00
Florent Kermarrec	aa2622b1f5	software/liblitedram: Add missing #ifdef SDRAM_DEBUG to fix compilation with large DRAMs. sdram_dbg seems to have current limitations: "At most 32 databits SDR or 16 databits DDR supported".	2021-05-18 11:36:19 +02:00
Jędrzej Boczar	93f357d853	soc/software/liblitedram: make leveling scores more robust by counting number of bitslips	2021-05-17 14:53:04 +02:00
Jędrzej Boczar	50805797c6	soc/software/liblitedram: optional write latency calibration debug output	2021-05-17 14:49:30 +02:00
Jędrzej Boczar	1f2b8621fe	soc/software/liblitedram: add sdram_debug command	2021-05-17 14:38:35 +02:00
Jędrzej Boczar	e5c1482572	soc/software/liblitedram: add sdram debugging utilities	2021-05-17 14:19:16 +02:00
Jędrzej Boczar	cd6f98c4c8	soc/software/liblitedram: use updated sdram_dfii_pix_X_addr interface	2021-05-17 14:11:10 +02:00
Jędrzej Boczar	33fb48584b	soc/software/libbase: add option for read retries in memtest_data	2021-05-17 13:56:31 +02:00
Jędrzej Boczar	d610c9da44	soc/software/libbase: limit number of errors printed when using MEMTEST_*_DEBUG	2021-05-17 13:53:32 +02:00
Vegard Storheil Eriksen	422c356930	software/liblitespi: Remove manual mode control.	2021-05-17 13:44:02 +02:00
Jędrzej Boczar	b90d0bd1f7	soc/software/libbase: make memtest_data more configurable, add on_error callback	2021-05-17 13:42:44 +02:00
Florent Kermarrec	13979a43b7	soc/add_cpu: Fix/Simplify CFU integration.	2021-05-17 12:04:37 +02:00
Florent Kermarrec	d0e8de077c	soc/SoCController: Add separate fields for SoC and CPU resets. As discussed in #909, in some specific cases, it can be interesting to be able to keep the CPU in reset while the rest of the SoC is still operating (ex the peripherals/bridges). With theses changes, the old behaviour is preserved to do a full SoC Reset (at the exception that writing a 1 is now mandatory) and a separate field specific to the CPU reset is added. The SoC Reset is a pulse (otherwise the system would be stuck in Reset) while the CPU Reset is based on the register value (so can be pulse or hold).	2021-05-17 11:43:04 +02:00
Florent Kermarrec	06f4658174	cpu: Specify clock domain (improve readability).	2021-05-17 10:51:54 +02:00
Florent Kermarrec	78bdde0424	cpu/vexriscv: Simplify CFU integration, use Cfu.v as default CFU when not specified and rename argument to --cpu-cfu.	2021-05-17 10:02:58 +02:00
Florent Kermarrec	a6c37df175	soc_core: Improve readability and move ROM initialization to SoCCore. (--integrated-rom-file args is also renamed to --integrated-rom-init to simplify support for str and list).	2021-05-17 09:55:28 +02:00
Florent Kermarrec	dd72b1acfe	soc/add_cpu: Add **kwargs support.	2021-05-17 09:53:40 +02:00
Florent Kermarrec	298f65e78e	cpu/vexriscv: Change methods' order to improve readability.	2021-05-17 08:54:53 +02:00
enjoy-digital	fc0e1440c5	Merge pull request #908 from antmicro/cfu-integration Add CFU integration	2021-05-17 08:43:38 +02:00
zyp	1571da4989	software/liblitespi: Fix speed test. (#911 ) Before this patch, the loop would finish with lowest_div either set to the first failing value or 0 even if it succeeded with 0. Fix it so that if all tests pass, it’ll end up being -1 before the incrementation. This patch also skips retesting the original value. If the retest failed, lowest_div would be incremented past the original value and could potentially wrap around.	2021-05-17 08:30:38 +02:00
Robert Szczepanski	d5dab98a2c	Add CFU integration	2021-05-14 09:20:58 +02:00
bunnie	53982acd9f	I2S fix: sample SYNC on the correct edge (#904 ) * resolve issue #862 add description to soc.svd The issue is that with no description provided it simply would not put out a description tag, which breaks compatibility with other programs. Insert a somewhat useful default description including a timestamp and the words "LiteX SoC". * I2S fix: sample SYNC on the correct edge The original Tx path implementation samples SYNC on the falling edge, out of convenience with the fact that teh data must also change on the falling edge. This works OK, until you have a CODEC which has a ~40ns max delay spec on the SYNC, and also has a slightly asymmetric SYNC edge (the SYNC signal is also the WCLK or LRCLK depending on which docs you read). The SYNC by spec is supposed to change on the falling edge, and this extra delay is enough to cause the SYNC to introduce occassional bit or frame shifts into the audio. This fix samples the SYNC on the rising edge, but still changes the data on the falling edge, thus allowing for implementations where SYNC has quite loose timings relative to everything else (as is the case on the TLV320AIC3200)	2021-05-07 08:17:49 +02:00
Hans Baier	5fd1cae618	lattice/programmer.py: Add iCESugar programmer	2021-05-07 10:55:48 +07:00
Florent Kermarrec	34ed5672c3	tools/litex_server/litex_term: Add --jtag-chain argument.	2021-05-06 15:41:25 +02:00
Florent Kermarrec	24105f12d5	openocd/stream: Expose chain parameter.	2021-05-06 15:25:18 +02:00
Florent Kermarrec	aea1e7fb20	jtag/jtagbone: Expose chain parameter.	2021-05-06 14:58:47 +02:00
Florent Kermarrec	3ce5f3867a	cores/video/VideoS7GTPHDMIPHY: Add refclk support (None, Differential or Single-Ended).	2021-05-06 10:50:29 +02:00
Florent Kermarrec	bfb90f5625	soc/cores/video: Add VideoS7GTPHDMIPHY (7-Series HDMI PHY over GTPs). Validated on Decklink Mini 4K Monitor at 1080p60 (should allow UHD/4K), still some fixed things, but should provide a good basis to go further...	2021-05-05 18:12:10 +02:00
Florent Kermarrec	1d21a90076	software/liblitespi: Fix compilation warning.	2021-05-03 10:34:45 +02:00
Tim Callahan	dcd13d27ef	Add 'lse' as a --synth-mode option with Radiant. Signed-off-by: Tim Callahan <tcal@google.com>	2021-05-01 21:12:56 -07:00
enjoy-digital	fb8f45be73	Merge pull request #901 from stffrdhrn/litex-sdcard-irq integration/soc: Wire up the sdirq to the CPU	2021-04-30 12:30:35 +02:00
Florent Kermarrec	59b968decc	cores/clock/gowin_gw1n: Fix indent.	2021-04-30 12:22:59 +02:00
Florent Kermarrec	5dc3ad3b29	soc/cores/spi/SPISlave: Minor cleanup.	2021-04-30 12:16:49 +02:00
Florent Kermarrec	75bb78a413	cores/clock: Add initial Gowin GW1N PLL support. For now limited to one output clock and not supporting phase/duty cycle adjustements.	2021-04-30 11:31:04 +02:00
Florent Kermarrec	fefc5aae66	cores/video/VideoVGAPHY: Add optional clk support. Some LCDs displays are almost VGA compatible (no DE, active low hsync/vsync) but require the clock.	2021-04-29 11:50:04 +02:00
Florent Kermarrec	87ebdea5a7	software/libliteeth: Add optional ETH_PHY_NO_RESET support to allow disabling software reset. Un-wanted when using the Hybrid LiteETHMAC since interrupt the hardware UDP/IP stack.	2021-04-29 11:50:00 +02:00
Stafford Horne	a9e935e61a	tools/litex_json2dts: Add interrupt settings for sdcard	2021-04-29 17:52:17 +09:00
Stafford Horne	dc1a4c5380	integration/soc: Wire up the sdirq to the CPU I am working on testing out the patches from: https://github.com/litex-hub/linux/pull/8 These linux patches take advantage of the sdcard interrupt to track when transfers finish. However, it seems the interrupt is not being connected to the CPU. This patch does that by allowing us to directly register and EventManager module with the irq handler.	2021-04-29 17:18:51 +09:00
Tim Ansell	11f091d4cf	Merge pull request #900 from stffrdhrn/rom-to-128k integration/soc_core: Increase default ROM size to 128K	2021-04-28 15:28:19 -07:00
Stafford Horne	2f96cf021c	integration/soc_core: Increase default ROM size to 128K With recent BIOS changes the default rom size on the mor1kx built just passes over the 64k boundary and the build fails. Since the 128K default is a soft limit and the ROM gets resized to the actual ROM requirements this should be relatively safe. Note, that if a RW rom is configured the full 128kb will be allocated. Fixes: #893	2021-04-29 06:52:49 +09:00
Florent Kermarrec	9098f5553c	software/liblitedram: Add liblitedram prefix to includes (to use copy of bist.c/sdram.c externally).	2021-04-28 17:21:04 +02:00
Florent Kermarrec	bb355a773a	integration/soc/video: Allow passing timings as str or tuple (name, dict). When passed as str, the timing dict will be extracted from litex.soc.cores.video.video_timings. When passed as tuple, custom dict will be directly passed to VTG.	2021-04-28 16:58:11 +02:00
Florent Kermarrec	c4e8e44cd9	cores/video/VideoTimingGenerator: Allow passing custom dict as default_video_timings. Allow only listing the classical video timings in the core and let user provide the timings specific to other configurations.	2021-04-28 16:56:28 +02:00
enjoy-digital	da1092d9c0	Merge pull request #896 from danc86/nodefaultlibs soc/software: link with compiler instead of ld	2021-04-28 15:44:49 +02:00
Florent Kermarrec	f7b615ffab	software/liblitedram/sdram.c: Avoid direct ddrphy_wdly_dq_rst during DQ-DQS training on Ultrascale/Ultrascale+ (seems to cause issue on some configurations/modules). Also add a delay to be similar to read_leveling reset/inc functions.	2021-04-28 14:42:41 +02:00
Florent Kermarrec	dc4f9772ba	software/liblitedram/sdram.c: Move common centering functions to separate section.	2021-04-28 14:15:48 +02:00
Florent Kermarrec	19d16fa27f	software/liblitedram/sdram/sdram_write_leveling_find_cmd_delay: Only update best_count when error < best_error.	2021-04-28 11:23:34 +02:00
Florent Kermarrec	c50989be8e	software/liblitedram/sdram: Add sdram_tck_taps variable and use it internally to avoid un-needed accesses to CSRs.	2021-04-28 11:22:07 +02:00
Florent Kermarrec	87c0e30cef	software/liblitedram/sdram.c: Remove residual wrap around code, fix some spaces/tabs.	2021-04-28 10:45:35 +02:00
Florent Kermarrec	74c42a55e2	tools/litex_json2dts/framebuffer: Use framebuffer_base.	2021-04-27 18:59:54 +02:00
Florent Kermarrec	a3f3d8f08f	software/liblitedram/sdram: Fix compilation warning.	2021-04-27 16:33:40 +02:00
Jędrzej Boczar	ad23130a9a	software/liblitedram: use single iteration of dq-dqs training	2021-04-27 10:54:32 +02:00
Dan Callaghan	020466a43e	soc/software: link with compiler instead of ld The linker does not actually recognise -nodefaultlibs, that is a compiler option. Prior to binutils 2.36, ld treated -nodefaultlibs as a string of short options and ignored them as unrecognised. Starting from binutils 2.36, it reports an error instead: riscv64-unknown-elf-ld: Error: unable to disambiguate: -nodefaultlibs (did you mean --nodefaultlibs ?) See also: https://sourceware.org/bugzilla/show_bug.cgi?id=27050 Fixes #825.	2021-04-27 15:36:13 +10:00
Florent Kermarrec	4c26dbe98f	cores/cpu/microwatt: Re-map csr/xics and keep the lower 128MBs for the SoC IO auto-allocation.	2021-04-26 18:37:40 +02:00
Florent Kermarrec	9a82fd1d54	tools/litex_sim: Use automatic ethmac allocation.	2021-04-26 18:33:50 +02:00
Florent Kermarrec	48ec20e2ef	software/liblitedram/sdram: Remove wraps around in sdram_leveling_center_module. Adding wraps around capability will have to be discussed, if implemented this has to be done very carefully since there are no relation between the total delay that can be compensated through the I/O-DELAYs and the SDRAM clock period. As implemented, it also produced confusing values in the logs: m0:0 m1:0 Read leveling: m0, b0: \|00000000000000000000000000000000\| delays: - m0, b1: \|00000000000011111111111111100000\| delays: 19+-07 m0, b2: \|00000000000000000000000000001111\| delays: 14+-17 m0, b3: \|00000000000000000000000000000000\| delays: - m0, b4: \|00000000000000000000000000000000\| delays: - m0, b5: \|00000000000000000000000000000000\| delays: - m0, b6: \|00000000000000000000000000000000\| delays: - m0, b7: \|00000000000000000000000000000000\| delays: - best: m0, b01 delays: 19+-07 m1, b0: \|00000000000000000000000000000000\| delays: - m1, b1: \|00000000000011111111111111000000\| delays: 19+-07 m1, b2: \|00000000000000000000000000001111\| delays: 15+-17 m1, b3: \|00000000000000000000000000000000\| delays: - m1, b4: \|00000000000000000000000000000000\| delays: - m1, b5: \|00000000000000000000000000000000\| delays: - m1, b6: \|00000000000000000000000000000000\| delays: - m1, b7: \|00000000000000000000000000000000\| delays: - best: m1, b01 delays: 19+-07 Switching SDRAM to hardware control. --> 14+-17 and 15+-17 are confusing.	2021-04-26 17:27:27 +02:00
enjoy-digital	a6c5fd7aed	Merge pull request #891 from antmicro/crosslink-nx-fix-sdr-buffers Lattice Crosslink NX: Fix clock port names in SDR{in/out} Impl	2021-04-26 11:19:44 +02:00
Jan Luebbe	f4c9bf0666	bios: support passing tftp filename to the 'netboot' command Signed-off-by: Jan Luebbe <jlu@pengutronix.de>	2021-04-25 20:45:03 +02:00
Karol Gugala	54f729fbc1	Lattice: Fix port names in SDR{in/out} Impl Signed-off-by: Karol Gugala <kgugala@antmicro.com>	2021-04-25 19:47:30 +02:00
Florent Kermarrec	22d763ee11	tools/litex_sim: Remove self.add_csr calls no longer required.	2021-04-23 19:33:51 +02:00
Florent Kermarrec	8c8c1fe6e0	tools/litex_sim: Fix cpu in configuration (allow list of supported CPU to be listed when invalid cpu_type is provided).	2021-04-23 19:16:18 +02:00
Florent Kermarrec	116c2f1549	cores/cpu: Cosmetic cleanups.	2021-04-23 16:16:31 +02:00
Florent Kermarrec	fe7029a7e0	software/liblitedram: Add missing read window re-centering after selecting bitslip in Write DQ-DQS training.	2021-04-22 17:08:20 +02:00
enjoy-digital	447d2648e8	Merge pull request #884 from antmicro/jboc/dq-dqs-training Write DQ-DQS training	2021-04-22 17:08:08 +02:00
Florent Kermarrec	0ed7852779	tools/litex_term: Add time.sleep on BridgeUART to avoid high CPU usage.	2021-04-22 17:07:33 +02:00
Florent Kermarrec	75045914b4	global: Bump copyright year.	2021-04-22 17:07:29 +02:00
Florent Kermarrec	b55af2156b	soc/add_sdcard: Fix cmd_done signal.	2021-04-21 13:38:00 +02:00
Paul Mackerras	e6765f847d	integration/soc/add_sdcard: Add an interrupt for command completion This is useful for long-running commands generally and in particular for those without any data transfer, such as erase. It is a level-sensitive interrupt because that makes it a little harder to lose interrupts due to incorrect programming. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>	2021-04-21 09:00:31 +10:00
Florent Kermarrec	2ac7e0b978	software/liblitesdcard: Update with LiteSDCard changes (SDCARD_CTRL_RESPONSE_SHORT_BUSY is now directly a supported command).	2021-04-20 14:30:28 +02:00
enjoy-digital	b29515bd1d	Merge pull request #885 from paulusmack/master software/liblitesdcard: Tell the controller when to wait while the card is busy	2021-04-20 14:30:08 +02:00
enjoy-digital	eea63968d2	Merge pull request #877 from rdolbeau/eth_int_fix Fix interrupt issue with ethernet on recent Linux-On-Litex-Vexriscv/SMP	2021-04-19 18:12:01 +02:00
Paul Mackerras	49c4d735c5	software/liblitesdcard: Tell the controller when to wait while the card is busy Bit 2 of the command register now tells the controller to wait while the card is indicating that it is busy (by pulling the DAT0 line low). The card can do this for commands 7 and 12 and app command 41 (and also for commands 20, 28, 29, 38 and 43, but we don't use those here.) This sets bit 2 for those commands. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>	2021-04-19 09:12:13 +10:00
Jędrzej Boczar	2a5973b21f	soc/software/liblitedram: refactor centering code into more generic function	2021-04-16 15:41:24 +02:00
Jędrzej Boczar	76d121ea36	soc/software/liblitedram: add DQ-DQS training procedure	2021-04-16 11:50:38 +02:00
Romain Dolbeau	f310dd52f3	Fix interrupt issue with ethernet on recent Linux-On-Litex-Vexriscv/SMP It seems an overreaching 'interrupt-parent' caused trouble to interrupt routing. This moves 'interrupt-parent' to the SoC entry.	2021-04-15 10:06:53 +02:00
developandplay	8ef7353fe5	Add interactivity option to simulation	2021-04-14 13:39:47 +02:00
enjoy-digital	246142256b	Merge pull request #880 from betrusted-io/issue-862 resolve issue #862 add description to soc.svd	2021-04-14 08:58:42 +02:00
enjoy-digital	01479ed541	Merge pull request #879 from betrusted-io/timer-doc use AutoDoc for timer documentation	2021-04-14 08:56:37 +02:00
Florent Kermarrec	f014e4cbd2	tools/litex_client: Add filter parameter to dump_registrers to only dump/display the filtered registers: ex: litex_cli --regs --filter=pcie_phy will only dump/display pcie_phy registers.	2021-04-13 13:44:41 +02:00
bunnie	1b78b12024	resolve feedback on import location	2021-04-12 22:27:22 +08:00
bunnie	ab0aab6913	resolve issue #862 add description to soc.svd The issue is that with no description provided it simply would not put out a description tag, which breaks compatibility with other programs. Insert a somewhat useful default description including a timestamp and the words "LiteX SoC".	2021-04-12 22:08:05 +08:00
bunnie	2bb830bb69	use AutoDoc for timer documentation Not sure why nobody else saw this, but sometime in the last month's patches sphinx started throwing an error when building docs for the timer block. The problem is that the body and title are 'None' and the doc code tries to invoke methods on None. Changing the doc methodology to AutoDoc and explicitly creating the intro section fixes this.	2021-04-12 21:53:05 +08:00
Florent Kermarrec	5011b564c3	integration/soc: Add _ prefix to build_name when build_name starts with digit (Invalid verilog top level name).	2021-04-12 08:32:05 +02:00
Florent Kermarrec	15cf4d75e9	software/liblitesdcard: Add SDCARD_CMD25_SUPPORT #define to allow disabling/enabling Multiple Block Writes and implement Multiple Block Writes.	2021-04-09 19:34:13 +02:00
Florent Kermarrec	5cdf621367	software/liblitesdcard: Add SDCARD_CMD18_SUPPORT #define to allow disabling/enabling Multiple Block Reads. Also use Single Block Read when only 1 block to read, avoid stop transmission.	2021-04-09 19:17:32 +02:00
Florent Kermarrec	9bec0ce7a2	soc/add_ethernet: Add with_timestamp parameter to enable Timestamping and use timer0.uptime_cycles as Timestamp source.	2021-04-08 14:37:48 +02:00
Florent Kermarrec	7caed56790	cores/timer: Expose uptime_cycles and allow multiple calls to add_uptime.	2021-04-08 14:36:10 +02:00
Florent Kermarrec	dbe09341c0	soc/add_pcie: Remove duplicate assert (already checked by check_if_exists).	2021-04-08 12:19:56 +02:00
enjoy-digital	37a81b145a	Merge pull request #875 from rdolbeau/reserve_fb_memory json2dts: add the framebuffer memory in the 'reserved-memory' entry, …	2021-04-07 12:17:00 +02:00
Florent Kermarrec	e5e472d469	soc/software: Remove SoCController dependency for BIOS compilation.	2021-04-07 10:45:43 +02:00
Florent Kermarrec	02328e5236	integration/soc: Add check_bios_requirements method and check for ctrl, timer0, rom and sram presence in the SoC when using the BIOS.	2021-04-07 10:37:48 +02:00
Florent Kermarrec	6940db7730	software/bios: Fix compilation without UART.	2021-04-07 09:03:07 +02:00
Romain Dolbeau	dac6c1cbb1	json2dts: add the framebuffer memory in the 'reserved-memory' entry, so that Linux doesn't try to use it for something else.	2021-04-06 13:44:50 +02:00
enjoy-digital	8db1a619f5	Merge pull request #874 from chmousset/enh/ECP5DifferentialInput [enh] ECP5 DIfferential input support	2021-04-06 12:27:33 +02:00
enjoy-digital	4500641d78	Merge pull request #873 from sthornington/master Fix yosys read command for SystemVerilog sources	2021-04-06 12:08:07 +02:00
Charles-Henri Mousset	51ea0c0427	[enh] ECP5 DIfferential input support	2021-04-05 17:24:51 +02:00
Simon Thornington	4b0a359675	Fix yosys read command for SystemVerilog sources	2021-04-05 10:37:17 -04:00
Romain Dolbeau	3addd587b6	640x480@60Hz (lowest bandwidth option yet)	2021-04-04 17:20:53 +02:00
Florent Kermarrec	080ecad522	cpu/vexriscv_smp: Add specialization of the RAM implementation based on the FPGA family (Platform). RAMXilinx was not infered correctly on Intel/Altera devices, we now have an Intel/Altera specific implementation and could add other specific implementations in the future if required.	2021-03-30 11:10:05 +02:00
Florent Kermarrec	70d11974fc	cores/video/framebuffer: Add support for video clock faster than sys_clk with DRAM's data-width > 32. In this, CDC has to be done first and Data-width conversion is then done in Video clock domain.	2021-03-30 10:14:10 +02:00
Florent Kermarrec	c182f4db5f	cores/video: Add check of Video Timings and list available ones when not supported.	2021-03-30 09:15:17 +02:00
Florent Kermarrec	2ed5f14e9e	integration/soc/soc_core: Remove --min-l2-data-width and --max-sdram-size that don't need to be configurable but can just be enforced in the target file.	2021-03-29 11:26:29 +02:00
Florent Kermarrec	ac7857fa4f	cores/video/add_video_framebuffer: Add workaround when SDRAM data_width < 32.	2021-03-29 11:25:34 +02:00
Florent Kermarrec	4a29e2403c	integration/soc/add_sdram: Directly use main_ram mem_map mapping if available.	2021-03-29 11:22:31 +02:00
Florent Kermarrec	99a26fc710	integration/soc/add_video_framebuffer: Modify default framebuffer base address.	2021-03-29 10:59:32 +02:00
Florent Kermarrec	bf999cfeac	cores/Video: Expose fifo_depth and add underflow signal that can be used investigate bandwidth issues.	2021-03-29 10:58:31 +02:00
enjoy-digital	544c0e2c84	Merge pull request #867 from geertu/json2dts-fixes2 Json2dts fixes2	2021-03-28 18:54:26 +02:00
Geert Uytterhoeven	24ad265a3b	tools/litex_json2dts: Fix i2c node i2c@f0000800: '#address-cells' is a required property From schema: Documentation/devicetree/bindings/i2c/litex,i2c.yaml i2c@f0000800: '#size-cells' is a required property From schema: Documentation/devicetree/bindings/i2c/litex,i2c.yaml Fix this by adding the missing properties. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-03-28 12:44:45 +02:00
Geert Uytterhoeven	e09b2bd1c5	tools/litex_json2dts: Fix gpio node gpio@f0003000: 'gpio-controller' is a required property From schema: Documentation/devicetree/bindings/gpio/litex,gpio.yaml gpio@f0003000: '#gpio-cells' is a required property From schema: Documentation/devicetree/bindings/gpio/litex,gpio.yaml Fix this by adding the missing properties. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-03-28 12:44:45 +02:00
Shawn Hoffman	fc75e57d9a	lattice: use pnmainc on windows	2021-03-27 04:36:02 -07:00
Shawn Hoffman	e56268d419	don't require compiler_rt if not used	2021-03-27 04:18:17 -07:00
Florent Kermarrec	b858dd62e9	liblitesdcard/sdcard: Remove divider workaround (was due to LiteSDCard backpressure issue).	2021-03-26 23:19:08 +01:00
Florent Kermarrec	37704195af	tools/litex_json2dts: Revert previous mac0 formating (thanks geertu).	2021-03-26 23:17:55 +01:00
Florent Kermarrec	9d62cbf56e	integration/soc/SoCCSRHandler: Only keep Auto-Allocation mode.	2021-03-26 23:11:39 +01:00
Florent Kermarrec	24ee6de5c2	cores/video: Make de pin optional on VideoDVIPHY.	2021-03-26 22:53:59 +01:00
Geert Uytterhoeven	a7a70fa2f0	tools/litex_json2dts: Fix mmc node mmc@f0006800:reg:0: [4026558464, 256, 4026560512, 256, 4026562560, 256, 4026564608, 256] is too long From schema: dt-schema/dtschema/schemas/simple-bus.yaml mmc@f0006800:reg:0: [4026558464, 256, 4026560512, 256, 4026562560, 256, 4026564608, 256] is too long From schema: dt-schema/dtschema/schemas/reg.yaml Fix this by grouping the tuples in the "reg" property using angle brackets. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-03-26 17:19:01 +01:00
Geert Uytterhoeven	54d2578f04	tools/litex_json2dts: Fix liteuart node serial@f0001000: 'device_type' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/serial/litex,liteuart.yaml Fix this by dropping the offending property. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-03-26 17:19:01 +01:00
Geert Uytterhoeven	bcef9a68ca	tools/litex_json2dts: Fix plic node interrupt-controller@f0c00000: compatible:0: 'sifive,plic-1.0.0' is not one of ['sifive,fu540-c000-plic', 'canaan,k210-plic'] From schema: Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml interrupt-controller@f0c00000: compatible:1: 'sifive,plic-1.0.0' was expected From schema: Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml interrupt-controller@f0c00000: '#address-cells' is a required property From schema: Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml Fix this by correcting the order of the compatible values, and adding the missing #address-cells property. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-03-26 17:19:01 +01:00
Geert Uytterhoeven	610bfe4d0c	tools/litex_json2dts: Fix DTS indentation - Replace bogus TAB by spaces, - Drop spaces from empty lines. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-03-26 17:19:01 +01:00
Florent Kermarrec	6b482bce54	tools/litex_json2dts/framebuffer: Switch to new simplified Video Framebuffer. Timings are already pre-initialized, so software will only have to configure/modify them to change the video resolution.	2021-03-26 16:25:06 +01:00
Florent Kermarrec	137274dfe0	integration/soc/add_video_framebuffer: Use mem_map for video base address (or defaults to 0x4800000) and pass constants to software.	2021-03-26 16:23:30 +01:00
Florent Kermarrec	ed1d29958a	cores/video/VideoFrameBuffer: Fix colors ordering.	2021-03-26 16:22:12 +01:00
Florent Kermarrec	714903e65b	cores/video/VideoTerminal: Write CSI interpreter color to term_mem (\e[92;1m\e[0m decoding working).	2021-03-26 11:15:27 +01:00
Florent Kermarrec	18f77ef378	cores/video/VideoTerminal: Also do a CLEAR-X after RST-X (Fix issue with lines displayed with previous contents).	2021-03-26 10:35:02 +01:00
Florent Kermarrec	438eec0268	integration/soc/add_sdcard: Re-Remove self.csr.add (was a false alarm, this also works with Linux-on-LiteX-Rocket).	2021-03-26 08:45:32 +01:00
Gabriel Somlo	c859c34844	json2dts.py: fix mac0 reg property style for consistency Assuming "#[address\|size]-cells = <1>", both of the following are equivalent: reg = <start1 size1>, <start2 size2>, ..., <startN sizeN>; reg = <start1 size1 start2 size2 ... startN sizeN>; The second form appears more widely used and popular, including in the output of json2dts.py, with the exception of the mac0 node, which uses the first form. This patch makes output generated for mac0 consistent with that for other DT nodes.	2021-03-25 15:50:12 -04:00
Florent Kermarrec	58701cc48c	tools/litex_client: Use CSR base as base address on PCIe designs.	2021-03-25 18:25:37 +01:00
enjoy-digital	518aaeaacb	Merge pull request #863 from Dolu1990/master cpu/vexriscv_smp add RVC support	2021-03-25 16:26:30 +01:00
Florent Kermarrec	4246f77a97	integration/soc/add_scard: Revert use of self.csr.add since to avoid breaking Linux driver that currently relies on implicit ordering (but probably shoudln't :)).	2021-03-25 14:54:34 +01:00
Dolu1990	e755a02b84	cpu/vexriscv_smp add RVC support	2021-03-25 14:17:19 +01:00
Florent Kermarrec	aad56a047a	integration/soc: Use CSR automatic allocation.	2021-03-25 10:09:54 +01:00
Florent Kermarrec	aa9eb1f6a3	integration/soc: Add CSR automatic allocation and enable it by default. Un-allocated CSRs were already automatically detected so when un-allocated we can just simply allocate them automatically instead of raising an error. This also allows simplifying user's code since self.csr.add/self.add_csr will no longer be required.	2021-03-25 09:49:59 +01:00
Florent Kermarrec	3def6ae985	integration/soc: Be sure all add_xy methods use check_if_exists, improve Video integration.	2021-03-25 09:29:33 +01:00
Florent Kermarrec	c9ac5424f4	integration/soc: Cosmetic cleanup pass.	2021-03-25 09:13:43 +01:00
Florent Kermarrec	6e23fb1d99	integration/soc: Move Identifier import to add_identifier.	2021-03-25 08:47:05 +01:00
Florent Kermarrec	e1b20a934a	integation/soc: Move VideoXY imports to add_video_xy.	2021-03-25 08:45:55 +01:00
Florent Kermarrec	1b9eefbee4	integration/soc: Move Timer import to add_timer.	2021-03-25 08:43:52 +01:00
Florent Kermarrec	01fdca9149	integration/soc: Move SPIMaster import to add_spi_sdcard.	2021-03-25 08:42:23 +01:00
Florent Kermarrec	5229727c2b	integration/soc: Move SpiFlash import to add_spi_flash.	2021-03-25 08:40:53 +01:00
Florent Kermarrec	c60938d7aa	integration/soc/ethernet: Simplify timing constraints.	2021-03-25 08:36:37 +01:00
Florent Kermarrec	e27330b0d9	integration/soc: Replace self.add_csr with self.csr.add.	2021-03-25 08:23:39 +01:00
Florent Kermarrec	36bb069b8b	interconnect/packet: Minor cleanup.	2021-03-24 18:04:20 +01:00
Florent Kermarrec	6c640b0693	compat/stream_sim: Remove TODO since will not be done.	2021-03-24 17:58:13 +01:00
Florent Kermarrec	9eb318e86a	soc/interconnect/stream_sim: Move to compat to prevent since no longer really used or recommended on new designs.	2021-03-24 17:56:21 +01:00
Florent Kermarrec	bc8974dad1	litex_sim: Switch to soc_core_args/soc_core_argdict.	2021-03-24 17:26:48 +01:00
Florent Kermarrec	ee36138f75	compat: Fix (only triggers notice when used) and enable SoCSDRAM compat.	2021-03-24 17:21:26 +01:00
Florent Kermarrec	50ed5e262d	integration/soc_core: Move L2/SDRAM arguments soc_core_args.	2021-03-24 17:21:22 +01:00
Florent Kermarrec	ad63f8edc8	compat: Add Retro-Compat for litex.soc.cores.up5kspram (that has now moved to litex.soc.cores.ram).	2021-03-24 17:21:18 +01:00
Florent Kermarrec	f7f277548e	Compat: Add litex.compat to handle retro-compatibility on API changes and move integration/soc_sdram to it. Compat Notice is not yet enabled for soc_sdram since targets first need to be updated.	2021-03-24 17:21:13 +01:00
enjoy-digital	cc02055b42	Merge pull request #859 from Dolu1990/master soc/cores/cpu/vexriscv_smp cpu per fpu ratio	2021-03-24 08:03:38 +01:00
Dolu1990	391a4429dc	soc/cores/cpu/vexriscv_smp add cpu_per_fpu option to change the ratio core count and FPU	2021-03-23 20:05:28 +01:00
Jędrzej Boczar	bea82efc5d	gtkwave: fix error when prefix is empty, make treeopen optional	2021-03-23 10:08:06 +01:00
Florent Kermarrec	9113c1a2f9	cores/gpio/GPIOIRQ: Add mode CSR (Edge or Change) and rename polarity CSR to edge. Allow interrupts on Change, Rising Edge or Falling Edge.	2021-03-20 21:49:12 +01:00
enjoy-digital	c2f65b2b04	Merge pull request #850 from Dolu1990/master cpu/vexriscv_smp add FPU support	2021-03-19 09:08:44 +01:00
enjoy-digital	db353526c1	Merge pull request #853 from mczerski/liteeth_slots liteeth: allow to specify nrxslots and ntxslots for liteeth	2021-03-19 08:58:44 +01:00
Florent Kermarrec	d0c4199096	cores/gpio: Fix GPIOIRQ. Compilation tested in Arty with: from litex.soc.cores.gpio import GPIOIn self.submodules.gpio_in = GPIOIn(platform.request("user_sw", 0), with_irq=True) self.add_csr("gpio_in") self.add_interrupt("gpio_in")	2021-03-18 19:05:12 +01:00
enjoy-digital	1bb4507d93	Merge pull request #846 from enjoy-digital/axi-lite-downconverter-fix interconnect/axi: Fix AXILiteDownverterWrite/Read base address.	2021-03-18 18:15:52 +01:00
Florent Kermarrec	8460523f27	cores/video: Add VideoECP5HDMI PHY and move 10to1 Serializer to Generic, share it for Spartan6/ECP5.	2021-03-18 14:43:21 +01:00
Florent Kermarrec	e5695f9934	cores/video: Add VideoS6HDMIPHY (using stream.Gearbox for 10:2 convertion).	2021-03-18 13:49:50 +01:00
Florent Kermarrec	c01284fa23	integration/soc/add_video_colorbars: Review/Fix #849 (Fix ColorBarsPattern clock domain).	2021-03-18 13:48:53 +01:00
Florent Kermarrec	675349055b	inteconnect/stream: Increase io_lcm size when io_lcm/i_dw or io_lcm/o_dw < 2. Allow supporting all cases.	2021-03-18 13:47:10 +01:00
Marek Czerski	d7c0b4c111	dts: gpio: interrupt controller definition for switches This commit adds support for enabling interupts in switches module. Declaring switches as GPIOIn module with with_irq=True will make dts generation add correct interrupt controller definition. Also, if SWITCHES_NGPIO constant is defined it will be used to specify correct number of gpios in dts. example: self.submodules.switches = GPIOIn(pads=switches_pads, with_irq=True) self.add_csr("switches") self.irq.add("switches", use_loc_if_exists=True) self.add_constant("SWITCHES_NGPIO", len(switches_pads))	2021-03-18 09:52:07 +01:00
Marek Czerski	6eaa426e37	liteeth: allow to specify nrxslots and ntxslots for liteeth	2021-03-18 09:24:48 +01:00
Dolu1990	6b387eb579	cpu/vexriscv_smp add FPU support	2021-03-17 13:20:45 +01:00
enjoy-digital	a166a8dba3	Merge pull request #849 from hansfbaier/add-video-colorbars video: convenience method to add color bar pattern	2021-03-16 12:51:27 +01:00
Florent Kermarrec	c071bb4ac7	software/liblitesdcard: Check sdcard_wait_data_done in sdcard_switch/sdcard_app_send_scr since requesting a data read transfer.	2021-03-16 12:44:00 +01:00
Hans Baier	f86c743c58	video: convenience method to add color bar pattern	2021-03-16 12:35:58 +07:00
Florent Kermarrec	04cb8e0e5e	cores/xadc: Review/Cleanup PR#838, rename _XADC to SystemMonitorDRP and USSYSMON to USSystemMonitor.	2021-03-15 10:35:10 +01:00
enjoy-digital	367b510590	Merge pull request #838 from jersey99/ussysmon Ussysmon: SYSMONE1 for US devices	2021-03-15 10:19:54 +01:00
Florent Kermarrec	13e13a094c	soc/interconnect/axi: Add AXILite Clock Domain Crossing module.	2021-03-15 10:18:12 +01:00
Benjamin Henrion	0456de50aa	Add support for xcompiler on Alpine 3.13 Problem: xcompiler on Alpine 3.13 was not found Solution is to add "riscv-none-elf-gcc": 1. Add Edge to your repositories: $ echo -e "http://dl-cdn.alpinelinux.org/alpine/edge/main\nhttp://dl-cdn.alpinelinux.org/alpine/edge/testing\nhttp://dl-cdn.alpine linux.org/alpine/edge/community" >> /etc/apk/repositories $ apk update $ apk add gcc-riscv-none-elf 2. The xcompiler should be found at: $ which riscv-none-elf-gcc /usr/bin/riscv-none-elf-gcc	2021-03-12 20:13:23 +01:00
Florent Kermarrec	1e9606f3fb	software/liblitedram: Improve find_cmd_delay to favor higher number of valid modules and centered scan. Also add an optional debug #define to look at cmd/clk centering scans: __ _ __ _ __ / / (_) /____ \| \|/_/ / /__/ / __/ -_)> < /____/_/\__/\__/_/\|_\| Build your hardware, easily! (c) Copyright 2012-2020 Enjoy-Digital (c) Copyright 2007-2015 M-Labs BIOS built on Mar 12 2021 14:06:20 BIOS CRC passed (116682af) Migen git sha1: 7014bdc LiteX git sha1: edcc0f88 --=============== SoC ==================-- CPU: VexRiscv @ 125MHz BUS: WISHBONE 32-bit @ 4GiB CSR: 32-bit data ROM: 64KiB SRAM: 8KiB L2: 8KiB SDRAM: 1048576KiB 64-bit @ 1000MT/s (CL-7 CWL-6) --========== Initialization ============-- Initializing SDRAM @0x40000000... Switching SDRAM to software control. Write leveling: tCK/4 taps: 6 Cmd/Clk scan (0-12) \|Cmd/Clk delay: 0 m0: \|11000000000000011111111111\| delay: 15 m1: \|00000000000000111111111111\| delay: 14 m2: \|11110000000000000111111111\| delay: 17 m3: \|11110000000000000011111111\| delay: 18 m4: \|11111111110000000000000111\| delay: - m5: \|11111111110000000000000111\| delay: - m6: \|11111111111000000000000001\| delay: - m7: \|11111111111000000000000011\| delay: - Delay mean: 22, ideal: 13 Cmd/Clk delay: 1 m0: \|11100000000000001111111111\| delay: 16 m1: \|10000000000000011111111111\| delay: 15 m2: \|11111000000000000011111111\| delay: 18 m3: \|11111000000000000001111111\| delay: 19 m4: \|11111111111000000000000011\| delay: - m5: \|11111111111000000000000011\| delay: - m6: \|11111111111100000000000000\| delay: - m7: \|11111111111100000000000001\| delay: - Delay mean: 23, ideal: 13 Cmd/Clk delay: 2 m0: \|11110000000000000111111111\| delay: 17 m1: \|11000000000000001111111111\| delay: 16 m2: \|11111100000000000001111111\| delay: - m3: \|11111100000000000000111111\| delay: - m4: \|11111111111100000000000001\| delay: - m5: \|11111111111100000000000001\| delay: - m6: \|11111111111110000000000000\| delay: - m7: \|11111111111110000000000000\| delay: - Delay mean: 22, ideal: 13 Cmd/Clk delay: 3 m0: \|11111000000000000011111111\| delay: 18 m1: \|11100000000000000111111111\| delay: 17 m2: \|11111110000000000000111111\| delay: - m3: \|11111110000000000000011111\| delay: - m4: \|11111111111110000000000000\| delay: - m5: \|11111111111110000000000000\| delay: - m6: \|01111111111111000000000000\| delay: 01 m7: \|01111111111111000000000000\| delay: 01 Delay mean: 15, ideal: 13 Cmd/Clk delay: 4 m0: \|11111100000000000001111111\| delay: - m1: \|11110000000000000011111111\| delay: 18 m2: \|11111111000000000000011111\| delay: - m3: \|11111111000000000000001111\| delay: - m4: \|11111111111111000000000000\| delay: - m5: \|11111111111111000000000000\| delay: - m6: \|00111111111111100000000000\| delay: 02 m7: \|00111111111111100000000000\| delay: 02 Delay mean: 13, ideal: 13 Cmd/Clk delay: 5 m0: \|11111110000000000000111111\| delay: - m1: \|11111000000000000001111111\| delay: 19 m2: \|11111111100000000000001111\| delay: - m3: \|11111111100000000000000111\| delay: - m4: \|01111111111111100000000000\| delay: 01 m5: \|01111111111111100000000000\| delay: 01 m6: \|00011111111111110000000000\| delay: 03 m7: \|00011111111111110000000000\| delay: 03 Delay mean: 11, ideal: 13 Cmd/Clk delay: 6 m0: \|11111111000000000000011111\| delay: - m1: \|11111100000000000000111111\| delay: - m2: \|11111111110000000000000111\| delay: - m3: \|11111111110000000000000011\| delay: - m4: \|00111111111111110000000000\| delay: 02 m5: \|00011111111111110000000000\| delay: 03 m6: \|00001111111111111000000000\| delay: 04 m7: \|00001111111111111000000000\| delay: 04 Delay mean: 9, ideal: 13 Cmd/Clk delay: 7 m0: \|11111111100000000000001111\| delay: - m1: \|11111110000000000000011111\| delay: - m2: \|11111111111000000000000011\| delay: - m3: \|11111111111000000000000001\| delay: - m4: \|00011111111111111000000000\| delay: 03 m5: \|00001111111111111000000000\| delay: 04 m6: \|00000111111111111100000000\| delay: 05 m7: \|00000111111111111100000000\| delay: 05 Delay mean: 10, ideal: 13 Cmd/Clk delay: 8 m0: \|11111111110000000000000111\| delay: - m1: \|11111111000000000000001111\| delay: - m2: \|11111111111100000000000001\| delay: - m3: \|11111111111100000000000000\| delay: - m4: \|00001111111111111100000000\| delay: 04 m5: \|00000111111111111100000000\| delay: 05 m6: \|00000011111111111110000000\| delay: 06 m7: \|00000011111111111110000000\| delay: 06 Delay mean: 11, ideal: 13 Cmd/Clk delay: 9 m0: \|11111111111000000000000011\| delay: - m1: \|11111111100000000000000111\| delay: - m2: \|11111111111110000000000000\| delay: - m3: \|11111111111110000000000000\| delay: - m4: \|00000111111111111110000000\| delay: 05 m5: \|00000011111111111110000000\| delay: 06 m6: \|00000001111111111111000000\| delay: 07 m7: \|00000001111111111111000000\| delay: 07 Delay mean: 12, ideal: 13 Cmd/Clk delay: 10 m0: \|11111111111100000000000011\| delay: - m1: \|11111111110000000000000011\| delay: - m2: \|01111111111111000000000000\| delay: 01 m3: \|01111111111111000000000000\| delay: 01 m4: \|00000011111111111111000000\| delay: 06 m5: \|00000001111111111111000000\| delay: 07 m6: \|00000000111111111111100000\| delay: 08 m7: \|00000000111111111111100000\| delay: 08 Delay mean: 11, ideal: 13 Cmd/Clk delay: 11 m0: \|11111111111110000000000001\| delay: - m1: \|11111111111000000000000001\| delay: - m2: \|00111111111111100000000000\| delay: 02 m3: \|00111111111111100000000000\| delay: 02 m4: \|00000001111111111111100000\| delay: 07 m5: \|00000000111111111111100000\| delay: 08 m6: \|00000000011111111111110000\| delay: 09 m7: \|00000000011111111111110000\| delay: 09 Delay mean: 12, ideal: 13 \| best: 11 Setting Cmd/Clk delay to 11 taps. Data scan: m0: \|11111111111110000000000001\| delay: - m1: \|11111111111000000000000001\| delay: - m2: \|00111111111111100000000000\| delay: 02 m3: \|00111111111111100000000000\| delay: 02 m4: \|00000001111111111111100000\| delay: 07 m5: \|00000000111111111111100000\| delay: 08 m6: \|00000000011111111111110000\| delay: 09 m7: \|00000000011111111111110000\| delay: 09 Write latency calibration: m0:6 m1:6 m2:6 m3:6 m4:6 m5:6 m6:6 m7:6 Read leveling: m0, b0: \|00000000000000000000000000000000\| delays: - m0, b1: \|00000000000000000000000000000000\| delays: - m0, b2: \|00000000000000000000000000000000\| delays: - m0, b3: \|11111111100000000000000000000000\| delays: 04+-04 m0, b4: \|00000000000001111111110000000000\| delays: 17+-04 m0, b5: \|00000000000000000000000000111111\| delays: 29+-03 m0, b6: \|00000000000000000000000000000000\| delays: - m0, b7: \|00000000000000000000000000000000\| delays: - best: m0, b03 delays: 04+-04 m1, b0: \|00000000000000000000000000000000\| delays: - m1, b1: \|00000000000000000000000000000000\| delays: - m1, b2: \|00000000000000000000000000000000\| delays: - m1, b3: \|11111111000000000000000000000000\| delays: 04+-04 m1, b4: \|00000000000011111111100000000000\| delays: 16+-04 m1, b5: \|00000000000000000000000000111111\| delays: 29+-03 m1, b6: \|00000000000000000000000000000000\| delays: - m1, b7: \|00000000000000000000000000000000\| delays: - best: m1, b04 delays: 16+-04 m2, b0: \|00000000000000000000000000000000\| delays: - m2, b1: \|00000000000000000000000000000000\| delays: - m2, b2: \|00000000000000000000000000000000\| delays: - m2, b3: \|11111110000000000000000000000000\| delays: 03+-03 m2, b4: \|00000000000111111111000000000000\| delays: 15+-04 m2, b5: \|00000000000000000000000011111111\| delays: 28+-04 m2, b6: \|00000000000000000000000000000000\| delays: - m2, b7: \|00000000000000000000000000000000\| delays: - best: m2, b04 delays: 15+-04 m3, b0: \|00000000000000000000000000000000\| delays: - m3, b1: \|00000000000000000000000000000000\| delays: - m3, b2: \|00000000000000000000000000000000\| delays: - m3, b3: \|11111110000000000000000000000000\| delays: 03+-03 m3, b4: \|00000000001111111110000000000000\| delays: 14+-04 m3, b5: \|00000000000000000000000011111111\| delays: 28+-04 m3, b6: \|00000000000000000000000000000000\| delays: - m3, b7: \|00000000000000000000000000000000\| delays: - best: m3, b04 delays: 14+-04 m4, b0: \|00000000000000000000000000000000\| delays: - m4, b1: \|00000000000000000000000000000000\| delays: - m4, b2: \|00000000000000000000000000000000\| delays: - m4, b3: \|10000000000000000000000000000000\| delays: - m4, b4: \|00001111111110000000000000000000\| delays: 08+-04 m4, b5: \|00000000000000000111111111000000\| delays: 22+-05 m4, b6: \|00000000000000000000000000000001\| delays: 31+-00 m4, b7: \|00000000000000000000000000000000\| delays: - best: m4, b04 delays: 08+-04 m5, b0: \|00000000000000000000000000000000\| delays: - m5, b1: \|00000000000000000000000000000000\| delays: - m5, b2: \|00000000000000000000000000000000\| delays: - m5, b3: \|00000000000000000000000000000000\| delays: - m5, b4: \|00001111111110000000000000000000\| delays: 08+-04 m5, b5: \|00000000000000000011111111000000\| delays: 22+-04 m5, b6: \|00000000000000000000000000000001\| delays: 31+-00 m5, b7: \|00000000000000000000000000000000\| delays: - best: m5, b04 delays: 08+-04 m6, b0: \|00000000000000000000000000000000\| delays: - m6, b1: \|00000000000000000000000000000000\| delays: - m6, b2: \|00000000000000000000000000000000\| delays: - m6, b3: \|00000000000000000000000000000000\| delays: - m6, b4: \|00111111110000000000000000000000\| delays: 06+-04 m6, b5: \|00000000000000111111111000000000\| delays: 18+-04 m6, b6: \|00000000000000000000000000001111\| delays: 30+-02 m6, b7: \|00000000000000000000000000000000\| delays: - best: m6, b05 delays: 19+-04 m7, b0: \|00000000000000000000000000000000\| delays: - m7, b1: \|00000000000000000000000000000000\| delays: - m7, b2: \|00000000000000000000000000000000\| delays: - m7, b3: \|00000000000000000000000000000000\| delays: - m7, b4: \|01111111111100000000000000000000\| delays: 06+-05 m7, b5: \|00000000000000011111111110000000\| delays: 20+-05 m7, b6: \|00000000000000000000000000001111\| delays: 30+-02 m7, b7: \|00000000000000000000000000000000\| delays: - best: m7, b04 delays: 06+-05 Switching SDRAM to hardware control. Memtest at 0x40000000 (2MiB)... Write: 0x40000000-0x40200000 2MiB Read: 0x40000000-0x40200000 2MiB Memtest OK Memspeed at 0x40000000 (2MiB)... Write speed: 40MiB/s Read speed: 33MiB/s --============== Boot ==================-- Booting from serial... Press Q or ESC to abort boot completely. sL5DdSMmkekro Timeout No boot medium found --============= Console ================--	2021-03-12 14:34:49 +01:00
Florent Kermarrec	3cbdc567ff	soc: Add init_rom to initialize ROM and contents and with auto_size option (enable by default) to reduce ROM size to length of contents when in Read Only mode. This ensures the integrated ROM is reduced to minimal size before build and avoid having to adjust it manually with --integrated-rom-size on targets.	2021-03-12 09:42:59 +01:00
Florent Kermarrec	d9b6d7608c	soc/integration/soc_core: Cleanup SoCCore arguments.	2021-03-12 09:03:17 +01:00
Florent Kermarrec	21273ffe87	soc/integration/builder: Cleanup and add comments.	2021-03-11 16:21:45 +01:00
enjoy-digital	cba4642444	Merge pull request #845 from meklort/meklort/xics-fix xics: Disable endianness swapping	2021-03-11 13:33:15 +01:00
Florent Kermarrec	a81d1da980	soc/integration/common: Improve get_mem_data error reporting.	2021-03-11 10:19:36 +01:00
Florent Kermarrec	26f55797cc	software/liblitedram: Make sure init_error is set before init_done. Useful for standalone core where the user logic can be looking at init_done/init_error to condition user accesses.	2021-03-10 19:41:02 +01:00
Florent Kermarrec	da1277021a	build/generic_platform: Minor cosmetic cleanups.	2021-03-10 19:21:02 +01:00
Florent Kermarrec	10eff37b84	interconnect/axi: Fix AXILiteDownverterWrite/Read base address. Downconverter should start on master's addr, not on aligned master's addr.	2021-03-10 18:54:02 +01:00
Evan Lojewski	08072eb872	xics: Disable endianness swapping The endianess swapping code caused the core to diverge from microwatt resulting in: - The xics tests not working as-is: https://github.com/antonblanchard/microwatt/blob/master/tests/xics/xics.h - byte writes writing to the incorrect byte This removes endianswapping and minimizes the delta from upstream for the xics irq.h header.	2021-03-10 07:39:19 -07:00
Evan Lojewski	c92e4cb3ca	xics: Ass missing static keywords to irq header.	2021-03-10 07:32:24 -07:00
Florent Kermarrec	9d08c65e8a	build/generic_platform: Make sure default_clk_period constraint is only applied when default_clk_period exists. In simulation, default_clk_period is not necessarily required.	2021-03-10 12:25:35 +01:00
enjoy-digital	ee2d373477	Merge pull request #843 from gregdavill/monitor_token_fix cores/stream/monitor: Fix typo	2021-03-10 11:00:55 +01:00
Florent Kermarrec	e48b269d77	build/generic_platform: Fix use_default_clk set when not user provided sys_clk. Prevented the default timing constraint to be generated in the timing constraint file.	2021-03-10 10:47:22 +01:00
Greg Davill	31cc7f1e42	cores/stream/monitor: Fix typo	2021-03-10 09:11:07 +10:30
Florent Kermarrec	0e7d8219ea	soc/cores/gpio: Simplify GPIOIn IRQ, make polarity configurable and also add optional IRQ to GPIOTristate. Ex of instance: from litex.soc.cores import gpio gpio_in_pads = Signal(16) self.submodules.gpio_in = gpio.GPIOIn(gpio_in_pads, with_irq=True) self.add_csr("gpio_in")	2021-03-09 13:57:48 +01:00
Florent Kermarrec	0d8b6f8fbb	csr_eventmanager/EventSourceProcess: Add Rising Edge support and Falling/Rising selection.	2021-03-09 13:55:43 +01:00
Florent Kermarrec	ece9005949	cpu/vexriscv/core: Rename timer_enabled parameter to with_timer (for consistency with codebase) and disable timer by default (since increasing resources and causing issue on some iCE40 designs).	2021-03-09 09:07:52 +01:00
gatecat	c64e2d3a85	build/radiant: Skip location constraint for X pins Signed-off-by: gatecat <gatecat@ds0.me>	2021-03-08 14:27:32 +00:00
Florent Kermarrec	5af8e5c934	soc/add_etherbone: Fix UDPIPCore clock domain (should still run at eth_clk even if Etherbone is running in sys_clk) since data-width convertion is done on UDP.	2021-03-08 13:50:22 +01:00
Vamsi Vytla	6bb0541f9a	Remove ussysmon.py as it is consolidated inside xadc.py	2021-03-06 14:31:24 -08:00
Florent Kermarrec	a1e54671be	sim/serial2console: Remove \r workaround since no longer required and generating double carrier return in simulation.	2021-03-06 17:36:21 +01:00
Florent Kermarrec	7e3912aaef	software/demo: Make hellocpp optional (only build with --with-cxx) to avoid adding g++ as a dependency for an optional feature.	2021-03-06 17:31:07 +01:00
Vamsi Vytla	647d3eb51a	soc/cores/xadc.py: Move ussysmon here	2021-03-06 08:14:13 -08:00
Florent Kermarrec	31ac6659c9	cores/video: Add VideoS7HDMIPHY for Xilinx 7-Series.	2021-03-05 14:30:28 +01:00
Florent Kermarrec	9624cce188	cores/video: Mode VideoVGAPHY/VideoDVIPHY and add separators.	2021-03-05 14:27:08 +01:00
Florent Kermarrec	0280a9dd57	soc/add_video_framebuffer: Pass clock_domain to VideoFrameBuffer.	2021-03-05 14:23:39 +01:00
Florent Kermarrec	8b531b4215	cores: Add code_tmds with TMDS Encoder from Mixxeo/LiteVideo.	2021-03-04 19:32:41 +01:00
Florent Kermarrec	10d87e4138	cores/video/VideoPHYs: Use IO primitives.	2021-03-04 18:22:34 +01:00
Florent Kermarrec	82d0ecd7bd	cores/video/VideoTerminal: Add CLEAR-XY after reset.	2021-03-04 17:55:37 +01:00
Florent Kermarrec	a1e7aab35c	cores/clock/xilinx_usp/USPIDELAYCTRL: Apply USIDELAYCTRL's changes.	2021-03-04 14:42:50 +01:00
Florent Kermarrec	60e2d3335f	cores/clock/xilinx_us: Remove USP modules (refactoring issue).	2021-03-04 14:42:03 +01:00
Florent Kermarrec	2d5b4b206b	bios: Add VideoFrameBuffer VTG/DMA initialisation. This just configures the enables for now since other parameters are pre-configured during the build.	2021-03-04 12:01:32 +01:00
Florent Kermarrec	f553b5fc83	soc/cores/video: Improve/Cleanup VideoFrameBuffer, disable by default and modify default hres/vres to 800/600.	2021-03-04 11:59:44 +01:00
Florent Kermarrec	0ee92448b9	soc/cores/dma: Add default parameters to add_csr (similar to LiteDRAMDMAs), minor cosmetic cleanups and also add offset CSRStatus on WishboneDMAWriter (for symetry with WishboneDMAReader). Defaults parameters can allow the FPGA gateware to behave by itself after initialization while still being configurable by software.	2021-03-04 11:53:43 +01:00
Florent Kermarrec	225a518f7e	soc/cores/video: Move LiteDRAMDMAReader import to VideoFramerBuffer to avoid LiteDRAM dependency.	2021-03-04 08:40:47 +01:00
Vamsi Vytla	ae5f67f6f0	litex/soc/cores/ussysmon.py: minor bug	2021-03-03 14:47:52 -08:00
Vamsi Vytla	1793efb50b	litex/soc/cores/ussysmon.py: dadr address space bump	2021-03-03 14:38:27 -08:00
Florent Kermarrec	ccc8916995	soc/cores/video: Add initial (and simple) VideoFrameBuffer core.	2021-03-03 19:58:11 +01:00
Vamsi Vytla	922f85e64b	litex/soc/cores/ussysmon.py: ADC transfer function	2021-03-03 10:50:58 -08:00
Florent Kermarrec	24fb153fa1	soc/integration: Add add_video_terminal method to LiteXSoC. Adds the new LiteX's VideoTerminal core to the SoC: self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga") self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")	2021-03-03 17:45:02 +01:00
Florent Kermarrec	35ffba8801	soc/cores: Add simple VideoOut core with VideoTimingGenerator, Video Patterns, VideoTerminal, VideoDVIPHY and VideoVGAPHY.	2021-03-03 16:17:12 +01:00
Florent Kermarrec	c5ee6741a0	software/liblitedram: Use new DQS delay reset procedure on Ultrascale(+) (by increments).	2021-03-03 11:32:43 +01:00
Florent Kermarrec	d3407c67b1	build/sim/core: Cast main_time to vluint64_t to avoid ambiguity error of the dump function to be used.	2021-03-03 09:25:54 +01:00
Florent Kermarrec	134c628357	cores/spi_flash: Minor cosmetic cleanups, SpiFlashQuadReadWrite has also been moved to the end with a Note since should probably be re-factored.	2021-03-03 09:15:51 +01:00
Florent Kermarrec	61dcd1e8fd	soc/cores/led: Minor cosmetic cleanups.	2021-03-03 09:02:41 +01:00
Florent Kermarrec	19b1e50cbd	soc/cores/icap: Minor cosmetic cleanups.	2021-03-03 09:01:41 +01:00
Florent Kermarrec	e6f1d677e7	soc/cores/freqmeter: Minor cosmetic cleanups.	2021-03-03 08:59:51 +01:00
Florent Kermarrec	ce5e3e3b93	soc/cores/ecc: Minor cosmetic cleanups.	2021-03-03 08:55:37 +01:00
Florent Kermarrec	2fd7451fc9	soc/cores/code_8b10b: Minor cosmetic cleanups.	2021-03-03 08:54:31 +01:00
Florent Kermarrec	2e531e0ec7	soc/cores/dna: Add separator/comment.	2021-03-03 08:49:47 +01:00
Vamsi Vytla	71f7ce6a57	soc/cores/ussysmon.py: Xilinx XADC like thingy for UltraScale devices	2021-03-02 20:31:52 -08:00
Sergiu Mosanu	7fd39235af	Merge pull request #1 from hplp/cppdemo demo with basic C and C++ examples	2021-03-02 01:31:46 -05:00
Sergiu Mosanu	769f36d468	extend demo with basic C and C++ examples	2021-03-02 01:28:21 -05:00
David Jablonski	ceb8a6502c	VexRiscv: More general mem_map	2021-02-25 10:36:43 +01:00
Florent Kermarrec	6e883b4513	tools/litex_sim: Add boot to main_ram when sdram_init contents provided.	2021-02-25 09:10:26 +01:00
Florent Kermarrec	8f5d2ba27f	tools/litex_sim: Disable SDRAM memtest when sdram_init contents provided. This avoid corrupting pre-initialized contents or disabling memtest manually.	2021-02-25 09:06:26 +01:00
Florent Kermarrec	80bd4ac4ec	bios: Add boot command to be able to boot directly from system memory. This is useful for un-usual boot sequences where the binaries are not loaded directly by the BIOS but externally (over a bridge for example). Example of use: $litex_sim $litex_bare_metal_demo --build-path=build/sim $litex_sim --ram-init=demo.bin Press Esc during the LiteX boot. litex> help LiteX BIOS, available commands: flush_cpu_dcache - Flush CPU data cache crc - Compute CRC32 of a part of the address space ident - Identifier of the system help - Print this help serialboot - Boot from Serial (SFL) romboot - Boot from ROM reboot - Reboot boot - Boot from Memory mem_speed - Test memory speed mem_test - Test memory access mem_copy - Copy address space mem_write - Write address space mem_read - Read address space mem_list - List available memory regions litex> litex> mem_list Available memory regions: ROM 0x00000000 0x8000 SRAM 0x01000000 0x2000 MAIN_RAM 0x40000000 0x10000000 CSR 0x82000000 0x10000 litex> litex> boot 0x40000000 Executing booted program at 0x40000000 --============= Liftoff! ===============-- LiteX minimal demo app built Feb 24 2021 11:30:05 Available commands: help - Show this command reboot - Reboot CPU donut - Spinning Donut demo litex-demo-app>	2021-02-24 11:41:01 +01:00
enjoy-digital	c18ea700cc	Merge pull request #822 from antmicro/bios-dynamic-ip software/bios: add an option to change ip and mac address in runtime	2021-02-24 09:27:48 +01:00
Aleksandra Swierkowska	7abd66d710	bios/boot: add functions changing local and remote IP in runtime	2021-02-23 20:52:53 +01:00
Aleksandra Swierkowska	1c8df130b4	integration/soc.py: add parameter dynamic_ip to add_ethernet	2021-02-23 20:52:53 +01:00
Aleksandra Swierkowska	fc6b02d0da	libliteeth/udp: add udp_set_ip and udp_set_mac functions	2021-02-23 20:52:43 +01:00
Florent Kermarrec	91cebb5159	cpu/microwatt: Set XICS_ICS's SRC_NUM to 16. Expected to be 16 in xics.vhdl: assert SRC_NUM = 16 report "Fixup address decode with log2";	2021-02-22 10:57:31 +01:00
Florent Kermarrec	a51bf60712	cpu/microwatt: Only add XICS for IRQ variants (fix standard variant).	2021-02-22 10:31:08 +01:00
enjoy-digital	d5c2f6760c	Merge pull request #824 from scanakci/blackparrot_litex Update BlackParrot Readme	2021-02-22 10:23:25 +01:00
sadullah	96d9971abe	Update BlackParrot Readme	2021-02-20 22:58:34 -05:00
Robert Wilbrandt	251cea5647	Add constants to SVD export	2021-02-20 21:16:45 +01:00
Florent Kermarrec	7513460572	integration/soc/add_pcie: add with_msi parameter to allow disabling MSI when not required. When just doing a PCIe to Wishbone Bridge (PCIeBone), DMAs and MSI are not required, with_msi will allow disabling MSI when set to False.	2021-02-19 11:35:49 +01:00
Florent Kermarrec	d4edc132c1	tools/remote/comm_pcie: fix typo.	2021-02-19 10:33:04 +01:00
Florent Kermarrec	b47160c74e	tools/litex_term: replace CrossoverUART with BridgeUART for more genericity, rework bridge/jtag args. The CrossoverUART was in fact a particular UART connected to a second UART. Being able to have access to multiple UARTs over a Bridge can be useful for several purposes, ex: SoC0 --> UART0 + JTAGBone + litex_term bridge --bridge-name=UART0 SoC1 --> UART1 +--> SoC --> UARTBone --> LiteX-Server + litex_term bridge --bridge-name=UART1 SoC2 --> UART2 + EtherBone + litex_term bridge --bridge-name=UART2	2021-02-18 18:02:05 +01:00
Florent Kermarrec	6ac410a462	cores/uart/UARTCrossover: increase rx_fifo_depth to allow speeding up litex_term.	2021-02-18 17:55:53 +01:00
Florent Kermarrec	fc83a9281a	interconnect/csr: remove address wrapping within a CSRBank. To minimize logic, decoding inside a CSRBank to limited to the CSRs inside the bank and could wraps since partially decoded: For example, accessing SoCController on addresses still on the CSRBank defined for real CSRs produced: litex> mem_read 0x82000000 128 Memory dump: 0x82000000 00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00 ....xV4......... 0x82000010 00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00 ....xV4......... 0x82000020 00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00 ....xV4......... 0x82000030 00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00 ....xV4......... 0x82000040 00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00 ....xV4......... 0x82000050 00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00 ....xV4......... 0x82000060 00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00 ....xV4......... 0x82000070 00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00 ....xV4......... This is generally not an issue on most of the systems, but it could confuse user or produce un-wanted behaviour when bus data-width converter are used. With this change, the address is fully decoded, which removes the address wrapping: litex> mem_read 0x82000000 128 Memory dump: 0x82000000 00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00 ....xV4......... 0x82000010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 0x82000020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 0x82000030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 0x82000040 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 0x82000050 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 0x82000060 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 0x82000070 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ Resource usage increase seems minimal.	2021-02-18 14:44:50 +01:00
Florent Kermarrec	12bdf43958	soc/cores/ecc: cosmetic cleanups.	2021-02-18 10:00:27 +01:00
Florent Kermarrec	7ce5aef428	soc/cores/led: add add_pwm method to allow adjusting brightness dynamically (or not). LedChaser without PWM: self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) self.add_csr("leds") Add PWM to it (with default values: 50% duty cycle): self.leds.add_pwm() Add PWM with custom default values (25% duty cycle here): self.leds.add_pwm(default_width=128, default_period=1024) Then adjust brightness dynamically from the BIOS or your software: $cat csr.csv: csr_register,leds_out,0x82003000,1,rw csr_register,leds_pwm_enable,0x82003004,1,rw csr_register,leds_pwm_width,0x82003008,1,rw csr_register,leds_pwm_period,0x8200300c,1,rw Set PWM to 0%: $mem_write 0x82003008 0 Set PWM to 25%: $mem_write 0x82003008 256 Set PWM to 50%: $mem_write 0x82003008 512 Set PWM to 75%: $mem_write 0x82003008 768 Set PWM to 100%: $mem_write 0x82003008 1024 You can also only use default values and disable CSR is dynamic configuration is not required (with_csr=False) or adjust PWM period if want to use a specific PWM period in your system.	2021-02-18 09:47:30 +01:00
Florent Kermarrec	fc282b3084	soc/cores/pwm: add configurable default enable/width/period values.	2021-02-18 09:39:18 +01:00
Florent Kermarrec	908e72e65b	cores/uart: rewrite RS232PHYTX/RX (with FSM and comments) and optimize resource usage (~100LCs).	2021-02-17 15:04:14 +01:00
enjoy-digital	7c7f540488	Merge pull request #821 from jersey99/master build/xilinx/vivado.py: Allow a tcl script to be added as ip	2021-02-17 08:12:09 +01:00
Florent Kermarrec	82c1f5dccb	litex_setup/ibex: add pythondata-misc-opentitan to litex_setup and use it for Ibex CPU.	2021-02-17 08:07:07 +01:00
Florent Kermarrec	285bb96278	cores/uart/RS232PHY: add with_dynamic_baudrate parameter and disable it by default. Dynamic baudrate is rarely used and enabling it has a non negligeable cost (~100LCs).	2021-02-16 20:00:43 +01:00
Florent Kermarrec	9a8a8c0fe5	software/liblitedram: remove SDRAM_PHY_WRITE_LEVELING_REINIT no longer required on Ultrascale(+).	2021-02-16 16:26:34 +01:00
Vamsi Vytla	385dec8560	Merge remote-tracking branch 'upstream/master'	2021-02-15 09:29:47 -08:00
Vamsi Vytla	1fde282291	build/xilinx/vivado.py: Allow a tcl script to be added as ip. These tcl scripts tend to generate .xci's on the fly. The tcl script can be looked up in the vivado console as the ip is generated	2021-02-15 09:29:00 -08:00
Gabriel Somlo	927fd675bc	sdclk: additional halving to prevent clock going "too fast" When the system/bus clock frequency is an exact power-of-2 multiple of the desired sdcard frequency, we can drive the latter at the "maximum" speed via the "perfect" divider. That sometimes turns out too fast, so in order to be conservative, we double the divider, thus halving the resulting sdclock.	2021-02-15 09:24:02 -05:00
Gabriel Somlo	b03f46ffec	soc: increase sdcard data/cmd timeout (from default 10e-3) This allows the Linux driver in single-block mode (cmd17-only) to operate solidly, without running into timeouts from LiteSDCard FSMs. FIXME: multi-block (cmd18) transfers still time out, so revisit this after some additional debugging.	2021-02-15 09:23:52 -05:00
enjoy-digital	07dd680a3e	Merge pull request #818 from tcal-x/vexLiteMul Vexriscv "lite" uses "--mulDiv true", so enable "mul" instructions.	2021-02-15 15:02:47 +01:00
Florent Kermarrec	510bda4c99	cores/cpu: add initial lowRISC's Ibex support (without interrupts). Working in simulation and on hardware: litex_sim --cpu-type=ibex, ./target.py --cpu-type=ibex. This is currently doing a git clone of ibex and opentitan repositories but we'll create a pythondata-cpu-ibex package in the future. litex_sim --cpu-type=ibex: __ _ __ _ __ / / (_) /____ \| \|/_/ / /__/ / __/ -_)> < /____/_/\__/\__/_/\|_\| Build your hardware, easily! (c) Copyright 2012-2020 Enjoy-Digital (c) Copyright 2007-2015 M-Labs BIOS built on Feb 15 2021 11:57:50 BIOS CRC passed (e7517f7b) Migen git sha1: 7014bdc LiteX git sha1: `ead12df2` --=============== SoC ==================-- CPU: Ibex @ 1MHz BUS: WISHBONE 32-bit @ 4GiB CSR: 32-bit data ROM: 32KiB SRAM: 8KiB MAIN-RAM: 262144KiB --============== Boot ==================-- Booting from serial... Press Q or ESC to abort boot completely. sL5DdSMmkekro Timeout No boot medium found --============= Console ================--	2021-02-15 12:02:25 +01:00
Tim Callahan	5cb467cae3	Vexriscv "lite" uses "--mulDiv true", so enable "mul" instructions. Signed-off-by: Tim Callahan <tcal@google.com>	2021-02-14 14:16:14 -08:00
Florent Kermarrec	ead12df21b	soc/cores/gpio: review/simplify #810 . Use irqs dict and "rise", "fall" strings instead of Enums: Ex: pads=Signal(8), irqs={} : 8-bit Input, No IRQ. pads=Signal(8), irqs={0: "rise", 7: "fall"}: 8-bit Input, rising IRQ on 0, falling IRQ on 1. Also simplify the logic.	2021-02-12 16:21:01 +01:00
enjoy-digital	89454d2df3	Merge pull request #810 from antmicro/gpio_interrupts Add support for interrupts on GPIOIn	2021-02-12 15:51:25 +01:00
Geert Uytterhoeven	d91262e85c	software/demo: Drop bogus "the" in README Fixes: `e7e28f2438` ("Change wording of demo README") Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-02-12 15:15:55 +01:00
enjoy-digital	0366a03c87	Merge pull request #813 from antmicro/jboc/lpddr4 software/bios: add option to disable BIOS prompt	2021-02-12 14:08:34 +01:00
Nick Østergaard	e7e28f2438	Change wording of demo README Change wording of demo README to make it more clear what the process is and how things related. This should help the newcomer and it still usefull for the triained. Change the command example to be more copy paste friendly. Fixes #814	2021-02-11 21:35:02 +01:00
Jędrzej Boczar	5f1edccd2e	software/bios: add option to disable BIOS prompt	2021-02-11 10:49:45 +01:00
Florent Kermarrec	041aa9bf6f	soc/cores/clock/xilinx_us/USIDELAYCTRL: make sure sys clock domain is reseted when reference clock domain is reseted.	2021-02-09 19:06:49 +01:00
Florent Kermarrec	126dd267d6	soc/interconnect/axi/AXIInterface: add optional tkeep.	2021-02-09 16:27:48 +01:00
Robert Szczepanski	15b3d932a4	gpio: add support for interrupts on GPIOIn	2021-02-09 15:29:31 +01:00
enjoy-digital	018094abb2	Merge pull request #809 from stffrdhrn/mor1kx-smp cpu/mor1kx: Add initial SMP support to cpu core	2021-02-09 09:54:49 +01:00
enjoy-digital	95b310ee0f	Merge pull request #807 from antmicro/revert-bitstream-device-changes build/xilinx/symbiflow: fix bitstream_device select	2021-02-09 09:26:48 +01:00
Stafford Horne	2f2b047f2e	cpu/mor1kx: Add initial SMP support to cpu core In order for mor1kx to run an SMP kernel shadow registers must be enabled. This patch adds two new variants: - linux+smp - basic linux + smp support - linux+smp+fpu - linux with FPU and smp support	2021-02-09 07:06:07 +09:00
Jan Kowalewski	ad760d491c	build/xilinx/symbiflow: fix bitstream_device select Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>	2021-02-08 15:38:30 +01:00
Geert Uytterhoeven	84e5130ac5	software/bios/console: Call putsnonl() from puts() puts() and putsnonl() are very similar, and can share code. Reduce code size by making the former call the latter. Impact for a RISC-V build: $ size console.o.orig console.o text data bss dec hex filename 868 0 12 880 370 console.o.orig 832 0 12 844 34c console.o Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-02-08 14:05:31 +01:00
Geert Uytterhoeven	8e4202ced1	software/bios/readline: Fix warnings if char is signed When building with --cpu-type=mor1kx: litex/soc/software/bios/readline.c: In function 'readline': litex/soc/software/bios/readline.c:271:3: warning: case label value exceeds maximum value for type [-Wswitch-outside-range] 271 \| case KEY_END: \| ^~~~ litex/soc/software/bios/readline.c:297:3: warning: case label value exceeds maximum value for type [-Wswitch-outside-range] 297 \| case KEY_DEL: \| ^~~~ litex/soc/software/bios/readline.c:281:3: warning: case label value exceeds maximum value for type [-Wswitch-outside-range] 281 \| case DEL: \| ^~~~ The C standard does not specify the signedness of "char", hence this depends on the implementation. On e.g. RISC-V, "char" is unsigned, but on OpenRISC, it is signed. Fix this by making the "ichar" variable explicitly unsigned. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-02-08 14:05:31 +01:00
Florent Kermarrec	5430c1455e	software/demo: add support for absolute/relative --build-path and simplify comment.	2021-02-08 10:29:26 +01:00
Hans Baier	7dae0aa09b	litex_term: support Intel/Altera nios2-terminal	2021-02-08 11:42:37 +07:00
Hans Baier	6f63fc104e	demo: more helpful usage message	2021-02-06 07:15:12 +07:00
Florent Kermarrec	5cb9f487a2	tools/litex_server: remove JTAGUART's binary_mode parameter (we are now only supporting binary_mode).	2021-02-05 12:38:20 +01:00
Florent Kermarrec	468b916a4f	tools/litex_term: add --jtag-config parameter to select OpenOCD JTAG configuration file.	2021-02-05 09:43:32 +01:00
Florent Kermarrec	4f15be746c	tools/litex_term: always use binary mode (for jtag_uart and jtagbone) and remove parameter. Fix jtag_uart regression and allow serialboot.	2021-02-05 09:40:21 +01:00
enjoy-digital	92f4cd1423	Merge pull request #799 from antmicro/add_xc7a200t_to_symbiflow build/xilinx: add xc7a200t-sbg484-1 to symbiflow toolchain	2021-02-04 16:41:45 +01:00
enjoy-digital	0006efe6ea	Merge pull request #800 from geertu/doc-sphinx-v1-fix doc: Fix doc build with Sphinx v1.x	2021-02-04 12:24:49 +01:00
Florent Kermarrec	4d1deffbb0	jtagbone/openocd: add binary mode on JTAGUART to fix "\n" to "\r" remapping that is not wanted in binary mode.	2021-02-04 11:44:43 +01:00
Geert Uytterhoeven	af13f43e60	doc: Fix doc build with Sphinx v1.x When building the linux-on-litex-vexriscv documentation with Sphinx v1.8.5: Sphinx error: master file linux-on-litex-vexriscv/build/orangecrab/doc/contents.rst not found The default value of "master_doc" was changed from "contents" to "index" in Sphinx v2[1]. As the LiteX doc system creates "index.rst", it thus fails to build with Sphinx v1.x. Explicitly configure "master_doc" to "index", to make it work with all versions of Sphinx, regardless of the default. [1] https://www.sphinx-doc.org/ca/latest/usage/configuration.html?highlight=master_doc Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-02-04 09:40:04 +01:00
Jan Kowalewski	57915db746	build/xilinx: add xc7a200t-sbg484-1 to symbiflow toolchain Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>	2021-02-03 15:18:48 +01:00
Jędrzej Boczar	b1fb141d1f	Fix gtkwave.py to be compatible with python 3.6	2021-02-02 11:14:16 +01:00
Florent Kermarrec	ba7c503fb6	tools/litex_sim: move gtkw import to generate_gtkw_savefile. This fixes litex_sim use with python 3.6 and raise an error when --gtkwave-savefile is used with python 3.6.	2021-02-02 10:13:23 +01:00
enjoy-digital	659751d202	Merge pull request #795 from antmicro/jboc/gtkwave-savefiles Add automatic generator of GTKWave savefiles	2021-02-02 09:59:18 +01:00
enjoy-digital	2f907d6e1e	Merge pull request #790 from antmicro/jboc/8phases software/liblitedram: support PHYs with more than 4 DFI phases	2021-02-02 09:43:17 +01:00
enjoy-digital	d76e0dcede	Merge pull request #791 from antmicro/jboc/init-mr software/liblitedram: selectable write leveling MR (for LPDDR4 support)	2021-02-02 09:36:31 +01:00
Geert Uytterhoeven	7b3737f531	cpu/vexriscv_smp: Make sbt failures fatal When using a non-default VexRiscv cluster config, the netlist for that config needs to be generated. This requires sbt to be installed. If sbt is missing, an error message is printed: sh: 1: sbt: not found This message may easily be lost in the noise, as the build continues, and fails later with: ERROR: Can't open input file `litex/pythondata-cpu-vexriscv-smp/pythondata_cpu_vexriscv_smp/verilog/VexRiscvLitexSmpCluster_Cc1_Iw32Is4096Iy1_Dw32Ds4096Dy1_Ood_Wm.v' for reading: No such file or directory Make the root cause more visible by raising an OSError, and aborting the build. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-02-01 13:54:59 +01:00
Jędrzej Boczar	fc9ef4c255	litex_sim: add --gtkwave-savefile argument with example signals	2021-02-01 13:22:30 +01:00
Jędrzej Boczar	01b900f4e0	Add GTKWave savefile generator	2021-02-01 13:22:30 +01:00
Florent Kermarrec	8623536a8a	build/generic_platform: avoid removing X pins from named_sc. We need them on Gowin FPGAs with embedded SDRAM where SDRAM pins are not real IOs.	2021-02-01 13:12:25 +01:00
Florent Kermarrec	f324f9531a	build/gowin: Don't generate IO_LOC is pin name is X.	2021-02-01 13:08:37 +01:00
enjoy-digital	fd33e360fb	Merge pull request #792 from euryecetelecom/master Add flash method to openFPGALoader class	2021-01-30 21:35:09 +01:00
Konstantin	3f27253ccc	cores/clock/lattice_ice40: add missing AsyncResetSynchronizer import.	2021-01-30 18:25:19 +01:00
Guillaume REMBERT	18a5ace637	Add flash method to openFPGALoader class for support with generic_programmer usage (needed for linux-on-litex-vexriscv) + add offset/address support for firmware load	2021-01-30 13:20:30 +01:00
enjoy-digital	69307cfdde	Merge pull request #789 from antmicro/jboc/litex-sim-fix-name litex_sim: fix old name: get_cl_cw -> get_default_cl_cwl	2021-01-29 19:13:34 +01:00
Jędrzej Boczar	61e605da92	litex_sim: fix old name: get_cl_cw -> get_default_cl_cwl	2021-01-29 11:31:40 +01:00
Florent Kermarrec	2287f73937	tools/litex_client: add --read/--write args to do simple MMAP accesses to SoC bus. ex reading/writing to scratch register over jtagbone: In the SoC: self.add_jtagbone() Open LiteX Server: litex_server --jtag Do the MMAP accesses: ./litex_cli --read 0x4 0x12345678 ./litex_clk --write 0x4 0x5aa55aa5 ./litex_cli --read 0x4 0x5aa55aa5	2021-01-28 17:46:18 +01:00
Jędrzej Boczar	38b819c42a	software/liblitedram: selectable write leveling MR (for LPDDR4 support)	2021-01-28 15:56:13 +01:00
Jędrzej Boczar	e3172faad9	software/liblitedram: support PHYs with more than 4 DFI phases	2021-01-28 15:53:40 +01:00
Florent Kermarrec	7abfbd9825	tools/litex_json2dts/ethernet: add missing 'status = "okay";'. Was causing https://github.com/litex-hub/linux-on-litex-vexriscv/issues/178.	2021-01-27 11:52:04 +01:00
Florent Kermarrec	b8bcbc522f	integration/export/triple: use LITEX_ENV_CC_TRIPLE instead of TRIPLE. triple can be used internally, but is too generic as an environment variable.	2021-01-27 08:25:48 +01:00
enjoy-digital	f331ddace8	Merge pull request #780 from garytwong/triple-option integration/export: allow manually specifying toolchain triple.	2021-01-27 08:16:41 +01:00
Florent Kermarrec	2f89e0aecf	soc/do_finalize: check that crg.rst is a Signal before connecting to ctrl._reset.	2021-01-26 17:08:43 +01:00
Florent Kermarrec	cafe0944f1	soc/add_uartbone/add_jtagbone: improve phy naming and add uartbone_phy to CSR.	2021-01-26 15:46:55 +01:00
enjoy-digital	7479cbe71b	Merge pull request #784 from Acathla-fr/patch-1 Update comm_usb.py	2021-01-26 14:36:07 +01:00
Florent Kermarrec	331124dd23	tools/litex_server: add --jtag-config args to provide OpenOCD configuration file.	2021-01-26 14:32:36 +01:00
Florent Kermarrec	2e1b9ed948	tools/litex_server: rename --jtag-uart to --jtag.	2021-01-26 14:12:54 +01:00
Florent Kermarrec	531ce0e8b7	soc: create specific add_jtagbone method instead of integrating it in add_uartbnone. Creates a JTAG bridge in the SoC simply with self.add_jtagbone(), almost comes for free :)	2021-01-26 14:12:19 +01:00
Acathla-fr	a092d5b28f	Update comm_usb.py typo : csr_csr replaced by csr_csv	2021-01-26 12:34:08 +01:00
Florent Kermarrec	ed1da7ed1e	soc/add_pcie: expose max_pending_requests parameter. Being able to configure it is useful to find resource usage/performance compromise.	2021-01-26 10:59:22 +01:00
Florent Kermarrec	dd985cd1d0	integration/export: disable CSRField extract/read functions generation for csr.size > 32-bit.	2021-01-26 10:23:56 +01:00
Florent Kermarrec	2a542e150d	jtag_uart/openocd: switch to raw tcp socket and get litex_server --jtag-uart working.	2021-01-25 16:33:43 +01:00
Florent Kermarrec	7799765471	soc/jtag: run JTAGPHY in sys_jtag clock domain (to fix behavior after reset).	2021-01-25 16:31:55 +01:00
Florent Kermarrec	213644af70	integration/soc/add_uart: ResetInserter no longer required on UART since reboot is now doing a full system reset.	2021-01-25 13:39:45 +01:00
Florent Kermarrec	8cada67f32	cores/jtag: cleanup instances.	2021-01-25 12:31:32 +01:00
Florent Kermarrec	0b5df58a1b	cores/jtag: cores/uart: expose jtag/tx/rx_cdc (to ease probing with LiteScope).	2021-01-25 12:30:43 +01:00
Florent Kermarrec	4df336341b	cores/uart: expose fsm/timer (to ease probing with LiteScope).	2021-01-25 12:29:18 +01:00
Florent Kermarrec	17195c5e96	cpu/vexriscv_smp: cleanup new args integration and fix cluster naming.	2021-01-25 11:48:05 +01:00
enjoy-digital	7fa03cb1f3	Merge pull request #782 from enjoy-digital/vexriscv-smp-no-litedram soc/cpu/vexriscv-smp: add args to disable out of order or direct path to LiteDRAM	2021-01-25 08:45:03 +01:00
Florent Kermarrec	1a38d51e08	libbase/memtest: remove 0x no longer required with %p.	2021-01-24 21:09:19 +01:00
Dolu1990	ae2cd31573	soc/cpu/vexriscv-smp add --without-out-of-order-decode and --with-wishbone-memory	2021-01-23 20:38:50 +01:00
Florent Kermarrec	01a2fc11e2	integration/soc/usb_acm: run USB ACM in sys_usb clock domain similar to sys clock domain but with rst disconnected.	2021-01-22 22:57:24 +01:00
Gary Wong	13d1d4cf8e	integration/export: allow manually specifying toolchain triple. If the environment variable TRIPLE is defined, use its value as the highest priority candidate. Useful for testing new cross-compilers, or selecting among toolchains in a different priority than the built-in list.	2021-01-22 12:11:03 -07:00
Florent Kermarrec	8623b0a16a	integration/soc/add_uartbone: fix jtag_uart integration.	2021-01-22 15:00:13 +01:00
Florent Kermarrec	d7aedfbc12	tools/litex_server: add initial JTAG-UART support.	2021-01-22 14:19:38 +01:00
Florent Kermarrec	697ff7447c	soc/integration: add initial JTAG-UART support to UARTbone.	2021-01-22 14:19:03 +01:00
Florent Kermarrec	e8cfe3b6ea	software/liblitedram: fix typo.	2021-01-22 11:57:06 +01:00
enjoy-digital	f22079dc94	Merge pull request #776 from geertu/compiler-warning-fixes Compiler warning fixes	2021-01-22 09:28:23 +01:00
Florent Kermarrec	4e5f20a060	software/liblitedram: rename Half Sys8x Taps to tCK/4 and display "-" during write calibration when no valid bitstlip found.	2021-01-21 20:00:29 +01:00
Florent Kermarrec	57289dd47c	software/liblitedram/write_leveling: display Half Sys8x Taps value before write_leveling.	2021-01-20 09:43:53 +01:00
Florent Kermarrec	acb6741b8a	software/bios: rename CONFIG_SIM_DISABLE_DELAY to CONFIG_DISABLE_DELAYS and disable timeout on serialboot's check_ack when CONFIG_DISABLE_DELAYS is set. This is useful in simulation to skip serialboot ack check.	2021-01-20 09:42:29 +01:00
Geert Uytterhoeven	0f28bc489d	software/include/base/stdio: Enable printf format strings checks Now all format issues are fixed, tag all functions taking printf()-style format specifiers with "__attribute__((format(printf, ...))", enabling format string checks ("-Wall" includes "-Wformat"). Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-01-19 15:03:48 +01:00

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