3595 commits

Author	SHA1	Message	Date
Florent Kermarrec	87ebdea5a7	software/libliteeth: Add optional ETH_PHY_NO_RESET support to allow disabling software reset. ... Un-wanted when using the Hybrid LiteETHMAC since interrupt the hardware UDP/IP stack.	2021-04-29 11:50:00 +02:00
Stafford Horne	a9e935e61a	tools/litex_json2dts: Add interrupt settings for sdcard	2021-04-29 17:52:17 +09:00
Stafford Horne	dc1a4c5380	integration/soc: Wire up the sdirq to the CPU ... I am working on testing out the patches from: https://github.com/litex-hub/linux/pull/8 These linux patches take advantage of the sdcard interrupt to track when transfers finish. However, it seems the interrupt is not being connected to the CPU. This patch does that by allowing us to directly register and EventManager module with the irq handler.	2021-04-29 17:18:51 +09:00
Tim Ansell	11f091d4cf	Merge pull request #900 from stffrdhrn/rom-to-128k ... integration/soc_core: Increase default ROM size to 128K	2021-04-28 15:28:19 -07:00
Stafford Horne	2f96cf021c	integration/soc_core: Increase default ROM size to 128K ... With recent BIOS changes the default rom size on the mor1kx built just passes over the 64k boundary and the build fails. Since the 128K default is a soft limit and the ROM gets resized to the actual ROM requirements this should be relatively safe. Note, that if a RW rom is configured the full 128kb will be allocated. Fixes: #893	2021-04-29 06:52:49 +09:00
Florent Kermarrec	9098f5553c	software/liblitedram: Add liblitedram prefix to includes (to use copy of bist.c/sdram.c externally).	2021-04-28 17:21:04 +02:00
Florent Kermarrec	bb355a773a	integration/soc/video: Allow passing timings as str or tuple (name, dict). ... When passed as str, the timing dict will be extracted from litex.soc.cores.video.video_timings. When passed as tuple, custom dict will be directly passed to VTG.	2021-04-28 16:58:11 +02:00
Florent Kermarrec	c4e8e44cd9	cores/video/VideoTimingGenerator: Allow passing custom dict as default_video_timings. ... Allow only listing the classical video timings in the core and let user provide the timings specific to other configurations.	2021-04-28 16:56:28 +02:00
enjoy-digital	da1092d9c0	Merge pull request #896 from danc86/nodefaultlibs ... soc/software: link with compiler instead of ld	2021-04-28 15:44:49 +02:00
Florent Kermarrec	f7b615ffab	software/liblitedram/sdram.c: Avoid direct ddrphy_wdly_dq_rst during DQ-DQS training on Ultrascale/Ultrascale+ (seems to cause issue on some configurations/modules). ... Also add a delay to be similar to read_leveling reset/inc functions.	2021-04-28 14:42:41 +02:00
Florent Kermarrec	dc4f9772ba	software/liblitedram/sdram.c: Move common centering functions to separate section.	2021-04-28 14:15:48 +02:00
Florent Kermarrec	19d16fa27f	software/liblitedram/sdram/sdram_write_leveling_find_cmd_delay: Only update best_count when error < best_error.	2021-04-28 11:23:34 +02:00
Florent Kermarrec	c50989be8e	software/liblitedram/sdram: Add sdram_tck_taps variable and use it internally to avoid un-needed accesses to CSRs.	2021-04-28 11:22:07 +02:00
Florent Kermarrec	87c0e30cef	software/liblitedram/sdram.c: Remove residual wrap around code, fix some spaces/tabs.	2021-04-28 10:45:35 +02:00
Florent Kermarrec	74c42a55e2	tools/litex_json2dts/framebuffer: Use framebuffer_base.	2021-04-27 18:59:54 +02:00
Florent Kermarrec	a3f3d8f08f	software/liblitedram/sdram: Fix compilation warning.	2021-04-27 16:33:40 +02:00
Jędrzej Boczar	ad23130a9a	software/liblitedram: use single iteration of dq-dqs training	2021-04-27 10:54:32 +02:00
Dan Callaghan	020466a43e	soc/software: link with compiler instead of ld ... The linker does not actually recognise -nodefaultlibs, that is a compiler option. Prior to binutils 2.36, ld treated -nodefaultlibs as a string of short options and ignored them as unrecognised. Starting from binutils 2.36, it reports an error instead: riscv64-unknown-elf-ld: Error: unable to disambiguate: -nodefaultlibs (did you mean --nodefaultlibs ?) See also: https://sourceware.org/bugzilla/show_bug.cgi?id=27050 Fixes #825.	2021-04-27 15:36:13 +10:00
Florent Kermarrec	4c26dbe98f	cores/cpu/microwatt: Re-map csr/xics and keep the lower 128MBs for the SoC IO auto-allocation.	2021-04-26 18:37:40 +02:00
Florent Kermarrec	9a82fd1d54	tools/litex_sim: Use automatic ethmac allocation.	2021-04-26 18:33:50 +02:00
Florent Kermarrec	48ec20e2ef	software/liblitedram/sdram: Remove wraps around in sdram_leveling_center_module. ... Adding wraps around capability will have to be discussed, if implemented this has to be done very carefully since there are no relation between the total delay that can be compensated through the I/O-DELAYs and the SDRAM clock period. As implemented, it also produced confusing values in the logs: m0:0 m1:0 Read leveling: m0, b0: |00000000000000000000000000000000| delays: - m0, b1: |00000000000011111111111111100000| delays: 19+-07 m0, b2: |00000000000000000000000000001111| delays: 14+-17 m0, b3: |00000000000000000000000000000000| delays: - m0, b4: |00000000000000000000000000000000| delays: - m0, b5: |00000000000000000000000000000000| delays: - m0, b6: |00000000000000000000000000000000| delays: - m0, b7: |00000000000000000000000000000000| delays: - best: m0, b01 delays: 19+-07 m1, b0: |00000000000000000000000000000000| delays: - m1, b1: |00000000000011111111111111000000| delays: 19+-07 m1, b2: |00000000000000000000000000001111| delays: 15+-17 m1, b3: |00000000000000000000000000000000| delays: - m1, b4: |00000000000000000000000000000000| delays: - m1, b5: |00000000000000000000000000000000| delays: - m1, b6: |00000000000000000000000000000000| delays: - m1, b7: |00000000000000000000000000000000| delays: - best: m1, b01 delays: 19+-07 Switching SDRAM to hardware control. --> 14+-17 and 15+-17 are confusing.	2021-04-26 17:27:27 +02:00
enjoy-digital	a6c5fd7aed	Merge pull request #891 from antmicro/crosslink-nx-fix-sdr-buffers ... Lattice Crosslink NX: Fix clock port names in SDR{in/out} Impl	2021-04-26 11:19:44 +02:00
Jan Luebbe	f4c9bf0666	bios: support passing tftp filename to the 'netboot' command ... Signed-off-by: Jan Luebbe <jlu@pengutronix.de>	2021-04-25 20:45:03 +02:00
Karol Gugala	54f729fbc1	Lattice: Fix port names in SDR{in/out} Impl ... Signed-off-by: Karol Gugala <kgugala@antmicro.com>	2021-04-25 19:47:30 +02:00
Florent Kermarrec	22d763ee11	tools/litex_sim: Remove self.add_csr calls no longer required.	2021-04-23 19:33:51 +02:00
Florent Kermarrec	8c8c1fe6e0	tools/litex_sim: Fix cpu in configuration (allow list of supported CPU to be listed when invalid cpu_type is provided).	2021-04-23 19:16:18 +02:00
Florent Kermarrec	116c2f1549	cores/cpu: Cosmetic cleanups.	2021-04-23 16:16:31 +02:00
Florent Kermarrec	fe7029a7e0	software/liblitedram: Add missing read window re-centering after selecting bitslip in Write DQ-DQS training.	2021-04-22 17:08:20 +02:00
enjoy-digital	447d2648e8	Merge pull request #884 from antmicro/jboc/dq-dqs-training ... Write DQ-DQS training	2021-04-22 17:08:08 +02:00
Florent Kermarrec	0ed7852779	tools/litex_term: Add time.sleep on BridgeUART to avoid high CPU usage.	2021-04-22 17:07:33 +02:00
Florent Kermarrec	75045914b4	global: Bump copyright year.	2021-04-22 17:07:29 +02:00
Florent Kermarrec	b55af2156b	soc/add_sdcard: Fix cmd_done signal.	2021-04-21 13:38:00 +02:00
Paul Mackerras	e6765f847d	integration/soc/add_sdcard: Add an interrupt for command completion ... This is useful for long-running commands generally and in particular for those without any data transfer, such as erase. It is a level-sensitive interrupt because that makes it a little harder to lose interrupts due to incorrect programming. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>	2021-04-21 09:00:31 +10:00
Florent Kermarrec	2ac7e0b978	software/liblitesdcard: Update with LiteSDCard changes (SDCARD_CTRL_RESPONSE_SHORT_BUSY is now directly a supported command).	2021-04-20 14:30:28 +02:00
enjoy-digital	b29515bd1d	Merge pull request #885 from paulusmack/master ... software/liblitesdcard: Tell the controller when to wait while the card is busy	2021-04-20 14:30:08 +02:00
enjoy-digital	eea63968d2	Merge pull request #877 from rdolbeau/eth_int_fix ... Fix interrupt issue with ethernet on recent Linux-On-Litex-Vexriscv/SMP	2021-04-19 18:12:01 +02:00
Paul Mackerras	49c4d735c5	software/liblitesdcard: Tell the controller when to wait while the card is busy ... Bit 2 of the command register now tells the controller to wait while the card is indicating that it is busy (by pulling the DAT0 line low). The card can do this for commands 7 and 12 and app command 41 (and also for commands 20, 28, 29, 38 and 43, but we don't use those here.) This sets bit 2 for those commands. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>	2021-04-19 09:12:13 +10:00
Jędrzej Boczar	2a5973b21f	soc/software/liblitedram: refactor centering code into more generic function	2021-04-16 15:41:24 +02:00
Jędrzej Boczar	76d121ea36	soc/software/liblitedram: add DQ-DQS training procedure	2021-04-16 11:50:38 +02:00
Romain Dolbeau	f310dd52f3	Fix interrupt issue with ethernet on recent Linux-On-Litex-Vexriscv/SMP ... It seems an overreaching 'interrupt-parent' caused trouble to interrupt routing. This moves 'interrupt-parent' to the SoC entry.	2021-04-15 10:06:53 +02:00
developandplay	8ef7353fe5	Add interactivity option to simulation	2021-04-14 13:39:47 +02:00
enjoy-digital	246142256b	Merge pull request #880 from betrusted-io/issue-862 ... resolve issue #862 add description to soc.svd	2021-04-14 08:58:42 +02:00
enjoy-digital	01479ed541	Merge pull request #879 from betrusted-io/timer-doc ... use AutoDoc for timer documentation	2021-04-14 08:56:37 +02:00
Florent Kermarrec	f014e4cbd2	tools/litex_client: Add filter parameter to dump_registrers to only dump/display the filtered registers: ... ex: litex_cli --regs --filter=pcie_phy will only dump/display pcie_phy registers.	2021-04-13 13:44:41 +02:00
bunnie	1b78b12024	resolve feedback on import location	2021-04-12 22:27:22 +08:00
bunnie	ab0aab6913	resolve issue #862 add description to soc.svd ... The issue is that with no description provided it simply would not put out a description tag, which breaks compatibility with other programs. Insert a somewhat useful default description including a timestamp and the words "LiteX SoC".	2021-04-12 22:08:05 +08:00
bunnie	2bb830bb69	use AutoDoc for timer documentation ... Not sure why nobody else saw this, but sometime in the last month's patches sphinx started throwing an error when building docs for the timer block. The problem is that the body and title are 'None' and the doc code tries to invoke methods on None. Changing the doc methodology to AutoDoc and explicitly creating the intro section fixes this.	2021-04-12 21:53:05 +08:00
Florent Kermarrec	5011b564c3	integration/soc: Add _ prefix to build_name when build_name starts with digit (Invalid verilog top level name).	2021-04-12 08:32:05 +02:00
Florent Kermarrec	15cf4d75e9	software/liblitesdcard: Add SDCARD_CMD25_SUPPORT #define to allow disabling/enabling Multiple Block Writes and implement Multiple Block Writes.	2021-04-09 19:34:13 +02:00
Florent Kermarrec	5cdf621367	software/liblitesdcard: Add SDCARD_CMD18_SUPPORT #define to allow disabling/enabling Multiple Block Reads. ... Also use Single Block Read when only 1 block to read, avoid stop transmission.	2021-04-09 19:17:32 +02:00
Florent Kermarrec	9bec0ce7a2	soc/add_ethernet: Add with_timestamp parameter to enable Timestamping and use timer0.uptime_cycles as Timestamp source.	2021-04-08 14:37:48 +02:00
Florent Kermarrec	7caed56790	cores/timer: Expose uptime_cycles and allow multiple calls to add_uptime.	2021-04-08 14:36:10 +02:00
Florent Kermarrec	dbe09341c0	soc/add_pcie: Remove duplicate assert (already checked by check_if_exists).	2021-04-08 12:19:56 +02:00
enjoy-digital	37a81b145a	Merge pull request #875 from rdolbeau/reserve_fb_memory ... json2dts: add the framebuffer memory in the 'reserved-memory' entry, …	2021-04-07 12:17:00 +02:00
Florent Kermarrec	e5e472d469	soc/software: Remove SoCController dependency for BIOS compilation.	2021-04-07 10:45:43 +02:00
Florent Kermarrec	02328e5236	integration/soc: Add check_bios_requirements method and check for ctrl, timer0, rom and sram presence in the SoC when using the BIOS.	2021-04-07 10:37:48 +02:00
Florent Kermarrec	6940db7730	software/bios: Fix compilation without UART.	2021-04-07 09:03:07 +02:00
Romain Dolbeau	dac6c1cbb1	json2dts: add the framebuffer memory in the 'reserved-memory' entry, so that Linux doesn't try to use it for something else.	2021-04-06 13:44:50 +02:00
enjoy-digital	8db1a619f5	Merge pull request #874 from chmousset/enh/ECP5DifferentialInput ... [enh] ECP5 DIfferential input support	2021-04-06 12:27:33 +02:00
enjoy-digital	4500641d78	Merge pull request #873 from sthornington/master ... Fix yosys read command for SystemVerilog sources	2021-04-06 12:08:07 +02:00
Charles-Henri Mousset	51ea0c0427	[enh] ECP5 DIfferential input support	2021-04-05 17:24:51 +02:00
Simon Thornington	4b0a359675	Fix yosys read command for SystemVerilog sources	2021-04-05 10:37:17 -04:00
Romain Dolbeau	3addd587b6	640x480@60Hz (lowest bandwidth option yet)	2021-04-04 17:20:53 +02:00
Florent Kermarrec	080ecad522	cpu/vexriscv_smp: Add specialization of the RAM implementation based on the FPGA family (Platform). ... RAMXilinx was not infered correctly on Intel/Altera devices, we now have an Intel/Altera specific implementation and could add other specific implementations in the future if required.	2021-03-30 11:10:05 +02:00
Florent Kermarrec	70d11974fc	cores/video/framebuffer: Add support for video clock faster than sys_clk with DRAM's data-width > 32. ... In this, CDC has to be done first and Data-width conversion is then done in Video clock domain.	2021-03-30 10:14:10 +02:00
Florent Kermarrec	c182f4db5f	cores/video: Add check of Video Timings and list available ones when not supported.	2021-03-30 09:15:17 +02:00
Florent Kermarrec	2ed5f14e9e	integration/soc/soc_core: Remove --min-l2-data-width and --max-sdram-size that don't need to be configurable but can just be enforced in the target file.	2021-03-29 11:26:29 +02:00
Florent Kermarrec	ac7857fa4f	cores/video/add_video_framebuffer: Add workaround when SDRAM data_width < 32.	2021-03-29 11:25:34 +02:00
Florent Kermarrec	4a29e2403c	integration/soc/add_sdram: Directly use main_ram mem_map mapping if available.	2021-03-29 11:22:31 +02:00
Florent Kermarrec	99a26fc710	integration/soc/add_video_framebuffer: Modify default framebuffer base address.	2021-03-29 10:59:32 +02:00
Florent Kermarrec	bf999cfeac	cores/Video: Expose fifo_depth and add underflow signal that can be used investigate bandwidth issues.	2021-03-29 10:58:31 +02:00
enjoy-digital	544c0e2c84	Merge pull request #867 from geertu/json2dts-fixes2 ... Json2dts fixes2	2021-03-28 18:54:26 +02:00
Geert Uytterhoeven	24ad265a3b	tools/litex_json2dts: Fix i2c node ... i2c@f0000800: '#address-cells' is a required property From schema: Documentation/devicetree/bindings/i2c/litex,i2c.yaml i2c@f0000800: '#size-cells' is a required property From schema: Documentation/devicetree/bindings/i2c/litex,i2c.yaml Fix this by adding the missing properties. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-03-28 12:44:45 +02:00
Geert Uytterhoeven	e09b2bd1c5	tools/litex_json2dts: Fix gpio node ... gpio@f0003000: 'gpio-controller' is a required property From schema: Documentation/devicetree/bindings/gpio/litex,gpio.yaml gpio@f0003000: '#gpio-cells' is a required property From schema: Documentation/devicetree/bindings/gpio/litex,gpio.yaml Fix this by adding the missing properties. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-03-28 12:44:45 +02:00
Shawn Hoffman	fc75e57d9a	lattice: use pnmainc on windows	2021-03-27 04:36:02 -07:00
Shawn Hoffman	e56268d419	don't require compiler_rt if not used	2021-03-27 04:18:17 -07:00
Florent Kermarrec	b858dd62e9	liblitesdcard/sdcard: Remove divider workaround (was due to LiteSDCard backpressure issue).	2021-03-26 23:19:08 +01:00
Florent Kermarrec	37704195af	tools/litex_json2dts: Revert previous mac0 formating (thanks geertu).	2021-03-26 23:17:55 +01:00
Florent Kermarrec	9d62cbf56e	integration/soc/SoCCSRHandler: Only keep Auto-Allocation mode.	2021-03-26 23:11:39 +01:00
Florent Kermarrec	24ee6de5c2	cores/video: Make de pin optional on VideoDVIPHY.	2021-03-26 22:53:59 +01:00
Geert Uytterhoeven	a7a70fa2f0	tools/litex_json2dts: Fix mmc node ... mmc@f0006800:reg:0: [4026558464, 256, 4026560512, 256, 4026562560, 256, 4026564608, 256] is too long From schema: dt-schema/dtschema/schemas/simple-bus.yaml mmc@f0006800:reg:0: [4026558464, 256, 4026560512, 256, 4026562560, 256, 4026564608, 256] is too long From schema: dt-schema/dtschema/schemas/reg.yaml Fix this by grouping the tuples in the "reg" property using angle brackets. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-03-26 17:19:01 +01:00
Geert Uytterhoeven	54d2578f04	tools/litex_json2dts: Fix liteuart node ... serial@f0001000: 'device_type' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/serial/litex,liteuart.yaml Fix this by dropping the offending property. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-03-26 17:19:01 +01:00
Geert Uytterhoeven	bcef9a68ca	tools/litex_json2dts: Fix plic node ... interrupt-controller@f0c00000: compatible:0: 'sifive,plic-1.0.0' is not one of ['sifive,fu540-c000-plic', 'canaan,k210-plic'] From schema: Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml interrupt-controller@f0c00000: compatible:1: 'sifive,plic-1.0.0' was expected From schema: Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml interrupt-controller@f0c00000: '#address-cells' is a required property From schema: Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml Fix this by correcting the order of the compatible values, and adding the missing #address-cells property. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-03-26 17:19:01 +01:00
Geert Uytterhoeven	610bfe4d0c	tools/litex_json2dts: Fix DTS indentation ... - Replace bogus TAB by spaces, - Drop spaces from empty lines. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-03-26 17:19:01 +01:00
Florent Kermarrec	6b482bce54	tools/litex_json2dts/framebuffer: Switch to new simplified Video Framebuffer. ... Timings are already pre-initialized, so software will only have to configure/modify them to change the video resolution.	2021-03-26 16:25:06 +01:00
Florent Kermarrec	137274dfe0	integration/soc/add_video_framebuffer: Use mem_map for video base address (or defaults to 0x4800000) and pass constants to software.	2021-03-26 16:23:30 +01:00
Florent Kermarrec	ed1d29958a	cores/video/VideoFrameBuffer: Fix colors ordering.	2021-03-26 16:22:12 +01:00
Florent Kermarrec	714903e65b	cores/video/VideoTerminal: Write CSI interpreter color to term_mem (\e[92;1m\e[0m decoding working).	2021-03-26 11:15:27 +01:00
Florent Kermarrec	18f77ef378	cores/video/VideoTerminal: Also do a CLEAR-X after RST-X (Fix issue with lines displayed with previous contents).	2021-03-26 10:35:02 +01:00
Florent Kermarrec	438eec0268	integration/soc/add_sdcard: Re-Remove self.csr.add (was a false alarm, this also works with Linux-on-LiteX-Rocket).	2021-03-26 08:45:32 +01:00
Gabriel Somlo	c859c34844	json2dts.py: fix mac0 reg property style for consistency ... Assuming "#[address|size]-cells = <1>", both of the following are equivalent: reg = <start1 size1>, <start2 size2>, ..., <startN sizeN>; reg = <start1 size1 start2 size2 ... startN sizeN>; The second form appears more widely used and popular, including in the output of json2dts.py, with the exception of the mac0 node, which uses the first form. This patch makes output generated for mac0 consistent with that for other DT nodes.	2021-03-25 15:50:12 -04:00
Florent Kermarrec	58701cc48c	tools/litex_client: Use CSR base as base address on PCIe designs.	2021-03-25 18:25:37 +01:00
enjoy-digital	518aaeaacb	Merge pull request #863 from Dolu1990/master ... cpu/vexriscv_smp add RVC support	2021-03-25 16:26:30 +01:00
Florent Kermarrec	4246f77a97	integration/soc/add_scard: Revert use of self.csr.add since to avoid breaking Linux driver that currently relies on implicit ordering (but probably shoudln't :)).	2021-03-25 14:54:34 +01:00
Dolu1990	e755a02b84	cpu/vexriscv_smp add RVC support	2021-03-25 14:17:19 +01:00
Florent Kermarrec	aad56a047a	integration/soc: Use CSR automatic allocation.	2021-03-25 10:09:54 +01:00
Florent Kermarrec	aa9eb1f6a3	integration/soc: Add CSR automatic allocation and enable it by default. ... Un-allocated CSRs were already automatically detected so when un-allocated we can just simply allocate them automatically instead of raising an error. This also allows simplifying user's code since self.csr.add/self.add_csr will no longer be required.	2021-03-25 09:49:59 +01:00
Florent Kermarrec	3def6ae985	integration/soc: Be sure all add_xy methods use check_if_exists, improve Video integration.	2021-03-25 09:29:33 +01:00
Florent Kermarrec	c9ac5424f4	integration/soc: Cosmetic cleanup pass.	2021-03-25 09:13:43 +01:00
Florent Kermarrec	6e23fb1d99	integration/soc: Move Identifier import to add_identifier.	2021-03-25 08:47:05 +01:00
Florent Kermarrec	e1b20a934a	integation/soc: Move VideoXY imports to add_video_xy.	2021-03-25 08:45:55 +01:00
Florent Kermarrec	1b9eefbee4	integration/soc: Move Timer import to add_timer.	2021-03-25 08:43:52 +01:00
Florent Kermarrec	01fdca9149	integration/soc: Move SPIMaster import to add_spi_sdcard.	2021-03-25 08:42:23 +01:00
Florent Kermarrec	5229727c2b	integration/soc: Move SpiFlash import to add_spi_flash.	2021-03-25 08:40:53 +01:00
Florent Kermarrec	c60938d7aa	integration/soc/ethernet: Simplify timing constraints.	2021-03-25 08:36:37 +01:00
Florent Kermarrec	e27330b0d9	integration/soc: Replace self.add_csr with self.csr.add.	2021-03-25 08:23:39 +01:00
Florent Kermarrec	36bb069b8b	interconnect/packet: Minor cleanup.	2021-03-24 18:04:20 +01:00
Florent Kermarrec	6c640b0693	compat/stream_sim: Remove TODO since will not be done.	2021-03-24 17:58:13 +01:00
Florent Kermarrec	9eb318e86a	soc/interconnect/stream_sim: Move to compat to prevent since no longer really used or recommended on new designs.	2021-03-24 17:56:21 +01:00
Florent Kermarrec	bc8974dad1	litex_sim: Switch to soc_core_args/soc_core_argdict.	2021-03-24 17:26:48 +01:00
Florent Kermarrec	ee36138f75	compat: Fix (only triggers notice when used) and enable SoCSDRAM compat.	2021-03-24 17:21:26 +01:00
Florent Kermarrec	50ed5e262d	integration/soc_core: Move L2/SDRAM arguments soc_core_args.	2021-03-24 17:21:22 +01:00
Florent Kermarrec	ad63f8edc8	compat: Add Retro-Compat for litex.soc.cores.up5kspram (that has now moved to litex.soc.cores.ram).	2021-03-24 17:21:18 +01:00
Florent Kermarrec	f7f277548e	Compat: Add litex.compat to handle retro-compatibility on API changes and move integration/soc_sdram to it. ... Compat Notice is not yet enabled for soc_sdram since targets first need to be updated.	2021-03-24 17:21:13 +01:00
enjoy-digital	cc02055b42	Merge pull request #859 from Dolu1990/master ... soc/cores/cpu/vexriscv_smp cpu per fpu ratio	2021-03-24 08:03:38 +01:00
Dolu1990	391a4429dc	soc/cores/cpu/vexriscv_smp add cpu_per_fpu option to change the ratio core count and FPU	2021-03-23 20:05:28 +01:00
Jędrzej Boczar	bea82efc5d	gtkwave: fix error when prefix is empty, make treeopen optional	2021-03-23 10:08:06 +01:00
Florent Kermarrec	9113c1a2f9	cores/gpio/GPIOIRQ: Add mode CSR (Edge or Change) and rename polarity CSR to edge. ... Allow interrupts on Change, Rising Edge or Falling Edge.	2021-03-20 21:49:12 +01:00
enjoy-digital	c2f65b2b04	Merge pull request #850 from Dolu1990/master ... cpu/vexriscv_smp add FPU support	2021-03-19 09:08:44 +01:00
enjoy-digital	db353526c1	Merge pull request #853 from mczerski/liteeth_slots ... liteeth: allow to specify nrxslots and ntxslots for liteeth	2021-03-19 08:58:44 +01:00
Florent Kermarrec	d0c4199096	cores/gpio: Fix GPIOIRQ. ... Compilation tested in Arty with: from litex.soc.cores.gpio import GPIOIn self.submodules.gpio_in = GPIOIn(platform.request("user_sw", 0), with_irq=True) self.add_csr("gpio_in") self.add_interrupt("gpio_in")	2021-03-18 19:05:12 +01:00
enjoy-digital	1bb4507d93	Merge pull request #846 from enjoy-digital/axi-lite-downconverter-fix ... interconnect/axi: Fix AXILiteDownverterWrite/Read base address.	2021-03-18 18:15:52 +01:00
Florent Kermarrec	8460523f27	cores/video: Add VideoECP5HDMI PHY and move 10to1 Serializer to Generic, share it for Spartan6/ECP5.	2021-03-18 14:43:21 +01:00
Florent Kermarrec	e5695f9934	cores/video: Add VideoS6HDMIPHY (using stream.Gearbox for 10:2 convertion).	2021-03-18 13:49:50 +01:00
Florent Kermarrec	c01284fa23	integration/soc/add_video_colorbars: Review/Fix #849 (Fix ColorBarsPattern clock domain).	2021-03-18 13:48:53 +01:00
Florent Kermarrec	675349055b	inteconnect/stream: Increase io_lcm size when io_lcm/i_dw or io_lcm/o_dw < 2. ... Allow supporting all cases.	2021-03-18 13:47:10 +01:00
Marek Czerski	d7c0b4c111	dts: gpio: interrupt controller definition for switches ... This commit adds support for enabling interupts in switches module. Declaring switches as GPIOIn module with with_irq=True will make dts generation add correct interrupt controller definition. Also, if SWITCHES_NGPIO constant is defined it will be used to specify correct number of gpios in dts. example: self.submodules.switches = GPIOIn(pads=switches_pads, with_irq=True) self.add_csr("switches") self.irq.add("switches", use_loc_if_exists=True) self.add_constant("SWITCHES_NGPIO", len(switches_pads))	2021-03-18 09:52:07 +01:00
Marek Czerski	6eaa426e37	liteeth: allow to specify nrxslots and ntxslots for liteeth	2021-03-18 09:24:48 +01:00
Dolu1990	6b387eb579	cpu/vexriscv_smp add FPU support	2021-03-17 13:20:45 +01:00
enjoy-digital	a166a8dba3	Merge pull request #849 from hansfbaier/add-video-colorbars ... video: convenience method to add color bar pattern	2021-03-16 12:51:27 +01:00
Florent Kermarrec	c071bb4ac7	software/liblitesdcard: Check sdcard_wait_data_done in sdcard_switch/sdcard_app_send_scr since requesting a data read transfer.	2021-03-16 12:44:00 +01:00
Hans Baier	f86c743c58	video: convenience method to add color bar pattern	2021-03-16 12:35:58 +07:00
Florent Kermarrec	04cb8e0e5e	cores/xadc: Review/Cleanup PR#838, rename _XADC to SystemMonitorDRP and USSYSMON to USSystemMonitor.	2021-03-15 10:35:10 +01:00
enjoy-digital	367b510590	Merge pull request #838 from jersey99/ussysmon ... Ussysmon: SYSMONE1 for US devices	2021-03-15 10:19:54 +01:00
Florent Kermarrec	13e13a094c	soc/interconnect/axi: Add AXILite Clock Domain Crossing module.	2021-03-15 10:18:12 +01:00
Benjamin Henrion	0456de50aa	Add support for xcompiler on Alpine 3.13 ... Problem: xcompiler on Alpine 3.13 was not found Solution is to add "riscv-none-elf-gcc": 1. Add Edge to your repositories: $ echo -e "http://dl-cdn.alpinelinux.org/alpine/edge/main\nhttp://dl-cdn.alpinelinux.org/alpine/edge/testing\nhttp://dl-cdn.alpine linux.org/alpine/edge/community" >> /etc/apk/repositories $ apk update $ apk add gcc-riscv-none-elf 2. The xcompiler should be found at: $ which riscv-none-elf-gcc /usr/bin/riscv-none-elf-gcc	2021-03-12 20:13:23 +01:00
Florent Kermarrec	1e9606f3fb	software/liblitedram: Improve find_cmd_delay to favor higher number of valid modules and centered scan. ... Also add an optional debug #define to look at cmd/clk centering scans: __ _ __ _ __ / / (_) /____ | |/_/ / /__/ / __/ -_)> < /____/_/\__/\__/_/|_| Build your hardware, easily! (c) Copyright 2012-2020 Enjoy-Digital (c) Copyright 2007-2015 M-Labs BIOS built on Mar 12 2021 14:06:20 BIOS CRC passed (116682af) Migen git sha1: 7014bdc LiteX git sha1: edcc0f88 --=============== SoC ==================-- CPU: VexRiscv @ 125MHz BUS: WISHBONE 32-bit @ 4GiB CSR: 32-bit data ROM: 64KiB SRAM: 8KiB L2: 8KiB SDRAM: 1048576KiB 64-bit @ 1000MT/s (CL-7 CWL-6) --========== Initialization ============-- Initializing SDRAM @0x40000000... Switching SDRAM to software control. Write leveling: tCK/4 taps: 6 Cmd/Clk scan (0-12) |Cmd/Clk delay: 0 m0: |11000000000000011111111111| delay: 15 m1: |00000000000000111111111111| delay: 14 m2: |11110000000000000111111111| delay: 17 m3: |11110000000000000011111111| delay: 18 m4: |11111111110000000000000111| delay: - m5: |11111111110000000000000111| delay: - m6: |11111111111000000000000001| delay: - m7: |11111111111000000000000011| delay: - Delay mean: 22, ideal: 13 Cmd/Clk delay: 1 m0: |11100000000000001111111111| delay: 16 m1: |10000000000000011111111111| delay: 15 m2: |11111000000000000011111111| delay: 18 m3: |11111000000000000001111111| delay: 19 m4: |11111111111000000000000011| delay: - m5: |11111111111000000000000011| delay: - m6: |11111111111100000000000000| delay: - m7: |11111111111100000000000001| delay: - Delay mean: 23, ideal: 13 Cmd/Clk delay: 2 m0: |11110000000000000111111111| delay: 17 m1: |11000000000000001111111111| delay: 16 m2: |11111100000000000001111111| delay: - m3: |11111100000000000000111111| delay: - m4: |11111111111100000000000001| delay: - m5: |11111111111100000000000001| delay: - m6: |11111111111110000000000000| delay: - m7: |11111111111110000000000000| delay: - Delay mean: 22, ideal: 13 Cmd/Clk delay: 3 m0: |11111000000000000011111111| delay: 18 m1: |11100000000000000111111111| delay: 17 m2: |11111110000000000000111111| delay: - m3: |11111110000000000000011111| delay: - m4: |11111111111110000000000000| delay: - m5: |11111111111110000000000000| delay: - m6: |01111111111111000000000000| delay: 01 m7: |01111111111111000000000000| delay: 01 Delay mean: 15, ideal: 13 Cmd/Clk delay: 4 m0: |11111100000000000001111111| delay: - m1: |11110000000000000011111111| delay: 18 m2: |11111111000000000000011111| delay: - m3: |11111111000000000000001111| delay: - m4: |11111111111111000000000000| delay: - m5: |11111111111111000000000000| delay: - m6: |00111111111111100000000000| delay: 02 m7: |00111111111111100000000000| delay: 02 Delay mean: 13, ideal: 13 Cmd/Clk delay: 5 m0: |11111110000000000000111111| delay: - m1: |11111000000000000001111111| delay: 19 m2: |11111111100000000000001111| delay: - m3: |11111111100000000000000111| delay: - m4: |01111111111111100000000000| delay: 01 m5: |01111111111111100000000000| delay: 01 m6: |00011111111111110000000000| delay: 03 m7: |00011111111111110000000000| delay: 03 Delay mean: 11, ideal: 13 Cmd/Clk delay: 6 m0: |11111111000000000000011111| delay: - m1: |11111100000000000000111111| delay: - m2: |11111111110000000000000111| delay: - m3: |11111111110000000000000011| delay: - m4: |00111111111111110000000000| delay: 02 m5: |00011111111111110000000000| delay: 03 m6: |00001111111111111000000000| delay: 04 m7: |00001111111111111000000000| delay: 04 Delay mean: 9, ideal: 13 Cmd/Clk delay: 7 m0: |11111111100000000000001111| delay: - m1: |11111110000000000000011111| delay: - m2: |11111111111000000000000011| delay: - m3: |11111111111000000000000001| delay: - m4: |00011111111111111000000000| delay: 03 m5: |00001111111111111000000000| delay: 04 m6: |00000111111111111100000000| delay: 05 m7: |00000111111111111100000000| delay: 05 Delay mean: 10, ideal: 13 Cmd/Clk delay: 8 m0: |11111111110000000000000111| delay: - m1: |11111111000000000000001111| delay: - m2: |11111111111100000000000001| delay: - m3: |11111111111100000000000000| delay: - m4: |00001111111111111100000000| delay: 04 m5: |00000111111111111100000000| delay: 05 m6: |00000011111111111110000000| delay: 06 m7: |00000011111111111110000000| delay: 06 Delay mean: 11, ideal: 13 Cmd/Clk delay: 9 m0: |11111111111000000000000011| delay: - m1: |11111111100000000000000111| delay: - m2: |11111111111110000000000000| delay: - m3: |11111111111110000000000000| delay: - m4: |00000111111111111110000000| delay: 05 m5: |00000011111111111110000000| delay: 06 m6: |00000001111111111111000000| delay: 07 m7: |00000001111111111111000000| delay: 07 Delay mean: 12, ideal: 13 Cmd/Clk delay: 10 m0: |11111111111100000000000011| delay: - m1: |11111111110000000000000011| delay: - m2: |01111111111111000000000000| delay: 01 m3: |01111111111111000000000000| delay: 01 m4: |00000011111111111111000000| delay: 06 m5: |00000001111111111111000000| delay: 07 m6: |00000000111111111111100000| delay: 08 m7: |00000000111111111111100000| delay: 08 Delay mean: 11, ideal: 13 Cmd/Clk delay: 11 m0: |11111111111110000000000001| delay: - m1: |11111111111000000000000001| delay: - m2: |00111111111111100000000000| delay: 02 m3: |00111111111111100000000000| delay: 02 m4: |00000001111111111111100000| delay: 07 m5: |00000000111111111111100000| delay: 08 m6: |00000000011111111111110000| delay: 09 m7: |00000000011111111111110000| delay: 09 Delay mean: 12, ideal: 13 | best: 11 Setting Cmd/Clk delay to 11 taps. Data scan: m0: |11111111111110000000000001| delay: - m1: |11111111111000000000000001| delay: - m2: |00111111111111100000000000| delay: 02 m3: |00111111111111100000000000| delay: 02 m4: |00000001111111111111100000| delay: 07 m5: |00000000111111111111100000| delay: 08 m6: |00000000011111111111110000| delay: 09 m7: |00000000011111111111110000| delay: 09 Write latency calibration: m0:6 m1:6 m2:6 m3:6 m4:6 m5:6 m6:6 m7:6 Read leveling: m0, b0: |00000000000000000000000000000000| delays: - m0, b1: |00000000000000000000000000000000| delays: - m0, b2: |00000000000000000000000000000000| delays: - m0, b3: |11111111100000000000000000000000| delays: 04+-04 m0, b4: |00000000000001111111110000000000| delays: 17+-04 m0, b5: |00000000000000000000000000111111| delays: 29+-03 m0, b6: |00000000000000000000000000000000| delays: - m0, b7: |00000000000000000000000000000000| delays: - best: m0, b03 delays: 04+-04 m1, b0: |00000000000000000000000000000000| delays: - m1, b1: |00000000000000000000000000000000| delays: - m1, b2: |00000000000000000000000000000000| delays: - m1, b3: |11111111000000000000000000000000| delays: 04+-04 m1, b4: |00000000000011111111100000000000| delays: 16+-04 m1, b5: |00000000000000000000000000111111| delays: 29+-03 m1, b6: |00000000000000000000000000000000| delays: - m1, b7: |00000000000000000000000000000000| delays: - best: m1, b04 delays: 16+-04 m2, b0: |00000000000000000000000000000000| delays: - m2, b1: |00000000000000000000000000000000| delays: - m2, b2: |00000000000000000000000000000000| delays: - m2, b3: |11111110000000000000000000000000| delays: 03+-03 m2, b4: |00000000000111111111000000000000| delays: 15+-04 m2, b5: |00000000000000000000000011111111| delays: 28+-04 m2, b6: |00000000000000000000000000000000| delays: - m2, b7: |00000000000000000000000000000000| delays: - best: m2, b04 delays: 15+-04 m3, b0: |00000000000000000000000000000000| delays: - m3, b1: |00000000000000000000000000000000| delays: - m3, b2: |00000000000000000000000000000000| delays: - m3, b3: |11111110000000000000000000000000| delays: 03+-03 m3, b4: |00000000001111111110000000000000| delays: 14+-04 m3, b5: |00000000000000000000000011111111| delays: 28+-04 m3, b6: |00000000000000000000000000000000| delays: - m3, b7: |00000000000000000000000000000000| delays: - best: m3, b04 delays: 14+-04 m4, b0: |00000000000000000000000000000000| delays: - m4, b1: |00000000000000000000000000000000| delays: - m4, b2: |00000000000000000000000000000000| delays: - m4, b3: |10000000000000000000000000000000| delays: - m4, b4: |00001111111110000000000000000000| delays: 08+-04 m4, b5: |00000000000000000111111111000000| delays: 22+-05 m4, b6: |00000000000000000000000000000001| delays: 31+-00 m4, b7: |00000000000000000000000000000000| delays: - best: m4, b04 delays: 08+-04 m5, b0: |00000000000000000000000000000000| delays: - m5, b1: |00000000000000000000000000000000| delays: - m5, b2: |00000000000000000000000000000000| delays: - m5, b3: |00000000000000000000000000000000| delays: - m5, b4: |00001111111110000000000000000000| delays: 08+-04 m5, b5: |00000000000000000011111111000000| delays: 22+-04 m5, b6: |00000000000000000000000000000001| delays: 31+-00 m5, b7: |00000000000000000000000000000000| delays: - best: m5, b04 delays: 08+-04 m6, b0: |00000000000000000000000000000000| delays: - m6, b1: |00000000000000000000000000000000| delays: - m6, b2: |00000000000000000000000000000000| delays: - m6, b3: |00000000000000000000000000000000| delays: - m6, b4: |00111111110000000000000000000000| delays: 06+-04 m6, b5: |00000000000000111111111000000000| delays: 18+-04 m6, b6: |00000000000000000000000000001111| delays: 30+-02 m6, b7: |00000000000000000000000000000000| delays: - best: m6, b05 delays: 19+-04 m7, b0: |00000000000000000000000000000000| delays: - m7, b1: |00000000000000000000000000000000| delays: - m7, b2: |00000000000000000000000000000000| delays: - m7, b3: |00000000000000000000000000000000| delays: - m7, b4: |01111111111100000000000000000000| delays: 06+-05 m7, b5: |00000000000000011111111110000000| delays: 20+-05 m7, b6: |00000000000000000000000000001111| delays: 30+-02 m7, b7: |00000000000000000000000000000000| delays: - best: m7, b04 delays: 06+-05 Switching SDRAM to hardware control. Memtest at 0x40000000 (2MiB)... Write: 0x40000000-0x40200000 2MiB Read: 0x40000000-0x40200000 2MiB Memtest OK Memspeed at 0x40000000 (2MiB)... Write speed: 40MiB/s Read speed: 33MiB/s --============== Boot ==================-- Booting from serial... Press Q or ESC to abort boot completely. sL5DdSMmkekro Timeout No boot medium found --============= Console ================--	2021-03-12 14:34:49 +01:00
Florent Kermarrec	3cbdc567ff	soc: Add init_rom to initialize ROM and contents and with auto_size option (enable by default) to reduce ROM size to length of contents when in Read Only mode. ... This ensures the integrated ROM is reduced to minimal size before build and avoid having to adjust it manually with --integrated-rom-size on targets.	2021-03-12 09:42:59 +01:00
Florent Kermarrec	d9b6d7608c	soc/integration/soc_core: Cleanup SoCCore arguments.	2021-03-12 09:03:17 +01:00
Florent Kermarrec	21273ffe87	soc/integration/builder: Cleanup and add comments.	2021-03-11 16:21:45 +01:00
enjoy-digital	cba4642444	Merge pull request #845 from meklort/meklort/xics-fix ... xics: Disable endianness swapping	2021-03-11 13:33:15 +01:00
Florent Kermarrec	a81d1da980	soc/integration/common: Improve get_mem_data error reporting.	2021-03-11 10:19:36 +01:00
Florent Kermarrec	26f55797cc	software/liblitedram: Make sure init_error is set before init_done. ... Useful for standalone core where the user logic can be looking at init_done/init_error to condition user accesses.	2021-03-10 19:41:02 +01:00
Florent Kermarrec	da1277021a	build/generic_platform: Minor cosmetic cleanups.	2021-03-10 19:21:02 +01:00
Florent Kermarrec	10eff37b84	interconnect/axi: Fix AXILiteDownverterWrite/Read base address. ... Downconverter should start on master's addr, not on aligned master's addr.	2021-03-10 18:54:02 +01:00
Evan Lojewski	08072eb872	xics: Disable endianness swapping ... The endianess swapping code caused the core to diverge from microwatt resulting in: - The xics tests not working as-is: https://github.com/antonblanchard/microwatt/blob/master/tests/xics/xics.h - byte writes writing to the incorrect byte This removes endianswapping and minimizes the delta from upstream for the xics irq.h header.	2021-03-10 07:39:19 -07:00
Evan Lojewski	c92e4cb3ca	xics: Ass missing static keywords to irq header.	2021-03-10 07:32:24 -07:00
Florent Kermarrec	9d08c65e8a	build/generic_platform: Make sure default_clk_period constraint is only applied when default_clk_period exists. ... In simulation, default_clk_period is not necessarily required.	2021-03-10 12:25:35 +01:00
enjoy-digital	ee2d373477	Merge pull request #843 from gregdavill/monitor_token_fix ... cores/stream/monitor: Fix typo	2021-03-10 11:00:55 +01:00
Florent Kermarrec	e48b269d77	build/generic_platform: Fix use_default_clk set when not user provided sys_clk. ... Prevented the default timing constraint to be generated in the timing constraint file.	2021-03-10 10:47:22 +01:00
Greg Davill	31cc7f1e42	cores/stream/monitor: Fix typo	2021-03-10 09:11:07 +10:30
Florent Kermarrec	0e7d8219ea	soc/cores/gpio: Simplify GPIOIn IRQ, make polarity configurable and also add optional IRQ to GPIOTristate. ... Ex of instance: from litex.soc.cores import gpio gpio_in_pads = Signal(16) self.submodules.gpio_in = gpio.GPIOIn(gpio_in_pads, with_irq=True) self.add_csr("gpio_in")	2021-03-09 13:57:48 +01:00
Florent Kermarrec	0d8b6f8fbb	csr_eventmanager/EventSourceProcess: Add Rising Edge support and Falling/Rising selection.	2021-03-09 13:55:43 +01:00
Florent Kermarrec	ece9005949	cpu/vexriscv/core: Rename timer_enabled parameter to with_timer (for consistency with codebase) and disable timer by default (since increasing resources and causing issue on some iCE40 designs).	2021-03-09 09:07:52 +01:00
gatecat	c64e2d3a85	build/radiant: Skip location constraint for X pins ... Signed-off-by: gatecat <gatecat@ds0.me>	2021-03-08 14:27:32 +00:00
Florent Kermarrec	5af8e5c934	soc/add_etherbone: Fix UDPIPCore clock domain (should still run at eth_clk even if Etherbone is running in sys_clk) since data-width convertion is done on UDP.	2021-03-08 13:50:22 +01:00
Vamsi Vytla	6bb0541f9a	Remove ussysmon.py as it is consolidated inside xadc.py	2021-03-06 14:31:24 -08:00
Florent Kermarrec	a1e54671be	sim/serial2console: Remove \r workaround since no longer required and generating double carrier return in simulation.	2021-03-06 17:36:21 +01:00
Florent Kermarrec	7e3912aaef	software/demo: Make hellocpp optional (only build with --with-cxx) to avoid adding g++ as a dependency for an optional feature.	2021-03-06 17:31:07 +01:00
Vamsi Vytla	647d3eb51a	soc/cores/xadc.py: Move ussysmon here	2021-03-06 08:14:13 -08:00
Florent Kermarrec	31ac6659c9	cores/video: Add VideoS7HDMIPHY for Xilinx 7-Series.	2021-03-05 14:30:28 +01:00
Florent Kermarrec	9624cce188	cores/video: Mode VideoVGAPHY/VideoDVIPHY and add separators.	2021-03-05 14:27:08 +01:00
Florent Kermarrec	0280a9dd57	soc/add_video_framebuffer: Pass clock_domain to VideoFrameBuffer.	2021-03-05 14:23:39 +01:00
Florent Kermarrec	8b531b4215	cores: Add code_tmds with TMDS Encoder from Mixxeo/LiteVideo.	2021-03-04 19:32:41 +01:00
Florent Kermarrec	10d87e4138	cores/video/VideoPHYs: Use IO primitives.	2021-03-04 18:22:34 +01:00
Florent Kermarrec	82d0ecd7bd	cores/video/VideoTerminal: Add CLEAR-XY after reset.	2021-03-04 17:55:37 +01:00
Florent Kermarrec	a1e7aab35c	cores/clock/xilinx_usp/USPIDELAYCTRL: Apply USIDELAYCTRL's changes.	2021-03-04 14:42:50 +01:00
Florent Kermarrec	60e2d3335f	cores/clock/xilinx_us: Remove USP modules (refactoring issue).	2021-03-04 14:42:03 +01:00
Florent Kermarrec	2d5b4b206b	bios: Add VideoFrameBuffer VTG/DMA initialisation. ... This just configures the enables for now since other parameters are pre-configured during the build.	2021-03-04 12:01:32 +01:00
Florent Kermarrec	f553b5fc83	soc/cores/video: Improve/Cleanup VideoFrameBuffer, disable by default and modify default hres/vres to 800/600.	2021-03-04 11:59:44 +01:00
Florent Kermarrec	0ee92448b9	soc/cores/dma: Add default parameters to add_csr (similar to LiteDRAMDMAs), minor cosmetic cleanups and also add offset CSRStatus on WishboneDMAWriter (for symetry with WishboneDMAReader). ... Defaults parameters can allow the FPGA gateware to behave by itself after initialization while still being configurable by software.	2021-03-04 11:53:43 +01:00
Florent Kermarrec	225a518f7e	soc/cores/video: Move LiteDRAMDMAReader import to VideoFramerBuffer to avoid LiteDRAM dependency.	2021-03-04 08:40:47 +01:00
Vamsi Vytla	ae5f67f6f0	litex/soc/cores/ussysmon.py: minor bug	2021-03-03 14:47:52 -08:00
Vamsi Vytla	1793efb50b	litex/soc/cores/ussysmon.py: dadr address space bump	2021-03-03 14:38:27 -08:00
Florent Kermarrec	ccc8916995	soc/cores/video: Add initial (and simple) VideoFrameBuffer core.	2021-03-03 19:58:11 +01:00
Vamsi Vytla	922f85e64b	litex/soc/cores/ussysmon.py: ADC transfer function	2021-03-03 10:50:58 -08:00
Florent Kermarrec	24fb153fa1	soc/integration: Add add_video_terminal method to LiteXSoC. ... Adds the new LiteX's VideoTerminal core to the SoC: self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga") self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")	2021-03-03 17:45:02 +01:00
Florent Kermarrec	35ffba8801	soc/cores: Add simple VideoOut core with VideoTimingGenerator, Video Patterns, VideoTerminal, VideoDVIPHY and VideoVGAPHY.	2021-03-03 16:17:12 +01:00
Florent Kermarrec	c5ee6741a0	software/liblitedram: Use new DQS delay reset procedure on Ultrascale(+) (by increments).	2021-03-03 11:32:43 +01:00
Florent Kermarrec	d3407c67b1	build/sim/core: Cast main_time to vluint64_t to avoid ambiguity error of the dump function to be used.	2021-03-03 09:25:54 +01:00
Florent Kermarrec	134c628357	cores/spi_flash: Minor cosmetic cleanups, SpiFlashQuadReadWrite has also been moved to the end with a Note since should probably be re-factored.	2021-03-03 09:15:51 +01:00
Florent Kermarrec	61dcd1e8fd	soc/cores/led: Minor cosmetic cleanups.	2021-03-03 09:02:41 +01:00
Florent Kermarrec	19b1e50cbd	soc/cores/icap: Minor cosmetic cleanups.	2021-03-03 09:01:41 +01:00
Florent Kermarrec	e6f1d677e7	soc/cores/freqmeter: Minor cosmetic cleanups.	2021-03-03 08:59:51 +01:00
Florent Kermarrec	ce5e3e3b93	soc/cores/ecc: Minor cosmetic cleanups.	2021-03-03 08:55:37 +01:00
Florent Kermarrec	2fd7451fc9	soc/cores/code_8b10b: Minor cosmetic cleanups.	2021-03-03 08:54:31 +01:00
Florent Kermarrec	2e531e0ec7	soc/cores/dna: Add separator/comment.	2021-03-03 08:49:47 +01:00
Vamsi Vytla	71f7ce6a57	soc/cores/ussysmon.py: Xilinx XADC like thingy for UltraScale devices	2021-03-02 20:31:52 -08:00
Sergiu Mosanu	7fd39235af	Merge pull request #1 from hplp/cppdemo ... demo with basic C and C++ examples	2021-03-02 01:31:46 -05:00
Sergiu Mosanu	769f36d468	extend demo with basic C and C++ examples	2021-03-02 01:28:21 -05:00
David Jablonski	ceb8a6502c	VexRiscv: More general mem_map	2021-02-25 10:36:43 +01:00
Florent Kermarrec	6e883b4513	tools/litex_sim: Add boot to main_ram when sdram_init contents provided.	2021-02-25 09:10:26 +01:00
Florent Kermarrec	8f5d2ba27f	tools/litex_sim: Disable SDRAM memtest when sdram_init contents provided. ... This avoid corrupting pre-initialized contents or disabling memtest manually.	2021-02-25 09:06:26 +01:00
Florent Kermarrec	80bd4ac4ec	bios: Add boot command to be able to boot directly from system memory. ... This is useful for un-usual boot sequences where the binaries are not loaded directly by the BIOS but externally (over a bridge for example). Example of use: $litex_sim $litex_bare_metal_demo --build-path=build/sim $litex_sim --ram-init=demo.bin Press Esc during the LiteX boot. litex> help LiteX BIOS, available commands: flush_cpu_dcache - Flush CPU data cache crc - Compute CRC32 of a part of the address space ident - Identifier of the system help - Print this help serialboot - Boot from Serial (SFL) romboot - Boot from ROM reboot - Reboot boot - Boot from Memory mem_speed - Test memory speed mem_test - Test memory access mem_copy - Copy address space mem_write - Write address space mem_read - Read address space mem_list - List available memory regions litex> litex> mem_list Available memory regions: ROM 0x00000000 0x8000 SRAM 0x01000000 0x2000 MAIN_RAM 0x40000000 0x10000000 CSR 0x82000000 0x10000 litex> litex> boot 0x40000000 Executing booted program at 0x40000000 --============= Liftoff! ===============-- LiteX minimal demo app built Feb 24 2021 11:30:05 Available commands: help - Show this command reboot - Reboot CPU donut - Spinning Donut demo litex-demo-app>	2021-02-24 11:41:01 +01:00
enjoy-digital	c18ea700cc	Merge pull request #822 from antmicro/bios-dynamic-ip ... software/bios: add an option to change ip and mac address in runtime	2021-02-24 09:27:48 +01:00
Aleksandra Swierkowska	7abd66d710	bios/boot: add functions changing local and remote IP in runtime	2021-02-23 20:52:53 +01:00
Aleksandra Swierkowska	1c8df130b4	integration/soc.py: add parameter dynamic_ip to add_ethernet	2021-02-23 20:52:53 +01:00
Aleksandra Swierkowska	fc6b02d0da	libliteeth/udp: add udp_set_ip and udp_set_mac functions	2021-02-23 20:52:43 +01:00
Florent Kermarrec	91cebb5159	cpu/microwatt: Set XICS_ICS's SRC_NUM to 16. ... Expected to be 16 in xics.vhdl: assert SRC_NUM = 16 report "Fixup address decode with log2";	2021-02-22 10:57:31 +01:00
Florent Kermarrec	a51bf60712	cpu/microwatt: Only add XICS for IRQ variants (fix standard variant).	2021-02-22 10:31:08 +01:00
enjoy-digital	d5c2f6760c	Merge pull request #824 from scanakci/blackparrot_litex ... Update BlackParrot Readme	2021-02-22 10:23:25 +01:00
sadullah	96d9971abe	Update BlackParrot Readme	2021-02-20 22:58:34 -05:00
Robert Wilbrandt	251cea5647	Add constants to SVD export	2021-02-20 21:16:45 +01:00
Florent Kermarrec	7513460572	integration/soc/add_pcie: add with_msi parameter to allow disabling MSI when not required. ... When just doing a PCIe to Wishbone Bridge (PCIeBone), DMAs and MSI are not required, with_msi will allow disabling MSI when set to False.	2021-02-19 11:35:49 +01:00
Florent Kermarrec	d4edc132c1	tools/remote/comm_pcie: fix typo.	2021-02-19 10:33:04 +01:00
Florent Kermarrec	b47160c74e	tools/litex_term: replace CrossoverUART with BridgeUART for more genericity, rework bridge/jtag args. ... The CrossoverUART was in fact a particular UART connected to a second UART. Being able to have access to multiple UARTs over a Bridge can be useful for several purposes, ex: SoC0 --> UART0 + JTAGBone + litex_term bridge --bridge-name=UART0 SoC1 --> UART1 +--> SoC --> UARTBone --> LiteX-Server + litex_term bridge --bridge-name=UART1 SoC2 --> UART2 + EtherBone + litex_term bridge --bridge-name=UART2	2021-02-18 18:02:05 +01:00
Florent Kermarrec	6ac410a462	cores/uart/UARTCrossover: increase rx_fifo_depth to allow speeding up litex_term.	2021-02-18 17:55:53 +01:00
Florent Kermarrec	fc83a9281a	interconnect/csr: remove address wrapping within a CSRBank. ... To minimize logic, decoding inside a CSRBank to limited to the CSRs inside the bank and could wraps since partially decoded: For example, accessing SoCController on addresses still on the CSRBank defined for real CSRs produced: litex> mem_read 0x82000000 128 Memory dump: 0x82000000 00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00 ....xV4......... 0x82000010 00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00 ....xV4......... 0x82000020 00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00 ....xV4......... 0x82000030 00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00 ....xV4......... 0x82000040 00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00 ....xV4......... 0x82000050 00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00 ....xV4......... 0x82000060 00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00 ....xV4......... 0x82000070 00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00 ....xV4......... This is generally not an issue on most of the systems, but it could confuse user or produce un-wanted behaviour when bus data-width converter are used. With this change, the address is fully decoded, which removes the address wrapping: litex> mem_read 0x82000000 128 Memory dump: 0x82000000 00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00 ....xV4......... 0x82000010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 0x82000020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 0x82000030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 0x82000040 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 0x82000050 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 0x82000060 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 0x82000070 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ Resource usage increase seems minimal.	2021-02-18 14:44:50 +01:00
Florent Kermarrec	12bdf43958	soc/cores/ecc: cosmetic cleanups.	2021-02-18 10:00:27 +01:00
Florent Kermarrec	7ce5aef428	soc/cores/led: add add_pwm method to allow adjusting brightness dynamically (or not). ... LedChaser without PWM: self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) self.add_csr("leds") Add PWM to it (with default values: 50% duty cycle): self.leds.add_pwm() Add PWM with custom default values (25% duty cycle here): self.leds.add_pwm(default_width=128, default_period=1024) Then adjust brightness dynamically from the BIOS or your software: $cat csr.csv: csr_register,leds_out,0x82003000,1,rw csr_register,leds_pwm_enable,0x82003004,1,rw csr_register,leds_pwm_width,0x82003008,1,rw csr_register,leds_pwm_period,0x8200300c,1,rw Set PWM to 0%: $mem_write 0x82003008 0 Set PWM to 25%: $mem_write 0x82003008 256 Set PWM to 50%: $mem_write 0x82003008 512 Set PWM to 75%: $mem_write 0x82003008 768 Set PWM to 100%: $mem_write 0x82003008 1024 You can also only use default values and disable CSR is dynamic configuration is not required (with_csr=False) or adjust PWM period if want to use a specific PWM period in your system.	2021-02-18 09:47:30 +01:00
Florent Kermarrec	fc282b3084	soc/cores/pwm: add configurable default enable/width/period values.	2021-02-18 09:39:18 +01:00
Florent Kermarrec	908e72e65b	cores/uart: rewrite RS232PHYTX/RX (with FSM and comments) and optimize resource usage (~100LCs).	2021-02-17 15:04:14 +01:00
enjoy-digital	7c7f540488	Merge pull request #821 from jersey99/master ... build/xilinx/vivado.py: Allow a tcl script to be added as ip	2021-02-17 08:12:09 +01:00
Florent Kermarrec	82c1f5dccb	litex_setup/ibex: add pythondata-misc-opentitan to litex_setup and use it for Ibex CPU.	2021-02-17 08:07:07 +01:00
Florent Kermarrec	285bb96278	cores/uart/RS232PHY: add with_dynamic_baudrate parameter and disable it by default. ... Dynamic baudrate is rarely used and enabling it has a non negligeable cost (~100LCs).	2021-02-16 20:00:43 +01:00
Florent Kermarrec	9a8a8c0fe5	software/liblitedram: remove SDRAM_PHY_WRITE_LEVELING_REINIT no longer required on Ultrascale(+).	2021-02-16 16:26:34 +01:00
Vamsi Vytla	385dec8560	Merge remote-tracking branch 'upstream/master'	2021-02-15 09:29:47 -08:00
Vamsi Vytla	1fde282291	build/xilinx/vivado.py: Allow a tcl script to be added as ip. These tcl scripts tend to generate .xci's on the fly. The tcl script can be looked up in the vivado console as the ip is generated	2021-02-15 09:29:00 -08:00
Gabriel Somlo	927fd675bc	sdclk: additional halving to prevent clock going "too fast" ... When the system/bus clock frequency is an exact power-of-2 multiple of the desired sdcard frequency, we can drive the latter at the "maximum" speed via the "perfect" divider. That sometimes turns out too fast, so in order to be conservative, we double the divider, thus halving the resulting sdclock.	2021-02-15 09:24:02 -05:00
Gabriel Somlo	b03f46ffec	soc: increase sdcard data/cmd timeout (from default 10e-3) ... This allows the Linux driver in single-block mode (cmd17-only) to operate solidly, without running into timeouts from LiteSDCard FSMs. FIXME: multi-block (cmd18) transfers still time out, so revisit this after some additional debugging.	2021-02-15 09:23:52 -05:00
enjoy-digital	07dd680a3e	Merge pull request #818 from tcal-x/vexLiteMul ... Vexriscv "lite" uses "--mulDiv true", so enable "mul" instructions.	2021-02-15 15:02:47 +01:00
Florent Kermarrec	510bda4c99	cores/cpu: add initial lowRISC's Ibex support (without interrupts). ... Working in simulation and on hardware: litex_sim --cpu-type=ibex, ./target.py --cpu-type=ibex. This is currently doing a git clone of ibex and opentitan repositories but we'll create a pythondata-cpu-ibex package in the future. litex_sim --cpu-type=ibex: __ _ __ _ __ / / (_) /____ | |/_/ / /__/ / __/ -_)> < /____/_/\__/\__/_/|_| Build your hardware, easily! (c) Copyright 2012-2020 Enjoy-Digital (c) Copyright 2007-2015 M-Labs BIOS built on Feb 15 2021 11:57:50 BIOS CRC passed (e7517f7b) Migen git sha1: 7014bdc LiteX git sha1: ead12df2 --=============== SoC ==================-- CPU: Ibex @ 1MHz BUS: WISHBONE 32-bit @ 4GiB CSR: 32-bit data ROM: 32KiB SRAM: 8KiB MAIN-RAM: 262144KiB --============== Boot ==================-- Booting from serial... Press Q or ESC to abort boot completely. sL5DdSMmkekro Timeout No boot medium found --============= Console ================--	2021-02-15 12:02:25 +01:00
Tim Callahan	5cb467cae3	Vexriscv "lite" uses "--mulDiv true", so enable "mul" instructions. ... Signed-off-by: Tim Callahan <tcal@google.com>	2021-02-14 14:16:14 -08:00
Florent Kermarrec	ead12df21b	soc/cores/gpio: review/simplify #810. ... Use irqs dict and "rise", "fall" strings instead of Enums: Ex: pads=Signal(8), irqs={} : 8-bit Input, No IRQ. pads=Signal(8), irqs={0: "rise", 7: "fall"}: 8-bit Input, rising IRQ on 0, falling IRQ on 1. Also simplify the logic.	2021-02-12 16:21:01 +01:00
enjoy-digital	89454d2df3	Merge pull request #810 from antmicro/gpio_interrupts ... Add support for interrupts on GPIOIn	2021-02-12 15:51:25 +01:00
Geert Uytterhoeven	d91262e85c	software/demo: Drop bogus "the" in README ... Fixes: e7e28f2438 ("Change wording of demo README") Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-02-12 15:15:55 +01:00
enjoy-digital	0366a03c87	Merge pull request #813 from antmicro/jboc/lpddr4 ... software/bios: add option to disable BIOS prompt	2021-02-12 14:08:34 +01:00
Nick Østergaard	e7e28f2438	Change wording of demo README ... Change wording of demo README to make it more clear what the process is and how things related. This should help the newcomer and it still usefull for the triained. Change the command example to be more copy paste friendly. Fixes #814	2021-02-11 21:35:02 +01:00
Jędrzej Boczar	5f1edccd2e	software/bios: add option to disable BIOS prompt	2021-02-11 10:49:45 +01:00
Florent Kermarrec	041aa9bf6f	soc/cores/clock/xilinx_us/USIDELAYCTRL: make sure sys clock domain is reseted when reference clock domain is reseted.	2021-02-09 19:06:49 +01:00
Florent Kermarrec	126dd267d6	soc/interconnect/axi/AXIInterface: add optional tkeep.	2021-02-09 16:27:48 +01:00
Robert Szczepanski	15b3d932a4	gpio: add support for interrupts on GPIOIn	2021-02-09 15:29:31 +01:00
enjoy-digital	018094abb2	Merge pull request #809 from stffrdhrn/mor1kx-smp ... cpu/mor1kx: Add initial SMP support to cpu core	2021-02-09 09:54:49 +01:00
enjoy-digital	95b310ee0f	Merge pull request #807 from antmicro/revert-bitstream-device-changes ... build/xilinx/symbiflow: fix bitstream_device select	2021-02-09 09:26:48 +01:00
Stafford Horne	2f2b047f2e	cpu/mor1kx: Add initial SMP support to cpu core ... In order for mor1kx to run an SMP kernel shadow registers must be enabled. This patch adds two new variants: - linux+smp - basic linux + smp support - linux+smp+fpu - linux with FPU and smp support	2021-02-09 07:06:07 +09:00
Jan Kowalewski	ad760d491c	build/xilinx/symbiflow: fix bitstream_device select ... Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>	2021-02-08 15:38:30 +01:00
Geert Uytterhoeven	84e5130ac5	software/bios/console: Call putsnonl() from puts() ... puts() and putsnonl() are very similar, and can share code. Reduce code size by making the former call the latter. Impact for a RISC-V build: $ size console.o.orig console.o text data bss dec hex filename 868 0 12 880 370 console.o.orig 832 0 12 844 34c console.o Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-02-08 14:05:31 +01:00
Geert Uytterhoeven	8e4202ced1	software/bios/readline: Fix warnings if char is signed ... When building with --cpu-type=mor1kx: litex/soc/software/bios/readline.c: In function 'readline': litex/soc/software/bios/readline.c:271:3: warning: case label value exceeds maximum value for type [-Wswitch-outside-range] 271 | case KEY_END: | ^~~~ litex/soc/software/bios/readline.c:297:3: warning: case label value exceeds maximum value for type [-Wswitch-outside-range] 297 | case KEY_DEL: | ^~~~ litex/soc/software/bios/readline.c:281:3: warning: case label value exceeds maximum value for type [-Wswitch-outside-range] 281 | case DEL: | ^~~~ The C standard does not specify the signedness of "char", hence this depends on the implementation. On e.g. RISC-V, "char" is unsigned, but on OpenRISC, it is signed. Fix this by making the "ichar" variable explicitly unsigned. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-02-08 14:05:31 +01:00
Florent Kermarrec	5430c1455e	software/demo: add support for absolute/relative --build-path and simplify comment.	2021-02-08 10:29:26 +01:00
Hans Baier	7dae0aa09b	litex_term: support Intel/Altera nios2-terminal	2021-02-08 11:42:37 +07:00
Hans Baier	6f63fc104e	demo: more helpful usage message	2021-02-06 07:15:12 +07:00
Florent Kermarrec	5cb9f487a2	tools/litex_server: remove JTAGUART's binary_mode parameter (we are now only supporting binary_mode).	2021-02-05 12:38:20 +01:00
Florent Kermarrec	468b916a4f	tools/litex_term: add --jtag-config parameter to select OpenOCD JTAG configuration file.	2021-02-05 09:43:32 +01:00
Florent Kermarrec	4f15be746c	tools/litex_term: always use binary mode (for jtag_uart and jtagbone) and remove parameter. ... Fix jtag_uart regression and allow serialboot.	2021-02-05 09:40:21 +01:00
enjoy-digital	92f4cd1423	Merge pull request #799 from antmicro/add_xc7a200t_to_symbiflow ... build/xilinx: add xc7a200t-sbg484-1 to symbiflow toolchain	2021-02-04 16:41:45 +01:00
enjoy-digital	0006efe6ea	Merge pull request #800 from geertu/doc-sphinx-v1-fix ... doc: Fix doc build with Sphinx v1.x	2021-02-04 12:24:49 +01:00
Florent Kermarrec	4d1deffbb0	jtagbone/openocd: add binary mode on JTAGUART to fix "\n" to "\r" remapping that is not wanted in binary mode.	2021-02-04 11:44:43 +01:00
Geert Uytterhoeven	af13f43e60	doc: Fix doc build with Sphinx v1.x ... When building the linux-on-litex-vexriscv documentation with Sphinx v1.8.5: Sphinx error: master file linux-on-litex-vexriscv/build/orangecrab/doc/contents.rst not found The default value of "master_doc" was changed from "contents" to "index" in Sphinx v2[1]. As the LiteX doc system creates "index.rst", it thus fails to build with Sphinx v1.x. Explicitly configure "master_doc" to "index", to make it work with all versions of Sphinx, regardless of the default. [1] https://www.sphinx-doc.org/ca/latest/usage/configuration.html?highlight=master_doc Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-02-04 09:40:04 +01:00
Jan Kowalewski	57915db746	build/xilinx: add xc7a200t-sbg484-1 to symbiflow toolchain ... Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>	2021-02-03 15:18:48 +01:00
Jędrzej Boczar	b1fb141d1f	Fix gtkwave.py to be compatible with python 3.6	2021-02-02 11:14:16 +01:00
Florent Kermarrec	ba7c503fb6	tools/litex_sim: move gtkw import to generate_gtkw_savefile. ... This fixes litex_sim use with python 3.6 and raise an error when --gtkwave-savefile is used with python 3.6.	2021-02-02 10:13:23 +01:00
enjoy-digital	659751d202	Merge pull request #795 from antmicro/jboc/gtkwave-savefiles ... Add automatic generator of GTKWave savefiles	2021-02-02 09:59:18 +01:00
enjoy-digital	2f907d6e1e	Merge pull request #790 from antmicro/jboc/8phases ... software/liblitedram: support PHYs with more than 4 DFI phases	2021-02-02 09:43:17 +01:00
enjoy-digital	d76e0dcede	Merge pull request #791 from antmicro/jboc/init-mr ... software/liblitedram: selectable write leveling MR (for LPDDR4 support)	2021-02-02 09:36:31 +01:00
Geert Uytterhoeven	7b3737f531	cpu/vexriscv_smp: Make sbt failures fatal ... When using a non-default VexRiscv cluster config, the netlist for that config needs to be generated. This requires sbt to be installed. If sbt is missing, an error message is printed: sh: 1: sbt: not found This message may easily be lost in the noise, as the build continues, and fails later with: ERROR: Can't open input file `litex/pythondata-cpu-vexriscv-smp/pythondata_cpu_vexriscv_smp/verilog/VexRiscvLitexSmpCluster_Cc1_Iw32Is4096Iy1_Dw32Ds4096Dy1_Ood_Wm.v' for reading: No such file or directory Make the root cause more visible by raising an OSError, and aborting the build. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-02-01 13:54:59 +01:00
Jędrzej Boczar	fc9ef4c255	litex_sim: add --gtkwave-savefile argument with example signals	2021-02-01 13:22:30 +01:00
Jędrzej Boczar	01b900f4e0	Add GTKWave savefile generator	2021-02-01 13:22:30 +01:00
Florent Kermarrec	8623536a8a	build/generic_platform: avoid removing X pins from named_sc. ... We need them on Gowin FPGAs with embedded SDRAM where SDRAM pins are not real IOs.	2021-02-01 13:12:25 +01:00
Florent Kermarrec	f324f9531a	build/gowin: Don't generate IO_LOC is pin name is X.	2021-02-01 13:08:37 +01:00
enjoy-digital	fd33e360fb	Merge pull request #792 from euryecetelecom/master ... Add flash method to openFPGALoader class	2021-01-30 21:35:09 +01:00
Konstantin	3f27253ccc	cores/clock/lattice_ice40: add missing AsyncResetSynchronizer import.	2021-01-30 18:25:19 +01:00
Guillaume REMBERT	18a5ace637	Add flash method to openFPGALoader class for support with generic_programmer usage (needed for linux-on-litex-vexriscv) + add offset/address support for firmware load	2021-01-30 13:20:30 +01:00
enjoy-digital	69307cfdde	Merge pull request #789 from antmicro/jboc/litex-sim-fix-name ... litex_sim: fix old name: get_cl_cw -> get_default_cl_cwl	2021-01-29 19:13:34 +01:00
Jędrzej Boczar	61e605da92	litex_sim: fix old name: get_cl_cw -> get_default_cl_cwl	2021-01-29 11:31:40 +01:00
Florent Kermarrec	2287f73937	tools/litex_client: add --read/--write args to do simple MMAP accesses to SoC bus. ... ex reading/writing to scratch register over jtagbone: In the SoC: self.add_jtagbone() Open LiteX Server: litex_server --jtag Do the MMAP accesses: ./litex_cli --read 0x4 0x12345678 ./litex_clk --write 0x4 0x5aa55aa5 ./litex_cli --read 0x4 0x5aa55aa5	2021-01-28 17:46:18 +01:00
Jędrzej Boczar	38b819c42a	software/liblitedram: selectable write leveling MR (for LPDDR4 support)	2021-01-28 15:56:13 +01:00
Jędrzej Boczar	e3172faad9	software/liblitedram: support PHYs with more than 4 DFI phases	2021-01-28 15:53:40 +01:00
Florent Kermarrec	7abfbd9825	tools/litex_json2dts/ethernet: add missing 'status = "okay";'. ... Was causing https://github.com/litex-hub/linux-on-litex-vexriscv/issues/178.	2021-01-27 11:52:04 +01:00
Florent Kermarrec	b8bcbc522f	integration/export/triple: use LITEX_ENV_CC_TRIPLE instead of TRIPLE. ... triple can be used internally, but is too generic as an environment variable.	2021-01-27 08:25:48 +01:00
enjoy-digital	f331ddace8	Merge pull request #780 from garytwong/triple-option ... integration/export: allow manually specifying toolchain triple.	2021-01-27 08:16:41 +01:00
Florent Kermarrec	2f89e0aecf	soc/do_finalize: check that crg.rst is a Signal before connecting to ctrl._reset.	2021-01-26 17:08:43 +01:00
Florent Kermarrec	cafe0944f1	soc/add_uartbone/add_jtagbone: improve phy naming and add uartbone_phy to CSR.	2021-01-26 15:46:55 +01:00
enjoy-digital	7479cbe71b	Merge pull request #784 from Acathla-fr/patch-1 ... Update comm_usb.py	2021-01-26 14:36:07 +01:00
Florent Kermarrec	331124dd23	tools/litex_server: add --jtag-config args to provide OpenOCD configuration file.	2021-01-26 14:32:36 +01:00
Florent Kermarrec	2e1b9ed948	tools/litex_server: rename --jtag-uart to --jtag.	2021-01-26 14:12:54 +01:00
Florent Kermarrec	531ce0e8b7	soc: create specific add_jtagbone method instead of integrating it in add_uartbnone. ... Creates a JTAG bridge in the SoC simply with self.add_jtagbone(), almost comes for free :)	2021-01-26 14:12:19 +01:00
Acathla-fr	a092d5b28f	Update comm_usb.py ... typo : csr_csr replaced by csr_csv	2021-01-26 12:34:08 +01:00
Florent Kermarrec	ed1da7ed1e	soc/add_pcie: expose max_pending_requests parameter. ... Being able to configure it is useful to find resource usage/performance compromise.	2021-01-26 10:59:22 +01:00
Florent Kermarrec	dd985cd1d0	integration/export: disable CSRField extract/read functions generation for csr.size > 32-bit.	2021-01-26 10:23:56 +01:00
Florent Kermarrec	2a542e150d	jtag_uart/openocd: switch to raw tcp socket and get litex_server --jtag-uart working.	2021-01-25 16:33:43 +01:00
Florent Kermarrec	7799765471	soc/jtag: run JTAGPHY in sys_jtag clock domain (to fix behavior after reset).	2021-01-25 16:31:55 +01:00
Florent Kermarrec	213644af70	integration/soc/add_uart: ResetInserter no longer required on UART since reboot is now doing a full system reset.	2021-01-25 13:39:45 +01:00
Florent Kermarrec	8cada67f32	cores/jtag: cleanup instances.	2021-01-25 12:31:32 +01:00
Florent Kermarrec	0b5df58a1b	cores/jtag: cores/uart: expose jtag/tx/rx_cdc (to ease probing with LiteScope).	2021-01-25 12:30:43 +01:00
Florent Kermarrec	4df336341b	cores/uart: expose fsm/timer (to ease probing with LiteScope).	2021-01-25 12:29:18 +01:00
Florent Kermarrec	17195c5e96	cpu/vexriscv_smp: cleanup new args integration and fix cluster naming.	2021-01-25 11:48:05 +01:00
enjoy-digital	7fa03cb1f3	Merge pull request #782 from enjoy-digital/vexriscv-smp-no-litedram ... soc/cpu/vexriscv-smp: add args to disable out of order or direct path to LiteDRAM	2021-01-25 08:45:03 +01:00
Florent Kermarrec	1a38d51e08	libbase/memtest: remove 0x no longer required with %p.	2021-01-24 21:09:19 +01:00
Dolu1990	ae2cd31573	soc/cpu/vexriscv-smp add --without-out-of-order-decode and --with-wishbone-memory	2021-01-23 20:38:50 +01:00
Florent Kermarrec	01a2fc11e2	integration/soc/usb_acm: run USB ACM in sys_usb clock domain similar to sys clock domain but with rst disconnected.	2021-01-22 22:57:24 +01:00
Gary Wong	13d1d4cf8e	integration/export: allow manually specifying toolchain triple. ... If the environment variable TRIPLE is defined, use its value as the highest priority candidate. Useful for testing new cross-compilers, or selecting among toolchains in a different priority than the built-in list.	2021-01-22 12:11:03 -07:00
Florent Kermarrec	8623b0a16a	integration/soc/add_uartbone: fix jtag_uart integration.	2021-01-22 15:00:13 +01:00
Florent Kermarrec	d7aedfbc12	tools/litex_server: add initial JTAG-UART support.	2021-01-22 14:19:38 +01:00
Florent Kermarrec	697ff7447c	soc/integration: add initial JTAG-UART support to UARTbone.	2021-01-22 14:19:03 +01:00
Florent Kermarrec	e8cfe3b6ea	software/liblitedram: fix typo.	2021-01-22 11:57:06 +01:00
enjoy-digital	f22079dc94	Merge pull request #776 from geertu/compiler-warning-fixes ... Compiler warning fixes	2021-01-22 09:28:23 +01:00
Florent Kermarrec	4e5f20a060	software/liblitedram: rename Half Sys8x Taps to tCK/4 and display "-" during write calibration when no valid bitstlip found.	2021-01-21 20:00:29 +01:00
Florent Kermarrec	57289dd47c	software/liblitedram/write_leveling: display Half Sys8x Taps value before write_leveling.	2021-01-20 09:43:53 +01:00
Florent Kermarrec	acb6741b8a	software/bios: rename CONFIG_SIM_DISABLE_DELAY to CONFIG_DISABLE_DELAYS and disable timeout on serialboot's check_ack when CONFIG_DISABLE_DELAYS is set. ... This is useful in simulation to skip serialboot ack check.	2021-01-20 09:42:29 +01:00
Geert Uytterhoeven	0f28bc489d	software/include/base/stdio: Enable printf format strings checks ... Now all format issues are fixed, tag all functions taking printf()-style format specifiers with "__attribute__((format(printf, ...))", enabling format string checks ("-Wall" includes "-Wformat"). Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-01-19 15:03:48 +01:00
Geert Uytterhoeven	c3dea1b9fd	software: Use "%p" to format pointer values ... To fix compiler warnings of the following type: warning: format '%x' expects argument of type 'unsigned int', but argument 2 has type 'foo *' [-Wformat=] Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-01-19 15:03:48 +01:00
Geert Uytterhoeven	19e7b53762	software: Use "l" length modifier to format long values ... To fix compiler warnings of the following type: warning: format '%x' expects argument of type 'unsigned int', but argument has type 'long unsigned int' [-Wformat=] Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-01-19 15:03:48 +01:00
Geert Uytterhoeven	a2389c71ea	software: Fix cast from pointer to integer of different size warnings ... litex/soc/software/liblitesdcard/sdcard.c: In function 'sdcard_read': litex/soc/software/liblitesdcard/sdcard.c:476:29: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] sdblock2mem_dma_base_write((uint64_t) buf); ^ litex/soc/software/liblitesdcard/sdcard.c: In function 'sdcard_write': litex/soc/software/liblitesdcard/sdcard.c:507:30: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] sdmem2block_dma_base_write((uint64_t) buf); ^ When casting a pointer (32-bit or 64-bit, depending on the platform) to a 64-bit integer, an intermediate cast to "uintptr_t" should be used to avoid warnings like the above. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-01-19 15:03:48 +01:00
Geert Uytterhoeven	5474f563c8	software/bios/readline: Use unsigned int for small numbers ... There is no need to use "unsigned long" for small numbers related to the number of characters in a line. Use "unsigned int" instead. This allows us to drop the casts when calling putnstr(), and fixes compiler warnings on 64-bit for callsites where the casts were missing: warning: field precision specifier '.*' expects argument of type 'int', but argument 2 has type 'long unsigned int' Reported-by: Gabriel Somlo <gsomlo@gmail.com> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-01-19 15:03:48 +01:00
Geert Uytterhoeven	ab8cee1b5e	software/bios/cmds/cmd_i2c: Use "%zu" to format size_t ... The sizeof operator returns "size_t", which is defined to be "unsigned int" on 32-bit, and "unsigned long" on 64-bit. Format it using "%zu", to fix compiler warnings of the following type on 64-bit: warning: format '%d' expects argument of type 'int', but argument has type 'long unsigned int' [-Wformat=] Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-01-19 15:03:48 +01:00
Geert Uytterhoeven	cbd54e7b5c	software/bios/cmds/cmd_bios: Make crc command 64-bit clean ... On 64-bit: litex/soc/software/bios/cmds/cmd_bios.c: In function 'crc_handler': litex/soc/software/bios/cmds/cmd_bios.c:110:30: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] printf("CRC32: %08x", crc32((unsigned char *)addr, length)); ^ Fix this by using the appropriate types (uintptr_t and size_t) for memory addresses and sizes, which are defined to 32-bit or 64-bit, depending on the platform. Note that the specified length must still be smaller than 4 GiB on 64-bit, or it will be truncated, as the crc32() function is currently limited to a 32-bit size anyway. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-01-19 15:03:48 +01:00
Geert Uytterhoeven	857ef69b3f	software/bios/boot: Fix cast to pointer from integer of different size warnings ... On 64-bit: litex/soc/software/bios/boot.c: In function 'serialboot': litex/soc/software/bios/boot.c:216:20: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] writepointer = (char *) get_uint32(&frame.payload[0]); ^ When casting from a 32-bit integer to a pointer (32-bit or 64-bit, depending on the platform), an intermediate cast to "uintptr_t" should be used to avoid warnings like the above. Note that using a 32-bit integer is OK, even on 64-bit, as this is specified by the boot protocol. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-01-19 15:03:48 +01:00
Geert Uytterhoeven	84e3a77724	software/liblitedram: Use "%u" to format uint32_t values ... To fix compiler warnings of the following type: warning: format '%lu' expects argument of type 'long unsigned int', but argument has type 'unsigned int' [-Wformat=] Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-01-19 15:03:48 +01:00
Geert Uytterhoeven	b979e69934	software/libbase: Remove empty printf statements ... To fix compiler warnings of the following type: warning: zero-length gnu_printf format string [-Wformat-zero-length] Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-01-19 15:03:48 +01:00
Geert Uytterhoeven	bff23b8f73	software/libbase/vsnprintf: Prefix pointers by "0x" ... Set the PRINTF_SPECIAL flag when printing pointers, so they are prefixed by "0x", to match glibc behavior. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-01-19 15:03:48 +01:00
Geert Uytterhoeven	91c9192626	software/include/base: Fix size_t, ptrdiff_t, and (u)intptr_t ... As per convention, the types of size_t, ptrdiff_t, intptr_t, and uintptr_t should be based on "long" or "int" depending on the platform (32-bit or 64-bit). This fixes compiler warnings of the following type: litex/soc/software/liblitesdcard/sdcard.c: In function 'sdcard_read': litex/soc/software/liblitesdcard/sdcard.c:476:39: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] sdblock2mem_dma_base_write((uint64_t)(uintptr_t) buf); ^ Reported-by: Gabriel Somlo <gsomlo@gmail.com> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-01-19 15:03:48 +01:00
Geert Uytterhoeven	1710c5f1ef	software/include/base/limits: Fix ULONG_MAX on 64-bit ... The value of ULONG_MAX should depend on the size of "long". While at it: - Add missing "UL" and "U" suffixes to large unsigned values, - Make INT_MIN and SHRT_MIN explicitly negative, - Use decimal instead of hexadecimal values, for easier comparison with /usr/include/limits.h. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-01-19 15:03:48 +01:00
Geert Uytterhoeven	e0786c3f94	software/include/base: Check __LP64__ instead of __WORDSIZE ... __WORDSIZE is defined by glibc, not by the compiler. Hence it is never defined for us, and checking __WORDSIZE to determine the size of "long" thus causes subtle misbehavings. Fix this by checking for the presence of __LP64__ instead. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-01-19 14:59:49 +01:00
Florent Kermarrec	41964f945c	litex_term/SFL: remove flashing capability. ... It's probably better not mixing uploading/flashing utilities. Flashing should be done with the proper bootloader (as we are doing on Fomu/OrangeCrab for example).	2021-01-18 16:47:47 +01:00
Florent Kermarrec	a0bcbeb68b	tools/litex_term: fully deprecate --no-crc argument.	2021-01-18 16:34:34 +01:00
Florent Kermarrec	2f5ad47f7a	tools/litex_term: fix get_args typo.	2021-01-18 16:30:27 +01:00
Florent Kermarrec	81f4ffafdb	build/tools/language_by_filename: add svo to system-verilog extensions.	2021-01-18 16:29:52 +01:00
enjoy-digital	2cb4f513f1	Merge pull request #775 from geertu/i2c-scan-fixes ... I2c scan fixes and cleanups	2021-01-15 17:50:20 +01:00
enjoy-digital	bf0f0176b3	Merge pull request #774 from antmicro/vex-debug ... CPU: Vex: add debug slave for dbg cpu variant	2021-01-15 17:49:33 +01:00
Geert Uytterhoeven	dc3306731c	software/bios/cmds/cmd_i2c: Simplify upper nibble calculation ... Use masking instead of division and multiplication. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-01-15 12:01:08 +01:00
Geert Uytterhoeven	28ed06f1c5	software/bios/cmds/cmd_i2c: Fix i2c_scan output ... "i2c_scan" prints random data instead of the intended slave address: 0x70: 10001ebc -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- instead of: 0x70: 70 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Fix this by adding the missing printf() parameter. Fixes: ee1ea9baab ("bios/cmd/cmd_i2c: make results similar to Linux's i2cdetect.") Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-01-15 12:01:08 +01:00
Karol Gugala	5d0c5d7088	CPU: Vex: add debug slave for dbg cpu variant ... Signed-off-by: Karol Gugala <kgugala@antmicro.com>	2021-01-15 09:28:03 +01:00
Florent Kermarrec	b1cad93e62	tools/litex_json2dts: add clock_frequency property to VexRiscv-SMP cpus. ... Required by some Linux drivers (SDCard for example).	2021-01-14 14:25:53 +01:00
Florent Kermarrec	50939fdd33	software/liblitedram/sdram_write_leveling: allow external configuration of cdly_range_start and cdly_range_end.	2021-01-14 13:18:10 +01:00
Florent Kermarrec	35a8b498a0	tools/litex_json2dts/sdcard: use sdphy base as csr base. ... To be similar with csr base defined used in linux-on-litex-rocket.	2021-01-14 09:28:06 +01:00
Florent Kermarrec	83fb79fb0c	tools/litex_term: review/simplify a bit PR #772.	2021-01-13 19:33:29 +01:00
William D. Jones	ce243820fe	tools/litex_term: Convert some common scan codes into ANSI codes on Windows.	2021-01-11 21:02:37 -05:00
William D. Jones	5babcadbed	tools/litex_term: Set ENABLE_VIRTUAL_TERMINAL_PROCESSING flag on Windows.	2021-01-11 19:54:21 -05:00
William D. Jones	bfc624f23e	tools/litex_term: Avoid importing termios and pty on Windows.	2021-01-11 14:51:55 -05:00
Florent Kermarrec	460fada3ac	tools/litex_term: revert LiteXTerm to threading (multiprocessing breaks Windows/OS-X). ... Ideally we should switch to AsyncIO as some point.	2021-01-11 19:29:15 +01:00
Florent Kermarrec	1ce194007b	software: allow BIOS compilation with UART disabled.	2021-01-08 19:18:44 +01:00
Florent Kermarrec	19fda3364a	tools/litex_term: fix 100% cpu load after refactoring (thanks sergpolkin).	2021-01-08 13:57:33 +01:00
Florent Kermarrec	5f9c4a4ab4	soc/cores/gpio: remove intermediate _pads signal.	2021-01-06 21:39:02 +01:00
Florent Kermarrec	0984308318	cores/gpio: add assertion on pads (has to be a Signal). ... Due to the bi-directional nature of tristate, Cat is not supported (so also not platform.request_all).	2021-01-06 09:56:56 +01:00
David Lattimore	875f34f8e2	Lattice NX: Allow up to 320KB of RAM	2021-01-06 09:45:08 +11:00
Florent Kermarrec	16008d3f3a	cpu/vexriscv/cpu-count: fix type and add comment (thanks dayjaby).	2021-01-04 14:43:08 +01:00
Florent Kermarrec	f31f9a20f0	boards: remove and switch to litex_boards. ... Keeping board definition files directly in LiteX is no longer useful since we are already relying on board definitions files from LiteX-Boards (https://github.com/litex-hub/litex-boards) in various benches/projects and having definitions files directly in LiteX creates confusion/additional work. For projects using board definition files from LiteX, the litex.boards import can just be replaced with litex_boards: from litex.boards.platforms import kc705 from litex_boards.platforms import kc705	2021-01-04 14:09:35 +01:00
William D. Jones	f65491c809	Use riscv32 gcc triples for picorv32- superset of riscv64 triples.	2020-12-31 03:22:56 -05:00
Florent Kermarrec	b9e0c95c18	cpu/microwatt: use 0xf9807b6 and fix compilation, working with IRQs :) ... Tested with: /arty.py --cpu-type=microwatt --cpu-variant=standard+irq --integrated-rom-size=0x10000 --build --load __ _ __ _ __ / / (_) /____ | |/_/ / /__/ / __/ -_)> < /____/_/\__/\__/_/|_| Build your hardware, easily! (c) Copyright 2012-2020 Enjoy-Digital (c) Copyright 2007-2015 M-Labs BIOS built on Dec 30 2020 15:59:16 BIOS CRC passed (fb76e85d) Migen git sha1: d42aa6f LiteX git sha1: 74844db3 --=============== SoC ==================-- CPU: Microwatt @ 100MHz BUS: WISHBONE 32-bit @ 4GiB CSR: 32-bit data ROM: 64KiB SRAM: 8KiB L2: 8KiB SDRAM: 262144KiB 16-bit @ 800MT/s (CL-6 CWL-5) --========== Initialization ============-- Initializing SDRAM @0x40000000... Switching SDRAM to software control. Write latency calibration: m0:0 m1:0 Read leveling: m0, b0: |00000000000000000000000000000000| delays: - m0, b1: |00000000000011111111111111100000| delays: 19+-07 m0, b2: |00000000000000000000000000001111| delays: 30+-02 m0, b3: |00000000000000000000000000000000| delays: - m0, b4: |00000000000000000000000000000000| delays: - m0, b5: |00000000000000000000000000000000| delays: - m0, b6: |00000000000000000000000000000000| delays: - m0, b7: |00000000000000000000000000000000| delays: - best: m0, b01 delays: 19+-07 m1, b0: |00000000000000000000000000000000| delays: - m1, b1: |00000000000011111111111111000000| delays: 19+-07 m1, b2: |00000000000000000000000000001111| delays: 30+-01 m1, b3: |00000000000000000000000000000000| delays: - m1, b4: |00000000000000000000000000000000| delays: - m1, b5: |00000000000000000000000000000000| delays: - m1, b6: |00000000000000000000000000000000| delays: - m1, b7: |00000000000000000000000000000000| delays: - best: m1, b01 delays: 19+-06 Switching SDRAM to hardware control. Memtest at 0x0000000040000000 (2MiB)... Write: 0x40000000-0x40200000 2MiB Read: 0x40000000-0x40200000 2MiB Memtest OK Memspeed at 0x0000000040000000 (2MiB)... Write speed: 32MiB/s Read speed: 54MiB/s --============== Boot ==================-- Booting from serial... Press Q or ESC to abort boot completely. sL5DdSMmkekro Timeout No boot medium found --============= Console ================-- litex>	2020-12-30 16:20:20 +01:00
Florent Kermarrec	74844db3b9	cores/cpu: add optional add_soc_components method and use it to add VexRiscv-SMP's PLIC/CLINT and Microwatt's XCIS. ... Also shorten XCIS name on Microwatt from HOSTXICS to XCIS.	2020-12-30 15:35:27 +01:00
Florent Kermarrec	49217ec6ea	cores/cpu/vexriscv_smp: minor cleanups.	2020-12-30 14:45:33 +01:00
Florent Kermarrec	a8ddbb190a	cores/cpu/vexriscv_smp: add standard variant (similar to Linux, avoid passing cpu-variant=linux when selection vexriscv_smp).	2020-12-30 14:41:54 +01:00
Florent Kermarrec	7bcebf4cdd	cpu/microwatt: improve/fix XICS controller integration for variants with irq.	2020-12-30 12:25:01 +01:00
Florent Kermarrec	0cba91022e	cpu/vexriscv_smp: move smp_slave to crt0. Fixes bare metal demo compilation with VexRiscv-SMP.	2020-12-30 11:56:11 +01:00
Florent Kermarrec	4f6bc32a5a	software/demo: make leds optional. ... Allow running demo directly with litex_sim: litex_sim (then exit with ctrl-c on BIOS prompt) litex_bare_metal_demo --build-path=build/sim/ litex_sim --ram-init=demo.bin	2020-12-30 11:25:32 +01:00
Florent Kermarrec	8ff26b7304	targets/arty: add variant support through --variant argument. ... ./arty.py --variant=a7-35 or a7-100	2020-12-29 18:45:41 +01:00
Florent Kermarrec	70d364cf4e	integration/soc: add software_debug parameter to add_ethernet, add_(spi)sdcard to ease enabling software debug traces from design.	2020-12-29 15:38:46 +01:00
Florent Kermarrec	c7056b77bb	tools/litex_json2dts/soc_controller: remove VexRiscv-SMP workaround now that we able to use upstream linux litex patches.	2020-12-29 12:25:38 +01:00
Florent Kermarrec	7627dadb9b	tools/litex_json2dts/soc_controller: add workaround for VexRiscv-SMP. ... We need to fix https://github.com/litex-hub/linux-on-litex-vexriscv/issues/176 to be able to switch to soc-controller with VexRiscv-SMP.	2020-12-29 09:29:23 +01:00
enjoy-digital	d5bf09d8f4	Merge pull request #747 from shenki/soc-controller-compatible ... dts: Fix soc controller compatible	2020-12-29 09:23:03 +01:00
Florent Kermarrec	bf32d23d9a	tools/litex_json2dts: add --polling args to allow forcing polling mode on peripherals. ... Can be useful for debug purpose or bring up of new hardware not yet supporting IRQs.	2020-12-29 09:03:35 +01:00
Florent Kermarrec	d9a44ce10f	tools/litex_json2dts: minor changes/cleanup on #745. ... - shorten args description. - avoid mixing initrd_start/initrd_start_offset: just use initrd_start and indicate it's relative. - others minor cleanups.	2020-12-29 08:36:55 +01:00
enjoy-digital	152ae03798	Merge pull request #745 from stffrdhrn/dts-interrupts ... RFC dts: Support generating interrupt config	2020-12-29 08:16:19 +01:00
Stafford Horne	a2c9b17959	dts: Allow specifying initrd position and size via args ... This is needed as my initrd size is much larger than the default 8mb. Also, sometimes the kernel I build is also large, so its good to be able to move the initrd starting position. Issue #748	2020-12-29 08:18:55 +09:00
Stafford Horne	5cc2c4aaf7	dts: Support generating interrupt config ... This addresses #744	2020-12-28 09:51:22 +09:00
Joel Stanley	13345bfe7f	dts: Fix soc controller compatible ... The version that landed upstream is spelt litex,soc-controller with a dash instead of an underscore. Signed-off-by: Joel Stanley <joel@jms.id.au>	2020-12-27 22:40:29 +10:30
rprinz08	c99c96bc68	Enable etherbone usage on multiple ethernet interfaces	2020-12-22 21:13:10 +01:00
Florent Kermarrec	1a338b602a	software/bios: add new mem_list command to list available memory regions. ... This is useful to know the memory regions available and use the mem_xy commands on them: List the memory regions: litex> mem_list Available memory regions: ROM 0x00000000 0x8000 SRAM 0x01000000 0x2000 MAIN_RAM 0x40000000 0x10000000 CSR 0x82000000 0x10000 Test 0x1000 bytes of MAIN_RAM: litex> mem_test 0x40000000 0x1000 Memtest at 0x40000000 (4KiB)... Write: 0x40000000-0x40001000 4KiB Read: 0x40000000-0x40001000 4KiB Memtest OK Test speed on 0x1000 bytes of MAIN_RAM: litex> mem_speed 0x40000000 0x1000 Memspeed at 0x40000000 (4KiB)... Write speed: 352KiB/s Read speed: 288KiB/s	2020-12-22 19:15:57 +01:00
Stafford Horne	3067c57080	mor1kx: Enable gcc compiler flag for cmov ... We enable this instruction so use it.	2020-12-22 22:10:42 +09:00
Stafford Horne	51327e00b5	mor1kx: Enable rotate, sign extend under linux, new fpu extension ... My thought is that if we are running linux the FPGA should be able to handle these extra instruction's footprint. Also, since we are running on linux there may be any kind of software running on the CPU, so allow handling these instructions. FPU is added bia a new +fpu extension. But really, I am running GLIBC tests and they run faster with this enabled.	2020-12-22 22:10:42 +09:00
Florent Kermarrec	d90d3e043b	software/liblitedram: add optional SDRAM_TEST_DISABLE that can be defined to full disable SDRAM test. ... This is useful in simulation where SDRAM contents is pre-initialized from files (ex Linux-on-LiteX-Vexriscv).	2020-12-22 10:50:15 +01:00
Florent Kermarrec	12dabde77c	integration/soc/add_ethernet: add phy_cd parameter to allow and demonstrate multiple PHYs support.	2020-12-22 09:03:00 +01:00
Florent Kermarrec	c79135c573	software/demo: add litex_bare_metal_demo pre-installed script. ... Build demo: litex_bare_metal_demo --build-path=build/arty/	2020-12-21 19:27:21 +01:00
Florent Kermarrec	4df56ed456	software/demo: add short README.	2020-12-21 18:44:10 +01:00
Florent Kermarrec	ef2ed8bbbc	tools/litex_json2dts: fix vexriscv-smp cpu reg numbering.	2020-12-21 18:16:44 +01:00
Florent Kermarrec	5ec5554713	tools/litex_json2dts: cleanup and reorganize peripherals.	2020-12-21 16:11:45 +01:00
Florent Kermarrec	df92e2aea7	tools/litex_json2dts: switch VexRiscv to SMP, update SDCard dts.	2020-12-21 16:11:32 +01:00
enjoy-digital	0a9c9562dc	Merge pull request #738 from antmicro/quartus-handle-includes ... Quartus: handle vh and svh files	2020-12-21 10:19:27 +01:00
Florent Kermarrec	90b9f4eca3	soc/interconnect/axi: fix AXIInterface.get_ios().	2020-12-21 08:51:04 +01:00
Karol Gugala	7f6af0a437	Quartus: handle vh and svh files ... Signed-off-by: Karol Gugala <kgugala@antmicro.com>	2020-12-20 11:53:08 +01:00
enjoy-digital	7fccf9fcd0	Merge pull request #736 from Disasm/ecpdap ... Add ECPDAP programmer	2020-12-18 15:39:24 +01:00
Florent Kermarrec	b7aec66929	soc/interconnect/axi: simplify AXI Full connect_to_pads and get_ios.	2020-12-18 15:35:04 +01:00
enjoy-digital	57d9816065	Merge pull request #734 from antmicro/axi4-slave-bridge ... Add get_ios for full AXI and add missing signals in connect_to_pads	2020-12-18 15:25:54 +01:00
enjoy-digital	9ae5a4f4ea	Merge pull request #735 from Dolu1990/vexriscv_smp ... cores/cpu/vexriscv_smp add AES support	2020-12-18 14:43:04 +01:00
enjoy-digital	f055b1be69	Merge pull request #732 from Disasm/ecp5-compress ... Add option for ECP5 bistream compression	2020-12-18 14:42:34 +01:00
Vadim Kaushan	0fe2477f69	Add ECPDAP programmer	2020-12-18 15:42:18 +03:00
Dolu1990	ee47c7b260	cores/cpu/vexriscv_smp add AES support	2020-12-18 12:10:33 +01:00
Piotr Binkowski	f26769eb4d	interconnect/axi: add connect_to_pads to full AXI	2020-12-18 09:06:45 +01:00
Piotr Binkowski	18e90234b0	interconnect/axi: add get_ios to full AXI	2020-12-18 08:59:11 +01:00
Vadim Kaushan	2bc76f3245	Add option for ECP5 bistream compression	2020-12-18 00:21:05 +03:00
Florent Kermarrec	4092180662	tools/lxterm/json: json file provide relative path, add json file directory to image names. ... Allow sharing same json file between serial boot and Ethernet/SDCard/SATAboot: boot.json: { "Image": "0x40000000", "rv32.dtb": "0x40ef0000", "rootfs.cpio": "0x41000000", "opensbi.bin": "0x40f00000" } If boot.json and images are located in images directory, using lxterm --images=images/boot.json will now work.	2020-12-17 16:08:32 +01:00
enjoy-digital	f777cddefe	Merge pull request #731 from lindemer/pmp ... Allow selection of VexRiscv_Secure* from lxsim CLI	2020-12-14 19:41:51 +01:00
Samuel Lindemer	c23a894014	Allow selection of VexRiscv_Secure* from lxsim CLI	2020-12-14 10:54:02 +01:00
Florent Kermarrec	bc2b7995f5	integration/export/get_csr_header: don't generate replace/write fields access functions when CSR is read only.	2020-12-14 10:51:37 +01:00
bunnie	649edd189a	Merge pull request #729 from betrusted-io/master ... another minor change - reveal STARTUPE2 block's ring oscillator	2020-12-13 02:19:56 +08:00
bunnie	422cc2baae	another minor change - reveal STARTUPE2 block's ring oscillator	2020-12-13 01:49:43 +08:00
Florent Kermarrec	fb3b09db15	integration/soc/add_uart: add crossover+bridge support. ... Useful to have both CPU UART and bridge debug capability.	2020-12-10 18:32:21 +01:00
Florent Kermarrec	88bd754dd6	software: add minimal baremetal demo app. ... Used to demonstrates how to easily create baremetal apps, boot to it with LiteX and also ease litex_term testing. To build it: export BUILD_DIR=xxyy/litex/litex/boards/targets/build/arty && make To load it: lxterm /dev/ttyUSB1 --kernel=demo.bin --============== Boot ==================-- Booting from serial... Press Q or ESC to abort boot completely. sL5DdSMmkekro [LXTERM] Received firmware download request from the device. [LXTERM] Uploading demo.bin to 0x40000000 (9264 bytes)... [LXTERM] Upload complete (9.8KB/s). [LXTERM] Booting the device. [LXTERM] Done. Executing booted program at 0x40000000 --============= Liftoff! ===============-- LiteX minimal demo app built Dec 10 2020 17:13:02 Available commands: help - Show this command reboot - Reboot CPU led - Led demo donut - Spinning Donut demo litex-demo-app> led Led demo... Counter mode... Shift mode... Dance mode... litex-demo-app> donut Donut demo... $$$$$@@@@@ $##########$$$$$$$$ ###*!!!!!!!!!***##$$$$$$ ***!!====;;;;===!!**###$$$$# **!===;;;:::::;:===!!**####$## !*!!==;;:~-,,.,-~::;;=!!**#######! !!!!=;:~-,.......-~::==!!***#####* !!!!==;~~-.........,-:;==!!***###**! !**!!=;:~-... ..-:;=!!!********! ;!*#####*!!;. ~:;==!!!******!!= :!*###$$$$#*! :;==!!!!!****!!!=; ~=!*#$$$@@@$$##!!!!!!!!!!!!****!!!!=; ;=!*#$$$@@@@$$#*******!*!!*!!!!!==;~ -;!*###$$$$$$$###******!!!!!!!===;~ -;!!*####$#####******!!!!!!==;;:- ,:=!!!!**#**#***!!!!!!!====;:~, -:==!!!*!!*!!!!!!!===;;;:~- .~:;;========;=;;:::~-, .--~~::::~:~~--,. litex-demo-app>	2020-12-10 17:16:28 +01:00
bunnie	ef6fd57613	Merge pull request #727 from betrusted-io/master ... fix a timing error in the S7 OPI block	2020-12-10 23:17:29 +08:00
Florent Kermarrec	ee41fbb338	tools: deprecate litex_jtag_uart (now directly integrated in litex_term).	2020-12-10 15:48:10 +01:00
bunnie	8ee0fdbf8e	fix a timing error in the S7 OPI block ... should have no impact on normal operation, the path is only for registering addresses that are correlated with ECC errors as reported by the OPI device.	2020-12-10 22:48:09 +08:00
Florent Kermarrec	39b84581f4	tools/litex_term: add JTAG UART support (litex_term jtag_uart).	2020-12-10 15:46:12 +01:00
Florent Kermarrec	384041affb	tools/litex_term/crossover: use burst to speed up reads.	2020-12-10 14:34:00 +01:00
Florent Kermarrec	48dc574703	integration/soc/add_uart: pass fifo_depth to UARTCrossover.	2020-12-10 14:33:29 +01:00
Florent Kermarrec	1976fd4b90	tools: deprecate litex_crossover_uart (now directly integrated in litex_term).	2020-12-10 13:54:21 +01:00
Florent Kermarrec	feeb2f72e0	tools/litex_term: add direct crossover UART bridge suppport (lxterm --crossover) and switch to multiprocessing.	2020-12-10 13:45:38 +01:00
Stéphane Gourichon	8a82ddf6e1	CSR fields: generate convenience functions (#725) ... Generate convenience methods to extract/replace bits in CSR fields, only generate replace if CSR register is writable.	2020-12-10 11:32:21 +01:00
Florent Kermarrec	cd80c87f1a	software/liblitedram/write_leveling: revert ideal_delay to 0, ensure write delay is set just before 0 to 1 transition.	2020-12-09 19:51:19 +01:00
Florent Kermarrec	5ebea9434b	software/liblitedram/sdram: improve comments.	2020-12-09 17:53:33 +01:00
enjoy-digital	44d21cb0f3	Merge pull request #722 from geertu/master ... tools/litex_json2dts: Miscellaneous fixes and improvements	2020-12-08 14:01:14 +01:00
enjoy-digital	a80398d2ab	Merge pull request #724 from sergachev/master ... soc/interconnect/axi: let connect_to_pads() be used by AXIInterface too	2020-12-08 13:45:12 +01:00
Florent Kermarrec	c6fb9ef939	software/liblitedram: limit clk/cmd scan to 1/2 tCK. ... Restrict the clk/cmd scan to 1/2 tCK since the full scan is not required and in some cases can compromise the calibration with the wrong best clk/cmd value selection. This should also allow using cmd_latency=0 in all cases.	2020-12-08 10:01:18 +01:00
Florent Kermarrec	c19c343ecf	software/libbase: add memtest_access before testing bus/addr/data to exit early if bus errors are detected.	2020-12-07 14:05:51 +01:00
Florent Kermarrec	fb05fbc5cc	software: always provide flush_l2_cache implementation (even if empty) to avoid #ifdefs CONFIG_L2_SIZE.	2020-12-07 13:45:05 +01:00
Florent Kermarrec	3ce74f6e29	software/libbase/memtest: cosmetic cleanups.	2020-12-07 13:23:58 +01:00
Ilia Sergachev	9af9ee6b66	soc/interconnect/axi: let connect_to_pads() be used by AXIInterface too	2020-12-06 00:23:30 +01:00
Florent Kermarrec	bed072ef19	tools/litex_term: use different payload_length/delay settings for USB-ACM.	2020-12-04 19:59:49 +01:00
Geert Uytterhoeven	d8b844bbda	tools/litex_json2dts: Group tuples in liteeth reg property ... To improve human readability and enable automatic validation, the tuples in "reg" properties should be grouped using angle brackets. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2020-12-04 16:38:48 +01:00
Geert Uytterhoeven	a17b535906	tools/litex_json2dts: Fix DTS indentation ... Make indentation of the generated DTS more consistent, by always using 8 spaces (no TABs), and aligning continued lines. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2020-12-04 16:21:52 +01:00
Geert Uytterhoeven	8265d06728	tools/litex_json2dts: Fix SPI bus #size-cells ... As per Documentation/devicetree/bindings/spi/spi-controller.yaml, "#size-cells" must be zero for a PCI bus. This gets rid of the following build warnings: build/orangecrab/orangecrab.dts:105.29-39: Warning (reg_format): /soc/spi@f0004800/mmc-slot@0:reg: property has invalid length (4 bytes) (#address-cells == 1, #size-cells == 1) buildroot/rv32.dtb: Warning (pci_device_reg): Failed prerequisite 'reg_format' buildroot/rv32.dtb: Warning (pci_device_bus_num): Failed prerequisite 'reg_format' buildroot/rv32.dtb: Warning (simple_bus_reg): Failed prerequisite 'reg_format' buildroot/rv32.dtb: Warning (i2c_bus_reg): Failed prerequisite 'reg_format' build/orangecrab/orangecrab.dts:91.46-110.19: Warning (spi_bus_bridge): /soc/spi@f0004800: incorrect #size-cells for SPI bus buildroot/rv32.dtb: Warning (spi_bus_reg): Failed prerequisite 'reg_format' buildroot/rv32.dtb: Warning (spi_bus_reg): Failed prerequisite 'spi_bus_bridge' Fixes: fafa844aa7 ("json2dts: Add Linux DT generation script") Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2020-12-04 16:19:29 +01:00
Florent Kermarrec	b7c0922ec1	tools/litex_term: increase outstanding to 128 (4 is slowing down speed with USB-FIFO).	2020-12-04 16:01:35 +01:00
Florent Kermarrec	894802d131	tools/litex_term: add sfl_outstanding parameter (set to 4), cleanup code and increase inter-frame delay. ... This fixes upload on OrangeCrab with USB-ACM, but we still need to understand why sfl_payload_length can't be set to 255 with USB-FIFO.	2020-12-04 15:46:18 +01:00
Florent Kermarrec	5e10552f3f	soc/interconnect/packet/Packetizer: fix last_be for 10gbe.	2020-12-03 17:11:04 +01:00
enjoy-digital	168c5380cf	Merge pull request #718 from trabucayre/zynq_fix_constraints ... don't add pins without pad location in constraints file	2020-12-03 16:21:06 +01:00
enjoy-digital	88023394fd	Merge pull request #721 from daveshah1/dave/nexus-pll-resetena ... clock/lattice_nx: Set PLLRESET_ENA parameter	2020-12-03 15:54:16 +01:00
Florent Kermarrec	dba6653cb4	tools/litex_term: reduce sfl_payload_length to 64 as before. ... See: https://github.com/enjoy-digital/litex/issues/720.	2020-12-03 12:52:00 +01:00
David Shah	90315868a8	clock/lattice_nx: Set PLLRESET_ENA parameter ... If this parameter isn't set to ENABLED; then the PLLRESET signal is ignored. Signed-off-by: David Shah <dave@ds0.me>	2020-12-03 11:49:48 +00:00
Florent Kermarrec	172dc18dfb	bios/boot: remove SFL_CMD_LOAD_NO_CRC support (non longer useful since CRC checking is now fast).	2020-12-03 12:11:48 +01:00
enjoy-digital	136db6a0ca	Merge pull request #719 from davidlattimore/no-error-recovery ... lxterm: Speed up CRC checked uploads	2020-12-03 12:06:46 +01:00
Florent Kermarrec	d6a49e85c4	integration/soc_core: only add IRQs from interrupt_map if SoC supports them.	2020-12-03 09:48:42 +01:00
Florent Kermarrec	42e7b8d35a	integration/soc/irq: improve error message.	2020-12-03 09:47:50 +01:00
David Lattimore	b421d50b40	lxterm: Increase maximum payload size to match BIOS ... sfl_frame (in sfl.h) already had a payload size of 255. This should give about a 10% speed gain due to reduced overhead. 8 bytes of header per 251 bytes sent, as opposed to 8 bytes of header per 60 bytes sent	2020-12-03 13:44:09 +11:00
David Lattimore	03c2257baf	lxterm: Deprecate --no-crc flag ... The flag is left, in case people are using it from scripts, but now does nothing besides printing a warning.	2020-12-03 13:37:43 +11:00
David Lattimore	513a799a39	lxterm: Don't attempt to recover from CRC errors during upload. ... This allows transfers to proceed at the full speed of the serial link. We still check all responses, but will now fail outright if a CRC error occurs.	2020-12-03 13:37:26 +11:00
Gwenhael Goavec-Merou	b896b20e46	don't add pins without pad location in constraints file	2020-12-02 13:24:15 +01:00
Florent Kermarrec	8eecbd7b57	integration/soc/add_sdcard: integrate interrupts.	2020-12-01 13:25:05 +01:00
Gabriel Somlo	5cc3db0176	soc: cosmetic: reduce horizontal indentation in IRQ init.	2020-11-30 16:29:16 -05:00
Gabriel Somlo	9af56cf247	soc: fix typo in IRQ handler exception	2020-11-30 16:27:31 -05:00
Florent Kermarrec	d193092e16	cores/cpu/cv32e40p/core: rewrite OBI2Wishbone to reduce write/read latency by 1 cycle.	2020-11-30 12:18:59 +01:00
Florent Kermarrec	18f66a79f2	cores/cpu/zynq7000: improve methods to pass provide/pass configuration to PS7. ... User can now only use set_ps7 and provides the .xci file, preset file or/and additional configuration: To use a .xci file, in the design do: self.cpu.set_ps7(xci="ps7.xci") To use a preset: self.cpu.set_ps7(preset="preset_name") To use a config dict: self.cpu.set_ps7(name="ps7_name", config={"param0": "0", "param1": "1"}) It's also possible to use preset and then pass and additionnal config dict: self.cpu.set_ps7(preset="preset_name") self.cpu.add_ps7_config({"param0": "0", "param1": "1"}) or all at once: self.cpu.set_ps7(preset="preset_name", config={"param0": "0", "param1": "1"})	2020-11-30 11:30:48 +01:00
enjoy-digital	30e8773819	Merge pull request #711 from trabucayre/ps7_config ... zynq7000: add tcl to create zynq IP based on board preset and custom configuration	2020-11-30 10:28:54 +01:00
Florent Kermarrec	c8fcaaea2d	integration/soc: use self.irq.enabled instead of hasattr(self.cpu, "interrupt").	2020-11-30 10:17:03 +01:00
Florent Kermarrec	146068b048	integration/soc/SoCIRQHandler: be sure IRQs can only be added when enabled. ... This prevents adding peripherals that requires IRQ support to SoC not supporting them. Enabling is done automatically when a CPU with interrupt support is added, but this can also be added manually.	2020-11-30 10:06:45 +01:00
gsomlo	d9f9b4aeb6	Merge pull request #713 from daveshah1/dave/rocket-reset-fix ... rocket: Fix UB due to optimised away DFFs	2020-11-28 08:12:33 -05:00
David Shah	61895bef37	rocket: Fix UB due to optimised away DFFs ... As both clock and async reset for the debug DFFs were 0, and there was no initial value on them, they were being validly optimised away by newer Yosys versions to 1'bx which was propagating into and breaking the core. This fixes the problem by tying the async resets to the CPU reset signal. Signed-off-by: David Shah <dave@ds0.me>	2020-11-28 11:15:42 +00:00
Florent Kermarrec	c491c60b7d	soc/cores/prbs/PRBSRX: add pause signal to pause errors counting. ... Simplify CDC when passing the errors to software by allowing the values to stabilized.	2020-11-28 11:33:57 +01:00
Florent Kermarrec	869e50ade8	soc/cores/prbs: minor cosmetic cleanups.	2020-11-28 10:27:22 +01:00
Florent Kermarrec	e2dcdcf917	build/lattice/programmer/load_bitstream: convert .bit to .svf with bit_to_svf it bitstream_file provided as .bit.	2020-11-28 08:58:57 +01:00
Florent Kermarrec	289234b102	build/lattice: add bit_to_svf script from Project Trellis to allow using OpenOCD with Diamond.	2020-11-28 08:58:04 +01:00
Gwenhael Goavec-Merou	08b6d0388c	zynq7000: add tcl to create zynq IP based on board preset and custom configuration	2020-11-28 08:56:47 +01:00
Florent Kermarrec	785bc7e86c	build/lattice/diamond: set timingstrict default value to False (similar to others build backends)	2020-11-28 07:56:30 +01:00
Florent Kermarrec	e5a7375b30	cores/clock/ECP5PLL: ensure ECP5PLL's locked is deasserted on reset. ... It seems EHXPLLL does not loose locked when reseted.	2020-11-26 18:56:24 +01:00
Florent Kermarrec	b02753ecfa	tools/comm_udp/litex_server: add --udp-scan args to scan network for available Etherbone/UDP devices. ... litex_server --udp --udp-scan --udp-ip=192.168.1.x --udp-port=1234 Etherbone scan on 192.168.1.x network: - 192.168.1.20 - 192.168.1.50	2020-11-26 13:33:20 +01:00
Florent Kermarrec	4a748a53b8	soc/interconnect/packet: add initial PacketFIFO. ... For now just ensures that we have a full packet in the FIFO before setting source.valid. It would be nice in the future to also be able to discard packets in the FIFO.	2020-11-26 11:27:42 +01:00
Florent Kermarrec	c3660379db	tools/remote/comm_udp: probe Etherbone server on open().	2020-11-26 09:06:52 +01:00
Florent Kermarrec	f390161baa	integration/soc/add_ethernet: don't add timing constraints with LiteEthPHYModel.	2020-11-26 09:06:06 +01:00
enjoy-digital	896d1ba988	Merge pull request #709 from daveshah1/oxide-build ... Add Yosys/nextpnr-nexus/oxide flow for CrossLink-NX	2020-11-25 19:21:11 +01:00
Florent Kermarrec	ad62e15d98	tools/litex_server: move PCIe specific bar renaming/enable to comm_pcie.	2020-11-25 16:25:31 +01:00
Florent Kermarrec	595c6738a3	tools/remote/etherbone: speed up encoding/decoding.	2020-11-25 16:08:12 +01:00
Florent Kermarrec	3d2574a488	tools/remote/comms: base CommXY on CSRBuilder to allow using Comms directly in python scripts. ... This way, user scripts can be use RemoteClient (communicating with the Server that has already been opened on the right interface) or directly use CommXY in the scripts. Using RemoteClient is more generic but can be slower (due to the Etherbone encoding between the client and server). On fixed configuration using CommXY directly can then be faster and also avoid manual opening of the server.	2020-11-25 15:05:28 +01:00
Florent Kermarrec	2c3687983c	tools/litex_server/client: cleanup.	2020-11-25 11:34:12 +01:00
Florent Kermarrec	fa9149720f	tools/remote/comm_udp: keep up to date with new encoding/decoding.	2020-11-25 11:33:44 +01:00
Florent Kermarrec	c003293b31	tools/remote/etherbone: simplify/speed up decoding.	2020-11-25 11:33:02 +01:00
David Shah	c0822bac1a	Add Yosys/nextpnr-nexus/oxide flow for CrossLink-NX ... Signed-off-by: David Shah <dave@ds0.me>	2020-11-25 09:44:51 +00:00
Florent Kermarrec	01e75addff	tools/remove/etherbone: simplify/speed up encoding.	2020-11-25 10:00:28 +01:00
Florent Kermarrec	2a1df9beeb	tools/remote/etherbone: replace merge_bytes with direct call to int.from_bytes.	2020-11-25 09:11:33 +01:00
Florent Kermarrec	4d5dca2d74	tools/remote/etherbone: replace split_bytes by direct call to int.to_bytes.	2020-11-25 09:07:58 +01:00
Florent Kermarrec	9b696373a2	tools/remove/etherbone: cosmetic cleanup, add assert for maximum burst size (255).	2020-11-25 08:53:11 +01:00
Robert Winkler	6684e7ae7a	symbiflow: restore add_false_path_constraint ... Restore the method to fix SymbiflowToolchain class API Signed-off-by: Robert Winkler <rwinkler@antmicro.com>	2020-11-24 15:34:32 +01:00
Florent Kermarrec	f918d0bf02	tools/remove: add 0x to hex debug prints.	2020-11-24 14:06:46 +01:00
Florent Kermarrec	cddf19df98	integration/soc/add_etherbone: expose buffer_depth.	2020-11-23 17:50:31 +01:00
enjoy-digital	a1bfa79092	Merge pull request #705 from betrusted-io/reset-docs ... correct the documentation for the ctrl reset register	2020-11-23 17:46:50 +01:00
bunnie	119062c068	Merge pull request #706 from betrusted-io/master ... add a hook for activating the GSR inside the STARTUPE2 block for spi_opi	2020-11-24 00:29:14 +08:00
bunnie	33f073a0a9	add a hook for activating the GSR inside the STARTUPE2 block for spi_opi	2020-11-24 00:27:18 +08:00
bunnie	4d7fe81a07	correct the documentation for the ctrl reset register	2020-11-24 00:19:05 +08:00
Alessandro Comodi	0431af729c	symbiflow: remove workarounds for symbiflow ... Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>	2020-11-23 10:33:11 +01:00
bunnie	8e39060d26	Merge pull request #701 from enjoy-digital/csr_eventmanager_cleanup ... interconnect/csr/EventManager: simpifly/cleanup code that documents C…	2020-11-20 03:24:09 +08:00
Florent Kermarrec	32989c17b6	soc: rename HAS_TIMESTAMP to WITH_BUILD_TIME.	2020-11-18 22:04:14 +01:00
enjoy-digital	1ac34bf5bf	Merge pull request #702 from antmicro/fix-disable-build-timestamp ... litex: soc: do not add the timestamp in the BIOS if it was disabled	2020-11-18 22:01:25 +01:00
Florent Kermarrec	9440975a1f	cores/ram: cosmetic cleanup.	2020-11-18 21:52:43 +01:00
Alessandro Comodi	3c0d41781f	litex: soc: do not add the timestamp in the BIOS if it was disabled ... Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>	2020-11-18 17:36:50 +01:00
Florent Kermarrec	444a605dea	build/xilinx: fix build with LITEX_ENV_VIVADO/LITEX_ENV_ISE set by user.	2020-11-18 15:40:15 +01:00
Florent Kermarrec	ee1ea9baab	bios/cmd/cmd_i2c: make results similar to Linux's i2cdetect.	2020-11-18 15:13:57 +01:00
Florent Kermarrec	470b6873ca	interconnect/csr/EventManager: simpifly/cleanup code that documents CSRs and always enable documentation. ... A read_only mode has been added to CSRStatus to allow enabling writes on pending register and get the written data used to clear events.	2020-11-18 13:06:55 +01:00
Florent Kermarrec	30b2f187f4	soc/integration/builder: add generate_doc parameter and --doc args to builder_args. ... This allows generating the documentation easily from target files with --doc.	2020-11-18 11:37:47 +01:00
enjoy-digital	b8b6fe2165	Merge pull request #699 from betrusted-io/document_events ... Create EventManager option for documented bits	2020-11-18 11:06:04 +01:00
Leon Schuermann	778afb45d2	Add SoC timer peripheral timer-uptime CLI parameter ... This allows enabling the uptime register in the timer core from the command line.	2020-11-17 23:29:11 +01:00
Jędrzej Boczar	3bd5d6cc0e	software/liblitedram: fix issues with command/write delays not being incremented.	2020-11-17 16:26:37 +01:00
bunnie	10256aa109	resolve xobs review comments	2020-11-17 05:10:16 +08:00
bunnie	377794748b	add API to turn on documentation in I2S block for interrupts	2020-11-17 04:55:46 +08:00
bunnie	3dc18efe70	make documented events optional	2020-11-15 23:18:46 +08:00
bunnie	5d6c851f32	try to fix issue with unnamed sources	2020-11-15 22:03:23 +08:00
bunnie	ea80e9ef32	improve documentation strings, try to handle unnamed events better	2020-11-15 21:50:26 +08:00
bunnie	6a0a896e96	improve documentation output	2020-11-15 17:07:33 +08:00
bunnie	6deb750d6e	Improve soc.svd output for eventmanager events ... Right now no data is created for which bit means what in the soc.svd file. Attempt to extend event manager finalization to use "fields" instead of bit positions, so that the SVD file can auto-generate the events correctly.	2020-11-15 16:33:14 +08:00
Florent Kermarrec	05f83ca978	tools/litex_term: minor cleanups (cosmetic).	2020-11-13 11:12:35 +01:00
Florent Kermarrec	5097b7ae5c	boards: keep up to date with litex-boards, remove pcie_screamer target.	2020-11-12 18:16:56 +01:00
Florent Kermarrec	103c7e90a5	integration/soc/LiteXSoC: add initial add_pcie integration method.	2020-11-12 16:07:40 +01:00
Florent Kermarrec	7a4b26d2ba	tools/litex_json2dts: fix missing {.	2020-11-12 14:45:46 +01:00
Florent Kermarrec	9c0f687922	build/generic_platform: use script filename as name when no Platform file.	2020-11-11 09:45:21 +01:00
Florent Kermarrec	275932f56c	gen/fhdl/verilog: improve clock domain error reporting.	2020-11-10 13:27:29 +01:00
Florent Kermarrec	2741fc2ba5	build/generic_programmer: add call method that raises OSError when failing and use it on specific programmers. ... This will avoid programming errors to be silently ignored and will raise the following error: OSError: Error occured during OpenOCD's call, please check: - OpenOCD installation. - access permissions. - hardware and cable.	2020-11-10 10:22:57 +01:00
Florent Kermarrec	a5bdfe3f4c	software/i2c: add i2c_scan command.	2020-11-10 09:47:28 +01:00
Florent Kermarrec	ce9f24748f	soc/cores/bitbang/I2C: use Tristate on SDL/SDA and only drive low (rely on I2C Pull-Ups for high).	2020-11-10 09:46:43 +01:00
Florent Kermarrec	221ea4c31a	tools/remote/comm_udp: revert try/except (was probably needed with CommUDP's max_length = 4).	2020-11-09 16:36:04 +01:00
Florent Kermarrec	5aa70d975c	tools/litex_server: revert CommUDP's max length to 1 (needs more testing).	2020-11-09 16:35:04 +01:00
Florent Kermarrec	1d04b1dd83	software/liblitesdcard: Operate the SDCard in 3.3V/High Speed. ... SDR50/Driver strength configuration is for 1.8V that is no longer supported (for simplicity).	2020-11-09 15:39:54 +01:00
Florent Kermarrec	b3a42d76ce	cores/cpu/microwatt: fix non irq variant, add standard+irq/"standard+gdhl+irq variants, move XICSSlave after CPU class.	2020-11-09 13:31:11 +01:00
enjoy-digital	3673f38d63	Merge pull request #653 from gsomlo/gls-dt-cpufreq ... RFC: json2dts: set CPU clock-frequency and SoC bus-frequency	2020-11-09 12:40:15 +01:00
enjoy-digital	ecaf69fe78	Merge pull request #688 from rprinz08/master ... Fix check for wrong named attributes	2020-11-09 11:22:08 +01:00