ecf999b8c7
soc/cores: add usb_fifo with FT245 USB FIFO PHY from LiteUSB, deprecate LiteUSB
...
LiteUSB was not up to date was not a real USB PHY but was just providing USB FIFO PHYs.
New true USB cores are now available: Daisho, ValentyUSB, so it's better using
then for true USB support. We only keep the FT245 FIFO PHY in LiteX that can be
useful to interface with USB2/USB3 USB FIFOs.
2019-06-24 10:58:36 +02:00
8f6e66ca52
make sure #!/usr/bin/env python3 is before copyright header
2019-06-24 07:29:24 +02:00
daa4307d9e
add CONTRIBUTORS file and add copyright header to all files
2019-06-23 23:23:56 +02:00
361f9d0dff
bios/sdram: set init_done/error when DDRCTRL is present (litedram_gen)
2019-06-22 10:55:15 +02:00
d8ac936206
Convert top level comment to a docstring.
2019-06-21 12:03:30 -07:00
7656f54d0a
soc: cores: add up5kspram module
...
The ICE40UP5K has 128 kB of SPRAM that's designed to be used
as memory for a softcore. This memory is actually 4 16-bit
chunks that we can gang together to give us either 64 kB or
128 kB.
Add a module that will allow us to use this memory in an ICE40.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-06-20 11:12:46 -07:00
73dbffe8f2
cores/frequency_meter: allow passing clk to be measured as a parameter
2019-06-20 09:03:30 +02:00
ab827d210d
tools/litex_sim: fix default endianness for mem_init
...
Initializing ROM and/or RAM content requires knowing the CPU
endianness before the SimSoC->SoCSDRAM->SoCCore constructor
sequence is invoked (before the SoC's self.cpu.endianness
could be accessed). Given that the majority of supported CPU
models use "little", set it as the new default, and override
only for the two models that use "big" endianness.
2019-06-18 16:55:58 -04:00
f75863fc31
cpu/rocket: add "linux" (MMU) and "full" (MMU & FPU) variants
2019-06-18 06:46:24 -04:00
c0df9e0823
cpu/rocket: update submodule
2019-06-18 09:44:13 +02:00
87118d509c
integration/soc_core: move cpu_variant checks/formating to cpu
2019-06-17 09:55:27 +02:00
f6b67a6dae
cpu/vexriscv: add "linux+no-dsp" variant
2019-06-17 09:54:17 +02:00
95b1b454f4
cpu/vexriscv: update
2019-06-17 09:24:57 +02:00
e46d287b64
targets/ulx3s: use CAS latency of 3 to be compatible with production boards
2019-06-17 09:20:21 +02:00
ca70ea91e4
bios: Fix build when ethphy is present but ethmac is not.
...
While testing my Ethernet DMA, I renamed the `ethmac` module to `ethmac_dma` so that it wouldn't be used from the BIOS, but I got an undefined reference to `eth_init` because `bios.c` checks different CSR defines than the code that defines `eth_init`.
2019-06-13 01:02:22 +02:00
33d7cc5fc8
Merge pull request #198 from TomKeddie/tomk_20190610_artyspi
...
boards/arty : Add directly connected spi clk pin
2019-06-11 15:50:02 +02:00
5346c3684f
boards/arty : Add directly connected spi clk pin to avoid need for STARTUPE2
2019-06-10 08:33:02 -07:00
243d7c7696
soc/cores: add PRBS (Pseudo Random Binary Sequence) Generator/Checker
...
Imported from LiteICLink. PRBS can be useful for different purposes, so is
better integrated in LiteX.
2019-06-10 16:05:36 +02:00
cfa952b062
tools/litex_term: exit on 2 consecutive CTRL-C
...
When running OS with LiteX and when LiteXTerm is use, we want to be able to
send CTRl-C to the OS. Ensure a specific sequence is sent to close the terminal.
2019-06-10 15:06:57 +02:00
1c34b4a015
cpu/vexriscv: update submodule
2019-06-10 12:57:21 +02:00
850b311d04
cpu/vexriscv: update submodule
2019-06-07 18:36:46 +02:00
755a2660ba
build/sim: allow configuring verilator optimization level
2019-06-07 12:28:20 +02:00
4b6ad8aa0d
build/sim: allow defining start/end cycles for tracing
2019-06-07 11:50:57 +02:00
ecb60f6e43
build/sim: use -O0 for verilator compilation
...
In most of the case, execution speed is already fast enough with -O0 and
with complex design -O0 is a lost faster to compile than -O3. In the future
we could add a switch to choose which optimization we want.
2019-06-07 11:16:39 +02:00
c64129dc69
soc/integration/soc_core: list rocket as supported CPU
2019-06-07 11:14:36 +02:00
ca4e7811e9
software/bios: change prompt to "litex" in green.
2019-06-07 11:13:36 +02:00
8d0f008a3b
integration/soc_core: improve readibility (add separators/comments)
2019-06-05 23:43:16 +02:00
e545b15f66
Merge pull request #196 from msloniewski/de10lite_support
...
De10lite support
2019-06-05 19:44:54 +02:00
04ce479035
boards/targets: add target for de10lite platform
2019-06-05 18:57:59 +02:00
f2a740d51d
boards/platforms: add de10lite Terasic platform support
2019-06-05 18:57:59 +02:00
a826aacac0
build/altera: Add possibility to turn off generation of .rbf file
...
For some FPGAs (e.g. MAX10) .rbf file cannot be generated.
Add possibility to turn off that feature for those chips.
2019-06-05 18:57:59 +02:00
93b61a65bf
integration/builder: generate flash_boot address to csv
2019-06-05 17:37:23 +02:00
d0b019b1f0
integration/builder: generate shadow_base address to mem.h and csv
2019-06-05 17:37:09 +02:00
f88b85a31c
software/libbase: memcpy: simple, arch-width agnostic implementation
...
Remove optimizations targeted specifically at rv32 architecture,
allowing memcpy to work on all word sizes.
Since this is "only" the BIOS, it is also arguably better to
optimize for size rather than performance, given that control
will be quickly handed over to some other program being loaded.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-06-04 14:48:51 -04:00
42e9d09755
Merge pull request #192 from sutajiokousagi/pr_c99_types
...
fix signed char type to be explicitly signed
2019-06-02 16:54:20 -07:00
ab0b2cac2e
fix signed char type to be explicitly signed
2019-06-03 06:01:13 +00:00
200d413def
update stdint.h to include c99 types
...
needed for some third party libraries to compile
2019-06-02 22:27:12 +00:00
db890736ea
fix csr_name in add_csr()
2019-06-02 20:56:02 +02:00
40cbe3a952
fix interrupt_name
2019-06-02 20:52:31 +02:00
220e2bdc6e
boards/platform/arty: add Arty A7-100 variant
2019-06-02 19:10:44 +02:00
8e6ecfb974
Merge pull request #189 from open-design/terasic-boards
...
Add support for Terasic DE2-115 and Terasic DE1-SoC boards
2019-06-02 18:40:57 +02:00
6cf1a814eb
boards: add Terasic DE2-115 initial support
...
See https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=502&PartNo=1
for board details.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
2019-06-02 11:33:10 +03:00
037259917a
boards: add Terasic DE1-SoC Board support
...
See https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=836
for board details.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
2019-06-02 11:26:21 +03:00
273a3ea15d
soc/integration/cpu_interface: improve code legibility
...
Factor out code appearing in both branches of an if/else.
2019-05-29 10:07:43 -04:00
08a811b1a5
soc/interconnect/gearbox: add msb_first/lsb_first order
2019-05-29 10:25:25 +02:00
675f78304e
boards/targets/arty: generate 25MHz ethernet clock with S7PLL
...
Allow ethernet to work when sys_clk_freq != 100MHz
2019-05-28 09:55:06 +02:00
26e6355fd6
litex/boards/targets: don't use tab for indentation
...
Fix pep8 E101 "indentation contains mixed spaces and tab" error.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
2019-05-26 12:00:03 +03:00
5109511259
soc/interconnect/axi: add round/robin arbitration between writes/reads
2019-05-25 10:02:31 +02:00
961101d809
bios/irc: remove compilation workaround
2019-05-25 09:24:48 +02:00
712977a0cf
software/bios/isr.c: workaround compilation issue (need to be fixed)
2019-05-24 10:18:50 +02:00
28ba8b3201
soc/integration/soc_core: revert default mem_map (do specific RocketChip remapping for now)
2019-05-24 10:18:32 +02:00
cf369c437c
boards/targets: revert default sys_clk_freq on nexys4ddr/versa_ecp5 (but add parameter to configure it)
2019-05-24 10:18:26 +02:00
019fd94005
fixup: generated-verilog submodule for experimental Rocket support
...
FIXME: This patch uses https://github.com/gsomlo/rocket-litex-verilog ,
however in the long term it would perhaps be better if enjoy-digital
hosted the generated-verilog repository.
Once that's in place, I'd be happy to re-spin (and squash) this patch
on top of its parent -- GLS
2019-05-23 18:22:37 -04:00
1a530cf27d
soc/cores/cpu/rocket: Support for 64-bit RocketChip (experimental)
...
Simulate a Rocket-based 64-bit LiteX SoC with the following command:
litex/tools/litex_sim.py [--with-sdram] --cpu-type=rocket
NOTE: Synthesizes to FPGA and passes timing at 50MHz on nexys4ddr
(with vivado) and ecp5versa (with yosys/trellis/nextpnr), but at
this time does not yet properly initialize physical on-board DRAM.
On ecp5versa, using '--with-ethernet', up to 97% of the available
TRELLIS_SLICE capacity is utilized.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-05-23 15:59:51 -04:00
e90caa8683
tools/litex_sim: restore functionality of '--with-sdram' option
...
After LiteDRAM commit #50e1d478, an additional positional argument
('databits') is required by the PhySettings() constructor.
The value used here (32) will generate a 64MByte simulated SDRAM.
2019-05-23 08:56:50 -04:00
014c950580
remote: usb: print "access denied" error
...
When we get an error with errno 13, it means that the user doesn't
have access to the USB device. Rather than silently eating this
error and returning -1, print out a message to aid in debugging.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-05-21 09:36:18 +08:00
faf6554c89
remote: usb: use 0x43/0xc3 for packet header
...
The previous value -- 0xc0 -- is used by Windows all the time to query
special descriptors. This was causing a conflict when using the USB
bridge on a Windows device.
Change the magic packet from "Vendor: Device" queries to "Vendor:
Other" by setting the bottom two bits.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-05-21 09:14:18 +08:00
10670e22ac
soc/cores/minerva: update to latest
2019-05-17 22:21:57 +02:00
5707bdc0a4
boards/nexys4ddr: ethernet support fix-up
...
Commit 5f6e7874
2019-05-17 10:06:12 -04:00
0a8699f1e6
Merge branch 'master' of http://github.com/enjoy-digital/litex
2019-05-16 15:15:30 +02:00
526ba1b165
soc_core: remove csr_expose and add add_csr_master method
...
This could be useful in specific case were we don't have a wishbone master
but just want to have a csr bus and allow the user to define it.
/!\ Since there is no arbitration on between the CSR masters, use this with
precaution /!\
2019-05-16 15:14:55 +02:00
1ea22d49b7
software/include/base/csr-defs.h: add specific CSR_IRQ_MASK/PENDING for Minerva
2019-05-15 22:40:32 +02:00
f25707012f
software/bios/boot: remove specific linux commands (not needed with device tree)
2019-05-14 11:45:16 +02:00
938d00c283
boards/targets/de0nano: reduce to 50MHz sys_clk, simplify CRG
2019-05-14 11:45:12 +02:00
11838bae20
platforms/de0nano: change serial pins (put then next to the GND pin)
2019-05-14 11:45:06 +02:00
eb6fa45833
cpu/vexriscv/core: update
2019-05-13 10:59:26 +02:00
0cad80e935
cpu/vexriscv: update submodule (new linux variant)
2019-05-13 10:59:03 +02:00
5f6e787494
boards/nexys4ddr: add ethernet support (RMII 100Mbps)
2019-05-13 10:18:23 +02:00
0ba1cb8756
boards/targets/netv2: +x
2019-05-11 12:39:02 +02:00
2f2b9b319f
soc/cores: remove cordic
...
Cordic is useful for DSP cores but not as a Soc building block.
2019-05-11 09:36:53 +02:00
6e4ac1c493
LICENSE: clarify
2019-05-11 09:26:51 +02:00
67159349d6
soc/interconnect: remove axi_lite
...
axi_lite code was defining AXI4Lite signals and doing a AXI4Lite bridge to the
CSR bus when LiteX was not having proper AXI support. LiteX now has proper AXI
support and it also cover what axi_lite was doing: To create a AXILite to CSR
bus, user can create an AXILite2Wishbone bridge and then connect the CSR bus
directly to the wishbone bus as done in the others non-AXI SoC.
2019-05-11 09:12:20 +02:00
745d83a332
boards: add initial NeTV2 support (clocks, leds, dram, ethernet)
2019-05-10 18:55:40 +02:00
a49d170a6d
soc/integration/soc_sdram: simplify/fix main_ram_size computation using new databits value of the phy
2019-05-10 15:46:22 +02:00
7445b9e2e0
soc/integration/soc_core: allow user to defined internal csr/interrupts
...
For some designs with different capabilities, we want to run the same software
and then have the CSRs/Interrupts defined to a specific location.
2019-05-10 11:05:34 +02:00
f333abcfcb
boards/targets: use new add_csr method
2019-05-09 23:50:43 +02:00
d76a2c7db2
tools/litex_sim: add uart csr (required when with_uart=False with new add_csr method)
2019-05-09 23:33:08 +02:00
b6be534cd6
soc/integration/soc_core: rework csr assignation/reservation
...
Similar refactor than on interrupts. Adds a add_csr method but still
retro-compatible with old way to declare CSRs.
2019-05-09 23:32:22 +02:00
3f09af6d6e
boards/targets: declare ethmac interrupt with new add_interrupt method
...
The previous way to define interrupt is still valid, but using add_interrupt
method will ease maintenance
2019-05-09 12:13:15 +02:00
2abb3e809c
Merge branch 'master' of http://github.com/enjoy-digital/litex
2019-05-09 11:57:19 +02:00
47dc87584f
integration/soc_core: rework interrupt assignation/reservation
...
The CPUs can now reserve specific interrupts with reserved_interrupts property.
User can still define interrupts in SoCCore.interrupt_map (old way) or use
add_interrupt method. Interrupts specific to SoCCore internal modules are
allocated automatically on the remaining free interrupt ids.
Priority for the interrupts allocation:
- 1) CPU reserved interrupts.
- 2) User interrupts.
- 3) SoCCore interrupts.
2019-05-09 11:54:22 +02:00
435cdad083
boards/targets: fix ulx3s/versa_ecp5 build
2019-05-09 11:48:32 +02:00
8caa38bc25
cpu: add `reserved_interrupts` property
2019-05-09 09:00:06 +02:00
c264a00964
soc/integration/cpu_interface: more arch-specific address size fixes
...
When generating arch-specific include files (generated/[mem|csr].h)
ensure address literal defines are suffixed by 'L', denoting their
'unsigned long' type. This inhibits compiler warnings when values
computed based on these constants are cast to pointers.
Also ensure csr_[read|write][b|w|l]() function declarations have
'unsigned long' address arguments.
Finally, restore the correct (32-bit, (unsigned *)) expected
behavior of the MMPTR() macro, inadvertently converted to an
arch-specific sized access (unsigned long *) by commit 5c2b8685
2019-05-08 16:03:36 -04:00
ff5179153c
boards/targets: make sys_clk_freq a parameter
...
Most of the targets can now generate an abritrary sys_clk_freq from onboard XO.
2019-05-07 18:44:03 +02:00
a8cbe4ad84
boards/targets/minispartan6: for now revert experimental s6pll clocking
2019-05-07 13:05:28 +02:00
6fcbf10eb9
boards/plarforms/minispartan6: default to xc6slx25
2019-05-07 12:48:36 +02:00
b7e3713388
bios/boot/ update linux memory mapping
2019-05-07 11:59:28 +02:00
190ff89aaa
tools/litex_term: add json support to load images to memory, allow passing speed as float
...
example json file (serialboot.json):
{
"binaries/Image": "0xc0000000",
"binaries/rootfs.cpio": "0xc2000000",
"binaries/rv32.dtb": "0xc3000000",
"emulator/emulator.bin": "0x20000000"
}
example command:
lxterm --images=serialboot.json /dev/ttyUSBX
2019-05-06 23:56:33 +02:00
a048ba47c4
vexriscv: Fix some floating signals
...
Signed-off-by: David Shah <dave@ds0.me>
2019-05-04 17:27:21 +01:00
fcd518b5d0
bios/boot: add specific flash_boot for linux with vexriscv
2019-05-04 11:27:01 +02:00
1ba1ad9a00
bios/boot: rename MM_RAM to EMULATOR_RAM
2019-05-03 19:47:36 +02:00
fbb24720f0
soc/get_mem_data: add direct support for regions
...
We now support passing filename (offset=0), json file and regions
2019-05-03 13:24:06 +02:00
0714816f31
soc/interconnect/axi: add AXI2AXILite converter and use it in AXI2Wishbone
2019-05-03 11:59:06 +02:00
c6d0d23445
soc/interconnect/axi: add AXI Lite definition
2019-05-03 09:43:12 +02:00
9fab4752c4
soc/interconnect/axi: add comment on axi signas that are present but not used
2019-05-03 09:30:59 +02:00
5989076346
cores/cpu/vexriscv: add VexRiscvTimer and use it for the linux variant
2019-05-03 09:30:26 +02:00
21bf10383d
bios/boot: add liftoff banner just before booting
2019-05-02 18:26:35 +02:00
8f4685b3b1
bios/boot/netboot: only get boot.bin as default, add linux_vexriscv netboot config
2019-05-02 16:34:41 +02:00
6cf1ff091c
soc/interconnect/axi: connect axi.ar/aw when selecting write or read
2019-05-02 09:58:55 +02:00
6affc56a09
soc/interconnect/axi: wishbone address shift is not always 2, make it generic
2019-05-02 09:35:07 +02:00
698bc88296
soc/interconnect/wishbone: allow setting adr_width (default to 30)
2019-05-02 09:34:30 +02:00
4dccb8a9eb
soc/interconnect/axi/AXI2Wishbone: add buffer on axi command to be sure command is accepted before response is sent
2019-05-01 12:59:04 +02:00
9f8f0eb18e
build/sim: update tapcfg
2019-05-01 12:34:12 +02:00
5c2b8685fc
software: use "unsigned long" for address values, also 8-byte alignment
...
Enable future support for 64-bit CPU models.
2019-04-29 15:03:38 -04:00
5c1d980540
soc/interconnect/axi: add burst support to AXI2Wishbone
2019-04-29 16:49:20 +02:00
6de2713524
soc/interconnect/axi: add capabilities to AXIBurst2Beat and simplify/optimize
2019-04-29 14:02:05 +02:00
305b8879de
integration/soc_core: use cpu name as cpu-type for all cpus (mor1kx was instanciated with or1k)
...
Keep or1k retro-compatibility for now but add a warning
2019-04-29 10:14:30 +02:00
4e50f36b72
build/tools: add deprecated_warning
2019-04-29 10:12:54 +02:00
b40d1b73c4
cpu_interface: default to gcc for all cpus unless told otherwise (mor1kx default was clang)
2019-04-29 10:00:04 +02:00
dbb71af189
cpu: use property methods to return name, endianness, gcc triple/flags, linker output format
2019-04-29 09:58:51 +02:00
d828c3a596
cpu: integrate nmigen version of Minerva, add submodule
2019-04-28 23:40:33 +02:00
bf27869ad9
fix vexriscv build
2019-04-28 11:10:20 +02:00
2d5bae3def
Merge pull request #175 from mithro/cpu-docs
...
Standardizing `cpu_variants` and adding lots of documentation
2019-04-27 21:24:06 +02:00
5cbc5bc199
Adding testing of cpu variants.
2019-04-26 18:57:49 -05:00
71a837315a
Work with no `cpu_variant` provided.
2019-04-26 17:44:36 -05:00
39c579baa2
Standardize the `cpu_variant` strings.
...
Current valid `cpu_variant` values;
* minimal (alias: min)
* lite (alias: light, zephyr, nuttx)
* standard (alias: std) - Default
* full (alias: everything)
* linux
Fully documented in the [docs/Soft-CPU.md](docs/Soft-CPU.md) file
mirrored from the
[LiteX-BuildEnv Wiki](https://github.com/timvideos/litex-buildenv/wiki ).
Also support "extensions" which are added to the `cpu_variant` with a
`+`. Currently only the `debug` extension is supported. In future hope
to add `mmu` and `hmul` extensions.
2019-04-26 17:44:30 -05:00
3a2e283613
.gitmodules: use our VexRiscv-verilog
2019-04-27 00:00:55 +02:00
78c09125be
soc/integration/soc_core: fix get_mem_data when not file is not multiple of 4 bytes
2019-04-25 23:43:10 +02:00
0175f86cb2
soc/integration/soc_core: fix get_mem_data for json files
2019-04-25 18:36:47 +02:00
4443b5075b
soc/integration/soc_core: add integrated_sram_init
2019-04-25 17:30:03 +02:00
f27084c6c0
soc/integration/cpu_interface: fix banner in get_mem_header
2019-04-24 22:44:37 +02:00
d21cba2f17
build: handle exceptional case when litex/migen not deployed as git repo
2019-04-24 12:50:47 -04:00
27fbb814ab
tools/remote/csr_builder: allow comments in csv file and cleanup
2019-04-24 12:25:49 +02:00
e8f3c49127
software/libnet/microudp: rearrange send_packet, add comments and remove txlen padding
2019-04-24 11:32:40 +02:00
44e0cdda9a
software/libnet/microudp: speed-up ARP by changing timeout/tries
...
First ARP request does not seem to be transmitted (the link is probably not
fully established). Reduce the timeout between tries and increase number of
tries.
2019-04-24 09:55:41 +02:00
3ee78a5b70
build/tools: fix typo
2019-04-23 18:10:51 +02:00
9ded2eb20b
tools/litex_term: change TERM prompt to LXTERM
2019-04-23 17:46:02 +02:00
475deb51ac
build: add migen and litex git revision to generated file
2019-04-23 17:40:24 +02:00
8b5cf29542
build/tools: git_revision is not doing what we want, return "--------" for now
2019-04-23 17:15:43 +02:00
0f60ec35e2
tools/litex_server: fix comms import
2019-04-23 14:25:27 +02:00
68f12495cf
soc/integration: also add sha-1/date to generated software files
2019-04-23 13:17:54 +02:00
425741226c
build: add sha-1/date to generated verilog, change git_version to git_revision
2019-04-23 12:59:25 +02:00
818dfae1e8
boards/platforms/ulx3s: fix default clock
2019-04-23 11:37:29 +02:00
17b6164cd9
boards/platforms/sp605: apply same simplifications than on others platforms
2019-04-23 11:21:55 +02:00
24bf02934e
boards/platforms: add SP605
2019-04-23 11:15:42 +02:00
10cf0fdea3
cores/cpu/vexriscv: fix wrong revert
2019-04-23 11:13:29 +02:00
d2ad14417a
targets/ac701: cleanup and make it similar to others targets.
...
Still supports EthernetSoC with RGMII and 1000BaseX.
2019-04-23 11:10:35 +02:00
a24bf72fc7
targets/xilinx: remove keep attribute on clock going to idelayctrl
...
Causes P&R issues with Vivado.
2019-04-23 10:51:36 +02:00
ea8dbff86e
boards/platform/ac701: add proper copyright, cleanup to be similar to others platforms
2019-04-23 10:50:19 +02:00
0122982e09
boards/platforms/kc705: provide only one default programmer as others platforms
2019-04-23 10:00:52 +02:00
89a590263f
boards: Xilinx ac701 dev board support
2019-04-23 09:48:16 +02:00
88b882c7e0
build/xilinx/ise.py: write .v file for post synthesis sim
2019-04-23 09:22:48 +02:00
7396ebbb38
build/xilinx/programmer: cleanup XC3SProg position parameter
2019-04-23 09:20:59 +02:00
f579cbc603
build/xilinx/programmer: add position parameter to XC3SProg
2019-04-23 09:16:42 +02:00
535d86727a
targets/minispartan6: use S6PLL in CRG
2019-04-23 06:44:29 +02:00
40342404f2
cores/clock: add divclk_divide_range on S6PLL/S6DCM
2019-04-23 06:43:48 +02:00
0d282f38f9
cores/clock: use common XilinxClocking class for all Xilinx clocking modules
2019-04-23 06:35:39 +02:00
83699ea0a5
cores/clock: add initial Spartan6 PLL/DCM support
2019-04-23 06:23:00 +02:00
eff141da2d
build: add git version (sha-1) used to create the scripts
2019-04-23 06:03:12 +02:00
cc141a64b9
build: scripts are generated by LiteX
2019-04-23 05:38:33 +02:00
115c842ef0
build/xilinx/vivado: cleanup pull request #170
2019-04-23 05:33:56 +02:00
fda18fd6ef
build/xilinx/vivado: only try Xilinx setup if vivado is not already in the path
...
Only affects the non-Windows code path.
Uses python distutils, already used elsewhere.
2019-04-22 15:42:31 -07:00
7d278854d5
global: switch to VexRiscv as the default CPU
...
VexRiscv can now replace LM32 for almost all usecases and we now have better
software support with RISC-V.
2019-04-22 09:41:07 +02:00
8c78997089
boards/platforms: add separators, cleanup imports
2019-04-21 00:44:23 +02:00
cb8c26d1b8
boards/platforms: provide only one default programmer per platform.
...
create_programmer is not really longer used, so try to keep it simple.
2019-04-21 00:17:03 +02:00
e1d202df02
boards/platforms/kc705: only keep Vivado support
...
There is no reason still using ISE on 7-Series.
2019-04-21 00:04:56 +02:00
53c7be6e46
boards: always define timing constraints the same way (1e9/freq_mhz)
2019-04-20 23:56:27 +02:00
02ffbed5e3
boards/targets/ulx3s: allow running test_targets on it
2019-04-20 23:47:05 +02:00
5a1925df2e
boards/targets: add keep attribute directly in crg
...
This makes it systematic and avoid having to add it later.
2019-04-20 23:43:44 +02:00
f71b8d4f57
litex_server: check socket flags exist before using them
...
Some flags are only available on certain platforms. Verify these flags
exist prior to using them when opening a socket.
See
https://stackoverflow.com/questions/14388706/socket-options-so-reuseaddr-and-so-reuseport-how-do-they-differ-do-they-mean-t
for more information
Signed-off-by: Sean Cross <sean@xobs.io>
2019-04-20 17:28:26 +08:00
9ee6c35b42
tools: move from litex.soc.tools to litex.tools and fix usb.core import
2019-04-20 10:44:53 +02:00
49fd93ae83
Merge pull request #165 from xobs/vexriscv-cpu-reset-address
...
Vexriscv cpu reset address
2019-04-19 19:16:16 +02:00
ca6065a6a1
Merge pull request #164 from xobs/litex-usb-server
...
Litex usb server support
2019-04-19 19:14:15 +02:00
c69183648f
utils: litex_server: add usb support
...
Add `--usb` and associated arguments to create a litex bridge over
USB. This makes use of the new CommUSB module.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-04-19 18:02:42 +01:00
9dd59d6301
tools: remote: add usb communications protocol
...
This adds a USB communications protocol to the suite of litex-supported
wishbone bridge protocols.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-04-19 17:29:50 +01:00
9cbed91b3e
soc/interconnect/axi: add AXIBurst2Beat
...
Converts AXI bursts commands to AXI beats.
2019-04-19 12:13:16 +02:00
5a8115d9e1
soc/interconnect/avalon: add description
2019-04-19 11:43:15 +02:00
c780fb22b7
Merge branch 'master' of https://github.com/enjoy-digital/litex
2019-04-19 16:47:55 +08:00
fa95608694
soc/integration/soc_zynq: fix HP0 connections
2019-04-19 10:21:56 +02:00
a78ca2de92
build/xilinx/vivado: only set library for vhdl files (not supported for verilog/system-verilog)
2019-04-19 09:18:25 +02:00
e2cf45b8a9
cpu: vexriscv: allow cpu_reset_address to be overridden
...
Allow the cpu_reset_address value to be overridden, for example allowing
it to be a signal. That way the reset address can be modified after
synthesis, in dual-core or debug situations.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-04-19 13:04:57 +08:00
a92e90b215
soc/interconnect: add avalon with converters to/from native streams
2019-04-18 18:42:29 +02:00
d860eeea4f
Merge pull request #162 from antmicro/full-conf-vexriscv
...
Add full and full_debug CPU variant of VexRiscv
2019-04-17 19:01:55 +02:00
e1683078ec
build/sim/core: Initialize Verilator commandArgs
...
Required when DUT is using plusargs. Prevents Verilator simulation
from crashing with "Verilog called $test$plusargs or $value$plusargs
without testbench C first calling Verilated::commandArgs(argc,argv)".
2019-04-17 10:39:35 -04:00
40de01bcb0
vexriscv: Add full and full_debug CPU variant
2019-04-17 09:09:35 +02:00
017147c623
build/altera: switch to sdc constraints, add add_false_path_constraints method
2019-04-16 16:57:23 +02:00
1275e2f150
build/xilinx/vivado: set quiet property on MultiReg/AsyncResetSynchronizer constraints
...
MultiReg/AsyncResetSynchronizer are not necessarily present in all design, set
quiet property to avoid generating false warnings.
2019-04-15 16:48:47 +02:00
c252972bef
soc/cores/clock: add divclk_divide/vco_margin support on S7/Ultrascale
2019-04-15 11:36:42 +02:00
f986974d60
soc/cores/clock: improve presentation
2019-04-15 10:57:00 +02:00
538ca59ab6
build/xilinx/vivado: round period constraints to lowest picosecond
...
Vivado will do the opposite if we don't do it, with this change we ensure the applied period constraints will always be >= to the requested constraint.
2019-04-15 10:51:17 +02:00
a2bc4bb777
litex_server: set socket.SO_REUSEPORT to avoid waiting 60s in case of unclean termination
2019-04-15 08:23:27 +02:00
be99083e2b
litex_server: add message and exit when mandarory arguments are missing.
2019-04-14 14:00:35 +02:00
db11aec961
litex_server: allow setting bind port, remove auto-incrementing on bind_port
2019-04-14 12:48:49 +02:00
76bc57851b
litex_server: refactor parameters and to allow setting bind address
...
In some cases, it can be useful to bind to "0.0.0.0" instead of "localhost".
While adding bind address support, parameters passing has also been refactored
to ease adding parameters in the future.
2019-04-14 09:00:08 +02:00
13a76ec7fb
software/libnet/microudp: simplify txbuffer managment
2019-04-12 18:47:31 +02:00
3441eb05cb
software/libnet/microudp: cleanup eth_init
2019-04-12 17:15:09 +02:00
92a79c6dc1
software/libnet/microudp: simplify rxbuffer managment
2019-04-12 17:14:07 +02:00
fdeff7f64f
software/libnet/microudp: set raw frame size to ETHMAC_SLOT_SIZE
2019-04-12 17:09:50 +02:00
1569e2e0cf
software/libnet: remove use of ethmac_mem.h
2019-04-12 17:08:29 +02:00
c7ac96761c
bios/sdram: add __attribute__((unused)) on cdelay
2019-04-11 22:26:58 +02:00
792245f196
boards/targets/kcu105: add Ethernet (with 1Gbps SFP adapter)
2019-04-10 16:36:49 +02:00
f8dcdb70d2
software/libnet: add #ifdef on eth_init
2019-04-10 16:16:47 +02:00
04939990ac
litex/build/altera/quartus: changes to make top level assigment in .qsf file with build name
2019-04-08 14:07:10 +03:00
8558065fca
litex/build/altera/common: added reset synchronizer
2019-04-08 14:06:24 +03:00
866fa34493
integration/soc_zynq: fix missing SoCCore.do_finalize
...
Signed-off-by: Florent Kermarrec <florent@enjoy-digital.fr>
2019-04-01 14:44:37 +02:00
794c3c5860
integration/soc_zynq: add add_hp0 method
2019-04-01 11:10:35 +02:00
38d404c3cb
integration/soc_zynq: use add methods to add optional peripherals
2019-04-01 10:50:04 +02:00
7375856bec
integration/soc_zynq: connect axi signals that were missing
2019-04-01 10:31:33 +02:00
b15fd9d834
interconnect/axi: add missing axi signals
2019-04-01 10:23:25 +02:00
1f0b3f8124
Add ifdef check for MAIN_RAM_SIZE
2019-03-31 10:33:39 -05:00
dd214d2d21
bios/main: align SoC info, show CPU speed on CPU line, show L2
2019-03-30 11:49:39 +01:00
6599f7bb50
bios/main: move sdrinit
2019-03-30 10:56:17 +01:00
b92b89ab92
bios/main: print boot sequence only if sdr_ok
2019-03-30 10:19:00 +01:00
f4369c8fb2
bios/main: remove csr functions (not used and only supported by lm32), improve help presentation
2019-03-29 19:40:24 +01:00
66dffb7071
software/bios: improve readibility, add soc informations
2019-03-29 00:51:16 +01:00
449632e430
soc/interconnect/axi: data/address length cleanup
...
Instead of hard-coding data and address width to 32, assert that
the AXI and Wishbone interfaces have *matching* address and data
widths.
2019-03-27 16:52:52 -04:00
552b0243b3
soc/interconnect/axi: remove dead code (thanks gsomlo)
2019-03-27 21:15:14 +01:00
b682dacdd7
Merge pull request #154 from daveshah1/yosys_xilinx_edif
...
build/xilinx: Update Yosys write_edif parameters
2019-03-22 17:43:40 +01:00
57e1ccd5f8
build/xilinx: Update Yosys write_edif parameters
2019-03-22 16:06:52 +00:00
fd7ed6c1ec
utils/litex_sim: fix main_ram_size
2019-03-16 21:25:02 +01:00
3f386dad7d
soc_core/get_mem_data: add json support
...
example of json file:
{
"vmlinux.bin": "0x00000000",
"vmlinux.dtb": "0x01000000",
"initramdisk.gz": "0x01002000"
}
2019-03-16 21:23:36 +01:00
7bc13ba841
build/microsemi/libero_soc: add linux build script support
2019-03-16 09:33:16 +01:00
7b88980d06
vexriscv: allow user to use an external variant
2019-03-15 18:16:25 +01:00
b04a756abb
vexriscv/core: fix min variant
2019-03-15 17:49:39 +01:00
a549f0941b
utils/litex_sim: handle cpu_endianness for rom-init/ram-init
2019-03-13 10:56:09 +01:00
411bca790a
utils/litex_sim: increase default integrated_main_ram_size to 256MB, automatically boot on main_ram when ram_init is specified
2019-03-13 10:42:10 +01:00
7ec3ed4d89
Merge pull request #153 from railnova/fix_utils
...
[fix] utils was omitted when installed from pip
2019-03-07 21:12:00 +01:00
aed2e9b4b5
[fix] utils was not installed from pip
2019-03-07 09:40:58 +01:00
b014c7194b
build/lattice/trellis: also generate bitstream in svf format
...
Before being able to program the board (e.g., with openocd), one
would have to convert the bitstream file to .svf using a python
script included with the source trellis distribution. However,the
trellis 'ecppack' utility can also generate .svf bitstream files
directly.
2019-03-06 16:29:18 -05:00
317dba8314
software/bios/sdram: use specific ERR_DDRPHY_BITSLIP/NMODULES computation
...
In the future, the PHYs should generated these constants.
2019-03-05 18:03:24 +01:00
7de1fe519a
targets/versa_ecp5: update ECP5DDRPHY on BaseSoC, add EthernetSoC
2019-03-05 13:27:11 +01:00
ca63db4040
bios/sdram: use burstdet detection for ECP5DDRPHY init
2019-03-05 13:27:06 +01:00
ebe8f600e1
lattice/common: Fix tristate buses with Trellis
...
Signed-off-by: David Shah <dave@ds0.me>
2019-03-04 10:50:56 +00:00
935f3a5337
boards/ulx3s: add device selection parameter
...
ULX3S can be populated with LFE5U-45F (default) or LFE5U-85F
2019-03-04 09:40:14 +01:00
e6f97e08d2
targets/ulx3s: use AsyncResetSynchronizer and derivate sys_clk/sys_clk_ps constraints from clk25
...
Now supported by Trellis/Nextpnr.
2019-03-04 09:27:31 +01:00
5ef28bdf75
build/lattice/trellis: add package support
2019-03-01 15:20:02 +01:00
1b34c07da9
build/lattice/trellis: basecfg now integrated in nextpnr
2019-03-01 14:20:00 +01:00
7e995eb418
boards/targets/ulx3s: allow building with diamond or trellis
2019-03-01 13:59:28 +01:00
4bf789eab9
soc/software/bios/boot: add vexriscv workaround
...
Flushing icache was working correctly on previous version of Vexriscv, understand
why it's no longer the case.
2019-03-01 09:16:48 +01:00
1fd81c2882
soc/integration: add initial SoCZynq SoC
2019-02-27 22:39:35 +01:00
3c527dcbdf
soc/interconnect: add initial axi code with bus definition and AXI2Wishbone
2019-02-27 22:26:57 +01:00
ed2578799b
test: add test_axi_lite (with test code from soc/interconnect/axi_lite lightly modified)
2019-02-27 22:24:56 +01:00
4aa07f2ae9
soc/interconnect: rename axi to axi_lite
2019-02-27 22:11:09 +01:00
c9f9e237d9
Merge pull request #149 from daveshah1/versa_trellis
...
Add trellis build option to versa_ecp5 and bring trellis support up to date
2019-02-25 19:26:07 +01:00
ff7e0fab6a
versa_ecp5: Add option to build with Trellis
2019-02-25 18:02:04 +00:00
024b41c5b2
trellis: Add LPF frequency constraints and remove -nomux
2019-02-25 18:01:35 +00:00
e38dfd99e8
soc/software/sdram: fix compilation on ultrascale
2019-02-25 16:12:21 +01:00
5f29a12ee7
targets/versa_ecp5: integrate DDR3
2019-02-25 15:27:08 +01:00
3dd529e40b
soc/software/bios/sdram: add ECP5 support
2019-02-25 14:41:33 +01:00
2fd6d0e7e1
soc/software/bios/sdram: improve write_level robustness
2019-02-25 14:38:24 +01:00
36772b75f6
soc/software/bios/sdram: improve sdrlevel readibility
2019-02-25 14:37:31 +01:00
6a980781d3
soc/software/bios/sdram: add helpers for rst/inc of delays
2019-02-25 14:36:47 +01:00
321dd8fcf6
versa_ecp5: Remove negative diff IO pins
...
In Lattice FPGAs only the positive side of differential pairs should
be specified (unlike Xilinx)
These are a warning on Diamond (which trims unused IO) and an error
with Yosys/nextpnr (which doesn't so they conflict when the positive
pin is 'expanded').
Already this is the case for the clock input, this commit performs
the same change for the DDR3 pins.
2019-02-22 12:12:10 +00:00
c03b1ad13a
platforms/versa_ecp5: add ddram pins
2019-02-20 22:45:19 +01:00
ff155a474d
soc/tools/remote/comm_uart: be sure to flush in waiting bytes before read and write
2019-02-16 00:08:24 +01:00
d3ecdd9995
soc/cores/clock: add actual clk_freqs to config
2019-02-14 10:41:27 +01:00
af52842fbb
soc_sdram: add use_full_memory_we parameter to allow disabling vivado workaround on small l2 caches
2019-02-12 12:12:40 +01:00
32543430c0
build/lattice/common/LatticeECXTrellisImpl: add support for nbits == 1
2019-02-11 19:41:12 +01:00
aabf042d38
soc_sdram: don't generate sdram initialization error message when integrated_main_ram is used
2019-02-11 09:23:39 +01:00
f51ad43607
build/lattice/common: add LatticeiCE40DDROutput
2019-02-07 16:23:55 +01:00
22ccf9ddf1
platforms/nexys_video: add LPC transceivers pins
2019-02-01 23:39:17 +01:00
1d9c55888f
build/sim: add jtagremote module (thanks LamdaConcept)
2019-01-30 14:01:19 +01:00
57b8bdd530
soc/integration/soc_core: allow disabling wishbone timeout
2019-01-29 12:47:11 +01:00
05dcb5cadc
soc/interconnect/wishbone: increase bus error timeout to 1e6 cycles
2019-01-27 08:28:01 +01:00
02708d3b0f
boards/platform/kc705: add sfp pins (both tx and rx)
2019-01-23 08:40:47 +01:00
8344a6a4ef
soc/cores/clock: add USIDELAYCTRL
2019-01-22 12:50:05 +01:00
7e0dd37616
soc/integration/soc_sdram: round port.data_width/l2_size to nearest power of 2 when it's not the case
...
With ECC configurations, native port data_width is not necessarily a power of 2.
2019-01-22 09:08:35 +01:00
871b958f85
boards/targets: improve presentation
2019-01-21 10:40:41 +01:00
a318343afb
boards/platforms/kcu105: add si570_refclk
2019-01-21 10:40:37 +01:00
48312890e5
boards/platforms/kc705: use vivado as default programmer
2019-01-21 10:40:32 +01:00
1b23890e0d
soc/cores/clock: allow ClockSignal to be used for clkin
2019-01-16 22:05:52 +01:00
387ee04130
build/sim/core: fix coverage
2019-01-11 15:01:58 +01:00
482abf9b43
build/sim/core: set -Wno-BLKANDNBLK (prevent blocking/non-blocking assigns on a same structure in system verilog)
2019-01-11 13:51:15 +01:00
9c5f654773
build/sim/core: set unroll-count to 256 to prevent Error-BLKLOOPINIT
2019-01-11 13:39:09 +01:00
f132012de1
build/sim: disable Warning-WIDTH
2019-01-10 16:03:09 +01:00
7c67bac723
soc/cores/cpu/vexriscv: set default variant to None in add_sources
2019-01-09 10:28:24 +01:00
648015d78e
soc/cores/cpu/vexriscv: move verilog variant selection to add_sources
2019-01-09 09:19:40 +01:00
2b5a6f1058
targets/kcu105: use USMMCM
2019-01-08 14:14:28 +01:00
86e19e6232
targets: pass speedgrade to S7PLL/S7MMCM
2019-01-08 13:50:12 +01:00
2581a00380
soc/cores/clock: add Xilinx Ultrascale PLL/MMCM
2019-01-08 13:21:53 +01:00
68e1dfca28
boards: avoid duplicating platforms that can be found in migen/litex-buildenv
...
The platforms that are kept are the ones used for litex development.
2019-01-06 19:01:19 +01:00
041bf41226
soc/integration/cpu_interface: generate name for Memories in get_csr_header
2019-01-05 10:57:37 +01:00
9f5d0cef6b
utils/litex_server: allow specify uart_baudrate as float
2019-01-03 10:38:14 +01:00
2c43f6f7dc
targets/ulx3s: use pll for phase shift, enable refresh, memtest ok
2018-12-28 15:58:28 +01:00
5ef4d09caa
targets/versa_ecp5: use pll for phase shift, enable refresh, memtest ok
2018-12-28 15:39:20 +01:00
9c801fbe50
soc/cores/clock/ECP5PLL: add basic phase support
2018-12-28 15:03:12 +01:00
a7b5b9d212
litex_sim: simplify, change sdram module and enable sdram refresh.
2018-12-27 20:36:50 +01:00
2deffd8c8a
build/sim/verilator: compile sim just before running and not when building.
2018-12-21 09:59:34 +01:00
291843ee76
Merge pull request #144 from mithro/nextpnr-migen-update
...
Integrate latest migen changes for lattice/icestorm.
2018-12-20 11:35:42 -08:00
53731b792b
Integrate latest migen changes for lattice/icestorm.
...
Integrated up to 37db6bb52532b6d1c6bc8b724c2e8c6a38546c2a.
2018-12-20 11:33:19 -08:00
180912a7a3
build/sim: handle verilog $finish and if coverage is enabled, write report at the end of the simulation.
2018-12-20 10:38:40 +01:00
b6c98cab0d
platforms/kcu105: change internal vref to 0.84v (recommended value for ddr4)
2018-12-19 11:33:32 +01:00
ebe0d567f8
bios/sdram: only show read delays when they are valid.
2018-12-19 11:19:47 +01:00
67a2590235
bios/sdram: reduce write leveling scan range
2018-12-19 11:18:19 +01:00
fe5cef4294
soc/cores/clock: remove return on S7PLL.create_clkout
2018-12-19 09:14:26 +01:00
eda1a83ea9
platforms/kcu105: set internal vref on ddr4 banks
2018-12-18 21:38:23 +01:00
a27b5a3be1
update Ultrascale DDRPHY
2018-12-18 11:25:21 +01:00
1c1c1bd122
Merge pull request #141 from mithro/xst-fix
...
Fix `-vlgincdir` for xst.
2018-12-17 21:24:15 -08:00
8b2abc7e89
Fix `-vlgincdir` for xst.
...
The command line is of the form;
```
-vlgincdir {"path1" "path2"}
```
Fixes the following error;
```
WARNING:Xst:3164 - Option "-vlgincdir" found multiple times in the command line. Only the first occurence is considered.
```
2018-12-17 21:11:14 -08:00
f8f3683aaa
bios/sdram: reduce scans verbosity on ultrascale
2018-12-17 16:00:44 +01:00
efce434aa9
bios/sdram: use ddrphy_half_sys8x_taps_read() for KUSDDRPHY
2018-12-17 11:43:21 +01:00
22d454efcd
Hack to fix #136 .
2018-12-16 14:40:10 -08:00
fa6fef1e15
Merge pull request #135 from mithro/icestorm-ice40up5k
...
Add uwg30 package and up3k part.
2018-12-16 14:04:19 -08:00
9481781d1c
Add uwg30 package and up3k part.
2018-12-16 14:03:29 -08:00
e9f1049200
soc/cores/cpu/vexriscv: add add_debug method for debug variants
2018-12-12 10:01:49 +01:00
35155e5172
soc/cores/cpu/vexriscv: add support for the new variants.
2018-12-12 09:39:30 +01:00
2ace45e6f8
soc/cores/cpu/vexriscv: update submodule
2018-12-12 09:38:53 +01:00
6d6c2b4c45
soc/cores/cpu/lm32: add submodule/rtl to include path (needed for lm32_include.v)
2018-12-12 09:38:10 +01:00
584fd51c01
build/sim/verilator: add support for plaform.sources, some cleanup
2018-12-12 09:37:24 +01:00
c9915f89ce
build/microsemi/libero_soc: fix typos
2018-12-12 09:34:43 +01:00
99578bc68c
gen/sim/core: add args support on Display
2018-12-09 09:46:10 +01:00
fa260f5b42
gen/fhdl: add simulation Display, Finish support.
...
In some simulation cases, it's easier to add debug traces directly in the code
than in the verilog/Migen testbench. This adds support for verilog $display in
Migen code.
Being able to terminate a simulation from the code is also useful, this also
add support for verilog $finish.
2018-12-09 09:45:17 +01:00
92a6169d2a
build/sim: add coverage parameter to enable code coverage
2018-12-09 08:10:50 +01:00
0c687bc29e
soc/interconnect/stream: add support for buffered async fifo
2018-12-08 01:24:08 +01:00
bf3b4eec34
gen: integrate migen changes
2018-12-04 21:06:51 +01:00
96527b5a3a
soc/interconnect/stream/gearbox: remove bit reversing by changing words order
2018-11-30 23:12:30 +01:00
1c8c2426b9
Merge branch 'master' of http://github.com/enjoy-digital/litex
2018-11-27 17:45:07 +01:00
8887fc24c4
build/xilinx/vivado: disable xpm by default (can be enabled by passing enable_xpm=True to build).
...
Old version of Vivado don't have XPM support and enable it break the build.
Enabling XPM is only useful in some cases, we can do it manually.
2018-11-27 17:42:39 +01:00
cc4ba65659
Merge pull request #130 from jfng/master
...
litex_sim: add --trace argument
2018-11-27 17:35:03 +01:00
ec46beeb47
targets/ulx3s, versa_ecp5: use ECP5PLL
2018-11-27 17:31:53 +01:00
71398e0155
litex_sim: add --trace argument
2018-11-27 17:26:32 +01:00
18048eb454
cores/clock: test and fix ECP5PLL, phase still not implemented.
2018-11-27 17:24:22 +01:00
20dd95c541
boards/platforms/ulx3s: add gpios 0-3
2018-11-27 14:15:35 +01:00
909cff1940
bios/sdram: flush l2 cache only when present
2018-11-26 18:37:45 +01:00
2ad83778bf
bios: allow testing main_ram at init when using an external controller
2018-11-26 15:21:00 +01:00
cdfe0454bb
build/microsemi/libero_soc: small cleanup
2018-11-26 11:35:06 +01:00
4592e3235b
Merge pull request #128 from mithro/small-fix
...
Two small fixes
2018-11-26 09:48:10 +01:00
4f565c5179
stream.Endpoint: Pass extra arguments to superclass.
2018-11-25 12:57:11 -08:00
3b9e4c4df6
wishbone.SRAM: Support non-32bit wishbone widths.
2018-11-25 12:56:37 -08:00
515c06219a
cores/clock: add ECP5PLL
2018-11-24 00:47:38 +01:00
7623b5dd96
soc/interconnect/stream/gearbox: inverse bit order
2018-11-23 18:34:24 +01:00
d32e393033
soc/cores/spi_flash: add missing endianness parameter
2018-11-23 18:33:53 +01:00
c954943e02
platforms/avalanche: add IOStandard on ddram pins
2018-11-23 12:47:45 +01:00
09a1cda943
build/microsemi/libero_soc: associate timings constraints with synthesis/place&route/timing verification
2018-11-23 09:30:13 +01:00
a98e1ad689
build/microsemi/libero_soc: add additional_timing_constraints
2018-11-23 09:04:42 +01:00
b166882308
build/microsemi/libero_soc: use die/package/speed from platform.device and add tcl_name helper
2018-11-23 08:26:31 +01:00
9df75d7d63
platforms/avalanche: add package/speed to platform.device
2018-11-23 08:24:29 +01:00
953b1f70df
build/microsemi/libero_soc: remove previous impl directory if exists
2018-11-23 08:11:57 +01:00
18d513a146
build/microsemi/libero_soc: give better names to pdc files: io/fp
2018-11-23 08:03:55 +01:00
4f092dbe35
build/microsemi/libero_soc: add additional_constraints
2018-11-22 18:40:19 +01:00
206c9a4697
platforms/avalanche: fix ddram dq7
2018-11-22 18:13:33 +01:00
f003407776
build/microsemi/libero_soc: add {} around port name.
2018-11-22 17:37:03 +01:00
beeca856e5
utils/litex_read_verilog: fix generated indent on instance
2018-11-22 17:33:46 +01:00
1fe7d09fb5
soc/integration/soc_core: add csr_map_update function
2018-11-21 08:39:52 +01:00
89c702187a
libbase/crt0-picorv32: Add support for .data sections.
2018-11-21 00:13:13 -05:00
80bdae0e55
build/sim/verilator: add trace parameter to enable tracer
2018-11-20 18:54:22 +01:00
7359a99bf9
soc_core: convert cpu_type="None" string to None
2018-11-20 17:45:11 +01:00
5805d63013
build/microsemi/libero_soc: only associate timings constraint to timing check (otherwise we loose io constraints...), use default settings for place & route
2018-11-19 16:36:30 +01:00
85f7666207
build/microsemi/common: add async reset synchronizer (using DFN1P0)
2018-11-19 15:35:59 +01:00
e3c6bd5846
build/microsemi/libero_soc: pass timing constraints to synthesis, place & route and timing verification tools
2018-11-19 12:50:07 +01:00
4c966114f8
build/microsemi/libero_soc: add timing constraints support
2018-11-19 09:40:16 +01:00
60faae490a
boards/platforms/avalanche: fix swapped serial pins
2018-11-19 08:45:55 +01:00
52396add5d
boards/platforms/avalanche: rename rst to rst_n (active low reset)
2018-11-19 08:14:46 +01:00
8e07e1a099
build/microsemi/libero_soc: associate .pdc to place and route tool.
...
For constraint to be applied, we also to associate them with the tool that will use it.
2018-11-19 08:07:36 +01:00
a5ed42ec68
soc/interconnect/stream: add Gearbox
2018-11-17 17:29:45 +01:00
a25645afa6
utils: add litex_read_verilog utility
...
generate Migen's modules from verilog files
2018-11-16 16:09:44 +01:00
a538d36268
create utils directory and move the litex utils to it
2018-11-16 14:37:19 +01:00
45ec78e93a
build/microsemi/libero_soc: able to generate design script (tcl) and design constraint (pdc) for libero soc / avalanche board.
2018-11-16 12:19:03 +01:00
4cb6583b4e
build: add microsemi template for polarfire fpgas support
2018-11-15 18:21:41 +01:00
b1425ba85f
lattice/icestorm: Add toolchain_path so it doesn't end up kwargs.
...
Fixes the following error;
```
make[1]: Leaving directory `/home/travis/build/mithro/litex-buildenv/build/ice40_hx8k_b_evn_base_lm32.lite/software/stub'
Traceback (most recent call last):
File "./make.py", line 164, in <module>
main()
File "./make.py", line 148, in main
vns = builder.build(**dict(args.build_option))
File "/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/soc/integration/builder.py", line 171, in build
toolchain_path=toolchain_path, **kwargs)
File "/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/soc/integration/soc_core.py", line 389, in build
return self.platform.build(self, *args, **kwargs)
File "/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/build/lattice/platform.py", line 29, in build
return self.toolchain.build(self, *args, **kwargs)
File "/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/build/lattice/icestorm.py", line 139, in build
v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
File "/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/build/lattice/platform.py", line 26, in get_verilog
**kwargs)
File "/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/build/generic_platform.py", line 368, in get_verilog
create_clock_domains=False, **kwargs)
TypeError: convert() got an unexpected keyword argument 'toolchain_path'
```
2018-11-13 16:18:08 -08:00
af25bf2bc0
soc_core: check for cpu before checking interrupt
2018-11-13 16:17:49 +01:00
b4bdf2a023
cores/clock/S7: just reset the generated clock, not the PLL/MMCM
2018-11-13 14:47:04 +01:00
86fd945bc3
bios/main: fix typo on mor1kx
2018-11-13 11:16:06 +01:00
af95028574
cpu/mor1kx: use clang only for linux variant
2018-11-13 11:09:39 +01:00
04523bc28a
xilinx/vivado: fix migen merge
2018-11-12 16:31:51 +01:00
f3343c46fc
platforms: remove versaecp55g_sdram
2018-11-12 12:45:33 +01:00
58414b1819
build/xilinx/vivado: merge migen change
2018-11-12 12:00:30 +01:00
a7f17f9915
build: use default toolchain_path on all backend when passed value is None
2018-11-12 11:48:30 +01:00
eed1d5cb2e
generic_platform: use set for sources
2018-11-12 11:47:39 +01:00
665fff8390
build: merge more migen changes
2018-11-12 11:26:35 +01:00
70f48775de
platforms/versa_ecp5: import migen changes
2018-11-12 10:52:28 +01:00
4ff241b981
targets/ulx3s,versa_ecp5: prjtrellis toolchain renamed to trellis
2018-11-12 10:47:33 +01:00
cb86728ad1
build/lattice: import changes from migen
2018-11-12 10:46:49 +01:00
8574c62f75
targets/versa_ecp5: increase sys_clk_freq to 50MHz
2018-11-12 10:12:10 +01:00
a752dafb14
targets: add versa_ecp5 with sdram (ecp5 soc hat) at 25MHz/no pll
2018-11-12 09:45:59 +01:00
87c7d23d16
targets/ulx3s: for now revert to 25MHz clock/no pll
2018-11-12 09:44:32 +01:00
d1baae36a6
platforms/versa_ecp5: add ecp5 soc hat ios
2018-11-12 09:43:31 +01:00
b3bf1c9517
Merge branch 'master' of http://github.com/enjoy-digital/litex
2018-11-12 08:12:07 +01:00
1be6762dfe
Merge pull request #125 from daveshah1/trellis_sdram
...
ecp5 soc hat wip
2018-11-12 08:11:57 +01:00
425ad755ec
plarforms: rename versa/versaecp55g to versa_ecp3/versa_ecp5
2018-11-12 08:06:22 +01:00
c57aa545ca
targets/ulx3s: get memtest working by disabling sdram refresh
...
Will need to be fixed...
2018-11-09 18:40:14 +01:00
9a6447172a
soc/integration/soc_sdram: allow using axi interface with litedram
2018-11-09 15:42:34 +01:00
416bdb6483
boards/platforms: add avalanche polarfire board ios definition
2018-11-08 18:24:12 +01:00
f08f80bed1
working on Versa-5G dram
...
Signed-off-by: David Shah <dave@ds0.me>
2018-11-06 14:39:25 +00:00
fc0d5c3963
bios/sdram: iterate multiple time for write leveling and add vote to eliminate transcients
2018-11-05 18:44:28 +01:00
09f962fdc4
target/kcu105: add reset button
2018-11-05 18:41:49 +01:00
169f8d8cb5
boards/platforms/kcu105: fix sdram/dq pin swap
2018-11-05 17:01:42 +01:00
d78d5d3e7f
Debugging ULX3S SDRAM
...
Signed-off-by: David Shah <dave@ds0.me>
2018-11-05 11:54:22 +00:00
2624ba48c2
bios/sdram: replace DDR3_MR1 constant with DDRX_MR1
2018-11-05 10:47:25 +01:00
6be74aa17f
boards/targets: add kcu105
2018-11-05 10:44:50 +01:00
93c623251b
Merge pull request #122 from daveshah1/trellis_ulx3s
...
Switch Trellis build to use LPF constraints; working on ULX3S
2018-11-02 19:59:23 +01:00
dcbe759b64
build/sim/verilator: don't use --threads when $(THREADS) is unset
2018-11-02 14:22:44 +01:00
6f38213acc
boards/platforms/kc705: add user_sma_mgt_refclk
2018-11-01 10:52:01 +01:00
4cdd679908
Merge pull request #123 from cr1901/prv32-min
...
PicoRV32 Enhancements
2018-11-01 10:45:32 +01:00
e56f71824d
libbase/crt0-picorv32: Emulate support for a relocatable IRQ vector (hardcoded at synthesis time).
2018-11-01 05:02:04 -04:00
f32121e0e1
cpu/picorv32: IRQ vector needs to be moved to 16 bytes after the RESET vector.
2018-11-01 02:23:01 -04:00
77389d27b5
libbase/crt0-picorv32: Ensure BSS is cleared on boot.
2018-11-01 02:18:03 -04:00
f7969b660a
cores/clock: add with_reset parameter (default to True)
...
In some cases we want to generate the reset externally.
2018-10-31 16:23:23 +01:00
0729b3a059
ulx3s: Connect SDRAM clock
...
Signed-off-by: David Shah <dave@ds0.me>
2018-10-31 13:29:35 +00:00
8404434956
Fix Trellis build; ULX3S demo boots to BIOS
...
Signed-off-by: David Shah <dave@ds0.me>
2018-10-31 12:27:05 +00:00
0c1d8d5993
trellis: Switch to using LPF for constraints
...
Signed-off-by: David Shah <dave@ds0.me>
2018-10-31 11:43:39 +00:00
445c49400f
boards/platforms/kcu105: add sfp_tx/rx definition
2018-10-31 10:48:48 +01:00
f69bd877b9
cpu/picorv32: Create minimal variant (disable mul/div insns, most speed optimizations).
2018-10-30 06:00:45 -04:00
d05fe673a0
cpu/picorv32: Extract picorv32 parameters from Instance constructor to facilitate creating variant CPUs.
2018-10-30 06:00:45 -04:00
e9d4c882ba
build/lattice/prjtrellis: fix default toolchain_path
2018-10-30 10:28:12 +01:00
468780c045
soc/cores/spi_flash: add endianness parameter
2018-10-30 10:19:21 +01:00
6f3131e259
soc/interconnect/stream_packet: use reverse_bytes from litex.gen
2018-10-30 10:16:55 +01:00
b796853893
gen: add common with reverse_bits/reverse_bytes functions
2018-10-30 10:15:29 +01:00
71fc34d7b6
boards/targets/ulx3s: reduce l2_size
2018-10-30 10:14:48 +01:00
75d073f394
build/lattice/prjtrellis: fix typo
2018-10-30 10:14:30 +01:00
6048a5291c
build/lattice/prjtrellis: modify generated verilog instead of creating a wrapper, handle inouts.
...
nextpnr expects TRELLIS_IO on all ios, it's not possible to ensure that with a wrapper.
We now just modify the generated verilog to insert the io constraints and TRELLIS_IOs.
2018-10-30 08:54:30 +01:00
2243f628f7
build/lattice/common: fix LatticeECPXPrjTrellisTristateImpl
2018-10-30 08:47:12 +01:00
f3111e1142
Update vivado.py
...
Fix regression which caused Vivado to not be run at all.
2018-10-29 23:43:32 -04:00
98fa899692
boards/targets: add ulx3s
2018-10-29 19:24:28 +01:00
7d779473f1
boards/platforms: add ulx3s
2018-10-29 19:23:59 +01:00
d9dcad33a4
build/lattice/prjtrellis: add inout support
2018-10-29 19:23:21 +01:00
091ad799b0
build/lattice/common: add tristate support
2018-10-29 19:22:04 +01:00
23acefb14e
boards/targets/versaecp55g_prjtrellis: simple.py example working, specific target no longer needed
...
simple.py configuration tested:
python3 simple.py --cpu-type=lm32 --gateware-toolchain=prjtrellis litex.boards.platforms.versaecp55g
python3 simple.py --cpu-type=vexriscv --gateware-toolchain=prjtrellis litex.boards.platforms.versaecp55g
2018-10-29 16:02:25 +01:00
1097f82283
build/lattice/prjtrellis: set default toolchain_path to "/opt/prjtrellis"
2018-10-29 15:58:54 +01:00
52917a710e
boards/targets/simple: add gateware-toolchain parameter
2018-10-29 15:56:46 +01:00
d84083f642
boards/platforms/versaecp55g: use ftdi serial pins
2018-10-29 15:39:51 +01:00
c05b9ef2ad
build/lattice/prjtrellis: test and fix iowrapper multi-bit signals support
2018-10-29 13:26:29 +01:00
a8f819fec2
Merge branch 'master' of http://github.com/enjoy-digital/litex
2018-10-29 11:48:10 +01:00
4eb314a252
boards/targets/versaecp55g: use new iowrapper support, basic led blink and ios working :)
2018-10-29 11:46:03 +01:00
27ec2a59e2
build/lattice/prjtrellis: generate iowrapper to set constraints and TRELLIS_IO
...
PrjTrellis does not yet have constraint files support, constraints are set
with signal attributes and specific TRELLIS_IO instances are requested. This
iowrapper does this work for us automatically.
Remove this code and replace with a constraint file generation code when
PrjTrellis will have constraint file support.
2018-10-29 11:44:31 +01:00
c506c9752c
gen/fhdl/verilog: set direction to io signals
2018-10-29 11:41:04 +01:00
1cac079efa
litex/build: Always run Vivado.
...
When using Yosys for synthesis, still need Vivado for place and route.
2018-10-29 02:04:44 -07:00
49dab3b448
build/lattice/prjtrellis: simplify code, remove some workarounds
2018-10-29 09:40:35 +01:00
a73d9d96b1
build/xilinx/vivado: fix merge issue
2018-10-29 08:26:13 +01:00
3e189379f9
boards/targets: add versa ecp55g prjtrellis target (experimental)
2018-10-28 19:34:17 +01:00
a69197d2db
build/lattice: add initial prjtrellis support
2018-10-28 17:51:16 +01:00
397e3c7682
build/lattice/diamond: use bash on linux
2018-10-28 15:40:52 +01:00
d029cd243d
build/lattice: improve special_overrides names (vendor_family)
2018-10-28 15:40:10 +01:00
b200ce9983
Merge branch 'master' into xilinx+yosys
2018-10-28 14:59:03 +01:00
ba0dd5728e
uart: Enable buffering the FIFO.
...
On the iCE40 FPGA, adding buffering allows the SyncFIFO to be placed in
block RAM rather than consuming a large amount of resources.
2018-10-27 16:04:58 -07:00
e3935b481e
build/sim/verilator: don't use THEADS parameters when threads=1
...
Allow using old (non multi-threaded) version of Verilator
2018-10-27 11:06:34 +02:00
a44181e716
soc_sdram: update litedram
2018-10-19 18:37:55 +02:00
ab6a530a24
bios/sdram: s7ddrphy now has bitslip in fabric, show scan for each module/bitslip and remove silent mode
2018-10-18 13:42:51 +02:00
b8be9545cc
build/xilinx/vivado: enable xpm libraries
2018-10-18 09:25:34 +02:00
ab8cf3e345
soc/cores/clock: add margin parameter to create_clkout (default = 1%)
2018-10-16 14:57:37 +02:00
915c2f417a
bios/sdram: improve write/read leveling
...
write_leveling: select last 0 to 1 transition.
read_leveling: do it by module (select best bitslip for each module)
2018-10-10 10:42:56 +02:00
deffa60324
platforms/kc705: add ddram_dual_rank
2018-10-09 15:39:03 +02:00
10624c26da
bios/main: handle all types of carriage return (\r, \n, \r\n or \n\r)
2018-10-09 10:06:51 +02:00
9f083e9bd3
Merge pull request #116 from stffrdhrn/sim-uart
...
sim: serial: Send '\r\n' instead of just '\n'
2018-10-09 07:32:31 +02:00
8877dba7e9
sim: serial: Send '\r\n' instead of just '\n'
...
This fixes an issue when running with the HDMI2USB firmware which
expects \r\n to come from the UART. Since the verilator adapter
is just sending \n commands cannot be executed.
Also, one minor whitespace cleanup. (could remove if needed)
2018-10-09 11:18:11 +09:00
d187921500
cpu_interface: fix select_triple when only one specified
2018-10-08 17:01:04 +02:00
3b27d2ae89
soc/integration/cpu_interface: generate error if unable to find any of the cross compilation toolchains
2018-10-06 21:32:38 +02:00
168b07b9a2
soc_core: add csr range check
2018-10-06 20:55:16 +02:00
ace976242e
build.xilinx: Convert attributes to something Yosys understands.
...
Convert keep, dont_touch and async_reg to something Yosys understands.
Write out an EDIF file with the attributes so that Vivado can use them.
(Requires Yosys with commit
115ca57647
2018-10-05 12:48:30 -07:00
6febb6826c
Merge pull request #112 from cr1901/8k-b-evn
...
build/platforms: Add ice40_hx8k_b_evn from Migen.
2018-10-04 21:12:33 +02:00
ff6de429f0
Fix help for or1k builds
...
The help said cpu-type could be mor1kx, which is correct but you must
pass or1k to get mor1kx. Fix the message to properly represent what
needs to be passed to the commandline.
2018-10-04 23:09:49 +09:00
dafdb8df72
Fix compiler warnings from GCC 8.1
...
Fix these 2 warnings:
litex/build/sim/core/libdylib.c:42:5: warning: 'strncpy' specified bound 2048 equals destination size
[-Wstringop-truncation]
strncpy(last_err, s, ERR_MAX_SIZE);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In function 'set_last_error',
litex/soc/software/libbase/exception.c:28:13: warning: function declaration isn't a prototype [-Wstrict-prototypes]
static char emerg_getc()
2018-10-04 23:07:48 +09:00
2be5205463
build/xilinx/common: update XilinxDDRInputImplS7 and XilinxDDRInputImplKU (from migen)
2018-10-04 08:17:44 +02:00
78414c0588
xilinx/viviado: Allow yosys for synthesis.
2018-10-03 21:58:03 -07:00
d13ac3b3d5
cpu/mor1kx: Adding verilog include directory.
2018-10-03 21:57:24 -07:00
9a44f08a3e
build/platforms: Add ice40_hx8k_b_evn from Migen.
2018-10-03 20:53:33 -04:00
dc7cd75757
build.xilinx: Run `phys_opt_design` and generate timing report.
...
Makes the flow more similar to migen.
2018-10-03 16:02:43 -07:00
948527b0fe
cores/cpu: revert vexriscv (it seems there is a regression in last version)
2018-10-02 12:30:11 +02:00
15bca4535f
targets/sim: fix integrated_main_ram_size when with_sdram
2018-10-02 11:31:08 +02:00
6e327cda26
bios/sdram: rewrite write_leveling (simplify and improve robustness)
2018-10-01 15:38:19 +02:00
975be6686f
platforms/genesys2: add eth clock timing constraint
2018-10-01 15:37:34 +02:00
934a5da559
soc/cores/clock: add expose_drp on S7PLL/S7MMCM
2018-09-28 13:02:10 +02:00
9097573e71
Merge pull request #109 from cr1901/xip-improve
...
Improve XIP Support
2018-09-25 15:32:04 +02:00
082b03016c
targets: use new clock abstraction on all 7-series targets
2018-09-25 09:31:30 +02:00
74e74dc0e7
soc/cores/clock: different clkin_freq_range for pll and mmcm
2018-09-25 09:09:47 +02:00
91d8cc2d6a
soc/cores/clock: different vco_freq_range for pll and mmcm
2018-09-25 09:04:38 +02:00
6cd954940c
soc/core/clock: allow selecting buffer type (None, BUFG, BUFR). (default = BUFG)
2018-09-25 08:36:18 +02:00
912ca3236b
soc/cores/clock: create specific S7IDELAYCTRL module
2018-09-24 23:22:59 +02:00
baec87f530
soc/cores/clock: add S7MMCM support
2018-09-24 23:20:12 +02:00
ef40524924
soc/cores/clocks/S7PLL: add speedgrade support, default to -1 (slowest)
2018-09-24 22:58:23 +02:00
5415b521be
targets/arty: use new clock abstraction module (compile, untested on board)
2018-09-24 22:49:30 +02:00
63fc395006
soc/cores: init clock abstraction module
2018-09-24 22:49:01 +02:00
0ff6d58605
Distinguish crt0 variants more clearly, update BIOS to use CTR variant (as it has no .data section).
2018-09-24 14:48:54 -04:00
8106008184
integration/builder: Create EXECUTE_IN_PLACE Makefile variable to complement COPY_TO_MAIN_RAM.
2018-09-24 12:28:45 -04:00
db90619067
integration/builder: Add LiteX define to generated variables (to distinguish MiSoC and LiteX).
2018-09-24 11:04:57 -04:00
70a32ed86f
sim/verilator: add multithread support (default=1)
2018-09-24 12:43:29 +02:00
7f0d116d88
soc_core: use cpu instead of cpu_or_bridge internally (keep retro-compat for now)
2018-09-24 10:59:32 +02:00
22febe9582
boards/targets: uniformize things between targets
2018-09-24 10:58:10 +02:00
01b025aafd
soc_core/get_mem_data: add endianness support and use it in builder/initialize_rom to avoid duplication
2018-09-24 08:01:32 +02:00
b528a005a0
cores/cpu: add software informations to cpu and simplify cpu_interface
2018-09-24 07:51:41 +02:00
2d785cb0ac
boards/plarforms: fix issues found while testing simple design on all platforms
2018-09-24 02:03:30 +02:00
c88029d330
soc_core: add uart-stub argument
2018-09-24 02:01:15 +02:00
e9ed737037
ease RemoteClient import
2018-09-23 10:23:00 +02:00
6f25a0d8a1
csr: use external csr_readl()/csr_writel() if present
...
If the variable CSR_ACCESSORS_DEFINED is set, then use external
csr_readl() and csr_writel() instead of locally-generated inline
functions.
With this patch, csr.h can be used with etherbone.h and litex_server to
prototype drivers remotely.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-09-22 16:55:09 +02:00
9a252e367c
csr: use readl()/writel() accessors for accessing mmio
...
Instead of directly dereferencing pointers, use variants on readl()/writel().
This way we can replace these functions with others for remote access
when writing drivers and code outside of the litex environment.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-09-22 16:54:46 +02:00
9d4da737ff
libbase/crt0-lm32.S: Add provisions for loading .data from flash.
...
:100644 100644 e0cd7153
2018-09-21 10:23:14 -04:00
15e584d880
targets/sim: generate analyzer.csv
2018-09-20 12:20:48 +02:00
cde72603a1
targets/sim: generate csr.csv
2018-09-20 11:17:18 +02:00
f62df5023f
targets/sim: add rom-init
2018-09-20 01:14:00 +02:00
1dbf591e78
targets/sim: add ram-init param to allow initializing ram from file (faster than tftp)
2018-09-20 01:00:13 +02:00
9893c2460a
integration/soc_core: add get_mem_data function to read memory content from file
2018-09-20 00:46:06 +02:00
a3eb2e403b
soc/intergration/builder: fix when no sdram
2018-09-19 23:59:42 +02:00
934b08ede8
targets/sim: merge in a single class and ease configuration
2018-09-19 23:59:15 +02:00
bd42b18856
Merge branch 'master' of http://github.com/enjoy-digital/litex
2018-09-19 19:21:14 +02:00
3e77ae788f
targets: replace MiniSoC with EthernetSoC
2018-09-19 19:19:50 +02:00
badd992469
targets/sim: add EtherboneSoC target (allow accessing wishbone over in simulation with litex_server)
2018-09-19 19:17:32 +02:00
537b0e9058
Merge pull request #101 from cr1901/icestorm-migen-pull
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Icestorm Improvements
2018-09-18 08:19:09 +02:00
5c83c88128
Pull in b2740d9 from Migen. nextpnr now default, write out build scripts on dry run.
2018-09-17 21:17:24 -04:00
9c6f76f18c
bios/sdram: mode sdhw()
2018-09-13 06:33:54 +02:00
a44bedd557
bios/sdram: add missing #ifdef
2018-09-13 06:30:37 +02:00
0e68daebf3
targets: self.pll_sys --> pll_sys
2018-09-13 05:31:35 +02:00
1468b9f3ba
bios/sdram: show all read scans when failing.
2018-09-13 05:26:51 +02:00
07e4c183cd
cpu/lm32: re-enable multiplier/divider in minimal variant (does not seem to work correctly on hardware otherwise)
2018-09-12 06:02:23 +02:00
df3f003ecd
soc_sdram: update with litedram
2018-09-09 02:13:00 +02:00
bebc667da6
Merge pull request #99 from cr1901/mk-copy-main-ram
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Add COPY_TO_MAIN_RAM generated Makefile variable to distinguish systems with/without "main_ram" region.
2018-09-08 03:55:23 +02:00
bd70ba278b
Add COPY_TO_MAIN_RAM generated Makefile variable to distinguish systems with/without main_ram region.
2018-09-07 21:49:24 -04:00
69716852f1
Merge pull request #100 from cr1901/tinyprog-fix
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lattice/programmer: Use --program-image option with tinyprog if addre…
2018-09-08 03:48:04 +02:00
12a8944711
soc_sdram: revert vivado l2 cache workaround (still seems to cause issues on some cases...)
2018-09-07 11:51:17 +02:00
2b786065b1
targets: pass endianness to LiteEThMAC, tftp working with RISC-V, still need to fix txlen
2018-09-07 10:37:15 +02:00
c812321a93
lattice/programmer: Use --program-image option with tinyprog if address is given.
2018-09-07 04:05:49 -04:00
26963d62fa
libnet/microudp: (WIP) fix endianness issues
2018-09-06 18:43:55 +02:00
22c0131324
fix typo and unused include
2018-09-06 17:07:14 +02:00
fb24ac0ecc
cpu/minerva: add workaround on import until code is released
2018-09-06 16:40:30 +02:00
8f377307d8
add Minerva support
2018-09-05 22:33:04 +02:00
1944289e64
litex_server: update pcie and remove bar_size parameter
2018-09-05 13:01:51 +02:00
c5a2d6f3ec
Merge pull request #96 from cr1901/tinyfpga_bx
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build/platforms: Add TinyFPGA BX board and programmer.
2018-09-03 20:49:33 -07:00
2949262449
build/platforms: Add TinyFPGA BX board and programmer.
2018-09-03 23:39:40 -04:00
ed507d618d
Add lm32 "lite" variant, remove mult/div from "minimal" and update compiler flags accordingly.
2018-09-03 19:48:19 -04:00
7af89efc70
lattice/icestorm: Add nextpnr pnr as alternate pnr tool.
2018-08-28 05:17:32 -04:00
ff908e404f
Merge pull request #92 from cr1901/l2-gate
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software/bios: Gate flush_l2_cache() if L2 Cache isn't present.
2018-08-23 13:15:49 +10:00
3146109af3
software/bios: Gate flush_l2_cache() if L2 Cache isn't present.
2018-08-22 23:03:08 -04:00
759e7d4dc3
bios/sdram: improve/simplify read window selection
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Compute a score for each window and select the best
2018-08-22 23:15:32 +02:00
09776b77e6
sim: run as root only when needed (ethernet module present)
2018-08-22 15:20:28 +02:00
06e835a3f8
builder: change call to get_sdram_phy_c_header and also pass timing_settings
2018-08-22 14:28:37 +02:00
ee26f8c5ae
soc_sdram: cosmetic
2018-08-22 13:40:22 +02:00
2db5424ae6
soc_sdram: vivado is now able to implement the l2_cache correctly (tested with vivado 2017.2 and >)
2018-08-22 13:28:23 +02:00
45e9a42c7e
soc_core: add cpu_endianness
2018-08-21 19:10:22 +02:00
3877d0f111
builder: get_sdram_phy_header renamed to get_sdram_phy_c_header
2018-08-21 18:15:57 +02:00
c64e44ef3f
soc_sdram: use new LiteDRAMWishbone2Native and port.data_width
2018-08-21 14:52:28 +02:00
2eeccc5054
vexriscv: update
2018-08-21 11:04:15 +02:00
eecc6f68ed
soc/integration: move sdram_init to litedram
2018-08-20 15:36:51 +02:00
077f939169
Vexriscv: update csr-defs.h
2018-08-18 14:15:43 +02:00
4225c3b87c
update Vexriscv
2018-08-18 14:14:00 +02:00
9547938527
bios/sdram: changes to ease manual read window selection
2018-08-18 13:45:22 +02:00
a760322fbd
litex_server: allow multiple clients to connect to the same server
2018-08-17 16:09:08 +02:00
8a69a47e7b
cpu/lm32: add minimal variant with no i/d cache, pipelined barrel shifter and multiplier (useful to build SoC on small FPGAs like ice40)
2018-08-17 08:32:32 +02:00
cb5b4ac468
bios/boot: flush all caches before running from ram
2018-08-16 19:47:43 +02:00
650ac18685
sim/verilator: catch ctrl-c on exit and revert default termios settings
2018-08-16 15:13:27 +02:00
0831ad5492
cpu_interace: use riscv64-unknown-elf if available else riscv32-unknown-elf
2018-08-16 10:04:09 +02:00
1610a7f3fb
bios/sdram: fix read_level_scan result
2018-08-14 18:33:36 +02:00
3c7890cdd4
Fix generating csr.csv file
...
Fix generating csr.csv file when no absolute path is given.
2018-08-12 13:37:39 +02:00
9fa234da50
soc/intergration/cpu_interface: typo
2018-08-08 08:53:54 +02:00
22f645adc1
bios/main: use edata instead of erodata
2018-08-07 09:02:09 +02:00
580efecc8c
picorv32: add reset signal
2018-08-07 08:59:34 +02:00
0429ee9f8f
soc/software/bios: add reboot command
2018-08-06 12:23:50 +02:00
da75159814
soc/integration/soc_core: add Controller with reset, scratch and bus_errors registers
2018-08-06 12:23:16 +02:00
8ba5625227
soc/interconnect/wishbone: add Timeout to avoid stalling bus when not responding and generate error.
2018-08-06 12:21:18 +02:00
c0989f65dd
soc/cores/cpu: add reset signal
2018-08-06 12:19:23 +02:00
fb145daced
tools: remove vexriscv_debug
...
This program is no longer needed.
The `openocd_vexriscv` package natively supports `etherbone`, and now
that the vexriscv debug module is available on Wishbone instead of as a
CSR, this module no longer works.
This change simplifies both tooling (because there is one fewer program
to run) and integration (because you don't need to modify your CSRs
anymore, just `register_mem()`.)
Signed-off-by: Sean Cross <sean@xobs.io>
2018-07-27 15:25:33 +08:00
f17b8324d4
vexriscv: reset wishbone bus on CPU reset
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If the CPU is resetting during a Wishbone transfer, assert the ERR line.
Because the resetOut line is likely multiple cycles long, this should
give Wishbone enough time to finish its transfer, which will cause d.stb
and i.stb to go to 0, which will return d_err and i_err to 0.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-07-27 15:24:43 +08:00
c87ca4f1c3
vexriscv: put debug bus directly on wishbone bus
...
By placing the VexRiscv debug bus on the Wishbone bus, the Etherbone
core can access 32-bit values directly from the core. Additionally,
both reading and writing are supported without the need to do a SYNC
register as before.
Additionally, the address of the Wishbone bus won't move around anymore,
as it's fixed when doing `self.register_mem()`.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-07-27 15:24:43 +08:00
8a311bf4a6
build/generic_platform: use list for sources instead of set
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Ideally, we want to use an ordered set (to be able to keep compilation order), to avoid using an external package, we use a list.
2018-07-20 10:01:33 +02:00
df7e5dbcf6
bios/sdram: add ERR_DDRPH_BITSLIP constant and some cleanup
2018-07-19 12:52:00 +02:00
1564b440eb
soc/integration/soc_sdram: add assertion on csr_data_width since BIOS only support SDRAM initialization for csr_data_width=8
2018-07-19 12:51:16 +02:00
c314193cc9
boards/plarforms/genesys2: replace user_dip_sw with user_sw
2018-07-18 12:48:44 +02:00
10dd55fd88
boards/platforms/genesys2: add minimum HPC connectors to be able to test SATA, add programmer parameter
2018-07-18 11:51:58 +02:00
85308672d3
software/bios/linker: revert data section since required by RISC-V compiler
2018-07-18 09:30:14 +02:00
55dd58b023
Merge pull request #80 from xobs/fix-vexriscv-csr-read
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vexriscv_debug: use csr read()/write() accessors
2018-07-17 17:31:48 +02:00
41a9e7d9ae
vexriscv_debug: use csr read()/write() accessors
...
CSR access widths can be different from register widths. 8-bit
registers are common.
The runtime-generated `read()` and `write()` functions handle this
mapping correctly. When direct register accesses are handled, this
mapping is lost.
Use the accessor functions rather than directly accessing the memory
addresses, so that we work on platforms other than 32-bit-wide.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-07-17 18:03:58 +08:00
7ecdcaca4b
soc/integration/sdram_init: use fixed burst_length for each memtype (even in 1:2, use BL8 for DDR3 since BL4 is not efficient)
2018-07-16 18:40:36 +02:00
a4caa8964a
targets/nexys_video: remove read leveling constants (now automatic)
2018-07-16 09:44:15 +02:00
d825004173
targets/nexys4ddr: s7ddrphy now supports ddr2, working
2018-07-16 09:43:09 +02:00
4f1274e6a6
bios/sdram: improve bitslip selection when window can't be optimal (not enough taps for a full window)
2018-07-16 09:42:09 +02:00
7dbd85a842
soc/cores/uart: rename UARTMultiplexer to RS232PHYMultiplexer. UARTMultiplexer now acts on serial signals (tx/rx)
2018-07-10 22:32:51 +02:00
ef1c778446
soc_core: add csr_expose parameter to be able to expose csr bus (useful when design is integrated in another)
2018-07-10 13:29:32 +02:00
f9104b201a
bios/sdram: improve read leveling (artix7 read-leveling is now done automatically at startup)
2018-07-06 19:22:33 +02:00
c84e189d6a
bios/sdram: fix compilation with no write leveling
2018-07-06 16:22:49 +02:00
be8eb5ff84
vexriscv: debug: fix reading DATA register
...
The REFRESH register accepts an 8-bit address and determines which
register to refresh. Since there are only two addresses currently in
use, this register can be either 0x00 or 0x04.
A refactor replaced the compare with one that checked for any 0 bits.
Since both 0x00 and 0x04 have 0 bits, this check always evaluated as
true, causing the logic to always refresh the CORE register.
Replace this check with an explicit check for 0x00.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-07-06 18:22:32 +08:00
6bc9265c2b
setup: add vexriscv_debug to list of entrypoints
...
Add the vexriscv_debug program to the list of scripts created when
installing this module. This program is a simple bridge that allows
openocd to talk to the vexriscv core so it can be debugged.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-07-06 16:22:11 +08:00
45a649be9b
tools: vexriscv_debug: add debug bridge
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Add a bridge that uses litex_server to go from openocd to wishbone.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-07-06 16:08:06 +08:00
c821a0feab
cores/cpu/vexriscv: create variants: None and "debug", some cleanup
2018-07-05 17:31:23 +02:00
59fa71593d
core/cpu/vexriscv/core: improve indentation
2018-07-05 16:51:40 +02:00
6068f6ce9c
Merge pull request #77 from xobs/debug-vexriscv-enjoy
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Enable support for vexriscv debugging
2018-07-05 16:46:24 +02:00
11e8491547
platforms/arty_s7: keep up to date with Migen
2018-07-05 12:02:14 +02:00
32d5a751db
soc_core: uart: add a reset line to the UART
...
Enable resetting the UART by adding a ResetInserter to the UART.
The UART must be reset when resetting the softcore.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-07-05 17:25:29 +08:00
1ef127e06d
soc: integration: use the new cpu_debugging flag for vexriscv
...
Allow a new cpu_debugging flag to be passed to the constructor to
enable in-circuit live debugging of the softcore under gdb.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-07-05 17:25:29 +08:00
e7c762c8c3
soc: vexriscv: add cpu debug support
...
Add support for debugging the CPU, and gate it behind a new cpu_debug
parameter. With this enabled, a simple Wishbone interface is provided.
The debug version of the core adds two 32-bit registers to the CPU.
The register at address 0 indicates status, and is used to halt
and reset the core.
The debug register at address 4 is used to inject opcodes into the
core, and read back the result.
A patched version of OpenOCD can be used to attach to this bus via
the Litex Ethernet or UART bridges.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-07-05 17:25:28 +08:00
2024542a3c
vexriscv: verilog: pull debug-enabled verilog
...
The upstream vexriscv repo now generates both the current VexRiscv.v
softcore, as well as VexRiscv-Debug.v. This -Debug varient exposes
their specialized debug bus that allows for attaching a modified version
of openocd.
Sync the litex repo with the upstream version to take advantage of debug
support.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-07-05 17:25:27 +08:00
d35dc5cdea
platforms/arty: merge with Migen
2018-07-05 11:18:49 +02:00
fa0215660b
platforms/kc705: keep up to date with Migen
2018-07-05 10:43:26 +02:00
b9f3b49c63
platforms/de0nano: keep up to date with Migen
2018-07-05 10:42:45 +02:00
df99cc66e8
bios/sdram: also check for last read of scan to choose optimal window
2018-07-02 14:12:27 +02:00
8ce7fcb237
bios/main: add cpu frequency to banner
2018-07-02 13:47:18 +02:00
477d224921
bios/sdram: check for optimal read window before doing read leveling, increment bitslip if not optimal.
2018-07-02 13:46:48 +02:00
9e737d3c57
soc/cores/code_8b10b: update (from misoc)
2018-06-29 14:24:44 +02:00
d58eb4ecb7
bios/sdram: use new phy, improve scan, allow disabling high skew
2018-06-28 18:43:48 +02:00
692cb14245
software/bios: fix picorv32 boot_helper
2018-06-28 11:42:43 +02:00
b5ee110e63
bios/sdram: add write/read leveling scans
2018-06-27 15:31:54 +02:00
34b2bd0c28
boards: add genesys2 (platform with clk/serial/dram/ethernet + target)
2018-06-27 11:27:05 +02:00
8edc659d7d
soc_core: remove assert on interrupt (added to catch design issues, but too restrictive for some usecases)
2018-06-19 11:15:29 +02:00
2c13b701f5
soc/integration/cpu_interface: add shadow_base parameter
2018-06-18 18:01:47 +02:00
7444992999
soc: bios: fix windows build
...
The BIOS builds just fine on Windows, but afterwards tries to run
`chmod`. This command does not exist on Windows, and is unnecessary.
Add a conditional guard to prevent this command from running on Windows.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-06-18 17:13:54 +08:00
18f86881d9
targets: change a7/k7ddrphy imports to s7ddrphy
2018-06-12 15:40:45 +02:00
3e723d152a
soc/cores/cpu: add add_sources static method
...
When creating SoC with multiple sub-SoC already generated, we need an
easy way to add cpu sources.
2018-06-12 10:54:20 +02:00
7353197e21
fix the vexriscv boot helper
2018-05-31 01:24:22 +08:00
34a9303448
Fix for missing connectors for arty boards
2018-05-24 21:55:52 +03:00
e7d1683e34
litex_term: cleanup getkey and revert default settings on KeyboardInterrupt
2018-05-24 08:10:05 +02:00
6854c7f5fc
soc/integration/cpu_interface: use riscv64 toolchain instead of riscv32 (prebuild toolchain for windows can be found at http://gnutoolchains.com/ )
2018-05-09 15:39:25 +02:00
66229c8c05
add VexRiscv support (imported/adapted from misoc)
2018-05-09 15:03:37 +02:00
f60da4a5dc
add VexRiscv submodule
2018-05-09 14:39:31 +02:00
d149f386c9
allow multiple riscv32 softcores (use picorv32 cpu_type instead of riscv32)
2018-05-09 13:26:55 +02:00
c3652935d9
build: use our own fhdl/verilog code (needed to avoid combinatorial loop in simulation)
2018-05-01 12:02:54 +02:00
121eaba722
soc/intergration/soc_core: don't delete uart/timer0 interrupts
2018-05-01 00:46:26 +02:00
39ffa532b0
xilinx/programmer: fix programmer
2018-05-01 00:44:13 +02:00
c001b8eaf6
build/xilinx/vivado: add vivado ip support
2018-04-12 17:55:46 +02:00
43f8c230a7
soc_core: uncomment uart interrupt deletion
2018-04-12 17:23:46 +02:00
d7c7474670
gen/sim: fix import to use litex simulator instead of migen simulator
2018-04-04 15:40:53 +02:00
b7f7c8d159
build/xilinx/common/XilinxDDROutputImplS6: DDR_ALIGNMENT="C0" requires SRTYPE to be "ASYNC"
2018-03-12 09:33:05 +01:00
4324c6f666
bios/sdram: update kuddrphy initialization procedure
2018-03-08 13:54:30 +01:00
90dcd45f0b
soc/software/main: go to new line at startup
2018-03-07 21:39:10 +01:00
6706b24167
software/bios/main: add missing space
2018-03-07 15:24:39 +01:00
2a50a8021a
soc/integration/soc_core: improve error message for missing csrs
2018-03-05 09:59:06 +01:00
5ef34500f7
Improving error message when csr name is not found.
...
Before;
```
"/usr/local/lib/python3.5/dist-packages/litex-0.1-py3.5.egg/litex/soc/integration/soc_core.py",
line 258, in get_csr_dev_address
return self.csr_map[name]
KeyError: 'core'
```
Now;
```
Traceback (most recent call last):
File "XXXX/github/enjoy-digital/litex/litex/soc/integration/soc_core.py", line 259, in get_csr_dev_address
return self.csr_map[name]
KeyError: 'ddrphy'
The above exception was the direct cause of the following exception:
Traceback (most recent call last):
...
File "XXXX/github/enjoy-digital/litex/litex/soc/interconnect/csr_bus.py", line 199, in scan
mapaddr = self.address_map(name, None)
File "XXXX/github/enjoy-digital/litex/litex/soc/integration/soc_core.py", line 269, in get_csr_dev_address
) from e
RuntimeError: Unable to find ddrphy in your SoC's csr address map.
Check BaseSoC.csr_map in XXXX/github/enjoy-digital/litex/litex/boards/targets/arty.py
Found l2_cache, timer0, ddrphy2, buttons, sdram, identifier_mem, uart, uart_phy, leds, crg in the csr_map
```
2018-03-03 16:02:44 -08:00
ab2a3277c3
Merge pull request #67 from cr1901/vivado-paths
...
xilinx/vivado: Provide a fallback mechanism for using the same root f…
2018-03-03 08:29:18 +01:00
db20df49f4
Merge pull request #65 from cr1901/tinyfpga-serial
...
platforms/tinyfpga_b: Move serial peripheral out of default I/O, make it
2018-03-03 08:28:57 +01:00
2b00b7eba4
xilinx/vivado: Provide a fallback mechanism for using the same root for Vivado and ISE toolchains.
2018-03-02 21:48:49 -05:00
fa6b256198
build/xilinx/platform: fix merge
2018-03-03 00:07:50 +01:00
d40c57739c
boards/arty_s7: Fix IOStandard on System Clock.
2018-03-02 13:35:43 -05:00
0332f73a7b
build/xilinx/vivado: revert toolchain_path
2018-02-28 23:45:26 +01:00
2ff50a8882
build: fix merge
2018-02-28 23:10:24 +01:00
64e4e1ce84
build: merge with migen.build 27beffe7
2018-02-28 16:49:12 +01:00
0edfd9b901
boards/kcu105: regroup sfp tx and rx
2018-02-28 14:11:58 +01:00
e71593d67e
platforms/tinyfpga_b: Move serial peripheral out of default I/O, make it
...
optional via `add_extension`.
2018-02-27 18:41:35 -05:00
1925ba176f
replace litex.gen imports with migen imports
2018-02-23 13:38:19 +01:00
43164b9a2c
remove migen fork from litex
2018-02-23 13:37:26 +01:00
688f26cc32
Change AXI interface and tidy code
...
Inspired by parts of https://github.com/peteut/migen-misc/
2018-02-21 00:00:58 +00:00
512ed2b3d6
Preliminary AXI4Lite CSR bridge support
...
This change introduces an AXI4Lite to CSR bridge. Hopefully it will
become extended in the future with full AXI support and more structures
(Wishbone bridge, interconnect, ...). For now this will do.
The bridge has been simulated (and includes an FHDL testbench) and
tested in hardware (on a Zynq 7020).
2018-02-20 21:27:51 +00:00
55fc9d2d6b
Merge pull request #60 from q3k/for-upstream/top-level-module-selection
...
Top module selection (for Verilator and Diamond)
2018-02-19 12:27:25 +01:00
7b5bd4041a
Merge pull request #57 from rohitk-singh/master
...
WIP - BIOS: Flashboot without main ram
2018-02-10 21:37:38 +01:00
c14502807e
board/targets/nexys4ddr: use MT47H64M16
2018-02-06 19:17:54 +01:00
95ebba428c
boards/platforms/nexys4ddr: add user_sw, user_btn, fix ddr3
2018-02-06 19:08:46 +01:00
ee4fa597b4
boards: add nexys4ddr
2018-02-06 14:43:20 +01:00
2ecd1b0666
Merge pull request #61 from PaulSchulz/master
...
platform/arty.py: Move Pmod definitions to 'connectors' section.
2018-01-26 01:58:37 +01:00
4607e5323f
boards/platforms: Add Arty S7 Board.
2018-01-25 18:36:32 -05:00
0ac35300c4
Merge branch 'master' of https://github.com/enjoy-digital/litex into upstream
2018-01-24 13:32:42 +10:30
4f2725809e
software/common: revert PYTHON to python3 (since breaking things)
2018-01-23 10:39:13 +01:00
4e168221d8
bios: fix riscv processor print
2018-01-23 10:33:05 +01:00
d448874879
sim: rename top module to dut and use --top-module parameter (needed for picorv32 simulation)
2018-01-23 10:28:16 +01:00
3ac28ed6f7
platform/arty.py: Move Pmod definitions to 'connectors' section.
2018-01-23 16:11:25 +10:30
ef511e7edc
Specify top-level module in Lattice Diemond build script.
...
When building multi-source files the toolchain gets confused as to which
module is top-level. This ensures that the build_name of the design is
selected.
2018-01-23 01:17:04 +00:00
ef6c517dad
Build top module as 'dut' in Verilator and set it as top-level.
...
When building a design with PicoRV32 we end up with multiple top-level
modules and Verilator becomes confused as to which is the right one.
This change ensures the dut.v generated by the sim build process has
it's top-level name set to 'dut' and that verilator is invoked with this
name.
2018-01-23 01:15:28 +00:00
21bd26dcdd
Allow for multiple synthesis directives in specials.
...
This is needed to specify timing constraints on some Lattice Diamond
library specials, like the EHXPLLL.
To keep backwards compatibility we allow the directive to still be a
single string. If it's not, we assume it's an iterable.
2018-01-23 00:27:49 +00:00
67f8718b26
minor cleanup
2018-01-23 00:35:20 +01:00
6daf3eabc5
Implement IRQ software support for RISC-V.
...
Well, at least PicoRV32-specific. Turns out there is no RISC-V
specification for simple microcontroller-like interrupts, so PicoRV32
implements its' own based on custom opcodes.
It's somewhat esoteric, and for example doesn't offer a global interrupt
enable/disable. For this we implement a thin wrapper in assembly and
then expose it via a few helpers in irq.h.
2018-01-22 18:50:26 +00:00
2108c97b9b
Import PicoRV32-specific instruction macros.
...
These come from the PicoRV32 repo and are released under the public
domain [1].
[1] - 70f3c33ac8/firmware/custom_ops.S
2018-01-22 18:50:26 +00:00
cf74c781f4
Write init files that respect CPU's endianness.
...
This is required for PicoRV32 support. We also drive-by enable
explicit specification of run= in Builder.build() by callers.
2018-01-22 18:50:26 +00:00
7176492231
Set the MABI and MArch of the riscv target.
...
Again, this should be tunable, and synchronized with the core settings.
2018-01-22 18:50:26 +00:00
7ea5a26734
Enable hardware multiplier and divider in PicoRV32
...
This should become tunable later once we can configure whether we link
in the soft mul library or not.
2018-01-22 18:50:26 +00:00
75e230aae7
Replace __riscv__ macros with __riscv.
...
The __riscv__ form is deprecated [1].
[1] - https://github.com/riscv/riscv-toolchain-conventions#cc-preprocessor-definitions
2018-01-22 18:50:26 +00:00
20ed23443b
Export trap signal from PicoRV32.
...
This is useful for handling crashes from hardware.
2018-01-22 18:50:26 +00:00
b0be563012
Bump PicoRV32 version.
2018-01-22 18:50:26 +00:00
75e7f9505a
BIOS: Flashboot without main ram
...
Modified flashboot() to skip copy to main ram if there is no main
ram, and instead execute in place out of SPI flash. (For this to
work the linker .ld will also need to redirect references to be
inside the SPI flash mapping.)
2018-01-20 15:05:47 +11:00
3a5f93db5d
software/bios: add litex logo
2018-01-19 18:41:13 +01:00
c553fe2bf3
Add mimasv2 platform (pulled from litex-buildenv).
2018-01-19 06:16:04 -05:00
ead88ed66d
Support forcing colorama colors on.
...
This is needed if you want colors but are using pipes and similar.
2018-01-18 14:41:45 +11:00
fcc22350fb
Merge pull request #52 from ewen-naos-nz/tftp-alt-port
...
BIOS: Support alternate TFTP server port
2018-01-18 13:40:28 +11:00
5ce8ca8e9b
BIOS: TFTP: try UDP/69 if specified port fails
2018-01-18 13:10:28 +11:00
cb31266500
BIOS: set TFTP_SERVER_PORT from enviroment
2018-01-18 13:09:34 +11:00
97f381baa6
BIOS: allow BIOS to specify TFTP server port
...
Swaps hard coded PORT_OUT in tftp.c for parameter on the tftp_get()
and tftp_put() functions. Allow TFTP_SERVER_PORT used by BIOS to be
set at compile time from compiler defines.
2018-01-18 12:03:35 +11:00
Florent Kermarrec
Tim 'mithro' Ansell
William D. Jones
Gabriel L. Somlo
Ambroz Bizjak
Tom Keddie
msloniewski
Mateusz Holenko
bunnie
Ilia Sergachev
Antony Pavlov
Sean Cross
David Shah
Kurt Kiefer
Michael Betz
Vamsi K Vytla
Larry Doolittle
Joanna Brozek
vytautasb
Caleb Jamison
chmousset
David Shah
Jean-François Nguyen
Stafford Horne
Jean-François Nguyen
Jean-François Nguyen
Peter Gielda
Deano Calver
Dolu1990
Sergiusz Bazanski
Paul Schulz
Ewen McNeill