litex

mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00

Author	SHA1	Message	Date
Greg Davill	31cc7f1e42	cores/stream/monitor: Fix typo	2021-03-10 09:11:07 +10:30
Florent Kermarrec	0e7d8219ea	soc/cores/gpio: Simplify GPIOIn IRQ, make polarity configurable and also add optional IRQ to GPIOTristate. Ex of instance: from litex.soc.cores import gpio gpio_in_pads = Signal(16) self.submodules.gpio_in = gpio.GPIOIn(gpio_in_pads, with_irq=True) self.add_csr("gpio_in")	2021-03-09 13:57:48 +01:00
Florent Kermarrec	0d8b6f8fbb	csr_eventmanager/EventSourceProcess: Add Rising Edge support and Falling/Rising selection.	2021-03-09 13:55:43 +01:00
Florent Kermarrec	ece9005949	cpu/vexriscv/core: Rename timer_enabled parameter to with_timer (for consistency with codebase) and disable timer by default (since increasing resources and causing issue on some iCE40 designs).	2021-03-09 09:07:52 +01:00
gatecat	c64e2d3a85	build/radiant: Skip location constraint for X pins Signed-off-by: gatecat <gatecat@ds0.me>	2021-03-08 14:27:32 +00:00
Florent Kermarrec	5af8e5c934	soc/add_etherbone: Fix UDPIPCore clock domain (should still run at eth_clk even if Etherbone is running in sys_clk) since data-width convertion is done on UDP.	2021-03-08 13:50:22 +01:00
Vamsi Vytla	6bb0541f9a	Remove ussysmon.py as it is consolidated inside xadc.py	2021-03-06 14:31:24 -08:00
Florent Kermarrec	a1e54671be	sim/serial2console: Remove \r workaround since no longer required and generating double carrier return in simulation.	2021-03-06 17:36:21 +01:00
Florent Kermarrec	7e3912aaef	software/demo: Make hellocpp optional (only build with --with-cxx) to avoid adding g++ as a dependency for an optional feature.	2021-03-06 17:31:07 +01:00
Vamsi Vytla	647d3eb51a	soc/cores/xadc.py: Move ussysmon here	2021-03-06 08:14:13 -08:00
Florent Kermarrec	31ac6659c9	cores/video: Add VideoS7HDMIPHY for Xilinx 7-Series.	2021-03-05 14:30:28 +01:00
Florent Kermarrec	9624cce188	cores/video: Mode VideoVGAPHY/VideoDVIPHY and add separators.	2021-03-05 14:27:08 +01:00
Florent Kermarrec	0280a9dd57	soc/add_video_framebuffer: Pass clock_domain to VideoFrameBuffer.	2021-03-05 14:23:39 +01:00
Florent Kermarrec	8b531b4215	cores: Add code_tmds with TMDS Encoder from Mixxeo/LiteVideo.	2021-03-04 19:32:41 +01:00
Florent Kermarrec	10d87e4138	cores/video/VideoPHYs: Use IO primitives.	2021-03-04 18:22:34 +01:00
Florent Kermarrec	82d0ecd7bd	cores/video/VideoTerminal: Add CLEAR-XY after reset.	2021-03-04 17:55:37 +01:00
Florent Kermarrec	a1e7aab35c	cores/clock/xilinx_usp/USPIDELAYCTRL: Apply USIDELAYCTRL's changes.	2021-03-04 14:42:50 +01:00
Florent Kermarrec	60e2d3335f	cores/clock/xilinx_us: Remove USP modules (refactoring issue).	2021-03-04 14:42:03 +01:00
Florent Kermarrec	2d5b4b206b	bios: Add VideoFrameBuffer VTG/DMA initialisation. This just configures the enables for now since other parameters are pre-configured during the build.	2021-03-04 12:01:32 +01:00
Florent Kermarrec	f553b5fc83	soc/cores/video: Improve/Cleanup VideoFrameBuffer, disable by default and modify default hres/vres to 800/600.	2021-03-04 11:59:44 +01:00
Florent Kermarrec	0ee92448b9	soc/cores/dma: Add default parameters to add_csr (similar to LiteDRAMDMAs), minor cosmetic cleanups and also add offset CSRStatus on WishboneDMAWriter (for symetry with WishboneDMAReader). Defaults parameters can allow the FPGA gateware to behave by itself after initialization while still being configurable by software.	2021-03-04 11:53:43 +01:00
Florent Kermarrec	225a518f7e	soc/cores/video: Move LiteDRAMDMAReader import to VideoFramerBuffer to avoid LiteDRAM dependency.	2021-03-04 08:40:47 +01:00
Vamsi Vytla	ae5f67f6f0	litex/soc/cores/ussysmon.py: minor bug	2021-03-03 14:47:52 -08:00
Vamsi Vytla	1793efb50b	litex/soc/cores/ussysmon.py: dadr address space bump	2021-03-03 14:38:27 -08:00
Florent Kermarrec	ccc8916995	soc/cores/video: Add initial (and simple) VideoFrameBuffer core.	2021-03-03 19:58:11 +01:00
Vamsi Vytla	922f85e64b	litex/soc/cores/ussysmon.py: ADC transfer function	2021-03-03 10:50:58 -08:00
Florent Kermarrec	24fb153fa1	soc/integration: Add add_video_terminal method to LiteXSoC. Adds the new LiteX's VideoTerminal core to the SoC: self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga") self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")	2021-03-03 17:45:02 +01:00
Florent Kermarrec	35ffba8801	soc/cores: Add simple VideoOut core with VideoTimingGenerator, Video Patterns, VideoTerminal, VideoDVIPHY and VideoVGAPHY.	2021-03-03 16:17:12 +01:00
Florent Kermarrec	c5ee6741a0	software/liblitedram: Use new DQS delay reset procedure on Ultrascale(+) (by increments).	2021-03-03 11:32:43 +01:00
Florent Kermarrec	d3407c67b1	build/sim/core: Cast main_time to vluint64_t to avoid ambiguity error of the dump function to be used.	2021-03-03 09:25:54 +01:00
Florent Kermarrec	134c628357	cores/spi_flash: Minor cosmetic cleanups, SpiFlashQuadReadWrite has also been moved to the end with a Note since should probably be re-factored.	2021-03-03 09:15:51 +01:00
Florent Kermarrec	61dcd1e8fd	soc/cores/led: Minor cosmetic cleanups.	2021-03-03 09:02:41 +01:00
Florent Kermarrec	19b1e50cbd	soc/cores/icap: Minor cosmetic cleanups.	2021-03-03 09:01:41 +01:00
Florent Kermarrec	e6f1d677e7	soc/cores/freqmeter: Minor cosmetic cleanups.	2021-03-03 08:59:51 +01:00
Florent Kermarrec	ce5e3e3b93	soc/cores/ecc: Minor cosmetic cleanups.	2021-03-03 08:55:37 +01:00
Florent Kermarrec	2fd7451fc9	soc/cores/code_8b10b: Minor cosmetic cleanups.	2021-03-03 08:54:31 +01:00
Florent Kermarrec	2e531e0ec7	soc/cores/dna: Add separator/comment.	2021-03-03 08:49:47 +01:00
Vamsi Vytla	71f7ce6a57	soc/cores/ussysmon.py: Xilinx XADC like thingy for UltraScale devices	2021-03-02 20:31:52 -08:00
Sergiu Mosanu	7fd39235af	Merge pull request #1 from hplp/cppdemo demo with basic C and C++ examples	2021-03-02 01:31:46 -05:00
Sergiu Mosanu	769f36d468	extend demo with basic C and C++ examples	2021-03-02 01:28:21 -05:00
David Jablonski	ceb8a6502c	VexRiscv: More general mem_map	2021-02-25 10:36:43 +01:00
Florent Kermarrec	6e883b4513	tools/litex_sim: Add boot to main_ram when sdram_init contents provided.	2021-02-25 09:10:26 +01:00
Florent Kermarrec	8f5d2ba27f	tools/litex_sim: Disable SDRAM memtest when sdram_init contents provided. This avoid corrupting pre-initialized contents or disabling memtest manually.	2021-02-25 09:06:26 +01:00
Florent Kermarrec	80bd4ac4ec	bios: Add boot command to be able to boot directly from system memory. This is useful for un-usual boot sequences where the binaries are not loaded directly by the BIOS but externally (over a bridge for example). Example of use: $litex_sim $litex_bare_metal_demo --build-path=build/sim $litex_sim --ram-init=demo.bin Press Esc during the LiteX boot. litex> help LiteX BIOS, available commands: flush_cpu_dcache - Flush CPU data cache crc - Compute CRC32 of a part of the address space ident - Identifier of the system help - Print this help serialboot - Boot from Serial (SFL) romboot - Boot from ROM reboot - Reboot boot - Boot from Memory mem_speed - Test memory speed mem_test - Test memory access mem_copy - Copy address space mem_write - Write address space mem_read - Read address space mem_list - List available memory regions litex> litex> mem_list Available memory regions: ROM 0x00000000 0x8000 SRAM 0x01000000 0x2000 MAIN_RAM 0x40000000 0x10000000 CSR 0x82000000 0x10000 litex> litex> boot 0x40000000 Executing booted program at 0x40000000 --============= Liftoff! ===============-- LiteX minimal demo app built Feb 24 2021 11:30:05 Available commands: help - Show this command reboot - Reboot CPU donut - Spinning Donut demo litex-demo-app>	2021-02-24 11:41:01 +01:00
enjoy-digital	c18ea700cc	Merge pull request #822 from antmicro/bios-dynamic-ip software/bios: add an option to change ip and mac address in runtime	2021-02-24 09:27:48 +01:00
Aleksandra Swierkowska	7abd66d710	bios/boot: add functions changing local and remote IP in runtime	2021-02-23 20:52:53 +01:00
Aleksandra Swierkowska	1c8df130b4	integration/soc.py: add parameter dynamic_ip to add_ethernet	2021-02-23 20:52:53 +01:00
Aleksandra Swierkowska	fc6b02d0da	libliteeth/udp: add udp_set_ip and udp_set_mac functions	2021-02-23 20:52:43 +01:00
Florent Kermarrec	91cebb5159	cpu/microwatt: Set XICS_ICS's SRC_NUM to 16. Expected to be 16 in xics.vhdl: assert SRC_NUM = 16 report "Fixup address decode with log2";	2021-02-22 10:57:31 +01:00
Florent Kermarrec	a51bf60712	cpu/microwatt: Only add XICS for IRQ variants (fix standard variant).	2021-02-22 10:31:08 +01:00
enjoy-digital	d5c2f6760c	Merge pull request #824 from scanakci/blackparrot_litex Update BlackParrot Readme	2021-02-22 10:23:25 +01:00
sadullah	96d9971abe	Update BlackParrot Readme	2021-02-20 22:58:34 -05:00
Robert Wilbrandt	251cea5647	Add constants to SVD export	2021-02-20 21:16:45 +01:00
Florent Kermarrec	7513460572	integration/soc/add_pcie: add with_msi parameter to allow disabling MSI when not required. When just doing a PCIe to Wishbone Bridge (PCIeBone), DMAs and MSI are not required, with_msi will allow disabling MSI when set to False.	2021-02-19 11:35:49 +01:00
Florent Kermarrec	d4edc132c1	tools/remote/comm_pcie: fix typo.	2021-02-19 10:33:04 +01:00
Florent Kermarrec	b47160c74e	tools/litex_term: replace CrossoverUART with BridgeUART for more genericity, rework bridge/jtag args. The CrossoverUART was in fact a particular UART connected to a second UART. Being able to have access to multiple UARTs over a Bridge can be useful for several purposes, ex: SoC0 --> UART0 + JTAGBone + litex_term bridge --bridge-name=UART0 SoC1 --> UART1 +--> SoC --> UARTBone --> LiteX-Server + litex_term bridge --bridge-name=UART1 SoC2 --> UART2 + EtherBone + litex_term bridge --bridge-name=UART2	2021-02-18 18:02:05 +01:00
Florent Kermarrec	6ac410a462	cores/uart/UARTCrossover: increase rx_fifo_depth to allow speeding up litex_term.	2021-02-18 17:55:53 +01:00
Florent Kermarrec	fc83a9281a	interconnect/csr: remove address wrapping within a CSRBank. To minimize logic, decoding inside a CSRBank to limited to the CSRs inside the bank and could wraps since partially decoded: For example, accessing SoCController on addresses still on the CSRBank defined for real CSRs produced: litex> mem_read 0x82000000 128 Memory dump: 0x82000000 00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00 ....xV4......... 0x82000010 00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00 ....xV4......... 0x82000020 00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00 ....xV4......... 0x82000030 00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00 ....xV4......... 0x82000040 00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00 ....xV4......... 0x82000050 00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00 ....xV4......... 0x82000060 00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00 ....xV4......... 0x82000070 00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00 ....xV4......... This is generally not an issue on most of the systems, but it could confuse user or produce un-wanted behaviour when bus data-width converter are used. With this change, the address is fully decoded, which removes the address wrapping: litex> mem_read 0x82000000 128 Memory dump: 0x82000000 00 00 00 00 78 56 34 12 00 00 00 00 00 00 00 00 ....xV4......... 0x82000010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 0x82000020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 0x82000030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 0x82000040 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 0x82000050 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 0x82000060 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 0x82000070 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ Resource usage increase seems minimal.	2021-02-18 14:44:50 +01:00
Florent Kermarrec	12bdf43958	soc/cores/ecc: cosmetic cleanups.	2021-02-18 10:00:27 +01:00
Florent Kermarrec	7ce5aef428	soc/cores/led: add add_pwm method to allow adjusting brightness dynamically (or not). LedChaser without PWM: self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) self.add_csr("leds") Add PWM to it (with default values: 50% duty cycle): self.leds.add_pwm() Add PWM with custom default values (25% duty cycle here): self.leds.add_pwm(default_width=128, default_period=1024) Then adjust brightness dynamically from the BIOS or your software: $cat csr.csv: csr_register,leds_out,0x82003000,1,rw csr_register,leds_pwm_enable,0x82003004,1,rw csr_register,leds_pwm_width,0x82003008,1,rw csr_register,leds_pwm_period,0x8200300c,1,rw Set PWM to 0%: $mem_write 0x82003008 0 Set PWM to 25%: $mem_write 0x82003008 256 Set PWM to 50%: $mem_write 0x82003008 512 Set PWM to 75%: $mem_write 0x82003008 768 Set PWM to 100%: $mem_write 0x82003008 1024 You can also only use default values and disable CSR is dynamic configuration is not required (with_csr=False) or adjust PWM period if want to use a specific PWM period in your system.	2021-02-18 09:47:30 +01:00
Florent Kermarrec	fc282b3084	soc/cores/pwm: add configurable default enable/width/period values.	2021-02-18 09:39:18 +01:00
Florent Kermarrec	908e72e65b	cores/uart: rewrite RS232PHYTX/RX (with FSM and comments) and optimize resource usage (~100LCs).	2021-02-17 15:04:14 +01:00
enjoy-digital	7c7f540488	Merge pull request #821 from jersey99/master build/xilinx/vivado.py: Allow a tcl script to be added as ip	2021-02-17 08:12:09 +01:00
Florent Kermarrec	82c1f5dccb	litex_setup/ibex: add pythondata-misc-opentitan to litex_setup and use it for Ibex CPU.	2021-02-17 08:07:07 +01:00
Florent Kermarrec	285bb96278	cores/uart/RS232PHY: add with_dynamic_baudrate parameter and disable it by default. Dynamic baudrate is rarely used and enabling it has a non negligeable cost (~100LCs).	2021-02-16 20:00:43 +01:00
Florent Kermarrec	9a8a8c0fe5	software/liblitedram: remove SDRAM_PHY_WRITE_LEVELING_REINIT no longer required on Ultrascale(+).	2021-02-16 16:26:34 +01:00
Vamsi Vytla	385dec8560	Merge remote-tracking branch 'upstream/master'	2021-02-15 09:29:47 -08:00
Vamsi Vytla	1fde282291	build/xilinx/vivado.py: Allow a tcl script to be added as ip. These tcl scripts tend to generate .xci's on the fly. The tcl script can be looked up in the vivado console as the ip is generated	2021-02-15 09:29:00 -08:00
Gabriel Somlo	927fd675bc	sdclk: additional halving to prevent clock going "too fast" When the system/bus clock frequency is an exact power-of-2 multiple of the desired sdcard frequency, we can drive the latter at the "maximum" speed via the "perfect" divider. That sometimes turns out too fast, so in order to be conservative, we double the divider, thus halving the resulting sdclock.	2021-02-15 09:24:02 -05:00
Gabriel Somlo	b03f46ffec	soc: increase sdcard data/cmd timeout (from default 10e-3) This allows the Linux driver in single-block mode (cmd17-only) to operate solidly, without running into timeouts from LiteSDCard FSMs. FIXME: multi-block (cmd18) transfers still time out, so revisit this after some additional debugging.	2021-02-15 09:23:52 -05:00
enjoy-digital	07dd680a3e	Merge pull request #818 from tcal-x/vexLiteMul Vexriscv "lite" uses "--mulDiv true", so enable "mul" instructions.	2021-02-15 15:02:47 +01:00
Florent Kermarrec	510bda4c99	cores/cpu: add initial lowRISC's Ibex support (without interrupts). Working in simulation and on hardware: litex_sim --cpu-type=ibex, ./target.py --cpu-type=ibex. This is currently doing a git clone of ibex and opentitan repositories but we'll create a pythondata-cpu-ibex package in the future. litex_sim --cpu-type=ibex: __ _ __ _ __ / / (_) /____ \| \|/_/ / /__/ / __/ -_)> < /____/_/\__/\__/_/\|_\| Build your hardware, easily! (c) Copyright 2012-2020 Enjoy-Digital (c) Copyright 2007-2015 M-Labs BIOS built on Feb 15 2021 11:57:50 BIOS CRC passed (e7517f7b) Migen git sha1: 7014bdc LiteX git sha1: `ead12df2` --=============== SoC ==================-- CPU: Ibex @ 1MHz BUS: WISHBONE 32-bit @ 4GiB CSR: 32-bit data ROM: 32KiB SRAM: 8KiB MAIN-RAM: 262144KiB --============== Boot ==================-- Booting from serial... Press Q or ESC to abort boot completely. sL5DdSMmkekro Timeout No boot medium found --============= Console ================--	2021-02-15 12:02:25 +01:00
Tim Callahan	5cb467cae3	Vexriscv "lite" uses "--mulDiv true", so enable "mul" instructions. Signed-off-by: Tim Callahan <tcal@google.com>	2021-02-14 14:16:14 -08:00
Florent Kermarrec	ead12df21b	soc/cores/gpio: review/simplify #810 . Use irqs dict and "rise", "fall" strings instead of Enums: Ex: pads=Signal(8), irqs={} : 8-bit Input, No IRQ. pads=Signal(8), irqs={0: "rise", 7: "fall"}: 8-bit Input, rising IRQ on 0, falling IRQ on 1. Also simplify the logic.	2021-02-12 16:21:01 +01:00
enjoy-digital	89454d2df3	Merge pull request #810 from antmicro/gpio_interrupts Add support for interrupts on GPIOIn	2021-02-12 15:51:25 +01:00
Geert Uytterhoeven	d91262e85c	software/demo: Drop bogus "the" in README Fixes: `e7e28f2438` ("Change wording of demo README") Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-02-12 15:15:55 +01:00
enjoy-digital	0366a03c87	Merge pull request #813 from antmicro/jboc/lpddr4 software/bios: add option to disable BIOS prompt	2021-02-12 14:08:34 +01:00
Nick Østergaard	e7e28f2438	Change wording of demo README Change wording of demo README to make it more clear what the process is and how things related. This should help the newcomer and it still usefull for the triained. Change the command example to be more copy paste friendly. Fixes #814	2021-02-11 21:35:02 +01:00
Jędrzej Boczar	5f1edccd2e	software/bios: add option to disable BIOS prompt	2021-02-11 10:49:45 +01:00
Florent Kermarrec	041aa9bf6f	soc/cores/clock/xilinx_us/USIDELAYCTRL: make sure sys clock domain is reseted when reference clock domain is reseted.	2021-02-09 19:06:49 +01:00
Florent Kermarrec	126dd267d6	soc/interconnect/axi/AXIInterface: add optional tkeep.	2021-02-09 16:27:48 +01:00
Robert Szczepanski	15b3d932a4	gpio: add support for interrupts on GPIOIn	2021-02-09 15:29:31 +01:00
enjoy-digital	018094abb2	Merge pull request #809 from stffrdhrn/mor1kx-smp cpu/mor1kx: Add initial SMP support to cpu core	2021-02-09 09:54:49 +01:00
enjoy-digital	95b310ee0f	Merge pull request #807 from antmicro/revert-bitstream-device-changes build/xilinx/symbiflow: fix bitstream_device select	2021-02-09 09:26:48 +01:00
Stafford Horne	2f2b047f2e	cpu/mor1kx: Add initial SMP support to cpu core In order for mor1kx to run an SMP kernel shadow registers must be enabled. This patch adds two new variants: - linux+smp - basic linux + smp support - linux+smp+fpu - linux with FPU and smp support	2021-02-09 07:06:07 +09:00
Jan Kowalewski	ad760d491c	build/xilinx/symbiflow: fix bitstream_device select Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>	2021-02-08 15:38:30 +01:00
Geert Uytterhoeven	84e5130ac5	software/bios/console: Call putsnonl() from puts() puts() and putsnonl() are very similar, and can share code. Reduce code size by making the former call the latter. Impact for a RISC-V build: $ size console.o.orig console.o text data bss dec hex filename 868 0 12 880 370 console.o.orig 832 0 12 844 34c console.o Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-02-08 14:05:31 +01:00
Geert Uytterhoeven	8e4202ced1	software/bios/readline: Fix warnings if char is signed When building with --cpu-type=mor1kx: litex/soc/software/bios/readline.c: In function 'readline': litex/soc/software/bios/readline.c:271:3: warning: case label value exceeds maximum value for type [-Wswitch-outside-range] 271 \| case KEY_END: \| ^~~~ litex/soc/software/bios/readline.c:297:3: warning: case label value exceeds maximum value for type [-Wswitch-outside-range] 297 \| case KEY_DEL: \| ^~~~ litex/soc/software/bios/readline.c:281:3: warning: case label value exceeds maximum value for type [-Wswitch-outside-range] 281 \| case DEL: \| ^~~~ The C standard does not specify the signedness of "char", hence this depends on the implementation. On e.g. RISC-V, "char" is unsigned, but on OpenRISC, it is signed. Fix this by making the "ichar" variable explicitly unsigned. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-02-08 14:05:31 +01:00
Florent Kermarrec	5430c1455e	software/demo: add support for absolute/relative --build-path and simplify comment.	2021-02-08 10:29:26 +01:00
Hans Baier	7dae0aa09b	litex_term: support Intel/Altera nios2-terminal	2021-02-08 11:42:37 +07:00
Hans Baier	6f63fc104e	demo: more helpful usage message	2021-02-06 07:15:12 +07:00
Florent Kermarrec	5cb9f487a2	tools/litex_server: remove JTAGUART's binary_mode parameter (we are now only supporting binary_mode).	2021-02-05 12:38:20 +01:00
Florent Kermarrec	468b916a4f	tools/litex_term: add --jtag-config parameter to select OpenOCD JTAG configuration file.	2021-02-05 09:43:32 +01:00
Florent Kermarrec	4f15be746c	tools/litex_term: always use binary mode (for jtag_uart and jtagbone) and remove parameter. Fix jtag_uart regression and allow serialboot.	2021-02-05 09:40:21 +01:00
enjoy-digital	92f4cd1423	Merge pull request #799 from antmicro/add_xc7a200t_to_symbiflow build/xilinx: add xc7a200t-sbg484-1 to symbiflow toolchain	2021-02-04 16:41:45 +01:00
enjoy-digital	0006efe6ea	Merge pull request #800 from geertu/doc-sphinx-v1-fix doc: Fix doc build with Sphinx v1.x	2021-02-04 12:24:49 +01:00
Florent Kermarrec	4d1deffbb0	jtagbone/openocd: add binary mode on JTAGUART to fix "\n" to "\r" remapping that is not wanted in binary mode.	2021-02-04 11:44:43 +01:00
Geert Uytterhoeven	af13f43e60	doc: Fix doc build with Sphinx v1.x When building the linux-on-litex-vexriscv documentation with Sphinx v1.8.5: Sphinx error: master file linux-on-litex-vexriscv/build/orangecrab/doc/contents.rst not found The default value of "master_doc" was changed from "contents" to "index" in Sphinx v2[1]. As the LiteX doc system creates "index.rst", it thus fails to build with Sphinx v1.x. Explicitly configure "master_doc" to "index", to make it work with all versions of Sphinx, regardless of the default. [1] https://www.sphinx-doc.org/ca/latest/usage/configuration.html?highlight=master_doc Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-02-04 09:40:04 +01:00
Jan Kowalewski	57915db746	build/xilinx: add xc7a200t-sbg484-1 to symbiflow toolchain Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>	2021-02-03 15:18:48 +01:00
Jędrzej Boczar	b1fb141d1f	Fix gtkwave.py to be compatible with python 3.6	2021-02-02 11:14:16 +01:00
Florent Kermarrec	ba7c503fb6	tools/litex_sim: move gtkw import to generate_gtkw_savefile. This fixes litex_sim use with python 3.6 and raise an error when --gtkwave-savefile is used with python 3.6.	2021-02-02 10:13:23 +01:00
enjoy-digital	659751d202	Merge pull request #795 from antmicro/jboc/gtkwave-savefiles Add automatic generator of GTKWave savefiles	2021-02-02 09:59:18 +01:00
enjoy-digital	2f907d6e1e	Merge pull request #790 from antmicro/jboc/8phases software/liblitedram: support PHYs with more than 4 DFI phases	2021-02-02 09:43:17 +01:00
enjoy-digital	d76e0dcede	Merge pull request #791 from antmicro/jboc/init-mr software/liblitedram: selectable write leveling MR (for LPDDR4 support)	2021-02-02 09:36:31 +01:00
Geert Uytterhoeven	7b3737f531	cpu/vexriscv_smp: Make sbt failures fatal When using a non-default VexRiscv cluster config, the netlist for that config needs to be generated. This requires sbt to be installed. If sbt is missing, an error message is printed: sh: 1: sbt: not found This message may easily be lost in the noise, as the build continues, and fails later with: ERROR: Can't open input file `litex/pythondata-cpu-vexriscv-smp/pythondata_cpu_vexriscv_smp/verilog/VexRiscvLitexSmpCluster_Cc1_Iw32Is4096Iy1_Dw32Ds4096Dy1_Ood_Wm.v' for reading: No such file or directory Make the root cause more visible by raising an OSError, and aborting the build. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-02-01 13:54:59 +01:00
Jędrzej Boczar	fc9ef4c255	litex_sim: add --gtkwave-savefile argument with example signals	2021-02-01 13:22:30 +01:00
Jędrzej Boczar	01b900f4e0	Add GTKWave savefile generator	2021-02-01 13:22:30 +01:00
Florent Kermarrec	8623536a8a	build/generic_platform: avoid removing X pins from named_sc. We need them on Gowin FPGAs with embedded SDRAM where SDRAM pins are not real IOs.	2021-02-01 13:12:25 +01:00
Florent Kermarrec	f324f9531a	build/gowin: Don't generate IO_LOC is pin name is X.	2021-02-01 13:08:37 +01:00
enjoy-digital	fd33e360fb	Merge pull request #792 from euryecetelecom/master Add flash method to openFPGALoader class	2021-01-30 21:35:09 +01:00
Konstantin	3f27253ccc	cores/clock/lattice_ice40: add missing AsyncResetSynchronizer import.	2021-01-30 18:25:19 +01:00
Guillaume REMBERT	18a5ace637	Add flash method to openFPGALoader class for support with generic_programmer usage (needed for linux-on-litex-vexriscv) + add offset/address support for firmware load	2021-01-30 13:20:30 +01:00
enjoy-digital	69307cfdde	Merge pull request #789 from antmicro/jboc/litex-sim-fix-name litex_sim: fix old name: get_cl_cw -> get_default_cl_cwl	2021-01-29 19:13:34 +01:00
Jędrzej Boczar	61e605da92	litex_sim: fix old name: get_cl_cw -> get_default_cl_cwl	2021-01-29 11:31:40 +01:00
Florent Kermarrec	2287f73937	tools/litex_client: add --read/--write args to do simple MMAP accesses to SoC bus. ex reading/writing to scratch register over jtagbone: In the SoC: self.add_jtagbone() Open LiteX Server: litex_server --jtag Do the MMAP accesses: ./litex_cli --read 0x4 0x12345678 ./litex_clk --write 0x4 0x5aa55aa5 ./litex_cli --read 0x4 0x5aa55aa5	2021-01-28 17:46:18 +01:00
Jędrzej Boczar	38b819c42a	software/liblitedram: selectable write leveling MR (for LPDDR4 support)	2021-01-28 15:56:13 +01:00
Jędrzej Boczar	e3172faad9	software/liblitedram: support PHYs with more than 4 DFI phases	2021-01-28 15:53:40 +01:00
Florent Kermarrec	7abfbd9825	tools/litex_json2dts/ethernet: add missing 'status = "okay";'. Was causing https://github.com/litex-hub/linux-on-litex-vexriscv/issues/178.	2021-01-27 11:52:04 +01:00
Florent Kermarrec	b8bcbc522f	integration/export/triple: use LITEX_ENV_CC_TRIPLE instead of TRIPLE. triple can be used internally, but is too generic as an environment variable.	2021-01-27 08:25:48 +01:00
enjoy-digital	f331ddace8	Merge pull request #780 from garytwong/triple-option integration/export: allow manually specifying toolchain triple.	2021-01-27 08:16:41 +01:00
Florent Kermarrec	2f89e0aecf	soc/do_finalize: check that crg.rst is a Signal before connecting to ctrl._reset.	2021-01-26 17:08:43 +01:00
Florent Kermarrec	cafe0944f1	soc/add_uartbone/add_jtagbone: improve phy naming and add uartbone_phy to CSR.	2021-01-26 15:46:55 +01:00
enjoy-digital	7479cbe71b	Merge pull request #784 from Acathla-fr/patch-1 Update comm_usb.py	2021-01-26 14:36:07 +01:00
Florent Kermarrec	331124dd23	tools/litex_server: add --jtag-config args to provide OpenOCD configuration file.	2021-01-26 14:32:36 +01:00
Florent Kermarrec	2e1b9ed948	tools/litex_server: rename --jtag-uart to --jtag.	2021-01-26 14:12:54 +01:00
Florent Kermarrec	531ce0e8b7	soc: create specific add_jtagbone method instead of integrating it in add_uartbnone. Creates a JTAG bridge in the SoC simply with self.add_jtagbone(), almost comes for free :)	2021-01-26 14:12:19 +01:00
Acathla-fr	a092d5b28f	Update comm_usb.py typo : csr_csr replaced by csr_csv	2021-01-26 12:34:08 +01:00
Florent Kermarrec	ed1da7ed1e	soc/add_pcie: expose max_pending_requests parameter. Being able to configure it is useful to find resource usage/performance compromise.	2021-01-26 10:59:22 +01:00
Florent Kermarrec	dd985cd1d0	integration/export: disable CSRField extract/read functions generation for csr.size > 32-bit.	2021-01-26 10:23:56 +01:00
Florent Kermarrec	2a542e150d	jtag_uart/openocd: switch to raw tcp socket and get litex_server --jtag-uart working.	2021-01-25 16:33:43 +01:00
Florent Kermarrec	7799765471	soc/jtag: run JTAGPHY in sys_jtag clock domain (to fix behavior after reset).	2021-01-25 16:31:55 +01:00
Florent Kermarrec	213644af70	integration/soc/add_uart: ResetInserter no longer required on UART since reboot is now doing a full system reset.	2021-01-25 13:39:45 +01:00
Florent Kermarrec	8cada67f32	cores/jtag: cleanup instances.	2021-01-25 12:31:32 +01:00
Florent Kermarrec	0b5df58a1b	cores/jtag: cores/uart: expose jtag/tx/rx_cdc (to ease probing with LiteScope).	2021-01-25 12:30:43 +01:00
Florent Kermarrec	4df336341b	cores/uart: expose fsm/timer (to ease probing with LiteScope).	2021-01-25 12:29:18 +01:00
Florent Kermarrec	17195c5e96	cpu/vexriscv_smp: cleanup new args integration and fix cluster naming.	2021-01-25 11:48:05 +01:00
enjoy-digital	7fa03cb1f3	Merge pull request #782 from enjoy-digital/vexriscv-smp-no-litedram soc/cpu/vexriscv-smp: add args to disable out of order or direct path to LiteDRAM	2021-01-25 08:45:03 +01:00
Florent Kermarrec	1a38d51e08	libbase/memtest: remove 0x no longer required with %p.	2021-01-24 21:09:19 +01:00
Dolu1990	ae2cd31573	soc/cpu/vexriscv-smp add --without-out-of-order-decode and --with-wishbone-memory	2021-01-23 20:38:50 +01:00
Florent Kermarrec	01a2fc11e2	integration/soc/usb_acm: run USB ACM in sys_usb clock domain similar to sys clock domain but with rst disconnected.	2021-01-22 22:57:24 +01:00
Gary Wong	13d1d4cf8e	integration/export: allow manually specifying toolchain triple. If the environment variable TRIPLE is defined, use its value as the highest priority candidate. Useful for testing new cross-compilers, or selecting among toolchains in a different priority than the built-in list.	2021-01-22 12:11:03 -07:00
Florent Kermarrec	8623b0a16a	integration/soc/add_uartbone: fix jtag_uart integration.	2021-01-22 15:00:13 +01:00
Florent Kermarrec	d7aedfbc12	tools/litex_server: add initial JTAG-UART support.	2021-01-22 14:19:38 +01:00
Florent Kermarrec	697ff7447c	soc/integration: add initial JTAG-UART support to UARTbone.	2021-01-22 14:19:03 +01:00
Florent Kermarrec	e8cfe3b6ea	software/liblitedram: fix typo.	2021-01-22 11:57:06 +01:00
enjoy-digital	f22079dc94	Merge pull request #776 from geertu/compiler-warning-fixes Compiler warning fixes	2021-01-22 09:28:23 +01:00
Florent Kermarrec	4e5f20a060	software/liblitedram: rename Half Sys8x Taps to tCK/4 and display "-" during write calibration when no valid bitstlip found.	2021-01-21 20:00:29 +01:00
Florent Kermarrec	57289dd47c	software/liblitedram/write_leveling: display Half Sys8x Taps value before write_leveling.	2021-01-20 09:43:53 +01:00
Florent Kermarrec	acb6741b8a	software/bios: rename CONFIG_SIM_DISABLE_DELAY to CONFIG_DISABLE_DELAYS and disable timeout on serialboot's check_ack when CONFIG_DISABLE_DELAYS is set. This is useful in simulation to skip serialboot ack check.	2021-01-20 09:42:29 +01:00
Geert Uytterhoeven	0f28bc489d	software/include/base/stdio: Enable printf format strings checks Now all format issues are fixed, tag all functions taking printf()-style format specifiers with "__attribute__((format(printf, ...))", enabling format string checks ("-Wall" includes "-Wformat"). Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-01-19 15:03:48 +01:00
Geert Uytterhoeven	c3dea1b9fd	software: Use "%p" to format pointer values To fix compiler warnings of the following type: warning: format '%x' expects argument of type 'unsigned int', but argument 2 has type 'foo *' [-Wformat=] Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-01-19 15:03:48 +01:00
Geert Uytterhoeven	19e7b53762	software: Use "l" length modifier to format long values To fix compiler warnings of the following type: warning: format '%x' expects argument of type 'unsigned int', but argument has type 'long unsigned int' [-Wformat=] Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-01-19 15:03:48 +01:00
Geert Uytterhoeven	a2389c71ea	software: Fix cast from pointer to integer of different size warnings litex/soc/software/liblitesdcard/sdcard.c: In function 'sdcard_read': litex/soc/software/liblitesdcard/sdcard.c:476:29: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] sdblock2mem_dma_base_write((uint64_t) buf); ^ litex/soc/software/liblitesdcard/sdcard.c: In function 'sdcard_write': litex/soc/software/liblitesdcard/sdcard.c:507:30: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] sdmem2block_dma_base_write((uint64_t) buf); ^ When casting a pointer (32-bit or 64-bit, depending on the platform) to a 64-bit integer, an intermediate cast to "uintptr_t" should be used to avoid warnings like the above. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-01-19 15:03:48 +01:00
Geert Uytterhoeven	5474f563c8	software/bios/readline: Use unsigned int for small numbers There is no need to use "unsigned long" for small numbers related to the number of characters in a line. Use "unsigned int" instead. This allows us to drop the casts when calling putnstr(), and fixes compiler warnings on 64-bit for callsites where the casts were missing: warning: field precision specifier '.*' expects argument of type 'int', but argument 2 has type 'long unsigned int' Reported-by: Gabriel Somlo <gsomlo@gmail.com> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-01-19 15:03:48 +01:00
Geert Uytterhoeven	ab8cee1b5e	software/bios/cmds/cmd_i2c: Use "%zu" to format size_t The sizeof operator returns "size_t", which is defined to be "unsigned int" on 32-bit, and "unsigned long" on 64-bit. Format it using "%zu", to fix compiler warnings of the following type on 64-bit: warning: format '%d' expects argument of type 'int', but argument has type 'long unsigned int' [-Wformat=] Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-01-19 15:03:48 +01:00
Geert Uytterhoeven	cbd54e7b5c	software/bios/cmds/cmd_bios: Make crc command 64-bit clean On 64-bit: litex/soc/software/bios/cmds/cmd_bios.c: In function 'crc_handler': litex/soc/software/bios/cmds/cmd_bios.c:110:30: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] printf("CRC32: %08x", crc32((unsigned char *)addr, length)); ^ Fix this by using the appropriate types (uintptr_t and size_t) for memory addresses and sizes, which are defined to 32-bit or 64-bit, depending on the platform. Note that the specified length must still be smaller than 4 GiB on 64-bit, or it will be truncated, as the crc32() function is currently limited to a 32-bit size anyway. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-01-19 15:03:48 +01:00
Geert Uytterhoeven	857ef69b3f	software/bios/boot: Fix cast to pointer from integer of different size warnings On 64-bit: litex/soc/software/bios/boot.c: In function 'serialboot': litex/soc/software/bios/boot.c:216:20: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] writepointer = (char *) get_uint32(&frame.payload[0]); ^ When casting from a 32-bit integer to a pointer (32-bit or 64-bit, depending on the platform), an intermediate cast to "uintptr_t" should be used to avoid warnings like the above. Note that using a 32-bit integer is OK, even on 64-bit, as this is specified by the boot protocol. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-01-19 15:03:48 +01:00
Geert Uytterhoeven	84e3a77724	software/liblitedram: Use "%u" to format uint32_t values To fix compiler warnings of the following type: warning: format '%lu' expects argument of type 'long unsigned int', but argument has type 'unsigned int' [-Wformat=] Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-01-19 15:03:48 +01:00
Geert Uytterhoeven	b979e69934	software/libbase: Remove empty printf statements To fix compiler warnings of the following type: warning: zero-length gnu_printf format string [-Wformat-zero-length] Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-01-19 15:03:48 +01:00
Geert Uytterhoeven	bff23b8f73	software/libbase/vsnprintf: Prefix pointers by "0x" Set the PRINTF_SPECIAL flag when printing pointers, so they are prefixed by "0x", to match glibc behavior. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-01-19 15:03:48 +01:00
Geert Uytterhoeven	91c9192626	software/include/base: Fix size_t, ptrdiff_t, and (u)intptr_t As per convention, the types of size_t, ptrdiff_t, intptr_t, and uintptr_t should be based on "long" or "int" depending on the platform (32-bit or 64-bit). This fixes compiler warnings of the following type: litex/soc/software/liblitesdcard/sdcard.c: In function 'sdcard_read': litex/soc/software/liblitesdcard/sdcard.c:476:39: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] sdblock2mem_dma_base_write((uint64_t)(uintptr_t) buf); ^ Reported-by: Gabriel Somlo <gsomlo@gmail.com> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-01-19 15:03:48 +01:00
Geert Uytterhoeven	1710c5f1ef	software/include/base/limits: Fix ULONG_MAX on 64-bit The value of ULONG_MAX should depend on the size of "long". While at it: - Add missing "UL" and "U" suffixes to large unsigned values, - Make INT_MIN and SHRT_MIN explicitly negative, - Use decimal instead of hexadecimal values, for easier comparison with /usr/include/limits.h. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-01-19 15:03:48 +01:00
Geert Uytterhoeven	e0786c3f94	software/include/base: Check __LP64__ instead of __WORDSIZE __WORDSIZE is defined by glibc, not by the compiler. Hence it is never defined for us, and checking __WORDSIZE to determine the size of "long" thus causes subtle misbehavings. Fix this by checking for the presence of __LP64__ instead. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-01-19 14:59:49 +01:00
Florent Kermarrec	41964f945c	litex_term/SFL: remove flashing capability. It's probably better not mixing uploading/flashing utilities. Flashing should be done with the proper bootloader (as we are doing on Fomu/OrangeCrab for example).	2021-01-18 16:47:47 +01:00
Florent Kermarrec	a0bcbeb68b	tools/litex_term: fully deprecate --no-crc argument.	2021-01-18 16:34:34 +01:00
Florent Kermarrec	2f5ad47f7a	tools/litex_term: fix get_args typo.	2021-01-18 16:30:27 +01:00
Florent Kermarrec	81f4ffafdb	build/tools/language_by_filename: add svo to system-verilog extensions.	2021-01-18 16:29:52 +01:00
enjoy-digital	2cb4f513f1	Merge pull request #775 from geertu/i2c-scan-fixes I2c scan fixes and cleanups	2021-01-15 17:50:20 +01:00
enjoy-digital	bf0f0176b3	Merge pull request #774 from antmicro/vex-debug CPU: Vex: add debug slave for dbg cpu variant	2021-01-15 17:49:33 +01:00
Geert Uytterhoeven	dc3306731c	software/bios/cmds/cmd_i2c: Simplify upper nibble calculation Use masking instead of division and multiplication. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-01-15 12:01:08 +01:00
Geert Uytterhoeven	28ed06f1c5	software/bios/cmds/cmd_i2c: Fix i2c_scan output "i2c_scan" prints random data instead of the intended slave address: 0x70: 10001ebc -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- instead of: 0x70: 70 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Fix this by adding the missing printf() parameter. Fixes: `ee1ea9baab` ("bios/cmd/cmd_i2c: make results similar to Linux's i2cdetect.") Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2021-01-15 12:01:08 +01:00
Karol Gugala	5d0c5d7088	CPU: Vex: add debug slave for dbg cpu variant Signed-off-by: Karol Gugala <kgugala@antmicro.com>	2021-01-15 09:28:03 +01:00
Florent Kermarrec	b1cad93e62	tools/litex_json2dts: add clock_frequency property to VexRiscv-SMP cpus. Required by some Linux drivers (SDCard for example).	2021-01-14 14:25:53 +01:00
Florent Kermarrec	50939fdd33	software/liblitedram/sdram_write_leveling: allow external configuration of cdly_range_start and cdly_range_end.	2021-01-14 13:18:10 +01:00
Florent Kermarrec	35a8b498a0	tools/litex_json2dts/sdcard: use sdphy base as csr base. To be similar with csr base defined used in linux-on-litex-rocket.	2021-01-14 09:28:06 +01:00
Florent Kermarrec	83fb79fb0c	tools/litex_term: review/simplify a bit PR #772 .	2021-01-13 19:33:29 +01:00
William D. Jones	ce243820fe	tools/litex_term: Convert some common scan codes into ANSI codes on Windows.	2021-01-11 21:02:37 -05:00
William D. Jones	5babcadbed	tools/litex_term: Set ENABLE_VIRTUAL_TERMINAL_PROCESSING flag on Windows.	2021-01-11 19:54:21 -05:00
William D. Jones	bfc624f23e	tools/litex_term: Avoid importing termios and pty on Windows.	2021-01-11 14:51:55 -05:00
Florent Kermarrec	460fada3ac	tools/litex_term: revert LiteXTerm to threading (multiprocessing breaks Windows/OS-X). Ideally we should switch to AsyncIO as some point.	2021-01-11 19:29:15 +01:00
Florent Kermarrec	1ce194007b	software: allow BIOS compilation with UART disabled.	2021-01-08 19:18:44 +01:00
Florent Kermarrec	19fda3364a	tools/litex_term: fix 100% cpu load after refactoring (thanks sergpolkin).	2021-01-08 13:57:33 +01:00
Florent Kermarrec	5f9c4a4ab4	soc/cores/gpio: remove intermediate _pads signal.	2021-01-06 21:39:02 +01:00
Florent Kermarrec	0984308318	cores/gpio: add assertion on pads (has to be a Signal). Due to the bi-directional nature of tristate, Cat is not supported (so also not platform.request_all).	2021-01-06 09:56:56 +01:00
David Lattimore	875f34f8e2	Lattice NX: Allow up to 320KB of RAM	2021-01-06 09:45:08 +11:00
Florent Kermarrec	16008d3f3a	cpu/vexriscv/cpu-count: fix type and add comment (thanks dayjaby).	2021-01-04 14:43:08 +01:00
Florent Kermarrec	f31f9a20f0	boards: remove and switch to litex_boards. Keeping board definition files directly in LiteX is no longer useful since we are already relying on board definitions files from LiteX-Boards (https://github.com/litex-hub/litex-boards) in various benches/projects and having definitions files directly in LiteX creates confusion/additional work. For projects using board definition files from LiteX, the litex.boards import can just be replaced with litex_boards: from litex.boards.platforms import kc705 from litex_boards.platforms import kc705	2021-01-04 14:09:35 +01:00
William D. Jones	f65491c809	Use riscv32 gcc triples for picorv32- superset of riscv64 triples.	2020-12-31 03:22:56 -05:00
Florent Kermarrec	b9e0c95c18	cpu/microwatt: use 0xf9807b6 and fix compilation, working with IRQs :) Tested with: /arty.py --cpu-type=microwatt --cpu-variant=standard+irq --integrated-rom-size=0x10000 --build --load __ _ __ _ __ / / (_) /____ \| \|/_/ / /__/ / __/ -_)> < /____/_/\__/\__/_/\|_\| Build your hardware, easily! (c) Copyright 2012-2020 Enjoy-Digital (c) Copyright 2007-2015 M-Labs BIOS built on Dec 30 2020 15:59:16 BIOS CRC passed (fb76e85d) Migen git sha1: d42aa6f LiteX git sha1: `74844db3` --=============== SoC ==================-- CPU: Microwatt @ 100MHz BUS: WISHBONE 32-bit @ 4GiB CSR: 32-bit data ROM: 64KiB SRAM: 8KiB L2: 8KiB SDRAM: 262144KiB 16-bit @ 800MT/s (CL-6 CWL-5) --========== Initialization ============-- Initializing SDRAM @0x40000000... Switching SDRAM to software control. Write latency calibration: m0:0 m1:0 Read leveling: m0, b0: \|00000000000000000000000000000000\| delays: - m0, b1: \|00000000000011111111111111100000\| delays: 19+-07 m0, b2: \|00000000000000000000000000001111\| delays: 30+-02 m0, b3: \|00000000000000000000000000000000\| delays: - m0, b4: \|00000000000000000000000000000000\| delays: - m0, b5: \|00000000000000000000000000000000\| delays: - m0, b6: \|00000000000000000000000000000000\| delays: - m0, b7: \|00000000000000000000000000000000\| delays: - best: m0, b01 delays: 19+-07 m1, b0: \|00000000000000000000000000000000\| delays: - m1, b1: \|00000000000011111111111111000000\| delays: 19+-07 m1, b2: \|00000000000000000000000000001111\| delays: 30+-01 m1, b3: \|00000000000000000000000000000000\| delays: - m1, b4: \|00000000000000000000000000000000\| delays: - m1, b5: \|00000000000000000000000000000000\| delays: - m1, b6: \|00000000000000000000000000000000\| delays: - m1, b7: \|00000000000000000000000000000000\| delays: - best: m1, b01 delays: 19+-06 Switching SDRAM to hardware control. Memtest at 0x0000000040000000 (2MiB)... Write: 0x40000000-0x40200000 2MiB Read: 0x40000000-0x40200000 2MiB Memtest OK Memspeed at 0x0000000040000000 (2MiB)... Write speed: 32MiB/s Read speed: 54MiB/s --============== Boot ==================-- Booting from serial... Press Q or ESC to abort boot completely. sL5DdSMmkekro Timeout No boot medium found --============= Console ================-- litex>	2020-12-30 16:20:20 +01:00
Florent Kermarrec	74844db3b9	cores/cpu: add optional add_soc_components method and use it to add VexRiscv-SMP's PLIC/CLINT and Microwatt's XCIS. Also shorten XCIS name on Microwatt from HOSTXICS to XCIS.	2020-12-30 15:35:27 +01:00
Florent Kermarrec	49217ec6ea	cores/cpu/vexriscv_smp: minor cleanups.	2020-12-30 14:45:33 +01:00
Florent Kermarrec	a8ddbb190a	cores/cpu/vexriscv_smp: add standard variant (similar to Linux, avoid passing cpu-variant=linux when selection vexriscv_smp).	2020-12-30 14:41:54 +01:00
Florent Kermarrec	7bcebf4cdd	cpu/microwatt: improve/fix XICS controller integration for variants with irq.	2020-12-30 12:25:01 +01:00
Florent Kermarrec	0cba91022e	cpu/vexriscv_smp: move smp_slave to crt0. Fixes bare metal demo compilation with VexRiscv-SMP.	2020-12-30 11:56:11 +01:00
Florent Kermarrec	4f6bc32a5a	software/demo: make leds optional. Allow running demo directly with litex_sim: litex_sim (then exit with ctrl-c on BIOS prompt) litex_bare_metal_demo --build-path=build/sim/ litex_sim --ram-init=demo.bin	2020-12-30 11:25:32 +01:00
Florent Kermarrec	8ff26b7304	targets/arty: add variant support through --variant argument. ./arty.py --variant=a7-35 or a7-100	2020-12-29 18:45:41 +01:00
Florent Kermarrec	70d364cf4e	integration/soc: add software_debug parameter to add_ethernet, add_(spi)sdcard to ease enabling software debug traces from design.	2020-12-29 15:38:46 +01:00
Florent Kermarrec	c7056b77bb	tools/litex_json2dts/soc_controller: remove VexRiscv-SMP workaround now that we able to use upstream linux litex patches.	2020-12-29 12:25:38 +01:00
Florent Kermarrec	7627dadb9b	tools/litex_json2dts/soc_controller: add workaround for VexRiscv-SMP. We need to fix https://github.com/litex-hub/linux-on-litex-vexriscv/issues/176 to be able to switch to soc-controller with VexRiscv-SMP.	2020-12-29 09:29:23 +01:00
enjoy-digital	d5bf09d8f4	Merge pull request #747 from shenki/soc-controller-compatible dts: Fix soc controller compatible	2020-12-29 09:23:03 +01:00
Florent Kermarrec	bf32d23d9a	tools/litex_json2dts: add --polling args to allow forcing polling mode on peripherals. Can be useful for debug purpose or bring up of new hardware not yet supporting IRQs.	2020-12-29 09:03:35 +01:00
Florent Kermarrec	d9a44ce10f	tools/litex_json2dts: minor changes/cleanup on #745 . - shorten args description. - avoid mixing initrd_start/initrd_start_offset: just use initrd_start and indicate it's relative. - others minor cleanups.	2020-12-29 08:36:55 +01:00
enjoy-digital	152ae03798	Merge pull request #745 from stffrdhrn/dts-interrupts RFC dts: Support generating interrupt config	2020-12-29 08:16:19 +01:00
Stafford Horne	a2c9b17959	dts: Allow specifying initrd position and size via args This is needed as my initrd size is much larger than the default 8mb. Also, sometimes the kernel I build is also large, so its good to be able to move the initrd starting position. Issue #748	2020-12-29 08:18:55 +09:00
Stafford Horne	5cc2c4aaf7	dts: Support generating interrupt config This addresses #744	2020-12-28 09:51:22 +09:00
Joel Stanley	13345bfe7f	dts: Fix soc controller compatible The version that landed upstream is spelt litex,soc-controller with a dash instead of an underscore. Signed-off-by: Joel Stanley <joel@jms.id.au>	2020-12-27 22:40:29 +10:30
rprinz08	c99c96bc68	Enable etherbone usage on multiple ethernet interfaces	2020-12-22 21:13:10 +01:00
Florent Kermarrec	1a338b602a	software/bios: add new mem_list command to list available memory regions. This is useful to know the memory regions available and use the mem_xy commands on them: List the memory regions: litex> mem_list Available memory regions: ROM 0x00000000 0x8000 SRAM 0x01000000 0x2000 MAIN_RAM 0x40000000 0x10000000 CSR 0x82000000 0x10000 Test 0x1000 bytes of MAIN_RAM: litex> mem_test 0x40000000 0x1000 Memtest at 0x40000000 (4KiB)... Write: 0x40000000-0x40001000 4KiB Read: 0x40000000-0x40001000 4KiB Memtest OK Test speed on 0x1000 bytes of MAIN_RAM: litex> mem_speed 0x40000000 0x1000 Memspeed at 0x40000000 (4KiB)... Write speed: 352KiB/s Read speed: 288KiB/s	2020-12-22 19:15:57 +01:00
Stafford Horne	3067c57080	mor1kx: Enable gcc compiler flag for cmov We enable this instruction so use it.	2020-12-22 22:10:42 +09:00
Stafford Horne	51327e00b5	mor1kx: Enable rotate, sign extend under linux, new fpu extension My thought is that if we are running linux the FPGA should be able to handle these extra instruction's footprint. Also, since we are running on linux there may be any kind of software running on the CPU, so allow handling these instructions. FPU is added bia a new +fpu extension. But really, I am running GLIBC tests and they run faster with this enabled.	2020-12-22 22:10:42 +09:00
Florent Kermarrec	d90d3e043b	software/liblitedram: add optional SDRAM_TEST_DISABLE that can be defined to full disable SDRAM test. This is useful in simulation where SDRAM contents is pre-initialized from files (ex Linux-on-LiteX-Vexriscv).	2020-12-22 10:50:15 +01:00
Florent Kermarrec	12dabde77c	integration/soc/add_ethernet: add phy_cd parameter to allow and demonstrate multiple PHYs support.	2020-12-22 09:03:00 +01:00
Florent Kermarrec	c79135c573	software/demo: add litex_bare_metal_demo pre-installed script. Build demo: litex_bare_metal_demo --build-path=build/arty/	2020-12-21 19:27:21 +01:00
Florent Kermarrec	4df56ed456	software/demo: add short README.	2020-12-21 18:44:10 +01:00
Florent Kermarrec	ef2ed8bbbc	tools/litex_json2dts: fix vexriscv-smp cpu reg numbering.	2020-12-21 18:16:44 +01:00
Florent Kermarrec	5ec5554713	tools/litex_json2dts: cleanup and reorganize peripherals.	2020-12-21 16:11:45 +01:00
Florent Kermarrec	df92e2aea7	tools/litex_json2dts: switch VexRiscv to SMP, update SDCard dts.	2020-12-21 16:11:32 +01:00
enjoy-digital	0a9c9562dc	Merge pull request #738 from antmicro/quartus-handle-includes Quartus: handle vh and svh files	2020-12-21 10:19:27 +01:00
Florent Kermarrec	90b9f4eca3	soc/interconnect/axi: fix AXIInterface.get_ios().	2020-12-21 08:51:04 +01:00
Karol Gugala	7f6af0a437	Quartus: handle vh and svh files Signed-off-by: Karol Gugala <kgugala@antmicro.com>	2020-12-20 11:53:08 +01:00
enjoy-digital	7fccf9fcd0	Merge pull request #736 from Disasm/ecpdap Add ECPDAP programmer	2020-12-18 15:39:24 +01:00
Florent Kermarrec	b7aec66929	soc/interconnect/axi: simplify AXI Full connect_to_pads and get_ios.	2020-12-18 15:35:04 +01:00
enjoy-digital	57d9816065	Merge pull request #734 from antmicro/axi4-slave-bridge Add get_ios for full AXI and add missing signals in connect_to_pads	2020-12-18 15:25:54 +01:00
enjoy-digital	9ae5a4f4ea	Merge pull request #735 from Dolu1990/vexriscv_smp cores/cpu/vexriscv_smp add AES support	2020-12-18 14:43:04 +01:00
enjoy-digital	f055b1be69	Merge pull request #732 from Disasm/ecp5-compress Add option for ECP5 bistream compression	2020-12-18 14:42:34 +01:00
Vadim Kaushan	0fe2477f69	Add ECPDAP programmer	2020-12-18 15:42:18 +03:00
Dolu1990	ee47c7b260	cores/cpu/vexriscv_smp add AES support	2020-12-18 12:10:33 +01:00
Piotr Binkowski	f26769eb4d	interconnect/axi: add connect_to_pads to full AXI	2020-12-18 09:06:45 +01:00
Piotr Binkowski	18e90234b0	interconnect/axi: add get_ios to full AXI	2020-12-18 08:59:11 +01:00
Vadim Kaushan	2bc76f3245	Add option for ECP5 bistream compression	2020-12-18 00:21:05 +03:00
Florent Kermarrec	4092180662	tools/lxterm/json: json file provide relative path, add json file directory to image names. Allow sharing same json file between serial boot and Ethernet/SDCard/SATAboot: boot.json: { "Image": "0x40000000", "rv32.dtb": "0x40ef0000", "rootfs.cpio": "0x41000000", "opensbi.bin": "0x40f00000" } If boot.json and images are located in images directory, using lxterm --images=images/boot.json will now work.	2020-12-17 16:08:32 +01:00
enjoy-digital	f777cddefe	Merge pull request #731 from lindemer/pmp Allow selection of VexRiscv_Secure* from lxsim CLI	2020-12-14 19:41:51 +01:00
Samuel Lindemer	c23a894014	Allow selection of VexRiscv_Secure* from lxsim CLI	2020-12-14 10:54:02 +01:00
Florent Kermarrec	bc2b7995f5	integration/export/get_csr_header: don't generate replace/write fields access functions when CSR is read only.	2020-12-14 10:51:37 +01:00
bunnie	649edd189a	Merge pull request #729 from betrusted-io/master another minor change - reveal STARTUPE2 block's ring oscillator	2020-12-13 02:19:56 +08:00
bunnie	422cc2baae	another minor change - reveal STARTUPE2 block's ring oscillator	2020-12-13 01:49:43 +08:00
Florent Kermarrec	fb3b09db15	integration/soc/add_uart: add crossover+bridge support. Useful to have both CPU UART and bridge debug capability.	2020-12-10 18:32:21 +01:00
Florent Kermarrec	88bd754dd6	software: add minimal baremetal demo app. Used to demonstrates how to easily create baremetal apps, boot to it with LiteX and also ease litex_term testing. To build it: export BUILD_DIR=xxyy/litex/litex/boards/targets/build/arty && make To load it: lxterm /dev/ttyUSB1 --kernel=demo.bin --============== Boot ==================-- Booting from serial... Press Q or ESC to abort boot completely. sL5DdSMmkekro [LXTERM] Received firmware download request from the device. [LXTERM] Uploading demo.bin to 0x40000000 (9264 bytes)... [LXTERM] Upload complete (9.8KB/s). [LXTERM] Booting the device. [LXTERM] Done. Executing booted program at 0x40000000 --============= Liftoff! ===============-- LiteX minimal demo app built Dec 10 2020 17:13:02 Available commands: help - Show this command reboot - Reboot CPU led - Led demo donut - Spinning Donut demo litex-demo-app> led Led demo... Counter mode... Shift mode... Dance mode... litex-demo-app> donut Donut demo... $$$$$@@@@@ $##########$$$$$$$$ ###!!!!!!!!!##$$$$$$ !!====;;;;===!!###$$$$# !===;;;:::::;:===!!####$## !!!==;;:~-,,.,-~::;;=!!#######! !!!!=;:~-,.......-~::==!!##### !!!!==;~~-.........,-:;==!!*###! !!!=;:~-... ..-:;=!!!*****! ;!#####!!;. ~:;==!!!****!!= :!###$$$$#! :;==!!!!!**!!!=; ~=!#$$$@@@$$##!!!!!!!!!!!!***!!!!=; ;=!#$$$@@@@$$#******!!!!!!!!==;~ -;!###$$$$$$$###*****!!!!!!!===;~ -;!!####$#####****!!!!!!==;;:- ,:=!!!!##!!!!!!!====;:~, -:==!!!!!*!!!!!!!===;;;:~- .~:;;========;=;;:::~-, .--~~::::~:~~--,. litex-demo-app>	2020-12-10 17:16:28 +01:00
bunnie	ef6fd57613	Merge pull request #727 from betrusted-io/master fix a timing error in the S7 OPI block	2020-12-10 23:17:29 +08:00
Florent Kermarrec	ee41fbb338	tools: deprecate litex_jtag_uart (now directly integrated in litex_term).	2020-12-10 15:48:10 +01:00
bunnie	8ee0fdbf8e	fix a timing error in the S7 OPI block should have no impact on normal operation, the path is only for registering addresses that are correlated with ECC errors as reported by the OPI device.	2020-12-10 22:48:09 +08:00
Florent Kermarrec	39b84581f4	tools/litex_term: add JTAG UART support (litex_term jtag_uart).	2020-12-10 15:46:12 +01:00
Florent Kermarrec	384041affb	tools/litex_term/crossover: use burst to speed up reads.	2020-12-10 14:34:00 +01:00
Florent Kermarrec	48dc574703	integration/soc/add_uart: pass fifo_depth to UARTCrossover.	2020-12-10 14:33:29 +01:00
Florent Kermarrec	1976fd4b90	tools: deprecate litex_crossover_uart (now directly integrated in litex_term).	2020-12-10 13:54:21 +01:00
Florent Kermarrec	feeb2f72e0	tools/litex_term: add direct crossover UART bridge suppport (lxterm --crossover) and switch to multiprocessing.	2020-12-10 13:45:38 +01:00
Stéphane Gourichon	8a82ddf6e1	CSR fields: generate convenience functions (#725 ) Generate convenience methods to extract/replace bits in CSR fields, only generate replace if CSR register is writable.	2020-12-10 11:32:21 +01:00
Florent Kermarrec	cd80c87f1a	software/liblitedram/write_leveling: revert ideal_delay to 0, ensure write delay is set just before 0 to 1 transition.	2020-12-09 19:51:19 +01:00
Florent Kermarrec	5ebea9434b	software/liblitedram/sdram: improve comments.	2020-12-09 17:53:33 +01:00
enjoy-digital	44d21cb0f3	Merge pull request #722 from geertu/master tools/litex_json2dts: Miscellaneous fixes and improvements	2020-12-08 14:01:14 +01:00
enjoy-digital	a80398d2ab	Merge pull request #724 from sergachev/master soc/interconnect/axi: let connect_to_pads() be used by AXIInterface too	2020-12-08 13:45:12 +01:00
Florent Kermarrec	c6fb9ef939	software/liblitedram: limit clk/cmd scan to 1/2 tCK. Restrict the clk/cmd scan to 1/2 tCK since the full scan is not required and in some cases can compromise the calibration with the wrong best clk/cmd value selection. This should also allow using cmd_latency=0 in all cases.	2020-12-08 10:01:18 +01:00
Florent Kermarrec	c19c343ecf	software/libbase: add memtest_access before testing bus/addr/data to exit early if bus errors are detected.	2020-12-07 14:05:51 +01:00
Florent Kermarrec	fb05fbc5cc	software: always provide flush_l2_cache implementation (even if empty) to avoid #ifdefs CONFIG_L2_SIZE.	2020-12-07 13:45:05 +01:00
Florent Kermarrec	3ce74f6e29	software/libbase/memtest: cosmetic cleanups.	2020-12-07 13:23:58 +01:00
Ilia Sergachev	9af9ee6b66	soc/interconnect/axi: let connect_to_pads() be used by AXIInterface too	2020-12-06 00:23:30 +01:00
Florent Kermarrec	bed072ef19	tools/litex_term: use different payload_length/delay settings for USB-ACM.	2020-12-04 19:59:49 +01:00
Geert Uytterhoeven	d8b844bbda	tools/litex_json2dts: Group tuples in liteeth reg property To improve human readability and enable automatic validation, the tuples in "reg" properties should be grouped using angle brackets. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2020-12-04 16:38:48 +01:00
Geert Uytterhoeven	a17b535906	tools/litex_json2dts: Fix DTS indentation Make indentation of the generated DTS more consistent, by always using 8 spaces (no TABs), and aligning continued lines. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2020-12-04 16:21:52 +01:00
Geert Uytterhoeven	8265d06728	tools/litex_json2dts: Fix SPI bus #size-cells As per Documentation/devicetree/bindings/spi/spi-controller.yaml, "#size-cells" must be zero for a PCI bus. This gets rid of the following build warnings: build/orangecrab/orangecrab.dts:105.29-39: Warning (reg_format): /soc/spi@f0004800/mmc-slot@0:reg: property has invalid length (4 bytes) (#address-cells == 1, #size-cells == 1) buildroot/rv32.dtb: Warning (pci_device_reg): Failed prerequisite 'reg_format' buildroot/rv32.dtb: Warning (pci_device_bus_num): Failed prerequisite 'reg_format' buildroot/rv32.dtb: Warning (simple_bus_reg): Failed prerequisite 'reg_format' buildroot/rv32.dtb: Warning (i2c_bus_reg): Failed prerequisite 'reg_format' build/orangecrab/orangecrab.dts:91.46-110.19: Warning (spi_bus_bridge): /soc/spi@f0004800: incorrect #size-cells for SPI bus buildroot/rv32.dtb: Warning (spi_bus_reg): Failed prerequisite 'reg_format' buildroot/rv32.dtb: Warning (spi_bus_reg): Failed prerequisite 'spi_bus_bridge' Fixes: `fafa844aa7` ("json2dts: Add Linux DT generation script") Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>	2020-12-04 16:19:29 +01:00
Florent Kermarrec	b7c0922ec1	tools/litex_term: increase outstanding to 128 (4 is slowing down speed with USB-FIFO).	2020-12-04 16:01:35 +01:00
Florent Kermarrec	894802d131	tools/litex_term: add sfl_outstanding parameter (set to 4), cleanup code and increase inter-frame delay. This fixes upload on OrangeCrab with USB-ACM, but we still need to understand why sfl_payload_length can't be set to 255 with USB-FIFO.	2020-12-04 15:46:18 +01:00
Florent Kermarrec	5e10552f3f	soc/interconnect/packet/Packetizer: fix last_be for 10gbe.	2020-12-03 17:11:04 +01:00
enjoy-digital	168c5380cf	Merge pull request #718 from trabucayre/zynq_fix_constraints don't add pins without pad location in constraints file	2020-12-03 16:21:06 +01:00
enjoy-digital	88023394fd	Merge pull request #721 from daveshah1/dave/nexus-pll-resetena clock/lattice_nx: Set PLLRESET_ENA parameter	2020-12-03 15:54:16 +01:00
Florent Kermarrec	dba6653cb4	tools/litex_term: reduce sfl_payload_length to 64 as before. See: https://github.com/enjoy-digital/litex/issues/720.	2020-12-03 12:52:00 +01:00
David Shah	90315868a8	clock/lattice_nx: Set PLLRESET_ENA parameter If this parameter isn't set to ENABLED; then the PLLRESET signal is ignored. Signed-off-by: David Shah <dave@ds0.me>	2020-12-03 11:49:48 +00:00
Florent Kermarrec	172dc18dfb	bios/boot: remove SFL_CMD_LOAD_NO_CRC support (non longer useful since CRC checking is now fast).	2020-12-03 12:11:48 +01:00
enjoy-digital	136db6a0ca	Merge pull request #719 from davidlattimore/no-error-recovery lxterm: Speed up CRC checked uploads	2020-12-03 12:06:46 +01:00
Florent Kermarrec	d6a49e85c4	integration/soc_core: only add IRQs from interrupt_map if SoC supports them.	2020-12-03 09:48:42 +01:00
Florent Kermarrec	42e7b8d35a	integration/soc/irq: improve error message.	2020-12-03 09:47:50 +01:00
David Lattimore	b421d50b40	lxterm: Increase maximum payload size to match BIOS sfl_frame (in sfl.h) already had a payload size of 255. This should give about a 10% speed gain due to reduced overhead. 8 bytes of header per 251 bytes sent, as opposed to 8 bytes of header per 60 bytes sent	2020-12-03 13:44:09 +11:00
David Lattimore	03c2257baf	lxterm: Deprecate --no-crc flag The flag is left, in case people are using it from scripts, but now does nothing besides printing a warning.	2020-12-03 13:37:43 +11:00
David Lattimore	513a799a39	lxterm: Don't attempt to recover from CRC errors during upload. This allows transfers to proceed at the full speed of the serial link. We still check all responses, but will now fail outright if a CRC error occurs.	2020-12-03 13:37:26 +11:00
Gwenhael Goavec-Merou	b896b20e46	don't add pins without pad location in constraints file	2020-12-02 13:24:15 +01:00
Florent Kermarrec	8eecbd7b57	integration/soc/add_sdcard: integrate interrupts.	2020-12-01 13:25:05 +01:00
Gabriel Somlo	5cc3db0176	soc: cosmetic: reduce horizontal indentation in IRQ init.	2020-11-30 16:29:16 -05:00
Gabriel Somlo	9af56cf247	soc: fix typo in IRQ handler exception	2020-11-30 16:27:31 -05:00
Florent Kermarrec	d193092e16	cores/cpu/cv32e40p/core: rewrite OBI2Wishbone to reduce write/read latency by 1 cycle.	2020-11-30 12:18:59 +01:00
Florent Kermarrec	18f66a79f2	cores/cpu/zynq7000: improve methods to pass provide/pass configuration to PS7. User can now only use set_ps7 and provides the .xci file, preset file or/and additional configuration: To use a .xci file, in the design do: self.cpu.set_ps7(xci="ps7.xci") To use a preset: self.cpu.set_ps7(preset="preset_name") To use a config dict: self.cpu.set_ps7(name="ps7_name", config={"param0": "0", "param1": "1"}) It's also possible to use preset and then pass and additionnal config dict: self.cpu.set_ps7(preset="preset_name") self.cpu.add_ps7_config({"param0": "0", "param1": "1"}) or all at once: self.cpu.set_ps7(preset="preset_name", config={"param0": "0", "param1": "1"})	2020-11-30 11:30:48 +01:00
enjoy-digital	30e8773819	Merge pull request #711 from trabucayre/ps7_config zynq7000: add tcl to create zynq IP based on board preset and custom configuration	2020-11-30 10:28:54 +01:00
Florent Kermarrec	c8fcaaea2d	integration/soc: use self.irq.enabled instead of hasattr(self.cpu, "interrupt").	2020-11-30 10:17:03 +01:00
Florent Kermarrec	146068b048	integration/soc/SoCIRQHandler: be sure IRQs can only be added when enabled. This prevents adding peripherals that requires IRQ support to SoC not supporting them. Enabling is done automatically when a CPU with interrupt support is added, but this can also be added manually.	2020-11-30 10:06:45 +01:00
gsomlo	d9f9b4aeb6	Merge pull request #713 from daveshah1/dave/rocket-reset-fix rocket: Fix UB due to optimised away DFFs	2020-11-28 08:12:33 -05:00
David Shah	61895bef37	rocket: Fix UB due to optimised away DFFs As both clock and async reset for the debug DFFs were 0, and there was no initial value on them, they were being validly optimised away by newer Yosys versions to 1'bx which was propagating into and breaking the core. This fixes the problem by tying the async resets to the CPU reset signal. Signed-off-by: David Shah <dave@ds0.me>	2020-11-28 11:15:42 +00:00
Florent Kermarrec	c491c60b7d	soc/cores/prbs/PRBSRX: add pause signal to pause errors counting. Simplify CDC when passing the errors to software by allowing the values to stabilized.	2020-11-28 11:33:57 +01:00
Florent Kermarrec	869e50ade8	soc/cores/prbs: minor cosmetic cleanups.	2020-11-28 10:27:22 +01:00
Florent Kermarrec	e2dcdcf917	build/lattice/programmer/load_bitstream: convert .bit to .svf with bit_to_svf it bitstream_file provided as .bit.	2020-11-28 08:58:57 +01:00
Florent Kermarrec	289234b102	build/lattice: add bit_to_svf script from Project Trellis to allow using OpenOCD with Diamond.	2020-11-28 08:58:04 +01:00
Gwenhael Goavec-Merou	08b6d0388c	zynq7000: add tcl to create zynq IP based on board preset and custom configuration	2020-11-28 08:56:47 +01:00
Florent Kermarrec	785bc7e86c	build/lattice/diamond: set timingstrict default value to False (similar to others build backends)	2020-11-28 07:56:30 +01:00
Florent Kermarrec	e5a7375b30	cores/clock/ECP5PLL: ensure ECP5PLL's locked is deasserted on reset. It seems EHXPLLL does not loose locked when reseted.	2020-11-26 18:56:24 +01:00
Florent Kermarrec	b02753ecfa	tools/comm_udp/litex_server: add --udp-scan args to scan network for available Etherbone/UDP devices. litex_server --udp --udp-scan --udp-ip=192.168.1.x --udp-port=1234 Etherbone scan on 192.168.1.x network: - 192.168.1.20 - 192.168.1.50	2020-11-26 13:33:20 +01:00
Florent Kermarrec	4a748a53b8	soc/interconnect/packet: add initial PacketFIFO. For now just ensures that we have a full packet in the FIFO before setting source.valid. It would be nice in the future to also be able to discard packets in the FIFO.	2020-11-26 11:27:42 +01:00
Florent Kermarrec	c3660379db	tools/remote/comm_udp: probe Etherbone server on open().	2020-11-26 09:06:52 +01:00
Florent Kermarrec	f390161baa	integration/soc/add_ethernet: don't add timing constraints with LiteEthPHYModel.	2020-11-26 09:06:06 +01:00
enjoy-digital	896d1ba988	Merge pull request #709 from daveshah1/oxide-build Add Yosys/nextpnr-nexus/oxide flow for CrossLink-NX	2020-11-25 19:21:11 +01:00
Florent Kermarrec	ad62e15d98	tools/litex_server: move PCIe specific bar renaming/enable to comm_pcie.	2020-11-25 16:25:31 +01:00
Florent Kermarrec	595c6738a3	tools/remote/etherbone: speed up encoding/decoding.	2020-11-25 16:08:12 +01:00
Florent Kermarrec	3d2574a488	tools/remote/comms: base CommXY on CSRBuilder to allow using Comms directly in python scripts. This way, user scripts can be use RemoteClient (communicating with the Server that has already been opened on the right interface) or directly use CommXY in the scripts. Using RemoteClient is more generic but can be slower (due to the Etherbone encoding between the client and server). On fixed configuration using CommXY directly can then be faster and also avoid manual opening of the server.	2020-11-25 15:05:28 +01:00
Florent Kermarrec	2c3687983c	tools/litex_server/client: cleanup.	2020-11-25 11:34:12 +01:00
Florent Kermarrec	fa9149720f	tools/remote/comm_udp: keep up to date with new encoding/decoding.	2020-11-25 11:33:44 +01:00
Florent Kermarrec	c003293b31	tools/remote/etherbone: simplify/speed up decoding.	2020-11-25 11:33:02 +01:00
David Shah	c0822bac1a	Add Yosys/nextpnr-nexus/oxide flow for CrossLink-NX Signed-off-by: David Shah <dave@ds0.me>	2020-11-25 09:44:51 +00:00
Florent Kermarrec	01e75addff	tools/remove/etherbone: simplify/speed up encoding.	2020-11-25 10:00:28 +01:00
Florent Kermarrec	2a1df9beeb	tools/remote/etherbone: replace merge_bytes with direct call to int.from_bytes.	2020-11-25 09:11:33 +01:00
Florent Kermarrec	4d5dca2d74	tools/remote/etherbone: replace split_bytes by direct call to int.to_bytes.	2020-11-25 09:07:58 +01:00
Florent Kermarrec	9b696373a2	tools/remove/etherbone: cosmetic cleanup, add assert for maximum burst size (255).	2020-11-25 08:53:11 +01:00
Robert Winkler	6684e7ae7a	symbiflow: restore add_false_path_constraint Restore the method to fix SymbiflowToolchain class API Signed-off-by: Robert Winkler <rwinkler@antmicro.com>	2020-11-24 15:34:32 +01:00
Florent Kermarrec	f918d0bf02	tools/remove: add 0x to hex debug prints.	2020-11-24 14:06:46 +01:00
Florent Kermarrec	cddf19df98	integration/soc/add_etherbone: expose buffer_depth.	2020-11-23 17:50:31 +01:00
enjoy-digital	a1bfa79092	Merge pull request #705 from betrusted-io/reset-docs correct the documentation for the ctrl reset register	2020-11-23 17:46:50 +01:00
bunnie	119062c068	Merge pull request #706 from betrusted-io/master add a hook for activating the GSR inside the STARTUPE2 block for spi_opi	2020-11-24 00:29:14 +08:00
bunnie	33f073a0a9	add a hook for activating the GSR inside the STARTUPE2 block for spi_opi	2020-11-24 00:27:18 +08:00
bunnie	4d7fe81a07	correct the documentation for the ctrl reset register	2020-11-24 00:19:05 +08:00
Alessandro Comodi	0431af729c	symbiflow: remove workarounds for symbiflow Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>	2020-11-23 10:33:11 +01:00
bunnie	8e39060d26	Merge pull request #701 from enjoy-digital/csr_eventmanager_cleanup interconnect/csr/EventManager: simpifly/cleanup code that documents C…	2020-11-20 03:24:09 +08:00
Florent Kermarrec	32989c17b6	soc: rename HAS_TIMESTAMP to WITH_BUILD_TIME.	2020-11-18 22:04:14 +01:00
enjoy-digital	1ac34bf5bf	Merge pull request #702 from antmicro/fix-disable-build-timestamp litex: soc: do not add the timestamp in the BIOS if it was disabled	2020-11-18 22:01:25 +01:00
Florent Kermarrec	9440975a1f	cores/ram: cosmetic cleanup.	2020-11-18 21:52:43 +01:00
Alessandro Comodi	3c0d41781f	litex: soc: do not add the timestamp in the BIOS if it was disabled Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>	2020-11-18 17:36:50 +01:00
Florent Kermarrec	444a605dea	build/xilinx: fix build with LITEX_ENV_VIVADO/LITEX_ENV_ISE set by user.	2020-11-18 15:40:15 +01:00
Florent Kermarrec	ee1ea9baab	bios/cmd/cmd_i2c: make results similar to Linux's i2cdetect.	2020-11-18 15:13:57 +01:00
Florent Kermarrec	470b6873ca	interconnect/csr/EventManager: simpifly/cleanup code that documents CSRs and always enable documentation. A read_only mode has been added to CSRStatus to allow enabling writes on pending register and get the written data used to clear events.	2020-11-18 13:06:55 +01:00
Florent Kermarrec	30b2f187f4	soc/integration/builder: add generate_doc parameter and --doc args to builder_args. This allows generating the documentation easily from target files with --doc.	2020-11-18 11:37:47 +01:00
enjoy-digital	b8b6fe2165	Merge pull request #699 from betrusted-io/document_events Create EventManager option for documented bits	2020-11-18 11:06:04 +01:00
Leon Schuermann	778afb45d2	Add SoC timer peripheral timer-uptime CLI parameter This allows enabling the uptime register in the timer core from the command line.	2020-11-17 23:29:11 +01:00
Jędrzej Boczar	3bd5d6cc0e	software/liblitedram: fix issues with command/write delays not being incremented.	2020-11-17 16:26:37 +01:00
bunnie	10256aa109	resolve xobs review comments	2020-11-17 05:10:16 +08:00
bunnie	377794748b	add API to turn on documentation in I2S block for interrupts	2020-11-17 04:55:46 +08:00
bunnie	3dc18efe70	make documented events optional	2020-11-15 23:18:46 +08:00
bunnie	5d6c851f32	try to fix issue with unnamed sources	2020-11-15 22:03:23 +08:00
bunnie	ea80e9ef32	improve documentation strings, try to handle unnamed events better	2020-11-15 21:50:26 +08:00
bunnie	6a0a896e96	improve documentation output	2020-11-15 17:07:33 +08:00
bunnie	6deb750d6e	Improve soc.svd output for eventmanager events Right now no data is created for which bit means what in the soc.svd file. Attempt to extend event manager finalization to use "fields" instead of bit positions, so that the SVD file can auto-generate the events correctly.	2020-11-15 16:33:14 +08:00
Florent Kermarrec	05f83ca978	tools/litex_term: minor cleanups (cosmetic).	2020-11-13 11:12:35 +01:00
Florent Kermarrec	5097b7ae5c	boards: keep up to date with litex-boards, remove pcie_screamer target.	2020-11-12 18:16:56 +01:00
Florent Kermarrec	103c7e90a5	integration/soc/LiteXSoC: add initial add_pcie integration method.	2020-11-12 16:07:40 +01:00
Florent Kermarrec	7a4b26d2ba	tools/litex_json2dts: fix missing {.	2020-11-12 14:45:46 +01:00
Florent Kermarrec	9c0f687922	build/generic_platform: use script filename as name when no Platform file.	2020-11-11 09:45:21 +01:00
Florent Kermarrec	275932f56c	gen/fhdl/verilog: improve clock domain error reporting.	2020-11-10 13:27:29 +01:00
Florent Kermarrec	2741fc2ba5	build/generic_programmer: add call method that raises OSError when failing and use it on specific programmers. This will avoid programming errors to be silently ignored and will raise the following error: OSError: Error occured during OpenOCD's call, please check: - OpenOCD installation. - access permissions. - hardware and cable.	2020-11-10 10:22:57 +01:00
Florent Kermarrec	a5bdfe3f4c	software/i2c: add i2c_scan command.	2020-11-10 09:47:28 +01:00
Florent Kermarrec	ce9f24748f	soc/cores/bitbang/I2C: use Tristate on SDL/SDA and only drive low (rely on I2C Pull-Ups for high).	2020-11-10 09:46:43 +01:00
Florent Kermarrec	221ea4c31a	tools/remote/comm_udp: revert try/except (was probably needed with CommUDP's max_length = 4).	2020-11-09 16:36:04 +01:00
Florent Kermarrec	5aa70d975c	tools/litex_server: revert CommUDP's max length to 1 (needs more testing).	2020-11-09 16:35:04 +01:00
Florent Kermarrec	1d04b1dd83	software/liblitesdcard: Operate the SDCard in 3.3V/High Speed. SDR50/Driver strength configuration is for 1.8V that is no longer supported (for simplicity).	2020-11-09 15:39:54 +01:00
Florent Kermarrec	b3a42d76ce	cores/cpu/microwatt: fix non irq variant, add standard+irq/"standard+gdhl+irq variants, move XICSSlave after CPU class.	2020-11-09 13:31:11 +01:00
enjoy-digital	3673f38d63	Merge pull request #653 from gsomlo/gls-dt-cpufreq RFC: json2dts: set CPU clock-frequency and SoC bus-frequency	2020-11-09 12:40:15 +01:00
enjoy-digital	ecaf69fe78	Merge pull request #688 from rprinz08/master Fix check for wrong named attributes	2020-11-09 11:22:08 +01:00
Florent Kermarrec	0627c01d89	soc/cores/spi_opi: move add_timing_constraints after __init__ to ease readability (first describe the logic then add the constraints).	2020-11-09 11:15:00 +01:00
enjoy-digital	5587ee5eea	Merge pull request #690 from betrusted-io/master Add arbitrary command (eg. write) capability to SPI DOPI	2020-11-09 11:12:13 +01:00
enjoy-digital	80883ef37e	Merge pull request #689 from DurandA/patch-7 libcompiler_rt: Remove duplicate mulsi3.o in Makefile	2020-11-09 11:08:29 +01:00
Florent Kermarrec	50a47f551e	soc/cores: create ram directory and move SPRAM/LRAM implementation to it. Will ease maintenance and future additions similarly to clock wrappers. Provide retro-compatibily layer for Up5kSPRAM that we could remove after next release.	2020-11-09 11:04:31 +01:00
Florent Kermarrec	ea8be6adcd	targets/kcu105: add missing AsyncResetSynchronizer import.	2020-11-09 10:40:36 +01:00
Florent Kermarrec	14e196ab5d	soc/cores/clock: create directory and split code in separate files to ease maintenance/adding new devices. clock.py was originally created/prototyped for 7-Series FPGAs, but has since been extended to almost all FPGA devices supported by LiteX making it large enough to justify the split. soc/cores/clock/__init__.py provides the retro-compatibily layer.	2020-11-09 10:33:12 +01:00
bunnie	036ea48a4d	update constraints to be in-line with litex methodology	2020-11-09 16:43:01 +08:00
davidcorrigan714	a6fd7b5d37	Lattice NX PLL Support	2020-11-08 20:34:10 -06:00
bunnie	b59711f89f	Merge remote-tracking branch 'origin/master'	2020-11-08 14:35:41 +08:00
Arnaud Durand	2c36098f45	libcompiler_rt: Remove duplicate mulsi3.o in Makefile	2020-11-08 03:21:39 +01:00
rprinz08	09ecd9abc9	Make commUDP more reliable in case of bad Ethernet connection	2020-11-07 11:32:50 +01:00
rprinz08	1c039389f2	Fix check for wrong named attributes	2020-11-07 11:13:51 +01:00
bunnie	d892c6f8f5	minor bug fixes in spi writing; USB-based flashing is not working	2020-11-07 03:57:46 +08:00
Florent Kermarrec	9359aa0688	tools/litex_server: revert CommUDP's max length to 4 now that https://github.com/enjoy-digital/liteeth/issues/52 is fixed).	2020-11-06 19:50:25 +01:00
Florent Kermarrec	9fe3a42072	software/liblitedra/sdram: minor cleanup, use identical delay after each delay increment.	2020-11-06 16:11:25 +01:00
Florent Kermarrec	d1ef64f9fd	tools/litex_server: revert CommUDP's max_length to 1. https://github.com/enjoy-digital/liteeth/issues/52 needs to be investigated before enabling _read_merger on UDP.	2020-11-06 13:01:56 +01:00
Florent Kermarrec	996be95725	tools/litex_sim: also add CPU's dbus to analyzer_signals (to demonstrate triggers in wiki).	2020-11-06 12:49:43 +01:00
bunnie	fc59bcd833	add facility for burst writing and fix pp4b command bug	2020-11-06 04:43:23 +08:00
Florent Kermarrec	61c009a393	revert get_data_mod change (Vexrisv SMP repo has been renamed to pythondata-cpu-vexriscv_smp).	2020-11-05 19:55:18 +01:00
Florent Kermarrec	c088cd5d22	cores/clock: only use locked on AsyncResetSynchronizer (already falling on reset) and add delay to reset to prevent interlocks with BIOS reboot command on Xilinx devices.	2020-11-05 19:43:11 +01:00
Florent Kermarrec	3e47a6e48b	get_data_mod: fix error message when module not found (pythondata modules are named only with "-" and not "_").	2020-11-05 15:58:32 +01:00
Florent Kermarrec	65f19b5c4a	integration/soc/add_sdram: add with_bist parameter to add LiteDRAM's BIST. sdram_bist command will then be available in the BIOS: litex> sdram_bist sdram_bist <burst_length> <random> litex> sdram_bist 256 0 Starting SDRAM BIST with burst_length=256 and random=0 WR-SPEED(MiB/s) RD-SPEED(MiB/s) TESTED(MiB) ERRORS 473 455 0 0 473 455 25 0 473 455 50 0 473 455 75 0 473 455 100 0 473 455 125 0 473 455 150 0 473 455 175 0 473 455 200 0 473 455 225 0 WR-SPEED(MiB/s) RD-SPEED(MiB/s) TESTED(MiB) ERRORS 473 455 250 0 473 455 275 0 473 455 300 0 473 455 325 0 473 455 350 0 473 455 375 0 473 455 400 0 473 455 425 0 473 455 450 0 473 455 475 0 WR-SPEED(MiB/s) RD-SPEED(MiB/s) TESTED(MiB) ERRORS 473 455 500 0 473 455 525 0 473 455 550 0 473 455 575 0 473 455 600 0 473 455 625 0 litex>	2020-11-05 13:41:37 +01:00
Florent Kermarrec	97b35a0771	software/liblitedram/bist: update generator/checker control to configure end CSR.	2020-11-05 13:39:48 +01:00
Florent Kermarrec	3dffdbf628	build/xilinx: add missing \n on error reporting.	2020-11-04 11:32:25 +01:00
Florent Kermarrec	897b2ea412	boards/targets: add rst signal to CRG to allow full reset of the SoC on reboot command.	2020-11-04 11:15:04 +01:00
Florent Kermarrec	ffc554dede	soc/integration/core: Connect SoCController's reset to CRG.rs do full reset of the SoC with reboot when signals are presents.	2020-11-04 10:58:16 +01:00
Florent Kermarrec	2c504783ca	bios/cmd/cmd_bios: add leds command to set leds value. Can be used as a first/simple/visual example to start interacting with the hardware from the CPU/BIOS.	2020-11-04 10:22:14 +01:00
Florent Kermarrec	db836e8e5d	build: add toolchain check before running build script and improve error reporting.	2020-11-04 09:42:18 +01:00
bunnie	6e806ce60c	refactor SPI DOPI interface to support arbitrary commands, not jsut reads lays the groundwork for doing page programming and sector erasing	2020-11-04 04:39:47 +08:00
Florent Kermarrec	f8cadc7b04	software/liblitesata/init: avoid reset when SATA PHY already ready (gateware is already hotplug capable).	2020-11-03 19:20:43 +01:00
enjoy-digital	b8d48385f6	Merge pull request #684 from sergachev/master cores/cpu/zynq7000: fix axi hp slave registration	2020-11-03 14:53:10 +01:00
Florent Kermarrec	99b103998d	software/liblitedram: expose sdram_bist_loop.	2020-11-03 13:03:45 +01:00
Florent Kermarrec	9d94bcdef7	boards/platforms: cleanup pass to uniformize comments/separators/orders.	2020-11-03 10:59:12 +01:00
Florent Kermarrec	b63e2d3b94	boards/platforms: remove pcie_screamer (we'll add it to litex-boards).	2020-11-03 10:53:26 +01:00
Ilia Sergachev	cc652dda77	cores/cpu/zynq7000: fix axi hp slave registration	2020-11-03 00:55:16 +01:00
Florent Kermarrec	081d883421	targets/kc705: revert sys_clk_freq to 150MHz.	2020-11-02 19:52:28 +01:00
Florent Kermarrec	c1c095fdd4	targets/nexys_video: add SATA support.	2020-11-02 19:46:11 +01:00
Florent Kermarrec	cc95d89a6f	boards/kc705: update sata integration.	2020-11-02 19:01:10 +01:00
Florent Kermarrec	d18157edde	software/bios/cmd_litesata: add sata_init/sata_write commmands.	2020-10-30 15:38:45 +01:00
Florent Kermarrec	cb1badb173	software/liblitesata: add sata_write and update #ifdefs.	2020-10-30 15:38:17 +01:00
Florent Kermarrec	638d28d8d4	soc/sata: fix typo in Mem2Sector DMA.	2020-10-30 15:37:20 +01:00
Florent Kermarrec	060bbf1d59	soc/sata: add write support with LiteSATAMem2SectorDMA.	2020-10-30 12:20:12 +01:00
Florent Kermarrec	c4a6fe7d96	soc/sata: update SATA integration (LiteSATABlock2MemDMA renamed to LiteSATASector2MemDMA).	2020-10-30 12:09:34 +01:00
Florent Kermarrec	7bcf8cb752	software/liblitedram: switch to uint32_t (as workaround for #322 ) and expose burst_length/random parameters to sdram_bist command.	2020-10-29 18:31:47 +01:00
Florent Kermarrec	07503d22ac	soc/software: move FatFs to libfatfs (avoid duplication in liblitesdcard/liblitesata).	2020-10-29 15:06:02 +01:00
Florent Kermarrec	b9ceed0f74	integration/soc/sata: fix sys_clk_freq vs sata_freq_clk check.	2020-10-29 10:50:10 +01:00
Florent Kermarrec	e7ad705359	integration/soc: add initial SATA integration with DMA read support.	2020-10-29 10:15:46 +01:00
bunnie	e8c39ec3d2	add generic command processing state machine facilitates page writes and sector erases first commit, debugging now commencing	2020-10-29 05:09:18 +08:00
Florent Kermarrec	9b123f7c9a	software/liblitesata: implement sata_init with new CSR registers.	2020-10-28 19:55:19 +01:00
Florent Kermarrec	1fca7b9a91	software/liblitesata/sata_read: handle errors.	2020-10-28 18:59:36 +01:00
Florent Kermarrec	2bb46b305b	software/liblitesata: fix warning, typo, add TODO.	2020-10-27 09:39:01 +01:00
Florent Kermarrec	c0ba03ef66	targets/kc705: add initial SATA support.	2020-10-26 15:14:40 +01:00
Florent Kermarrec	4127af36b5	soc/software: add initial minimal LiteSATA support (allow booting from SATA drive).	2020-10-26 15:13:56 +01:00
bunnie	37f2ebe675	add responder for type 0 cti, so that wb debug access works	2020-10-25 17:50:56 +08:00
Florent Kermarrec	c474272f53	soc/interconnect/stream: comment reset_less on payload since cause issue with LiteSATA, understand why.	2020-10-23 14:33:24 +02:00
Florent Kermarrec	e94876753d	soc/cores/icap: add back missing add_csr (was missing after adding add_reload method).	2020-10-23 08:00:43 +02:00
Florent Kermarrec	0dec446434	tools/litex_client: add utils to dump FPGA identifier and registers and expose it as litex_cli. Dump FPGA identifier: litex_cli --ident Dump FPGA registers: litex_cli --regs	2020-10-22 17:45:45 +02:00
Florent Kermarrec	30b226f895	soc/intergration/export: additional name override fix.	2020-10-22 08:55:14 +02:00
enjoy-digital	abdc8bb26e	Merge pull request #681 from Disasm/fix-svd-soc-name Fix SoC name in SVD generator	2020-10-22 08:53:32 +02:00
Florent Kermarrec	4eb634ba2d	soc/interconnect/csr: fix CSRAccess values check.	2020-10-21 21:43:08 +02:00
enjoy-digital	e7b33a9ea8	Merge pull request #680 from daveshah1/dave/radiant-portname-fix radiant: Use {} string for bus port names	2020-10-21 21:23:05 +02:00
enjoy-digital	7bbde6d05a	Merge pull request #679 from DurandA/patch-6 Add integer limits to stdint.h	2020-10-21 21:22:37 +02:00
Florent Kermarrec	c430587e91	soc/interconnect/stream/Shifter: add shift signal as optional parameter.	2020-10-21 15:52:53 +02:00
Vadim Kaushan	e4997295bd	Fix SoC name in SVD generator The name was overwritten with one of the CSR region names	2020-10-21 16:40:35 +03:00
David Shah	66eb38cf84	radiant: Escape bus port names Signed-off-by: David Shah <dave@ds0.me>	2020-10-21 14:05:33 +01:00
Florent Kermarrec	5a6b8f452d	soc/interconnect/stream: add Shifter. Useful to shift stream data (ex for SerDes alignment).	2020-10-21 12:47:55 +02:00
Florent Kermarrec	ad04365e20	soc/cores/code_8b10b: add K helper.	2020-10-21 09:49:38 +02:00
Florent Kermarrec	e91ec2ed83	soc/cores/code_8b10b: add StreamEncoder/Decoder (to be used with LiteX's streams). With improvements to handle backpressure on non-continous streams.	2020-10-21 09:29:21 +02:00
Arnaud Durand	eb26d09dbe	Add integer limits to stdint.h	2020-10-21 01:48:29 +02:00
Florent Kermarrec	918a0d95ba	platforms/targets: keep up to date with litex-boards.	2020-10-20 12:00:33 +02:00
enjoy-digital	84c358889d	Merge pull request #677 from madscientist159/master Add initial interrupt support for Microwatt in LiteX	2020-10-20 08:56:39 +02:00
enjoy-digital	72140f6df9	Merge pull request #674 from daveshah1/radiant-yosys-synth build/radiant: Allow synthesis with Yosys	2020-10-20 08:15:36 +02:00
Raptor Engineering Development Team	90d71ec247	Add initial interrupt support for Microwatt in LiteX There is a conflict between the LiteX way of doing things and the POWER way of handling interrupt tables. LiteX expects to be able to put a ROM at address 0 and load an application into RAM at a higher address; POWER is architected to jump to exception handlers at 0x100...0x1000. As a result of this, we have taken the approach of placing generic exception handler entry / exit routines into ROM, and reserving a single pointer in SRAM to determine the C ISR handler location. If no application is loaded, this pointer is set to the BIOS ROM ISR. When an application loads, before reenabling interrupts, it needs to set __rom_isr_address to the address of the application's ISR, otherwise the BIOS ROM ISR will continue to be used. Tested to operate with the built-in UART in IRQ mode, both in BIOS and in loaded RAM application.	2020-10-16 14:49:05 -05:00
Raptor Engineering Development Team	af82abb807	Allow SoCCore instances to set maximum interrupt number	2020-10-16 14:48:04 -05:00
Florent Kermarrec	288306c86a	software/liblitedram: add initial Build-In Self-Test software. To be used with LiteDRAM's BIST Generator/Checker, ex: from litedram.frontend.bist import LiteDRAMBISTGenerator, LiteDRAMBISTChecker self.submodules.sdram_generator = LiteDRAMBISTGenerator(self.sdram.crossbar.get_port()) self.add_csr("sdram_generator") self.submodules.sdram_checker = LiteDRAMBISTChecker(self.sdram.crossbar.get_port()) self.add_csr("sdram_checker")	2020-10-15 16:20:05 +02:00
Florent Kermarrec	c6f7f0210a	soc/cores/spi_opi: expose dq/dq_copi to allow constrainting them from design.	2020-10-14 10:31:29 +02:00
David Shah	15dc97476c	build/radiant: Allow synthesis with Yosys Signed-off-by: David Shah <dave@ds0.me>	2020-10-13 12:11:48 +01:00
Florent Kermarrec	f0abc185e1	targets/sim: update sdram (manual cmd_latency no longer needed).	2020-10-12 18:47:09 +02:00
Florent Kermarrec	bc68351475	software/liblitedram: use SDRAM_PHY_WRITE_LATENCY_CALIBRATION_CAPABLE flag.	2020-10-12 16:05:44 +02:00
Florent Kermarrec	c596135274	bios/cmd/cmd_litedram: add sdram_test command.	2020-10-12 13:52:15 +02:00
Florent Kermarrec	d4d4ca53b0	software/liblitedram/sdram.c: move activate/precharge to sdram_write_read_check_test_pattern, change second seed.	2020-10-12 13:00:44 +02:00
Florent Kermarrec	d1f04e67c5	software/liblitedram: use 2 cycles increment on write bitslip (for tCK steps).	2020-10-12 10:58:43 +02:00
Florent Kermarrec	3d5bc29dd1	software/liblitedram: add initial write latency calibration.	2020-10-09 20:04:16 +02:00
Florent Kermarrec	3518223c84	software/liblitedram: add functions to simplify read_leveling and do the test with 2 seeds. Doing the test with 2 seeds prevents the test to success if previous content in DRAM was still the expected one (ex after a sdram_cal command that succeded).	2020-10-09 15:50:44 +02:00
Florent Kermarrec	69177c9251	software/liblitesdram: add initial support for write leveling bitslip (configurable via bios commands).	2020-10-08 19:38:57 +02:00
Florent Kermarrec	004924a319	soc/interconnect/csr: expose re on CSRStatus (to allow triggering actions on CSRStatus writes).	2020-10-08 11:34:57 +02:00
Florent Kermarrec	b904aa7d18	libbase/memtest: simplify logs and add test size to memtest/memspeed banner.	2020-10-08 09:11:28 +02:00
Florent Kermarrec	e4fe0d9ef4	soc/cores/spi_flash: fix with_bitbang=False compilation.	2020-10-07 19:32:10 +02:00
Florent Kermarrec	375b6f2dc7	soc/cores/spi_flash: fix Dual mode compilation.	2020-10-07 19:28:13 +02:00
Florent Kermarrec	a2b71fde4a	soc: change default CSR bus data-width to 32. A CSR bus data-width of 32 has been validated on very various design and is now recommended. It provides better performance without impacting resource usage (even on iCE40).	2020-10-07 16:38:49 +02:00
Florent Kermarrec	4f30a5b8e5	libbase/memtest: add memtest_data_speed function that prints speed in B/KiB/MiB/GiB/s depending the value.	2020-10-07 13:01:14 +02:00
Florent Kermarrec	0a80e4c3d6	libbase/memtest: revert previous printf (the informations are provided below and this make it too verbose).	2020-10-07 12:42:58 +02:00
enjoy-digital	5e2a4efac6	Merge pull request #665 from fidergo-stephane-gourichon/more_precise_log More precise memory performance test.	2020-10-07 12:38:44 +02:00
enjoy-digital	83b4447f0e	Merge pull request #662 from fidergo-stephane-gourichon/dfu-util_with_-R Unconditionally ask dfu-util to "Issue USB Reset"	2020-10-07 12:37:53 +02:00
Florent Kermarrec	ad7671f811	soc/cores/icap/ICAP: add with_csr parameter and add_reload method to allow reloading the FPGA from the logic.	2020-10-06 17:38:39 +02:00
Gabriel Somlo	026d40ffab	bios: add command returning card-detect pin status	2020-10-05 14:32:06 -04:00
enjoy-digital	6916674ff6	Merge pull request #664 from antmicro/symbiflow_a100T build/xilinx/symbiflow: Add xc7a100tscg324-1 to supported devices	2020-10-05 19:25:18 +02:00
enjoy-digital	81257da9b4	Merge pull request #663 from fidergo-stephane-gourichon/fix_crash_on_minimal_cpu Fix SoC CPU crash on minimal variants on call to flush_cpu_dcache().	2020-10-05 19:24:43 +02:00
enjoy-digital	1a603b3fee	Merge pull request #654 from pepijndevos/gowin Build support for Gowin	2020-10-05 19:23:47 +02:00
Stephane Gourichon	f71275a3f1	Show speeds in bytes per second. Forcing megabytes per second for everyone does not make sense. Showing bytes per second allows to distinguish between low performance and a performance measurement bug. Anyway previous code claims speeds were in MiB/s, they were not, actually MB/s.	2020-10-05 18:46:05 +02:00
Stephane Gourichon	cbbbb3f468	Only display write speed if write test actually performed.	2020-10-05 18:43:45 +02:00
Stephane Gourichon	5b0ced00b5	Confirm parameters in log.	2020-10-05 17:58:44 +02:00
Stephane Gourichon	48638f936b	Fix SoC CPU crash on minimal variants on call to flush_cpu_dcache(). Generated soc.h says for example but code tester for CONFIG_CPU_VARIANT_MIN not MINIMAL. Attempted to run instruction unknown to this CPU, most likely cause of hang.	2020-10-05 17:16:35 +02:00
Stephane Gourichon	e47f84ea79	Unconditionally ask dfu-util to "Issue USB Reset signalling once we're finished". Some host machines need it. If issuing -R always does not cause any trouble, then do it.	2020-10-05 17:16:10 +02:00
enjoy-digital	aebe08d841	Merge pull request #661 from yetifrisstlama/fix_stream2wishbone Fix stream2wishbone	2020-10-05 17:16:04 +02:00
Robert Winkler	ff4afda305	build/xilinx/symbiflow: Add xc7a100tscg324-1 to supported devices Signed-off-by: Robert Winkler <rwinkler@antmicro.com>	2020-10-05 17:02:51 +02:00
Michael Betz	acdfae202b	Stream2Wishbone: drive sink.ready line	2020-10-04 18:19:39 -07:00
Michael Betz	6e3e979a0b	serial2tcp.c json error handling, respect rx.ready	2020-10-04 18:17:28 -07:00
Shawn Anastasio	fa82d97aa5	cores/cpu: Add riscv-unknown-linux-gnu triple, fix riscv-linux-gnu Add riscv-unknown-linux-gnu to known triples, and fix the existing riscv-linux-gnu by removing the incorrect -gcc suffix from the triple.	2020-10-02 18:31:48 -05:00
Shawn Anastasio	6fd48ca2ce	software: Use -fno-stack-protector This allows riscv*-gnu-linux toolchains to be used to build LiteX software. Without this, references to undefined stack guard symbols get generated and linking fails.	2020-10-02 13:42:16 -05:00
Gabriel Somlo	c77da3a8bc	RFC: json2dts: set CPU clock-frequency and SoC bus-frequency FIXME: timebase-frequency isn't to be used as the raw CPU clock, so on vexriscv we might want to re-evaluate also setting that to the `CONFIG_CLOCK_FREQUENCY`. Decide whether to keep the SoC's `bus-frequency` cell, or whether to go with the CPU's `clock-frequency` only.	2020-10-01 06:59:45 -04:00
Florent Kermarrec	ba2ff8cf71	tools/litex_sim: update get_sdram_phy_settings (rd/wrcmdphase no longer exposed as PhySettings).	2020-10-01 11:27:33 +02:00
Florent Kermarrec	2b62802961	tools/litex_sim: minor review cleanup.	2020-10-01 10:36:37 +02:00
Florent Kermarrec	23e319732c	tools/litex_server: minor review cleanup.	2020-10-01 10:35:11 +02:00
Vamsi Vytla	e8c0360fa5	tools/{litex_sim, litex_server}.py: Minor clean-up (#657 ) Enable litex_server debug and create function to add for litex_sim args.	2020-10-01 10:32:44 +02:00
Pepijn de Vos	890ccaf4bd	support writing bitstream to flash	2020-10-01 08:39:32 +02:00
Florent Kermarrec	29bff18e69	software/liblitedram: add SDRAM CL/CWL printf to BIOS.	2020-09-30 19:00:12 +02:00
Florent Kermarrec	f476b32ada	software/liblitedram: rename SDRAM_TEST_SIZE to MEMTEST_DATA_SIZE (since used in benchs to force test size).	2020-09-30 18:34:48 +02:00
Florent Kermarrec	f7e49cc23a	software/liblitedram: add SDRAM_TEST_SIZE (2MiB as previously defined in memtest).	2020-09-30 18:02:07 +02:00
Florent Kermarrec	fdf7981f40	software/libbase/memtest: remove size restriction and don't execute memspeed.	2020-09-30 17:49:51 +02:00
Florent Kermarrec	ed21c983cb	Merge branch 'master' of http://github.com/enjoy-digital/litex	2020-09-30 17:29:04 +02:00
Florent Kermarrec	c154f1cbb2	software/liblitedram: add support for dynamic read/write phase and add command to BIOS to force them.	2020-09-30 17:09:19 +02:00
enjoy-digital	6f136f9faa	Merge pull request #655 from betrusted-io/svd_memregion add memory regions to soc.svd	2020-09-30 11:43:14 +02:00
Konrad Beckmann	39d144626b	Fix build issue where sdram_leveling is not found `4f76656` rewrote how sdram_leveling() was called, leading to linking problems for targets with sdram but with write leveling disabled, e.g. ulx3s.	2020-09-29 22:49:41 +02:00
Florent Kermarrec	a9234a8793	software/liblitedram: allow cmd_delay adjustment even when enforced by the phy.	2020-09-29 16:02:21 +02:00
Pepijn de Vos	eca5a25e27	add dummy attr_translate	2020-09-29 15:55:07 +02:00
Florent Kermarrec	4f76656018	software/liblitedram: simplify vtc/hardware/software controls. - move vtc control to sdram_software_control_on/off. - remove sdram_calibration (duplicate of sdram_leveling). - be sure to call sdram_software_control_on/off before all litedram bios commands.	2020-09-29 15:40:26 +02:00
Pepijn de Vos	dd2b1f21f0	typo and dead code	2020-09-29 15:24:36 +02:00
Florent Kermarrec	e4555df095	tools/litex_server/pcie: enable pcie device if not already enabledd. Avoid having to do it manually or through a driver.	2020-09-29 13:38:19 +02:00
Florent Kermarrec	bc5873f78c	tools/litex_server/pcie: allow passing pcie bar as reported by lspci. ex: $lspci [...] 06:00.0 RF controller: Xilinx Corporation Device 7022 (rev 01) sudo litex_server --pcie --pcie-bar=06:00.0	2020-09-29 13:10:05 +02:00
Florent Kermarrec	6d07f01f5b	tools/litex_client/RemoteClient: allow use without local csr.csv file. In some case, we just want to access MMAP manually without having the csr.csv file: wb = RemoteClient() wb.open() wb.read(0x40000000) wb.close()	2020-09-29 13:01:44 +02:00
bunnie	7b42992383	add <memoryRegions> outer tag to series of <memoryRegion> for future proofing	2020-09-29 14:11:55 +08:00
bunnie	4a94bb78f6	add memory regions to soc.svd svd2rust does not recognize memory regions, but we'd like to make an access crate for Rust that does. This patch adds memory regions to soc.svd using the "vendorExtensions" tag, as specified in https://www.keil.com/pack/doc/cmsis/SVD/html/svd_Format_pg.html The vendorExtensions is added as a block after the Peripherals level, and has a format like this: ```xml <memoryRegion> <name>SRAM</name> <baseAddress>0x10000000</baseAddress> <size>0x00020000</size> </memoryRegion> <memoryRegion> <name>VEXRISCV_DEBUG</name> <baseAddress>0xEFFF0000</baseAddress> <size>0x00000100</size> </memoryRegion> <memoryRegion> <name>CSR</name> <baseAddress>0xF0000000</baseAddress> <size>0x00040000</size> </memoryRegion> ```	2020-09-29 01:30:09 +08:00
Pepijn de Vos	95564b7475	change name->devicename, working bios	2020-09-28 17:49:41 +02:00
Pepijn de Vos	c0fa4fd1f4	initial build support for Gowin	2020-09-28 13:12:07 +02:00
Florent Kermarrec	a1c023b900	software/bios/cmds/cmd_litedram: enable sdram_software_control before sdram_mode_register_write.	2020-09-24 14:58:42 +02:00
Florent Kermarrec	90a2b80b6a	software/liblitedram/sdram_write_leveling_rst_cmd_delay: fix printf location (do it before taps is decremented).	2020-09-24 13:54:08 +02:00
Florent Kermarrec	7617a82fe6	targets/kcu105: create specific cd_eth for ethernet.	2020-09-24 10:27:48 +02:00
Florent Kermarrec	a3c616028e	software/liblitedram/sdram: fix cmd_delays -> dat_delays.	2020-09-23 19:43:28 +02:00
Gabriel Somlo	8e7596d330	liblitesdcard/sdcard.c: ensure effective sdcard clock is <= requested With the way the clock divider is currently calculated, it is possible for the effective sdcard clock to end up higher than the requested `clk_freq` value. Calculate the divider starting with the `CONFIG_CLOCK_FREQUENCY/clk_freq` ratio which is then rounded up to the nearest power-of-two, ensuring that the resulting, effective clock frequency is <= to the requested frequency. Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>	2020-09-22 15:15:50 -04:00
Florent Kermarrec	ac32b92e9f	targets/kcu105: add etherbone.	2020-09-22 18:31:06 +02:00
Florent Kermarrec	a601415bf0	software/liblitedram: add functions/commands to reset and force cmd/dat write leveling delays. Useful to investigate/speed-up new board support.	2020-09-21 19:53:34 +02:00
Florent Kermarrec	a39660fa99	software/liblitedram/sdram.c: fix typo.	2020-09-17 18:19:12 +02:00
Florent Kermarrec	a0d66dd60e	software/liblitesdcard/sdcard: move busy_wait in sdcard_wait_cmd_done (fixes sdcardboot being stuck since code refactoring) and reduce busy_wait value.	2020-09-17 10:52:21 +02:00
Florent Kermarrec	de4fc14cf9	software/bios/cmds/cmd_litsdcard: make sure all commands generate a report.	2020-09-17 10:41:49 +02:00
Florent Kermarrec	6c4abe2185	software/bios/cmds/cmd_liteeth: make sure all commands generate a report and improve it.	2020-09-17 09:10:58 +02:00
Florent Kermarrec	7d6818ab07	software/bios/command: avoid too much groups, reorganize a bit.	2020-09-17 09:07:36 +02:00
Florent Kermarrec	88ef2a330b	software/bios/cmds/cmd_litedram: rename spdread command to sdram_spd.	2020-09-16 22:48:32 +02:00
Florent Kermarrec	3380de4adf	software/bios/cmds/cmd_i2c: rename commands to i2c_xy.	2020-09-16 22:45:19 +02:00
Florent Kermarrec	79009f762d	software/bios/cmds/cmd_spiflash: rename commands to flash_xy.	2020-09-16 22:44:47 +02:00
Florent Kermarrec	cb55d7119c	software/bios/cmds/cmd_liteeth: rename commands to mdio_xy.	2020-09-16 22:39:56 +02:00
Florent Kermarrec	d5162a2a2b	software/bios/cmds: use _handler suffix on all cmds functions.	2020-09-16 22:37:46 +02:00
Florent Kermarrec	d4018b7ccf	software/bios/cmds/cmd_litesdcard: rename commands to sdcard_xy.	2020-09-16 22:32:27 +02:00
Florent Kermarrec	400bf13400	bios/cmds/cmd_mem: rename commands to mem_xy.	2020-09-16 22:25:33 +02:00
Florent Kermarrec	21cc7df2fa	software/bios/cmds/cmd_mem: remove debug cmds that shouldn't have been merged.	2020-09-16 21:18:37 +02:00
Florent Kermarrec	74fb086322	software/liblitedram: rename functions/commands and expose mode register write function to user.	2020-09-16 20:01:39 +02:00
Florent Kermarrec	dc087f948a	software/liblitedram/sdram: keep sdrwlon/sdrwloff private.	2020-09-16 11:56:39 +02:00
Florent Kermarrec	9c2975e8b4	software/liblitedram/sdram: remove low level manual controls of the DFI interface. This was too low level and unused.	2020-09-16 11:22:15 +02:00
Florent Kermarrec	8a9d17c768	software/liblitedram/sdram.c: move sdrwl_delays definition to write_leveling section and add #ifdef on reinitialization.	2020-09-16 11:03:10 +02:00
Gabriel Somlo	9729d053eb	software/memtest: use "unsigned long" to represent pointers	2020-09-15 14:46:18 -04:00
Gabriel Somlo	6c838cedcd	libbase/sim_debug: wrap markers variables within appropriate #ifdef	2020-09-15 14:46:18 -04:00
Gabriel Somlo	e2719d4d71	fixup for `e28e808c` - don't define variable in .h file	2020-09-15 14:46:18 -04:00
Florent Kermarrec	a69273db50	boards/targets/arty: switch SDRAM to NETWORKING mode (interface_type no longer supported).	2020-09-15 19:59:20 +02:00
Florent Kermarrec	404104be21	software/liblitedram/sdram.c: increase ddrphy reset time.	2020-09-15 19:58:17 +02:00
Florent Kermarrec	cfe6f56572	software/liblitedram/sdram.c: improve reporting. - ident sub-reports. - avoid displaying software/hardware swich if set to previous value.	2020-09-15 19:41:20 +02:00
Florent Kermarrec	e63a40370e	software/libbase/memtest: improve reporting. - indent sub-reports. - report speed in MiB/s.	2020-09-15 19:37:09 +02:00
Florent Kermarrec	e28e808c24	software/liblitedram: allow forced write leveling delays, improve delay printf when failing.	2020-09-15 19:34:09 +02:00
Florent Kermarrec	1d63d66a09	software/libbase/memtest: improve memtest_data progress. Add base/current tested address and current/total tested size. ex: Memtest at 0x40000000... Write: 0x40000000-0x40200000 (2/2MiB) Read: 0x40000000-0x40200000 (2/2MiB)	2020-09-14 11:51:16 +02:00
Florent Kermarrec	b39fea4ecb	software/liblitedram/write_level_scan: reset write delay even if not succeeding.	2020-09-07 18:53:31 +02:00
Florent Kermarrec	658f712001	software/liblitedram/write_level: add support for manual command delay. Required on some configurations where automatic cmd/clk scan still has troubles.	2020-09-07 18:47:18 +02:00
enjoy-digital	5ee074f422	Merge pull request #642 from gsomlo/gls-sdcard-blk-vs-sec RFC: bios/sdcard: use (512 byte) blocks as the smallest addressable data unit	2020-09-07 17:41:50 +02:00
Jędrzej Boczar	7c3fbf1d06	sim: improve tracing reset value and behaviour with sim_debug=False	2020-09-07 15:29:02 +02:00
Jędrzej Boczar	3fd567c4c9	sim: additional simulation tracing and debugging tools	2020-09-07 15:28:26 +02:00
Florent Kermarrec	c247814ed4	software/liblitedram/sdram.c: add ifdef on MPR functions.	2020-09-05 11:37:07 +02:00
Florent Kermarrec	f7b6dd05ae	cores/clock: add initial Xilinx Ultrascale Plus PLL/MMCM/IDELAYCTRL support.	2020-09-03 18:58:10 +02:00
Florent Kermarrec	6d8a367abe	software/liblitedram: add separators, expose read_level.	2020-09-03 17:47:32 +02:00
Florent Kermarrec	ae152e28a7	software/liblitedram: add sdrmpr functions.	2020-09-03 15:25:04 +02:00
Florent Kermarrec	3e083958b0	software/liblitedram: move calibration to sdrcal function.	2020-09-03 14:55:37 +02:00
Florent Kermarrec	31afe55821	tools/litex_sim: avoid build/run duplication.	2020-09-03 09:21:37 +02:00
Florent Kermarrec	e8f21cd958	build/sim/verilator: cleanup SimVerilatorToolchain, return to initial path after build/run.	2020-09-03 09:21:14 +02:00
Gabriel Somlo	d86d20671e	bios/sdcard: use (512 byte) blocks as the smallest addressable data unit In liblitesdcard/sdcard.c, replace s/sector/block/ as the 512 byte sized unit of data transfer to/from the sdcard. In bios/cmds/cmd_litesdcard.c, do NOT multiply block numbers by 512, allowing any "block" (a.k.a. "sector") on the sdcard to be addressed for testing. Before this patch, user-input "block numbers" were multiplied by 512 and passed into sdcard_[read\|write]() as "sector numbers", with the sdcard logic internally treating these as 512-byte sized addressable units on the card. This resulted in only every 512'th 512-byte sized "sector" being accessible from the bios command line. Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>	2020-09-02 12:07:38 -04:00
Florent Kermarrec	222e3f4003	tools/remote/comm_uart: fix offset on write bursts.	2020-09-02 17:23:56 +02:00
Florent Kermarrec	6250d4fa41	integration/builder: fix bios_option typo.	2020-09-01 15:39:43 +02:00
Florent Kermarrec	267f3e30df	integration/soc/add_spi_flash: update to use new API.	2020-09-01 12:27:43 +02:00
enjoy-digital	ee6dd5cd20	Merge pull request #644 from Xiretza/sdram-csr-map integration/soc: use csr.add() instead of add_csr()	2020-09-01 12:08:33 +02:00
Florent Kermarrec	2538b2c300	soc/cores/clock: add with_reset parameter to create_clkout on iCE40PLL/ECP5PLL (similar to others PLLs). Avoid instantiating the AsyncResetSynchronizer manually.	2020-09-01 11:50:08 +02:00
Florent Kermarrec	f07efcb97f	integration/builder: change bios_options to list and add assert for supported options.	2020-09-01 11:48:52 +02:00
Xiretza	05e8ecf2e2	integration/soc: use csr.add() instead of add_csr() add_csr() is defined by SoCCore, so won't work for any instances of LiteXSoC that aren't also SoCCores. Also, use use_loc_if_exists=True so SoCCore.csr_map can be used without double allocation errors.	2020-08-31 19:09:49 +02:00
Florent Kermarrec	043cfc5df7	soc/interconnect/axi/AXIStreamInterface: manage user as param.	2020-08-31 09:59:05 +02:00
Greg Davill	632cfcc257	soc/cores/cpu/serv: fix crt0 .data initialize	2020-08-30 10:52:16 +09:30
Greg Davill	dcd99cc999	soc/cores/cpu/minerva: fix crt0 .data initialize	2020-08-30 10:52:04 +09:30
Florent Kermarrec	bda54b1177	software/liblitedram: reset ddrphy before initialization if rst CSR present (added on 7-series).	2020-08-28 17:59:24 +02:00
Florent Kermarrec	b44ca6d61a	soc/core/uart: add fixed burst support to UARTBone. Allows speeding-up consecutives accesses on the same address. This is currently used by LiteDRAM bench to speed-up the logging of the BIOS over the crossover UART, but could be useful for other purposes.	2020-08-28 03:49:50 +02:00
Florent Kermarrec	1fb48d308e	soc/cores/uart: add clock domain support to UARTBone. In some cases, we want to run UARTBone in a specific clock domain. For example in LiteDRAM bench, UARTBone is controlling the SoC and the main PLL generating the sys_clk is reconfigured dynamically, so we want to run UARTBone in a specific (and fixed) clock domain.	2020-08-28 03:49:45 +02:00
Florent Kermarrec	566fbd60c3	cores/uart: minor cleanups on RS232PHYRX/TX.	2020-08-28 03:49:38 +02:00
Florent Kermarrec	587e09e3d6	software/liblitesdcard: increase sdcard_wait_cmd_done/sdcard_wait_data_done busy_wait. Required after the command refactoring, will need to be adjusted.	2020-08-27 12:52:11 +02:00
Florent Kermarrec	4025257d8d	software/liblitesdcard/sdcard: cleanup, update copyrights. - improve indent. - remove do/while in block functions (block's length/count only need to be configured once). - update copyrights.	2020-08-27 12:36:35 +02:00
Florent Kermarrec	334635a97f	software/liblitesdcard: remove wait for DMA Reader to complete, fix ifdef on SDCARD_CMD23_SUPPORT. The FIFO after the DMA has been reduced and is no longer able to store an entire block, so the DMA will not complete if write is not released.	2020-08-26 12:47:50 +02:00
Florent Kermarrec	4ac0ed49e1	software/liblitesdcard/bios: add sdfreq command to configure SDCard clock frequency.	2020-08-26 12:43:09 +02:00
Florent Kermarrec	3897acb9e4	lattice/nx: update copyrights.	2020-08-24 22:32:49 +02:00
Florent Kermarrec	4364043b08	integration/soc: expose integrated_rom_mode to allow ROM to be writable (useful for BIOS/ROM development where content is reloaded over UARTBone/Etherbone).	2020-08-24 18:19:03 +02:00
Piense	885c339d97	soc/cores: add initial NX-LRAM support.	2020-08-24 16:24:34 +02:00
Piense	cf13833e3c	cores/clock: add initial NX-OSCA support.	2020-08-24 16:23:27 +02:00
Piense	e441bd60fa	build/lattice: add initial Radiant support for NX FPGA family (Crosslink-NX/Certus-NX).	2020-08-24 16:23:22 +02:00
enjoy-digital	8a44464a45	Merge pull request #640 from antmicro/mor1kx_dt litex_json2dts: Add support for mor1kx	2020-08-24 14:26:11 +02:00
Florent Kermarrec	4f1c32abdc	targets/de0nano: set sys2x_ps to 180° for sdram_rate=1:2.	2020-08-24 09:30:38 +02:00
Florent Kermarrec	d16051ff90	boards/ulx3s: keep up to date with litex-boards.	2020-08-24 09:08:30 +02:00
Florent Kermarrec	d826c60658	soc/cores/clock/ECP5PLL: specificy CLKOS3_F/CPHASE and -1 on cphase to match Clarity Designer values.	2020-08-24 09:04:33 +02:00
Florent Kermarrec	9e37b16ec0	soc/interconnect/axi/AXILite2CSR: add register parameter for genericity. Not yet used, but simplify SoC integration.	2020-08-24 09:03:04 +02:00
Mateusz Holenko	4dab1eb0c8	litex_json2dts: Add support for mor1kx	2020-08-24 08:02:16 +02:00
Florent Kermarrec	42d8fc226a	Merge branch 'master' of https://github.com/enjoy-digital/litex	2020-08-23 15:42:39 +02:00
Florent Kermarrec	b8371ef480	tools: add SPDX License identifier to header and specify file is part of LiteX.	2020-08-23 15:37:16 +02:00
Florent Kermarrec	93d906f9d1	soc: add SPDX License identifier and specify file is part of LiteX.	2020-08-23 15:33:01 +02:00
Florent Kermarrec	e52ffd2da0	gen: add specify SPDX License identifier and specify file is part of Migen and has been modified/adapted for LiteX.	2020-08-23 15:19:46 +02:00
Florent Kermarrec	70610b2332	build: add SPDX License identifier and specify file is part of LiteX.	2020-08-23 15:14:45 +02:00
Florent Kermarrec	6ee882d1ec	platforms/targets: add SPDX License identifier to header and specify file is part of LiteX.	2020-08-23 15:08:15 +02:00
enjoy-digital	ee0e240242	Merge pull request #631 from gsomlo/gls-abc9-fixup build/lattice/trellis: make "-abc9" an optional argument	2020-08-22 20:06:57 +02:00
Florent Kermarrec	9950e75654	build/io: fix InferedSDRIO (thanks @mtdudek).	2020-08-22 19:49:34 +02:00
enjoy-digital	bae871a884	Merge pull request #632 from gsomlo/gls-sdcard-refactor refactor sdcard (bios) software	2020-08-22 19:44:59 +02:00
enjoy-digital	3206dba911	Merge pull request #636 from Xiretza/minerva-cli-filetype Fix call to generation of minerva output file	2020-08-22 19:41:07 +02:00
enjoy-digital	8bc5dd7c8c	Merge pull request #635 from Xiretza/collections-abc-deprecation Fix DeprecationWarning for collections.abc	2020-08-22 19:40:44 +02:00
enjoy-digital	7984436248	Merge pull request #634 from betrusted-io/spi_opi_timing_only add a pipe register to relax an async_default timing path	2020-08-22 19:39:51 +02:00
Xiretza	e3bb3a9488	Fix call to generation of minerva output file With nmigen/nmigen#a7b8ced, cli.py no longer defaults to generating verilog code, so -t/--type has to be specified explicitly. $ pytest test/test_targets.py -k test_variants_minerva [...] cli.py: error: specify file type explicitly with -t	2020-08-22 14:54:40 +02:00
Xiretza	fcc7058bfc	Fix DeprecationWarning for collections.abc DeprecationWarning: Using or importing the ABCs from 'collections' instead of from 'collections.abc' is deprecated since Python 3.3, and in 3.9 it will stop working	2020-08-22 13:39:30 +02:00
bunnie	d783e86ff6	add a pipe register to relax an async_default timing path there is an async reset signal going to a FIFO that can't be false_path'd because its timing is important to making sure that the burst FIFO is reset to zero when a miss happens in the burst cache. Unfortunately as designs get full, the routability of this signal becomes difficult and drives up the compile time and reduces quality of results. There is enough time in the design to insert a single pipe stage to alleviate the timing somewhat. This commit adds that register.	2020-08-20 04:14:10 +08:00
Gabriel Somlo	e0b2b8153f	liblitesdcard/sdcard: read sdcard response only when needed Instead of reading the 128 byte sdcard response after each operation, read it only during debugging and/or when it's necessary (to retrieve the relative card address, rca). We no longer need a global sdcard_response array, and refactor the various retrieval and reporting functions to contain a local buffer for that purpose, only if/when necessary. Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>	2020-08-17 18:45:24 -04:00
Gabriel Somlo	a47b2de5fe	sdcard: refactor command functions Factor out common portion of command functions. Also use appropriate unsigned int width (e.g., uint16_t) for arguments. Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>	2020-08-17 18:45:24 -04:00
Gabriel Somlo	bfd6b3c3f4	liblitesdcard/sdcard: cosmetic fixes (indentation, #ifdef, etc.)	2020-08-17 18:45:24 -04:00
Gabriel Somlo	37ebcd3be7	factor out busy_wait_us()	2020-08-17 18:45:24 -04:00
Gabriel Somlo	c4710b371a	build/lattice/trellis: make "-abc9" an optional argument Fix up earlier commit (#6c298cb7) and make the '-abc9' optional argument to yosys' synth_ecp5 actually optional (and off by default) in LiteX's trellis build infrastructure. Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>	2020-08-15 16:49:08 -04:00
Florent Kermarrec	35929c0f8a	soc/integration/csr_bridge: use registered version only when SDRAM is present. Seems to be a good compromise for now.	2020-08-14 15:29:49 +02:00
Florent Kermarrec	e4f5dd987e	interconnect/wishbone/Wishbone2CSR: add registered version and use it as default.	2020-08-14 00:47:05 +02:00
Florent Kermarrec	b344196aba	build/lattice/diamond: use diamondc instead of pnmainc (avoid having to set environment variables). http://www.latticesemi.com/en/Support/AnswerDatabase/5/5/2/5522	2020-08-14 00:10:56 +02:00
Dolu1990	f730f1d7ba	cores/cpu/vexriscv_smp fix argument parsing	2020-08-13 12:52:05 +02:00
Florent Kermarrec	0e480dd662	bios/main/sdram: fix speed reporting (Mbps/pin not MHz).	2020-08-11 22:13:14 +02:00
Gabriel Somlo	ba34c85284	cores/dma, liblitesdcard/sdcard: use 64 bits for dma base address Make the DMA base address register 64-bit wide, to cover situations in which the physical memory being accessed is above the 4GB limit (e.g., on 64-bit systems with more than 4GB of provisioned physical memory). Also update DMA reader/writer setup call sites in the bios (currently only used by litesdcard). Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>	2020-08-10 14:09:25 -04:00
Florent Kermarrec	4cf28a0107	software/bios: display SDRAM databits and freq.	2020-08-07 19:49:02 +02:00
Florent Kermarrec	6f69679d21	cpu/vexriscv_smp: more coherent_dma to __init__ instead of add_memory_buses. LiteX is creating the SoC.dma_bus just after the CPU is declared, so declaring it in add_memory_buses was preventing it. It's also more coherent to move it to __init__ since not related to the memory_buses.	2020-08-07 14:47:21 +02:00
Florent Kermarrec	b3531cd2a8	cores/cpu: add external cpu_type. Allows fully pluggable CPUs where cpu_type is set to "external" and cpu_cls provided externally.	2020-08-07 11:16:00 +02:00
Florent Kermarrec	b9d3aab59d	targets: use platform.request_all on LedChaser.	2020-08-06 20:02:17 +02:00
Florent Kermarrec	14c9166429	build/generic_platform: add request_all method.	2020-08-06 20:00:07 +02:00
Florent Kermarrec	57335b9971	cores/cpu/zynq7000: simplify using new loose parameter of Platform.request. And avoid the try/except that can mask others errors.	2020-08-06 19:44:46 +02:00
enjoy-digital	4867f2b324	Merge pull request #624 from trabucayre/emio_zynq soc/cores/cpu/zynq7000: add enet0, enet0_mdio, sdio, sdio_cd and sdio_wp only when configured in EMIO mode	2020-08-06 19:34:03 +02:00
Florent Kermarrec	48d63f2362	build/generic_plaform: add loose parameter to return None when not available/existing. Similar to loose parameter already present on Platform.lookup_request.	2020-08-06 19:33:04 +02:00
enjoy-digital	81df7b7036	Merge pull request #625 from scanakci/blackparrot_litex Blackparrot human name change (IMA), minor transducer fix	2020-08-06 18:50:39 +02:00
Florent Kermarrec	188e6f573a	integration/soc/add_etherbone: pass phy to ethcore not self.ethphy. Similar in most of the cases but added restrictions.	2020-08-06 18:23:04 +02:00
sadullah	2457859b2d	update BlackParrot transducer	2020-08-06 12:21:38 -04:00
sadullah	d2dabcef9a	Blackparrot human name update	2020-08-06 12:21:38 -04:00
Gwenhael Goavec-Merou	87c26a30fd	soc/cores/cpu/zynq7000: add enet0, enet0_mdio, sdio, sdio_cd and sdio_wp only when configured in EMIO mode	2020-08-06 16:45:39 +02:00
Dolu1990	07a8e696ce	cpu/vexriscv_smp Add --with-coherent-dma	2020-08-06 13:33:11 +02:00
Florent Kermarrec	9a4c5aa1ef	integration/soc/add_sdram: update rules to connect main bus to dram. Requires connection when CPU does not have memory buses of when CPU has memory buses but no DMA bus.	2020-08-05 18:01:12 +02:00
Florent Kermarrec	a1644510bf	cpu/vexriscv_smp: fix args_read.	2020-08-05 17:59:30 +02:00
Florent Kermarrec	896b68cd6b	cpu/vexriscv_smp: cleanup, fix coherent_dma connection.	2020-08-05 17:25:13 +02:00
enjoy-digital	342f359e1c	Merge pull request #622 from antmicro/fix_connectors arty: Change USB-uart and I2S Pmod configuration	2020-08-05 12:30:34 +02:00
Florent Kermarrec	3b293612a8	soc/interconnect/axi: minor cleanups.	2020-08-05 12:11:28 +02:00
Florent Kermarrec	303d6cca7e	interconnect/stream: set default AsyncFIFO depth to None and add depth parameter to ClockDomainCrossing.	2020-08-05 12:11:12 +02:00
Pawel Sagan	de9ea19cc7	arty: Change USB-uart and I2S Pmod configuration This makes it compatible with the Arty A7 expansion board by Antmicro (https://github.com/antmicro/arty-expansion-board).	2020-08-05 11:38:51 +02:00
Florent Kermarrec	00629c45b0	interconnect/csr: add CSR registers ordering support. The original CSR registers ordering (big: MSB on lower addresses) is not convenient when the SoC is interfaced with a real OS (for example as a PCIe add-on board or with a CPU running Linux). With this, the original ordering is kept as default (big), but it can now be switched to little to avoid software workarounds in drivers and should probably be in the future the default for PCIe/Linux SoCs.	2020-08-05 08:57:19 +02:00
Florent Kermarrec	ee7a7f4693	soc/interconnect/csr: improve ident.	2020-08-05 07:59:35 +02:00
Florent Kermarrec	b1008b0164	integration/soc: add expection on decoder when full address space is mapped.	2020-08-04 19:56:26 +02:00
Florent Kermarrec	b831dc8c55	wishbone: revert default adr_width to 30.	2020-08-04 19:55:46 +02:00
Florent Kermarrec	abc49964ea	tools/litex_json2dts: add missing copyrights.	2020-08-04 16:38:02 +02:00
Florent Kermarrec	aed0dcee4c	setup: add litex_json2dts to console_scripts.	2020-08-04 16:07:53 +02:00
enjoy-digital	b64209b38b	Merge pull request #620 from antmicro/add_litex_json2dts Add Linux DT generation script	2020-08-04 16:04:57 +02:00
Florent Kermarrec	0ca99b798f	build/sim/config: add default_clk/default_clk_freq parameters for retro-compatibility with previous API.	2020-08-04 15:49:53 +02:00
Florent Kermarrec	696ea468b8	build/sim: use json_object_get_int64 instead of json_object_get_uint64. json_object_get_uint64 does not seem supported with old json-c versions.	2020-08-04 15:49:26 +02:00
enjoy-digital	382c1a3a44	Merge pull request #619 from antmicro/jboc/sim-clocker Allow to define multiple simulation clocks	2020-08-04 15:38:28 +02:00
Mateusz Holenko	fafa844aa7	json2dts: Add Linux DT generation script	2020-08-04 15:13:17 +02:00
Jędrzej Boczar	f778ff09dc	build/sim: improve timebase calculation (strict checks) and update modules	2020-08-04 14:00:58 +02:00
Florent Kermarrec	e0f131a317	cores/uart: add txempty/rxfull CSRs. Useful in some use cases, like flushing tx.	2020-08-04 13:50:46 +02:00
Florent Kermarrec	2a3e39b10e	tools/litex_server: enable read_merger with CommUDP. Limited to 4 (current size of the buffer in liteeth.frontend.etherbone).	2020-08-04 10:55:51 +02:00
Florent Kermarrec	a5d0a340c3	test: specify wishbone adr_width on AXI(Lite)<-->Wishbone tests and remove debug traces.	2020-08-04 09:39:23 +02:00
Gabriel Somlo	561331ed97	debug: make CI print offending values	2020-08-03 16:59:39 -04:00
Gabriel Somlo	df3428be07	liblitesdcard/sdcard: (temporarily) slow down SDCARD_CLK_FREQ to 25MHz Rocket's DMA slave interface (and/or internal routing) currently appears unable to route DMA writes from LiteSDCard at frequencies above 25MHz (as tested on nexys4ddr, with Rocket, at 75MHz main system clock frequency). Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>	2020-08-03 16:14:11 -04:00
Gabriel Somlo	2d9dc8f939	cores/cpu/rocket: expose slave port for DMA Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>	2020-08-03 16:14:11 -04:00
Gabriel Somlo	d8161e5a86	integration/soc: make DMA slave region cover (at least) the lower 4GB Assuming we currently support a 32-bit (4GB) physical address space, ensure that the dma_bus slave covers the entire range, covering any possible layout of the LiteX SoC memory map (e.g., rocket has MMIO in a wide range of registers located below 2GB, and DRAM starting at the 2GB mark, needing DMA accesses to be routed appropriately for the entire 4GB physical address range). Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>	2020-08-03 16:14:11 -04:00
Gabriel Somlo	70eae5cbf9	interconnect/wishbone: increase WB address width to 31 This is needed to support memory regions up to 4GB in size (currently limited to 2GB, or 0x8000_0000). FIXME: CI complains about assertions re. axi_lite.address_width in relationship to len(wishbone.adr) and wishbone_adr_shift, which seems to be a problem on the 32bit (vexriscv?) CPU used for CI, but seems to work fine on Rocket. Signed-off-by: Gabriel Somlo <gsomlo@gmail.com> foo	2020-08-03 16:11:26 -04:00
Gabriel Somlo	b8c9da81ea	soc/interconnect/axi: add Wishbone2AXI converter	2020-08-03 12:50:00 -04:00
Florent Kermarrec	2ec4604c41	cores/gpio: add support for Record on GPIOOut, GPIOIn and GPIOInOut.	2020-08-03 18:47:17 +02:00
Jędrzej Boczar	c1ae7e596c	build/sim: allow for arbitrary clocks generation using clockers	2020-08-03 17:06:38 +02:00
Jędrzej Boczar	38054874ac	build/sim: use a real timebase in the simulation	2020-08-03 15:21:24 +02:00
enjoy-digital	5e53e5d73a	Merge pull request #615 from pepijndevos/openfpgaloader Add openFPGALoader programmer	2020-08-03 14:01:50 +02:00
Pepijn de Vos	79ca4d9640	remove debugging	2020-08-01 11:07:04 +02:00
Pepijn de Vos	f6e20700d4	add openFPGAloader programmer	2020-08-01 11:05:09 +02:00
Florent Kermarrec	eab0726cc8	cpu/vexriscv/core: use variant name as human_name. Allow it to be shown in the BIOS and help support.	2020-07-31 08:59:53 +02:00
Florent Kermarrec	e0a763e534	cpu/vexriscv/system.h: provide empty flush_cpu_i/dcache functions for variants with no i/d cache.	2020-07-31 08:58:30 +02:00
Florent Kermarrec	3ff1bcaf05	cpu/zynq7000: set csr map to 0x00000000.	2020-07-30 21:37:25 +02:00
enjoy-digital	c0253e3f77	Merge pull request #611 from antmicro/jboc/axi-lite soc/interconnect/axi: add AXILite -> AXI converter	2020-07-30 14:22:21 +02:00
Florent Kermarrec	cc8440549f	tools/litex_server/read_merger: review/simplify a bit.	2020-07-30 13:58:40 +02:00
enjoy-digital	4f382ccf55	Merge pull request #605 from cklarhorst/feature-uart-read-merger Merge sequential reads for the UART litex_server backend	2020-07-30 13:56:48 +02:00
Jędrzej Boczar	e78d950a31	soc/interconnect/axi: add AXILite -> AXI converter	2020-07-30 13:50:34 +02:00
Florent Kermarrec	a942e358b9	cpu/blackparrot: minor cleanups, add sim variant (since use different flist).	2020-07-30 12:10:32 +02:00
Dolu1990	023ab15ec1	soc/cores/cpu/vexriscv_smp enable dynamic litedram datawidth	2020-07-29 12:40:16 +02:00
Dolu1990	e5cd5d5466	Merge branch 'master' into vexriscv_smp	2020-07-29 11:14:09 +02:00
Florent Kermarrec	1938ce363d	integration/soc/add_sdram: allow the CPU to add the direct memory buses when adding the sdram. This is useful for CPUs elaborated at buildtime to use sdram's native data width on the CPU memory ports.	2020-07-29 11:10:05 +02:00
Florent Kermarrec	6576416b8e	cores/cpu/rocket: add use_memory_bus parameter to easily disable direct memory bus for testing. Useful for current tests with LiteSDCard using DMA and that requires the DMA to be connnected to the DMA bus of Rocket when the direct memory bus is used.	2020-07-29 09:35:15 +02:00
Dolu1990	789a70e7c8	Merge branch 'master' into vexriscv_smp	2020-07-28 19:11:54 +02:00
Dolu1990	d284dfbea9	soc/cores/cpu/vexriscv_smp config update	2020-07-28 19:07:02 +02:00
Florent Kermarrec	fe38e12b21	cpu/vexriscv_smp: move litedram import, remove os.path import.	2020-07-28 18:10:32 +02:00
Dolu1990	aa57c7a25e	soc/cores/cpu/vexriscv_smp integration	2020-07-28 16:20:16 +02:00

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3595 commits