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1111 commits

Author SHA1 Message Date
Florent Kermarrec
2418df9f2b pr243: Add @tweakoz copyrights. 2021-07-27 12:21:23 +02:00
enjoy-digital
369d2cf49d
Merge pull request #243 from tweakoz/master 
add FPGA Boards (Digilent CMOD A7, Digilent Nexys 4, Micronova Mercury2)
 2021-07-27 12:17:04 +02:00
Florent Kermarrec
10bfd50e22 targets/1bitsquared_icebreaker: Revert to 128KB SPRAM. 2021-07-27 12:03:39 +02:00
enjoy-digital
4d20cfe5cd
Merge pull request #245 from racerxdl/feat/MuselabIceSugarPro 
muselab_icesugar_pro: initial support
 2021-07-23 14:34:57 +02:00
Lucas Teske
5852dbb88f
muselab_icesugar_pro: initial support 2021-07-22 11:26:27 -03:00
Florent Kermarrec
a3f479837c digilent_arty: Allow exposing raw PMOD IOs (for tests with MicroPython). 2021-07-21 13:50:12 +02:00
Florent Kermarrec
a455713e0c kosagi_fomu: Handle bios_flash_offset in flash function and make DFU flash offset explicit. 2021-07-21 11:41:35 +02:00
enjoy-digital
fbcecee1f8
Merge pull request #242 from tcal-x/fix-basys3-rst 
Basys3: Invert reset button, so that the board is reset when btnc is pushed.
 2021-07-20 19:47:53 +02:00
Florent Kermarrec
8c8e163eee trenz_tec0117: Add SDCard (SPI and SD mode), move SPI Flash to 0x00000000 and use default l2_cache_min_data_width. 2021-07-20 17:25:51 +02:00
Michael Mayers
75cadf845f add FPGA Boards 
1.  Digilent CMOD A7
      https://reference.digilentinc.com/programmable-logic/cmod-a7/start

2. Digilent Nexys 4
      https://reference.digilentinc.com/programmable-logic/nexys-4/start

3. MicroNova Mercury 2
      https://www.micro-nova.com/mercury-2
 2021-07-17 22:03:17 -06:00
Tim Callahan
5da2bdefb7 Invert reset button, so that board is reset when btn is pushed. 
Signed-off-by: Tim Callahan <tcal@google.com>
 2021-07-16 13:08:18 -07:00
enjoy-digital
4b48f15265
Merge pull request #236 from JosephBushagour/jbushagour_with_led_chaser 
Add with_led_chaser argument to constructor of boards using LedChaser submodule.
 2021-07-16 14:41:05 +02:00
Florent Kermarrec
a74b6e83f7 trenz_tec0117: Add clock constraints. 2021-07-15 11:07:05 +02:00
Florent Kermarrec
6648b2f907 targets/trenz_tec0117: Switch SPI Flash to QSPI mode. 2021-07-15 09:15:34 +02:00
Florent Kermarrec
c369f4bb7f trenz_tec0117: Get BIOS XiP from SPI Flash working, remove CPU variant force since can now fit default VexRiscv config. 2021-07-14 12:49:03 +02:00
Florent Kermarrec
132feaf3e8 trenz_tec0117: Prepare for 1:2 SDRAM rate (Not yet working at 1:2 but one step closer...). 2021-07-14 10:43:26 +02:00
Florent Kermarrec
ba8321a3ab trenz_tec0117: Use new DDROutput to generate SDRAM Clk. 2021-07-14 10:02:58 +02:00
Florent Kermarrec
94b985ac56 trenz_tec0117: Use new integrated reset from GW1NPLL. 2021-07-14 09:55:00 +02:00
Florent Kermarrec
6e31d12fa9 trenz_tec0117: Avoid forcing CPU type (only force to lite variant when VexRiscv is selected=default). 2021-07-13 19:39:53 +02:00
Joey Bushagour
1920db3535 Add with_led_chaser argument to constructor of boards using LedChaser submodule. 2021-07-06 16:39:37 -05:00
Florent Kermarrec
8c1e6c6a02 decklink_quad_hdmi_recorder: Remove WIP (SoC + DDR3 now working) and add build/use instructions. 2021-07-02 15:54:57 +02:00
Florent Kermarrec
2dff854b7a decklink_quad_hdmi_recorder: Enable second DDR3 module. 2021-07-02 15:52:12 +02:00
Florent Kermarrec
a02855d105 decklink_quad_hdmi_recorder: Increase sys_clk to 200MHz. 2021-07-02 15:07:13 +02:00
Florent Kermarrec
b18f6a2c7f decklink_quad_hdmi_recorder: Enable DRAM modules 0 and 1, fix pre placement constraints. 2021-07-02 14:32:53 +02:00
Florent Kermarrec
548f77c79c decklink_quad_hdmi_recorder: Add INTERNAL_VREF constraint on DRAM banks. 2021-07-02 14:32:14 +02:00
Florent Kermarrec
7442639a5e targets/digilent_arty: Add default value for CRG's with_mapped_flash. 
Otherwise break retro-compat on external design importing CRG without passing this new parameter.
 2021-07-02 09:33:06 +02:00
Florent Kermarrec
1b65bad4c2 decklink_quad_hdmi: Add Clk IOs, use clk200 as primary clk and add JTAGBone. 2021-07-01 20:00:35 +02:00
Florent Kermarrec
18b2758e4e decklink_quad_hdmi_recorder: Add other DDR3 SDRAM modules building but untested. 2021-06-30 11:50:42 +02:00
Florent Kermarrec
e65308ee13 decklink_quad_hdmi_recorder: Add DDR3 SDRAM (only first module), building but untested. 2021-06-30 09:40:08 +02:00
Florent Kermarrec
84cb5d797d decklink_intensity_pro_4k: Add WIP. 2021-06-30 09:06:00 +02:00
Sylvain Munaut
7cb155fb9c icebreaker: Minor fix to usb (add PMOD2 position and fix typo) 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2021-06-27 16:00:09 +02:00
Florent Kermarrec
591377cf95 decklink: Pinout fixes on itensity_pro_4k and quad_hdm_recorder. 2021-06-25 11:19:05 +02:00
Florent Kermarrec
ebfb4fad57 Add initial Decklink Intensity Pro 4K support (with documented PCIe / Untested). 2021-06-24 19:55:40 +02:00
Florent Kermarrec
5f8560bf69 Add initial Decklink Quad HDMI Recorder support (with documented PCIe/HDMI In). 
LitePCIe Gen3 X4 enumerating correctly.
 2021-06-24 19:48:31 +02:00
Florent Kermarrec
8ec1435e65 targets/decklink_mini_4k: Fix typos. 2021-06-24 19:13:18 +02:00
Sylvain Munaut
87cd56d187 targets: Add new 1bitsquared_icebreaker_bitsy target 
Most basic SoC ever but ... it runs

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2021-06-21 22:11:53 +02:00
Sylvain Munaut
2ebcb4a726 platforms: Add new 1bitsquared_icebreaker_bitsy platform 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2021-06-21 16:17:54 +02:00
Sylvain Munaut
4c758dc0e3 platforms/1bitsquared_icebreaker: Fix wrong URL in header 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2021-06-21 16:16:47 +02:00
Sylvain Munaut
675616493c platform/1bitsquare_icebreaker: Add possible USB pinouts 
The pin outs come from LUNA :
https://github.com/greatscottgadgets/luna/blob/main/luna/gateware/platform/icebreaker.py#L94

and are some commonly used ones from other projects / pmods.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2021-06-20 22:25:49 +02:00
Florent Kermarrec
caac75c7db trenz_max1000: Review/Cleanup. 2021-06-16 18:04:55 +02:00
Antti Lukats
8ef138eaa0 added MAX1000 board 2021-06-16 17:55:06 +02:00
Florent Kermarrec
fa045e6fa4 enclustra_mercury_kx2: Comment user_led2/3 (Conflicting with DRAM pins). 2021-06-16 11:54:52 +02:00
David Sawatzke
fe7b3968e4 Fix colorlight 5a 75b v6.1 flash pins 
As with the other versions, the clk pin can't be directly driven
 2021-06-06 02:59:48 +02:00
enjoy-digital
588b430a0c
Merge pull request #217 from hansfbaier/master 
QMTech EP4CE15: Add daughterboard support, small DECA addition
 2021-05-25 10:15:26 +02:00
Florent Kermarrec
df10fc54ad muselab_icesugar/trenz_cyc1000: +x. 2021-05-25 08:46:33 +02:00
Florent Kermarrec
1c4825e7c4 basys3: Review/Simplify and fix build. 2021-05-25 08:44:26 +02:00
enjoy-digital
25867c4dcb
Merge pull request #218 from helium729/master 
Add digilent basys3 board support
 2021-05-23 19:46:58 +02:00
Jakub Cabal
dd5a4bdc92 CYC1000: Add initial support of CYC1000 board 2021-05-22 21:17:27 +02:00
Florent Kermarrec
bf123db20b icebreaker/fomu: Update flashing and disconnect reset from SoC (will need proper support in iCE40PLL). 2021-05-20 09:14:54 +02:00
helium729
ce5b2a74a1 add digilent basys3 support 2021-05-17 16:39:16 +08:00
Hans Baier
f01e0c02c9 qmtech ep4ce15: Add daughterboard support, add spiflash 2021-05-15 13:16:43 +07:00
enjoy-digital
c010b9a335
Merge pull request #215 from hansfbaier/qmtech-xc7a35t 
Qmtech xc7a35t
 2021-05-10 08:31:08 +02:00
Hans Baier
ddaab5317e qmtech_xc7a35 set symbiflow_device, needed when using symbiflow 2021-05-08 18:01:01 +07:00
Hans Baier
df447ddc87 QMTech XC7A35T: fix argument parser description 2021-05-08 08:49:07 +07:00
Hans Baier
f2b51b0233 icesugar: map the usb port 2021-05-08 07:34:10 +07:00
Florent Kermarrec
5027b270fd __init__.py: Add muselab to vendors. 2021-05-07 09:10:51 +02:00
Florent Kermarrec
e99272cb07 muselab_icesugar: Modify comments a bit. 2021-05-07 08:57:34 +02:00
enjoy-digital
5ae130661f
Merge pull request #213 from hansfbaier/icesugar 
muselab_icesugar: first basic version which boots
 2021-05-07 08:50:50 +02:00
enjoy-digital
2c2a9db3cc
Merge pull request #212 from hansfbaier/qmtech-xc7a35t 
add QMTECH XC7A35T core board + daughter board
 2021-05-07 08:32:16 +02:00
enjoy-digital
9e86c094c9
Merge pull request #211 from Acathla-fr/master 
Lattice iCE40 UltraPlus Breakout board (iCE40UP5K-B-EVN) added
 2021-05-07 08:30:01 +02:00
Hans Baier
c2e0f6026e muselab_icesugar: first basic version that boots 2021-05-07 11:50:28 +07:00
Florent Kermarrec
3bb84b0071 Add initial Blackmagic Decklink Mini 4K support (with UART, DDR3, PCIe, Video Out). 
Mini Monitor 4K and Mini Recorder 4K are almost the same hardware with just changes on
the Video In/Out. For now tests have been done on the Mini Monitor 4K, but the aim  is
support both boards in the same platform/target in the future, thus the mini_4k naming.

These boards could be used as affordable Artix7 dev boards for LiteX, to run Linux with
LiteX (512MB of RAM + a Video Framebuffer) or to create custom systems like a fast software
defined signal generator/recorder directly from a PC over PCIe, custom HDMI/SDI video
cards, etc... lots of possibilities :)
 2021-05-06 09:47:01 +02:00
Hans Baier
eec1078736 add QMTECH XC7A35T core board + daughter board 2021-05-06 05:50:48 +07:00
Fabien
213d100860 Lattice iCE40 UltraPlus Breakout board (iCE40UP5K-B-EVN) added 2021-05-04 12:19:21 +02:00
enjoy-digital
026c623e17
Merge pull request #207 from hplp/master 
Minor fixes for AU280 [work in progress]
 2021-05-03 10:20:34 +02:00
Florent Kermarrec
2c5bf95f70 targets/trenz_tec0117: Switch to new GW1NPLL. 2021-04-30 11:32:24 +02:00
Sergiu Mosanu
4f45462b95 Merge branch 'master' of https://github.com/litex-hub/litex-boards 2021-04-29 15:41:03 -04:00
Florent Kermarrec
9686db0ed3 targets: Update names in build descriptions. 2021-04-29 11:56:52 +02:00
Florent Kermarrec
6117b98049 siglent_sds1104xe: Avoid disabling hardware interface with BIOS ethernet reset. 2021-04-29 11:52:41 +02:00
Florent Kermarrec
c28a161392 siglent_sds1104xe: Expose ethphy (to allow correct .dts generation). 2021-04-29 11:02:13 +02:00
Florent Kermarrec
7d651a9a17 siglent_sds1104xe: Switch to VideoVGAPHY and adjust timings. 2021-04-29 10:41:19 +02:00
Florent Kermarrec
cfbcb8538d siglent_sds1104xe: Use custom 800x480 video timings. 2021-04-28 16:59:09 +02:00
enjoy-digital
84e65d2113
Merge pull request #204 from hansfbaier/master 
terasic_sockit: fix: make video clock also optional as video terminal is optional
 2021-04-28 09:42:13 +02:00
enjoy-digital
be6d08aff1
Merge pull request #205 from antmicro/jboc/lpddr4-tb-eth-delay 
antmicro_lpddr4_test_board: fix ethernet rx delay issue
 2021-04-28 09:41:11 +02:00
Sergiu Mosanu
8ad91d9eb3 fix cmdltncy, with_led 2021-04-27 17:30:56 -04:00
Florent Kermarrec
f7ee3fa454 sds1104xe: Framebuffer fixes. 2021-04-27 19:32:03 +02:00
Hans Baier
694608688d terasic_sockit: fix: make video clock also optional as video terminal is optional 2021-04-27 08:52:11 +07:00
Florent Kermarrec
5bfeb999e4 targets/digilent_arty/flash: Simplify, use Quad mode and sys_clk (fast enough ~5MB/s). 2021-04-26 16:30:35 +02:00
Karol Gugala
2854df5028 Arty: move spiflash PHY do 4x faster clk domain 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2021-04-26 12:52:36 +02:00
Karol Gugala
84ae2b2bbc arty: add option to use litespi QSPI controller 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2021-04-26 12:52:30 +02:00
Jędrzej Boczar
2d2a10621f antmicro_lpddr4_test_board: fix ethernet rx delay issue 2021-04-23 15:25:47 +02:00
Florent Kermarrec
228a9650d4 sqrl_acorn: Add flashing/reload support when used with PCIe, fix JTAG flash. 2021-04-21 17:00:40 +02:00
Florent Kermarrec
443b954c0c platforms/xilinx_kcu105: Add Pmod0/1 connectors. 2021-04-19 15:11:43 +02:00
Shinken Sanada
d2eabd112d Add E-Elements Ego1 initial board support. 2021-04-12 08:20:46 +02:00
Shinken Sanada
cd3d4c826e Add Trenz te0725 initial board support. 2021-04-12 08:16:45 +02:00
Sergiu Mosanu
5519c931f8 xilinx_alveo_u280: Fix DDR4 (tested with 8 modules on C0 and C1). 2021-04-12 08:07:16 +02:00
enjoy-digital
d830ef8393
Merge pull request #200 from rdolbeau/wukong_ethfix_fb 
Qmtech Wukong: updates
 2021-04-11 14:44:25 +02:00
enjoy-digital
2a7d8c5330
Merge pull request #199 from zyp/ignore_missing_deps 
boards/compat: Skip targets with unsatisfied dependencies.
 2021-04-11 14:43:01 +02:00
Vegard Storheil Eriksen
bad8821c2d platforms/ecpix5: Add ULPI signals. 2021-04-11 11:12:56 +02:00
Romain Dolbeau
d5318dcb03 Qmtech Wukong: updates 
fix ethernet clock (it's a GMII), add FB support over the HDMI connector (hdmi clock set from the resolution)
 2021-04-10 16:26:25 +02:00
Vegard Storheil Eriksen
2e204285de boards/compat: Skip targets with unsatisfied dependencies. 
Fixes #194
 2021-04-10 11:41:13 +02:00
Florent Kermarrec
03accabc25 lpddr4_test_board: Add antmicro vendor prefix. 2021-03-31 09:48:23 +02:00
Jędrzej Boczar
a834985e00 Add target for LPDDR4 Test Board 2021-03-30 14:50:02 +02:00
Florent Kermarrec
d5ce1901d8 targets/digilent_nexys_video: Add specific Video PLL to give more flexibility on supported Video Timings. 2021-03-30 10:17:50 +02:00
Florent Kermarrec
9417044584 targets: Minor cleanup, make sure all targets can be built with default settings. 2021-03-29 16:22:39 +02:00
Florent Kermarrec
1ca8ef97a1 targets/add_sdram: Specific size only when useful (ie for targets with > 1GB of RAM). 2021-03-29 16:03:19 +02:00
Florent Kermarrec
ba01776432 targets/add_sdram: Simplify call by removing useless arguments. 
- main_ram mem_map is now directly used by add_sdram when origin is None.
- max_sdram_size/min_l2_data_width are no longer exposed as targets arguments this can
still be used enforced directly in the few cases it is useful.
 2021-03-29 15:28:31 +02:00
Florent Kermarrec
58286ce29e minispartan6: Change video resolution to 640x480, framebuffer working with Linux-on-LiteX-Vexriscv. 2021-03-29 14:36:34 +02:00
Florent Kermarrec
09700b28d0 ulx3s: Change video resolution to 640x480, framebuffer working with Linux-on-LiteX-Vexriscv. 2021-03-29 11:35:55 +02:00
Romain Dolbeau
73ce7f9df1 ztex213 fix; propagate variant from targets to platform 2021-03-27 11:04:51 +01:00
Florent Kermarrec
7c537748a0 colorlight_i5: Remove PRBS (too specific to application). 
If useful for several boards, this should probably be provided directly by LiteX.
 2021-03-27 09:31:48 +01:00
Florent Kermarrec
7737575b88 terasic_deca: Remove --integrated-ram-size parameter (--integrated-main-ram-size provides the same functionnality). 2021-03-27 08:58:49 +01:00
Florent Kermarrec
f714e1210a terasic_deca: Remove enforced CPU variant/debug: --cpu-variant=imac or --cpu-variant=imac+debug can be used for this. 
The default CPU/Variant is defined in LiteX, enforcing the variant on the target
prevent usage of the other CPUs and also complicate maintenance.
 2021-03-27 08:56:46 +01:00
Florent Kermarrec
a48def1352 rhsresearchllc_litefury: Remove since already supported by ./acorn.py --variant=cle-101. 2021-03-26 23:54:56 +01:00
Florent Kermarrec
4329a69128 sqrl_acorn_cle_215: Rename to sqrl_acorn and add support for all variants (CLE-101, 215 and 215+). 2021-03-26 23:52:36 +01:00
Florent Kermarrec
87df45e625 siglent_sds1104xe: Allow build without Etherbone. 2021-03-26 23:25:42 +01:00
Florent Kermarrec
c6ced293d4 targets/siglent_sds1104xe: Integrate VideoTerminal/VideoFrameBuffer. 2021-03-26 22:55:25 +01:00
Florent Kermarrec
52ded1c9aa terasic_deca: Fix default_clk_name. 2021-03-26 22:43:40 +01:00
Florent Kermarrec
b54eed0859 terasic_sockit: Review/Cleanup for consistency with other boards. 2021-03-26 22:39:19 +01:00
Florent Kermarrec
53a767c85c terasic_deca: Review/Cleanup for consistency with other boards. 2021-03-26 22:12:13 +01:00
enjoy-digital
be4965ca78
Merge pull request #192 from hansfbaier/deca_fixes 
terasic_deca: fix cable name, ulpi, names, add gpio_serial
 2021-03-26 21:52:31 +01:00
Florent Kermarrec
9fea5a7fc6 targets/digilent_nexys_video: Cleanup/Simplify #191. 2021-03-26 21:49:22 +01:00
Alessandro Comodi
df58639916 nexys_video: choose VADJ value with arguments 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-26 14:50:05 +01:00
Hans Baier
8c0ddd140b terasic_deca: fix cable name, ulpi, names, add gpio_serial 2021-03-26 10:46:37 +07:00
Florent Kermarrec
e2de69496a targets/lattice_crossing: Avoid direct override of SoCCore.mem_map (break default SoCore.mem_map with updated imports). 2021-03-25 22:41:26 +01:00
Florent Kermarrec
b284fe47c3 targets/terasic_sockit: Fix compilation. 2021-03-25 19:35:44 +01:00
Florent Kermarrec
22f167dde4 targets/sqrl_acorn_cle_215: Add missing false path constraints. 2021-03-25 18:19:20 +01:00
Florent Kermarrec
7d130d6981 targets/pcie: Cleanup. 2021-03-25 17:47:06 +01:00
Florent Kermarrec
333fb362ca Move import Compat directly to litex_boards.__init__.py and simplify. 2021-03-25 16:47:47 +01:00
Florent Kermarrec
062b899e29 platforms/targets: Add mode Vendor prefixes. 2021-03-25 16:19:11 +01:00
Florent Kermarrec
7633eae360 targets/colorlight_i5: Remove l2-size args (already provided by soc_core_args. 2021-03-25 14:44:52 +01:00
Florent Kermarrec
5253a3c43e test/ci: Fix/Update. 2021-03-25 14:21:13 +01:00
Florent Kermarrec
9a45c49918 targets/versa_ecp5: Also add Vendor prefix. 2021-03-25 14:13:32 +01:00
Florent Kermarrec
8a3cacae32 boards: Add Vendor prefix to platforms/targets name when useful and when multiple boards from the same vendor. (With Retro-Compat on the imports). 2021-03-25 14:11:17 +01:00
enjoy-digital
219067ed3a
Merge pull request #190 from kazkojima/colorlight_i5-video 
colorlight_i5: Integrate Video Terminal and Video Framebuffer with ne…
 2021-03-25 10:28:52 +01:00
Florent Kermarrec
47bdf5f759 targets: Use new CSR automatic allocation (self.add_csr will still work but is no longer required). 2021-03-25 10:11:24 +01:00
Florent Kermarrec
b3786c5e52 fomu/icebreaker: Update Up5KSPRAM import (litex.soc.cores.up5kspram deprecated, still supported for now but triggers a compat notice). 2021-03-24 17:22:55 +01:00
Florent Kermarrec
5995769b46 targets: Switch to soc_core_args/soc_core_argdict (instead of soc_sdram that is now deprecated, but still supported for now). 2021-03-24 17:22:51 +01:00
Kaz Kojima
cb4e00c3f2 colorlight_i5: Integrate Video Terminal and Video Framebuffer with new VideoECP5HDMIPHY. 2021-03-20 07:56:59 +09:00
Gabriel Somlo
7a1fe7a6bc nexys4ddr: add pmod connectors, and optional sdcard on pmodd 2021-03-19 12:33:11 -04:00
enjoy-digital
6d32c76aa2
Merge pull request #188 from hansfbaier/848-deca-video-bloat 
fix #848: allow ram initialization in bitstream to enable block ram
 2021-03-19 11:11:05 +01:00
Florent Kermarrec
ddd46205aa ulx3s: Integrate Video Terminal and Video Framebuffer with new VideoECP5HDMIPHY. 2021-03-18 15:06:35 +01:00
Florent Kermarrec
4330769add minispartan6: Integrate Video Terminal and Video Framebuffer with new VideoS6HDMIPHY. 2021-03-18 14:10:42 +01:00
Hans Baier
b7d86df01d fix #848: allow ram initialization in bitstream to enable block ram inference for ROM/RAM with initial value 2021-03-18 08:41:19 +07:00
Hans Baier
8b69ee57a6 arrow_sockit: get video terminal working on VGA 2021-03-16 12:31:41 +07:00
Florent Kermarrec
75f7120ff9 targets/Ultrascale: Fix build since idelay's reset is now handled by the PLL (with_reset=True). 2021-03-11 10:00:06 +01:00
Florent Kermarrec
8d3aaa8ea9 targets/nexys_video: Revert clk100 to avoid breaking Linux-on-LiteX-VexRiscv (we'll remove it when the switch the simple framebuffer will be done). 2021-03-11 09:48:26 +01:00
Florent Kermarrec
0e2d9a571e alveo_u280: Fix copyrights (avoid too much cascading on Platforms/Targets) and generate reset on idelay clock domain (similarly to recent change on others Ultrascale+ boards). 2021-03-10 11:23:27 +01:00
enjoy-digital
f4ea3fb0d9
Merge pull request #168 from hplp/alveo_u280 
Alveo U280 board
 2021-03-10 11:16:32 +01:00
enjoy-digital
7c6876df42
Merge pull request #186 from gatecat/mipi_pins_x 
crosslink_nx_vip: Remove constraints for hard MIPI pins
 2021-03-10 11:13:49 +01:00
enjoy-digital
61f44739d7
Merge pull request #185 from stffrdhrn/arty-jtagbone 
arty: Add an option to enable jtagbone
 2021-03-10 11:12:20 +01:00
Florent Kermarrec
47faaf20d5 deca: Integrate Video Terminal (untested, resource issue). 2021-03-09 15:02:30 +01:00
Florent Kermarrec
8fb80053f7 targets/versa_ecp5: Fix LiteEthPHYRMGII tx/rx delays (need to be updated due to a bug fix in the ECP5RGMII PHY). 2021-03-08 17:39:13 +01:00
gatecat
496cae54ff crosslink_nx_vip: Remove constraint for MIPI pins 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-08 14:26:40 +00:00
Florent Kermarrec
9cdcb8cb43 ecpix5: Add Etherbone (--with-etherbone). 2021-03-08 13:45:09 +01:00
Stafford Horne
52ce49cf0c arty: Add an option to enable jtagbone 
Then adds jtagbone for arty.  I have tested with the following
litex_server and it seems to work fine.

  litex_server --jtag --jtag-config openocd_xc7_ft2232.cfg

Note, the jtagbone and etherbone may be mutually exclusive, but I am not
sure how to define that in the args.
 2021-03-08 07:05:54 +09:00
enjoy-digital
6139bd7eba
Merge pull request #183 from gatecat/vip_split_mclk 
crosslink_nx_vip: Camera IO fixes
 2021-03-06 11:20:53 +01:00
Florent Kermarrec
e280bff1ec targets/video: Simplify/Cleanup integration. 2021-03-05 14:40:27 +01:00
Florent Kermarrec
ce669ac8cd targets/nexys_video: Add optional VideoTerminal/VideoFramebuffer. 2021-03-05 14:33:22 +01:00
gatecat
547157c9ca crosslink_nx_vip: Fix cam_reset IO configuration 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-05 11:26:56 +00:00
gatecat
542001dddf crosslink_nx_vip: Split camera MCLK to its own resource 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-05 11:18:37 +00:00
Florent Kermarrec
21207533b0 targets/Ultrascale(+): Generate Reset to idelay clock domain (to be sure to follow UG571 reset sequence). 2021-03-04 19:49:03 +01:00
Florent Kermarrec
71652e8d44 icebreaker: Lower VideoTerminal resolution to use default 24MHz sys_clk. 2021-03-04 18:29:21 +01:00
Florent Kermarrec
253d8129af nexys4ddr: Integrate simple VideoFrameBuffer. 2021-03-03 20:00:31 +01:00
Florent Kermarrec
51a0bbfa65 platforms/targets: Harmonize VGA pins and use new Video Terminal on all targets with VGA support. 2021-03-03 18:05:24 +01:00
Florent Kermarrec
465a95d2a6 icebreaker/nexys4ddr: Use new LiteXSoC's add_video_terminal method to add the Video Terminal. 2021-03-03 17:47:20 +01:00
Florent Kermarrec
3af8ec0c8d targets/nexys4ddr: Replace VGA terminal with new LiteX's VideoTerminal. 2021-03-03 17:10:22 +01:00
Florent Kermarrec
7e3b8ab3b5 icebreaker: Add optional DVI Video Terminal with new LiteX's VideoOut core. 
Tested with: ./icebreaker.py --cpu-type=serv --with-video-terminal --build --flash

https://twitter.com/enjoy_digital/status/1365324823447171074
 2021-03-03 16:21:04 +01:00
enjoy-digital
aa5c4f9e5a
Merge branch 'master' into arty-numato-sdcard-pmod 2021-02-25 09:37:34 +01:00
Florent Kermarrec
768c10c630 targets/arty: rebase/merge PR179, rename adaptor to adapter. 2021-02-25 09:36:26 +01:00
Hans Baier
6f558a5d65 Add board support for Terasic/Arrow DECA board 2021-02-25 12:25:43 +07:00
enjoy-digital
98c80f0b2b
Merge pull request #177 from antmicro/arty-dynamic-ip 
target/arty: add eth_ip_configurable switch
 2021-02-24 09:29:55 +01:00
Joel Stanley
08ccf384aa targets/arty: Allow selection of sdcard mod adaptor 
The default stays with the Digilent/Antmicro layout, but the user can
optionally provide --sdcard-adaptor numato to use the Numato layout.

Signed-off-by: Joel Stanley <joel@jms.id.au>
 2021-02-24 14:59:50 +10:30
Joel Stanley
2b49082696 platforms/arty: Add numato sd card pmod 
It has a different layout.

Thanks to David for documenting the pinout in this issue:
https://github.com/enjoy-digital/litex/issues/817

 Expansion Pin 	SD 	SPI SD 	Artix 	Arty-A7 	PMOD PIN 	PMOD Index
 2 		DATA_2 	  	D4 	JD1 		1 		0
 4 		CMD 	MOSI 	D3 	JD2 		2 		1
 6 		DATA_0 	MISO 	F4 	JD3 		3 		2
   		CD 	  	F3 	JD4 		4 		3
 1 		DATA_3 	CS_N 	E2 	JD7 		7 		4
 3 		CLK 	CLK 	D2 	JD8 		8 		5
 5 		DATA_1 	  	H2 	JD9 		9 		6
   	  		  	G2 	JD10

Signed-off-by: Joel Stanley <joel@jms.id.au>
 2021-02-24 14:59:50 +10:30
Aleksandra Swierkowska
ae0d4dc0d8 target/arty: add eth_dynamic_ip switch 2021-02-23 21:01:27 +01:00
Florent Kermarrec
aad8154e3a targets/sds1104xe: Enable both Ethernet/Etherbone with hybrid LiteEthMAC. 2021-02-23 15:27:50 +01:00
enjoy-digital
5b28c619d5
Merge pull request #178 from yetifrisstlama/vc707_clk 
fix vc707 default_clk_period
 2021-02-23 12:17:45 +01:00
Florent Kermarrec
a90c0bc8f9 platforms/sds1104xe: Integrate changes from https://github.com/360nosc0pe/scope. 2021-02-22 13:45:48 +01:00
Michael Betz
09c3bd616b Merge branch 'master' into vc707_clk 2021-02-19 22:49:46 -08:00
Michael Betz
c32e790421 vc707: fix default clock frequency 2021-02-19 22:47:18 -08:00
Florent Kermarrec
11405d9ee3 targets/sds1104xe/BaseSoC: Enable Etherbone by default also defaults to Crossover UART when kwargs is empty. 2021-02-18 19:30:05 +01:00
enjoy-digital
1fcd96971d
Merge pull request #172 from hansfbaier/master 
sockit: Add an option to plug in an UART via the GPIO daughter board, make connector pin numbers one-based
 2021-02-16 22:44:52 +01:00
Florent Kermarrec
975150ca68 platforms/sds1104xe: fix ddram IOStandard (SSTL15, thanks @tmbinc) and add INTERNAL_VREF on ddram banks. 2021-02-16 17:32:41 +01:00
Florent Kermarrec
9baa9d5d83 platform/de10nano: fix programmer (thanks @Godtec, see https://github.com/enjoy-digital/litex/pull/811). 2021-02-12 15:23:17 +01:00
Hans Baier
9a94e835c3 sockit: Add an option to plug in an UART via the GPIO daughter board 2021-02-10 14:52:19 +07:00
Michael Betz
7442c2dada vc707.py: clk156 add missing constraint 2021-02-08 19:04:01 -08:00
Florent Kermarrec
fef9dd036a platforms/de0nano: directly use JP1 connector for serial pins. 2021-02-08 09:52:26 +01:00
enjoy-digital
ea58ef94a7
Merge pull request #170 from hansfbaier/master 
arrow_sockit: add support for MiSTer XS SDRAM modules
 2021-02-04 16:44:58 +01:00
enjoy-digital
38242b713f
Merge pull request #171 from antmicro/symbiflow_nexys_video_support 
nexys_video: enable symbiflow toolchain
 2021-02-04 16:42:34 +01:00
Sergiu Mosanu
e6d05001aa use parameter for dram channel 0 or 1 and LedChaser 2021-02-03 17:29:30 -05:00
Jan Kowalewski
cdff5e3ca3 nexys_video: enable symbiflow toolchain 
Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
 2021-02-03 14:52:54 +01:00
Hans Baier
c64e13f687 arrow_sockit: add support for MiSTer XS SDRAM modules 2021-02-03 09:37:03 +07:00
Kaz Kojima
8692ed462f targets/colorlight_i5: use .bit stream instead of .svf when loading. 2021-02-03 08:17:24 +09:00
Sergiu Mosanu
31d7f810e7 use SDRAM C1 sysclk and constraints 2021-02-02 11:15:25 -05:00
enjoy-digital
f32c61d5d2
Merge pull request #163 from garytwong/friendly-incompatible-options 
Be friendlier about incompatible options.
 2021-02-02 08:51:46 +01:00
Sergiu Mosanu
a1d830566a added ddr4_sdram_c1 constraints 2021-02-01 12:22:41 -05:00
Florent Kermarrec
7c48af9b50 tec0117: get SDRAM working and increase sys_clk_freq to 25MHz. 
./tec0117.py --build --load

Still some FIXMEs but validate use of the embedded SDRAM with LiteDRAM/LiteX:

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2020 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Feb  1 2021 13:09:35
 BIOS CRC passed (5abceb2e)

 Migen git sha1: 40b1092
 LiteX git sha1: f324f953

--=============== SoC ==================--
CPU:		VexRiscv_Lite @ 25MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		24KiB
SRAM:		4KiB
L2:		0KiB
SDRAM:		8192KiB 16-bit @ 25MT/s (CL-2 CWL-2)

--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2MiB)...
  Write: 0x40000000-0x40200000 2MiB
   Read: 0x40000000-0x40200000 2MiB
Memtest OK
Memspeed at 0x40000000 (2MiB)...
  Write speed: 5MiB/s
   Read speed: 6MiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex> mem_list

Available memory regions:
ROM       0x00000000 0x6000
SRAM      0x01000000 0x1000
SPIFLASH  0x80000000 0x1000000
MAIN_RAM  0x40000000 0x800000
CSR       0x82000000 0x10000

litex> mem_test 0x40000000 0x800000

Memtest at 0x40000000 (8MiB)...
  Write: 0x40000000-0x40800000 8MiB
   Read: 0x40000000-0x40800000 8MiB
Memtest OK

litex>
 2021-02-01 13:32:01 +01:00
Florent Kermarrec
51c5d69586 targets/tec0117: use custom CPU/ROM/SRAM config to minimize resources. 2021-02-01 13:31:56 +01:00
Florent Kermarrec
538878ce13 tec0117: disable BIOS XIP from SPI Flash for now since not working (SPÏ Flash set to power down mode with bitstream?). 2021-02-01 13:31:51 +01:00
Florent Kermarrec
6cce07d9db tec0117: add spiflash4x pins, rework flash function to flash both bitstream/bios. 2021-02-01 13:31:44 +01:00
Florent Kermarrec
0831b33285 tec0117: fix copyrights. 2021-02-01 13:31:39 +01:00
Hans Baier
5e4b29c0b5 sockit: Fix cable name, default to jtag_atlantic 2021-02-01 11:48:06 +07:00
enjoy-digital
601c297c8f
Merge pull request #164 from rdolbeau/ztex213 
Support file for the ZTEX USB-FPGA Module 2.13
 2021-01-30 21:43:07 +01:00
Guillaume REMBERT
31df53ef0a Add flash to SPI flash support for board ECPIX5 (needs update to openfpgaloader.py from litex to work) 2021-01-30 13:19:08 +01:00
Romain Dolbeau
027e57b851 Support file for the ZTEX USB-FPGA Module 2.13 2021-01-30 05:19:18 -05:00
Gary Wong
99e2f04ee5 Be friendlier about incompatible options. 
Collect --with-ethernet/--with-etherbone, --with-spi-sdcard/--with-sdcard,
etc. into ArgumentParser.add_mutually_exclusive_group()s.  That way, we
get pretty --help output, and appropriate error messages if somebody
tries to ask for something that doesn't make sense.
 2021-01-29 18:08:38 -07:00
Florent Kermarrec
abccd12058 tec0117: add initial SDRAM support for the embedded SDRAM of the SIP. 
Still a WIP but able to do the P&R with modifications on LiteX to generate
the IO_PORT constraints but not the IO_LOC for the SDRAM pins.
 2021-01-29 22:28:40 +01:00
Florent Kermarrec
edb99797aa targets/tec0117: minor cleanups. 2021-01-29 21:25:10 +01:00
Vadzim Dambrouski
345feddce9 ECPIX-5: ddram: Add missing address pin. 
Fixes #161
 2021-01-29 16:03:43 +03:00
Florent Kermarrec
7525b8772f platforms/fpc_iii: avoid dummy pin on ethernet.rst_n. 
rst_n is optional in LiteEth's PHYs.
 2021-01-29 09:33:33 +01:00
Florent Kermarrec
19767e1a2a platforms/fpc_iii: avoid using dummy pin on odt. 
Now possible with 2f5784432d.
 2021-01-29 09:30:54 +01:00
Florent Kermarrec
3deeb69531 targets/fpc_iii: review/cleanup to increase similarities with others targets to ease maintenance. 2021-01-29 08:46:31 +01:00
Florent Kermarrec
6c6d8a1393 platforms/fpc_iii: review/cleanup to increase similarities with others platforms and ease maintenance. 2021-01-29 08:41:10 +01:00
Sergiu Mosanu
1916677dc9 use VREF constraint for DDR4 C0 2021-01-28 19:58:38 -05:00
Gary Wong
4e5bb1bf1e Add FPC-III board support. 
FPC-III is the Free Permutable Computer; details on the board are
available from:

    https://repo.or.cz/fpc-iii.git
 2021-01-28 09:51:42 -07:00
Florent Kermarrec
9bd667720d targets/ecpix5: add LedChaser with red leds. 
Fits nicely LambdaConcept colors and Blue/Green leds are too bright and would need to be controlled through a PWM.
 2021-01-28 14:29:07 +01:00
Florent Kermarrec
aa20fca1f1 ecpix5: reorder rgb_leds to have ld7:0, ld8:1, ld5:2, ld6:3. 2021-01-28 14:25:16 +01:00
enjoy-digital
691bfd8b70
Merge pull request #159 from euryecetelecom/master 
Add ECPIX5 board components and pinouts (sata/spiflash/PMOD) + review openocd IDs
 2021-01-28 14:01:01 +01:00
Alessandro Comodi
bd716d956f netv2: add device variant to allow 100T as well 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-01-28 13:19:53 +01:00
Guillaume REMBERT
9beba7209d Add ECPIX5 components and pinouts (pmod/sata/spiflash) + review IDs from ECPIX5 openocd configuration 2021-01-28 12:00:28 +01:00
Kaz Kojima
aef78831c8 colorlight_i5: Use tx_delay=0 for LiteEthPHYRGMII instead of target specifig bios initialization 2021-01-27 18:19:27 +09:00
Sergiu Mosanu
84656a9c2e re-compare and adjust to u250 2021-01-26 23:03:09 -05:00
Kaz Kojima
c3fa0eac8b Add colorlight i5 board support 2021-01-27 11:44:59 +09:00
Florent Kermarrec
5fd04a97ea targets/netv2/pcie: reduce max_pending_requests to 2 to reduce resource usage. 2021-01-26 11:01:51 +01:00
Florent Kermarrec
d256cc8bd6 camlink_4k: disable leds when serial is used (since pin is shared). 2021-01-25 12:19:29 +01:00
Florent Kermarrec
1e1bec10c4 orangecrab: remove dm_remapping workaround: we are now using Wihsbone/L2 path with VexRiscv-SMP on this board. 2021-01-25 11:52:59 +01:00
Florent Kermarrec
537f494cbb arrow_sockit: review/harmonize with others boards. 2021-01-25 09:14:46 +01:00
Florent Kermarrec
4adc1b14c4 platforms/de0nano: use separator for connectors. 2021-01-25 08:58:12 +01:00
enjoy-digital
bbaa2fdc98
Merge pull request #149 from hansfbaier/master 
Add board support for Terasic/Arrow SocKit, Add connectors to de0-nano
 2021-01-25 08:55:48 +01:00
enjoy-digital
45f538b1d3
Merge pull request #155 from blakesmith/add_spi_flash 
ULX3S: Make spiflash optionally accessible from the SoC, and bootable
 2021-01-24 21:22:35 +01:00
enjoy-digital
8132f9f65b
Merge pull request #154 from euryecetelecom/master 
Fix SDCard issue when no SDCard inserted in ECPIX5 board.
 2021-01-24 21:14:58 +01:00
enjoy-digital
72985c72ca
Merge pull request #153 from Disasm/ecpix5-add-45f 
ECPIX-5: add option to select ECP5 device
 2021-01-24 21:14:14 +01:00
Blake Smith
cae51c0c24 ULX3S: Make spiflash optionally accessible from the SoC, and bootable 2021-01-23 14:44:26 -06:00
Hans Baier
aa771e9ff4 de0-nano: add connectors 2021-01-23 20:18:15 +07:00
Hans Baier
c9f0745d54 sockit: add board definitions for Terasic SocKit 2021-01-23 20:17:38 +07:00
Florent Kermarrec
23760e2eae orangecrab/CRGSDRAM: add missing rst signal (to reset from the SoC). 2021-01-22 22:55:02 +01:00
Guillaume REMBERT
b386ee5059 Fix SDCard issue when no SDCard inserted in ECPIX5 board. Now enable to detect SDCard presence. 
https://github.com/litex-hub/linux-on-litex-vexriscv/issues/171
 2021-01-20 18:02:13 +01:00
Vadim Kaushan
a678672fc9
ecpix5: add option to select ECP5 device 2021-01-19 01:22:52 +03:00
Gabriel Somlo
e71a4940c0 nexys4ddr: etherbone support 2021-01-15 12:14:40 -05:00
Sergiu Mosanu
7a738245af fix bitstream problem 2021-01-14 21:53:25 -05:00
Sergiu Mosanu
5a73eb0b6d initiate target and platform for alveo_u280 board 2021-01-14 18:35:43 -05:00
Florent Kermarrec
6a5f2f59a6 targets/orangecrab: use new ECP5DDRPHY's cmd_delay to add extra delay on DDR3's Clock/Commands. 
This fixes https://github.com/enjoy-digital/litedram/issues/130 and has been tested
at 48/64/96MHz on MT41K64M16 and MT41K512M16 variants.

Also remove un-needed cd_sys2x_eb.
 2021-01-12 18:57:22 +01:00
Florent Kermarrec
9ff90eb9fe targets/c10lprefkit: fix default sys-clk-freq. 2021-01-12 16:15:52 +01:00
Florent Kermarrec
0a7443d273 targets/orangecrab: make usr_btn optional to fix compilation with revision 0.1. 2021-01-08 19:30:37 +01:00
Florent Kermarrec
ae5494d7b6 orangecrab: defaults to USB-ACM UART. 2021-01-08 19:01:41 +01:00
Florent Kermarrec
c6e75122d9 sds1104xe: defaults to Crossover UART. 2021-01-08 19:00:41 +01:00
Florent Kermarrec
ab72f69937 targets/ac701: rename --ethernet-phy to --eth-phy for consistency with others targets. 2021-01-08 18:50:01 +01:00
Hans Baier
0ee62dd681 add etherbone ip address option for relevant boards 2021-01-08 18:44:31 +01:00
Florent Kermarrec
869cce2bba targets/colorlight_5a_75x: rename etherbone-ip args to eth-ip. 
eth-ip will also be used to configure Ethernet IP addresss.
 2021-01-07 09:26:38 +01:00
Florent Kermarrec
c829a47c31 targets/colorlight_5a_75x: Automatically disable Led Chaser when serial is used. 2021-01-07 09:17:28 +01:00
enjoy-digital
adbcc81ecf
Merge pull request #145 from hansfbaier/master 
colorlight: Add option for etherbone ip address and LED chaser
 2021-01-07 09:08:43 +01:00
enjoy-digital
a6e867c691
Merge pull request #144 from gsomlo/gls-genesys2-sdcard 
genesys2: LiteSDCard support
 2021-01-07 08:12:24 +01:00
enjoy-digital
d2d17e00a2
Merge pull request #142 from geertu/master 
platforms/ecp5: Fix slewrate configuration
 2021-01-07 08:11:30 +01:00
Florent Kermarrec
d73bd2f7ce targets/xilinx: add comment on sys_clk to pll.clkin false path. 2021-01-07 08:01:54 +01:00
Florent Kermarrec
1ac1c6857f targets/xilinx: add false path constraint between sys_clk and pll.clkin. 
The SoC reset added recently creates a path between sys_clk and pll.clkin
clock domains that is reported by the tools but that can be safely ignored.
 2021-01-07 00:02:46 +01:00
Hans Baier
0d69cfa6b0 colorlight: make LEDs optional 2021-01-05 08:03:26 +07:00
Hans Baier
4bec17e1a7 colorlight: Add option for etherbone ip address 2021-01-05 07:49:44 +07:00
Gabriel Somlo
2589d9f704 genesys2: add (spi-)sdcard build options 
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2021-01-04 13:57:21 -05:00
Gabriel Somlo
4eb0026a69 genesys2: add "rst" and "cd" signals to (spi-)sdcard records 
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2021-01-04 13:10:13 -05:00
Geert Uytterhoeven
4a95b94dbf platforms/ecp5: Fix slewrate configuration 
When building linux-on-litex-vexriscv for OrangeCrab:

    Warning: IOBUF 'spisdcard_clk' attribute 'SLEW' is not recognised (on line 207)
    Warning: IOBUF 'spisdcard_mosi' attribute 'SLEW' is not recognised (on line 210)
    Warning: IOBUF 'spisdcard_cs_n' attribute 'SLEW' is not recognised (on line 214)
    Warning: IOBUF 'spisdcard_miso' attribute 'SLEW' is not recognised (on line 218)

Platforms using litex.build.lattice.LatticePlatform seem to support only
"SLEWRATE", not "SLEW".  Fix the few offenders in the LogicBone and
OrangeCrab platform definitions.

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
 2021-01-04 17:08:51 +01:00
Florent Kermarrec
fe67766fb7 targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl). 2021-01-04 11:38:07 +01:00
Florent Kermarrec
0e3c03f2f6 mercury_xu5: remove unneeded cmd_latency=0 (now defaulting to 0). 2021-01-04 10:48:34 +01:00
Florent Kermarrec
5cc49bafbd orangecrab: Run reset_timer with por/48MHz clock domain (sys clock domain is now directly reseted on usr_btn press). 2021-01-04 09:42:05 +01:00
Florent Kermarrec
1fb24d4c71 orangecrab: Avoid usb clock domain reset on usr_btn press or SoC reset. 
Allows the USB-ACM link to stay up during reset.
 2021-01-04 09:05:19 +01:00
Florent Kermarrec
06cb49af37 targets/arty: add variant support through --variant args. 
./arty.py --variant=a7-35 or a7-100
./arty_s7.py --variant=s7-50 or s7-25
 2020-12-29 18:43:14 +01:00
Florent Kermarrec
02a81d54e2 targets/ecpix5/eth: set rx_delay to 0ns (tested with netboot on R01). 2020-12-29 16:01:12 +01:00
Florent Kermarrec
93779ecb95 platforms/colorlight_5a_75b: revert toolchain args. 
Useful to do tests with Diamiond.
 2020-12-29 14:22:42 +01:00
enjoy-digital
f2985f1e71
Merge pull request #141 from la6m/Colorlight_v8.0 
add colorlight v8.0 PCB
 2020-12-29 14:20:29 +01:00
Florent Kermarrec
84098d2de5 targets/qmtech_wukong: submitted target was the platform file, update with target shared in #133. 
Build tested with /qmtech_wukong.py --with-sdcard --with-ethernet --integrated-rom-size=0x10000 --build.
 2020-12-29 14:13:11 +01:00
Florent Kermarrec
b67b18caad qmtech_wukong: review/cleanup platform. 2020-12-29 14:10:49 +01:00
la6m
3e6b934961 add colorlight v8.0 PCB 2020-12-29 13:52:13 +01:00
Florent Kermarrec
e380f24655 targets/qmtech_wukong: +x. 2020-12-29 13:24:41 +01:00
Shinken Sanada
4b721eded7 add QmTech Wukong board support. 2020-12-29 13:20:42 +01:00
Florent Kermarrec
9beaf25822 nexys4ddr: fix eth/int_n pin (B8) and use 4-bit on vga.blue. 2020-12-24 10:15:29 +01:00
Sahaj Sarup
2a04c5c74e nexys4ddr: add support for litexvideo VGA Terminal 
This commit adds VGA support for the Nexys A7/ Nexys 4 DDR.

The VGA is however limited to RGB443 instead of the full 12bit RGB444.
This is because IO D8 which is MSB for Blue, is also used for ETH int_n.
This makes the final output have a yellow tint.
 2020-12-23 02:24:18 +05:30
Vadim Kaushan
f6a106cdf4
Fix orangecrab target 2020-12-20 01:07:43 +03:00
Florent Kermarrec
00fc2c5166 targets/orangecrab: use new DM remapping capability of LiteDRAM to fix LDM/UDM. 
Required by VexRiscv-SMP that uses DMs on LiteDRAM interface.
 2020-12-16 11:52:58 +01:00
Vadim Kaushan
bb58258fd4
Fix de10nano target 2020-12-14 15:27:33 +03:00
Florent Kermarrec
ec4ccc9fa5 platforms/xcu1525: fix ddram 1/2/3 pinout. 
DDR4 now validated successfully with LiteDRAM on the 4 channels.
 2020-12-11 13:58:26 +01:00
Florent Kermarrec
519f9449fa targets/sds1104: litex_term now directly supports crossover uart. 2020-12-10 13:56:01 +01:00
Robert Winkler
18337cdf25 targets/arty: sync with litex repository 
Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
 2020-12-07 17:32:40 +01:00
Alessandro Comodi
f66860c201 zybo_z7: fix clock pin constraint 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-12-07 16:46:20 +01:00
Geert Uytterhoeven
8e5f955e4e targets/orangecrab: Fix --sdram-device help text 
Obviously --sdram-device takes the SDRAM device, not the ECP5 FPGA
device.

Fixes: bf3c9dc9bf ("orangecrab: Add sdram selection option")
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
 2020-12-04 14:34:01 +01:00
Florent Kermarrec
fe563baec7 targets/fomu: modification to ValentyUSB no longer required. 
Following commits make it generic/portable while still using IOBuffers:
77b9d01058
371526e432
 2020-11-27 19:40:45 +01:00
Florent Kermarrec
5a4e28d47d target/usb_acm: switch git clone to litex-hub/valentyusb repo (up to date with LiteX). 2020-11-27 18:53:45 +01:00
Gwenhael Goavec-Merou
8d1095224f add support for redpitaya14/16 2020-11-26 06:54:11 +01:00
David Shah
11fa5c34ac nexus: Allow selection of toolchain 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-25 09:45:25 +00:00
Florent Kermarrec
159a0c751c targets/colorlight_5a_75x: update instructions and LiteEthPHYRGMII's tx_delay (required with LiteEth fixes). 2020-11-23 12:30:36 +01:00
Florent Kermarrec
03bb929f27 colorlight_5a_75x: add LedChaser. 2020-11-23 10:14:20 +01:00
Florent Kermarrec
d18deef10d colorlight_5a_75x: switch prog to FT232 based programmer (ex: JTAG HS2). 2020-11-23 10:13:57 +01:00
Jędrzej Boczar
ce38cff41d mercury_xu5: reduce cmd_latency to fix problems with DRAM leveling 2020-11-20 15:31:47 +01:00
enjoy-digital
a2f3add24e
Merge pull request #123 from teknoman117/litefury 
Support for the RHS Research LiteFury
 2020-11-20 08:44:27 +01:00
Nathaniel R. Lewis
389b623fe2 targets/litefury: new target 
LiteFury is an Artix-7 development board in the M.2 form factor
for PCIe accelerator development. It's similar to the Aller but
with an xc7a100t rather than an xc7a200t and no TPM module.

https://rhsresearch.com/collections/rhs-public/products/litefury
 2020-11-19 21:52:14 -08:00
Florent Kermarrec
49e1c34dfd targets/acorn_cle_215: add SATA. 2020-11-18 19:14:18 +01:00
Florent Kermarrec
778ce53865 targets/xcu1525: add SATA. 2020-11-17 15:27:42 +01:00
Florent Kermarrec
27e19644f4 targets/kcu105: add SATA. 2020-11-16 18:44:18 +01:00
Florent Kermarrec
27f60b2e93 add initial Siglent SDS1104X-E support (Ethernet & DDR3 validated). 
Pinout from https://github.com/360nosc0pe project.
 2020-11-13 12:20:15 +01:00
Florent Kermarrec
d42af3ea19 targets: add --sys-clk-freq support to all targets. 2020-11-12 18:07:28 +01:00
Florent Kermarrec
72afb95329 targets: create platform on BaseSoC for all targets (consitency). 2020-11-12 16:57:31 +01:00
Florent Kermarrec
843e724e3d targets/pcie: simplify using new LiteX's add_pcie method and enable it on all devices supported by LitePCIe. 2020-11-12 16:39:42 +01:00
Florent Kermarrec
9f11bfb0d1 qmtech_ep4ce15: convert name to lowercase, minor cleanup and add to test_targets. 2020-11-12 14:33:45 +01:00
enjoy-digital
31eb74dc2d
Merge pull request #122 from baselsayeh/master 
add Qmtech EP4CE15 coreboard support
 2020-11-12 14:27:49 +01:00
Florent Kermarrec
46e8a957fe platforms/zybo_z7: fix default_clk typo. 2020-11-12 14:26:36 +01:00
Florent Kermarrec
ac075f18c7 platforms/crosslink_nx_evn/vip: add default_clk. 2020-11-12 14:26:17 +01:00
Florent Kermarrec
f3ccd140c2 targets/simple: add try/except on leds. 2020-11-12 14:26:00 +01:00
Basel Sayeh
0fc67ddfdb
update copyright 2020-11-12 15:25:39 +02:00
Florent Kermarrec
7c6df67739 targets: add tinyfpga_bx target (based on icebreaker/fomu targets). 2020-11-12 14:09:25 +01:00
Florent Kermarrec
302e4ffdff targets/simple: simplify (only keep minimal SoC + Leds) and add load argument. 
ex of use:
./simple.py litex_boards.platform.ulx3s --build --load
./simple.py litex_boards.platform.trellisboard --build --load
./simple.py litex_boards.platform.arty --build --load
etc...
 2020-11-12 13:54:30 +01:00
Florent Kermarrec
a4d05522d4 platforms/ice40/ecp5: add toolchain parameter with default to trellis (ECP5) or icestorm (iCE40). 
Required to simplify simple.py target and use trellis/icestorm as default toolchain.
 2020-11-12 13:33:30 +01:00
Florent Kermarrec
5cf7731f37 targets/netv2: add PCIe. 2020-11-12 12:16:01 +01:00
Florent Kermarrec
7a9f175450 targets/pcie: remove force of csr_data_width to 32 (this is now the default) but just add a check on the pcie block. 2020-11-12 12:08:20 +01:00
Florent Kermarrec
4401fec1e6 targets: remove add_csr("crg") (no longer needed). 2020-11-12 11:54:11 +01:00
Florent Kermarrec
bd4e92ad13 targets: cleanup, uniformize build arguments between targets. 2020-11-12 11:46:00 +01:00
Basel Sayeh
1b1ed5ebf1
add Qmtech EP4CE15 coreboard support 2020-11-12 01:56:36 +02:00
Florent Kermarrec
5fbb176c2a targets/crosslink_nx: update NXLRAM import. 2020-11-09 11:05:18 +01:00
Florent Kermarrec
afe44e2bd6 targets/crosslink_nx_evn: update NXPLL import. 2020-11-09 10:25:30 +01:00
Florent Kermarrec
39d979a9d3 targets/Ultrascale: add missing AsyncResetSynchronizer import. 2020-11-09 10:25:05 +01:00
davidcorrigan714
97b64d16a6 Lattice NX PLL Support 2020-11-08 20:34:46 -06:00
Florent Kermarrec
1f52fbaca6 xcu1525: fix last ddram channel numbering. 2020-11-06 10:48:26 +01:00
Florent Kermarrec
2b17dc1b89 target: add rst signal to CRG to allow full reset of the SoC on reboot command. 2020-11-04 11:13:42 +01:00
Florent Kermarrec
aa6b9cab4a targets/crosslink_nx_vip: +x. 2020-11-04 09:30:57 +01:00
Florent Kermarrec
ce14775dfb targets/tec0117: move SerialFlashManager import to flash function. 2020-11-04 09:30:31 +01:00
Florent Kermarrec
2da4eabffe platforms/icebreaker: fix refactoring typo. 2020-11-04 09:30:01 +01:00
Florent Kermarrec
c093d0d0fc platforms: cleanup pass to uniformize comments/separators/orders. 2020-11-03 10:48:57 +01:00
Florent Kermarrec
8d26c241cd kc705: revert sys_clk_freq to 125MHz. 2020-11-02 19:51:48 +01:00
Florent Kermarrec
babf638c2b targets/nexys_video: add SATA support. 2020-11-02 19:43:25 +01:00
Kevin Mehall
d1c9cc7553 Add LFE5U-12F device for ULX3S 2020-11-01 23:45:32 +00:00
Florent Kermarrec
e950a4a588 targets/kc705: update sata pads. 2020-10-30 17:12:59 +01:00
Florent Kermarrec
a410e447e1 targets/kc705/sata: enable write support. 2020-10-30 14:51:40 +01:00
Florent Kermarrec
d626861e95 platforms/acorn_cle_215: add serial_io (on P2). 2020-10-29 12:10:12 +01:00
Florent Kermarrec
f9252fdd45 targets/kc705: simplify SATA using LiteX's add_sata integration method. 2020-10-29 10:16:40 +01:00
Florent Kermarrec
7da8628fba targets/kc705: switch SATA to gen2. 2020-10-28 19:09:30 +01:00
Florent Kermarrec
931f6667ac targets/kc705: add initial SATA support. 2020-10-26 15:15:24 +01:00
enjoy-digital
51934567fe
Merge pull request #118 from daveshah1/lifcl-vip 
Add CrossLink-NX VIP board platform and target
 2020-10-22 11:03:47 +02:00
Florent Kermarrec
a38c1e7062 mist: add copyrights. 2020-10-22 10:48:58 +02:00
David Shah
20720693c4 crosslink_nx_vip: Add HyperRAM support 
Signed-off-by: David Shah <dave@ds0.me>
 2020-10-22 09:15:40 +01:00
David Shah
b278d8bccc Add CrossLink-NX VIP board platform and target 2020-10-22 09:15:35 +01:00
YanekJ
4541c39e94 Initial support for the MIST board (https://github.com/mist-devel/mist-board/wiki) 2020-10-17 12:28:22 +02:00
Florent Kermarrec
814e7630e4 targets/xilinx: use generic name for idelay clk (avoid clk200, clk400, etc...) since we somtimes want to change it. 2020-10-13 12:10:29 +02:00
Florent Kermarrec
06137452d2 targets/xcu1525: use ddram_channel to select clk300. 2020-10-13 11:57:00 +02:00
Florent Kermarrec
982cfd5ad5 platforms/xcu1525: fix ddram constraints, add clk300 constraints for all channels. 2020-10-13 11:50:36 +02:00
Florent Kermarrec
c3ea04b6e9 targets/s7/us: update sdram (manual cmd_latency no longer needed). 2020-10-12 18:46:21 +02:00
Florent Kermarrec
ddf7038c78 ulx3s: add 1.7 and 2.0 revisions support. 2020-10-12 13:23:26 +02:00
enjoy-digital
204d22c62b
Merge pull request #115 from BryanJacobs/master 
platforms/ulx3s: Update ULX3S SD pins for revision 2.0
 2020-10-12 12:55:17 +02:00
Bryan Jacobs
3b11e60fb1 Update ULX3S SD pins for revision 2.0 2020-10-11 14:17:48 +11:00
Konrad Beckmann
5e67853a21 versa_ecp5: Add --eth-phy to select ethernet phy 
This also simplifies the logic a bit.
 2020-10-09 23:56:16 +02:00
Konrad Beckmann
477734ff06 versa_ecp5: Add etherbone support 
Etherbone can be enabled with --with-etherbone
 2020-10-09 00:53:08 +02:00
Florent Kermarrec
55da8b867a platforms/zedboard: minor cleanups to uniformize with other platforms. 2020-10-07 11:25:20 +02:00
Michael Betz
e225cbd28f add zedboard platform to CI 2020-10-06 11:35:03 -07:00
Michael Betz
8ee20a3f30 clean up imports 2020-10-06 11:24:34 -07:00
Michael Betz
865c2bd98c zedboard platform: clean up 
* remove unused code
  * remove oled integration code
  * openocd = default programmer
 2020-10-06 11:00:36 -07:00
Michael Betz
94ef096e77 Merge branch 'master' of https://github.com/litex-hub/litex-boards into HEAD 2020-10-06 10:05:34 -07:00
Florent Kermarrec
fff20f7532 targets/fomu: base it on iCEBreaker target + USB-ACM. 
This uniformizes Fomu target with others, provide a simple example of LiteX SoC
on Fomu and will ease maintenance.
 2020-10-06 11:39:30 +02:00
Michael Betz
12aed44577 add zedboard platform 2020-10-06 00:28:54 -07:00
enjoy-digital
79ef091a06
Merge pull request #110 from pepijndevos/gowin 
Add initial support for Trenz TEC0117 board
 2020-10-05 19:50:09 +02:00
enjoy-digital
2ee32f2a15
Merge pull request #109 from geertu/orangecrab-Fix-r0.1-user_led-mapping 
orangecrab: Fix r0.1 user_led mapping
 2020-10-02 09:40:41 +02:00
enjoy-digital
062fbd6c63
Merge pull request #108 from daveshah1/dave/nx-evn-doc 
crosslink_nx_evn: Improve documentation on UART jumpers
 2020-10-02 09:40:04 +02:00
Pepijn de Vos
18e5def9f2 don't verify erase, very slow 2020-10-01 08:41:16 +02:00
Pepijn de Vos
81e4f1f158 add initial support for Trenz TEC0117 board 2020-09-30 14:01:36 +02:00
Geert Uytterhoeven
b2e34f5faf orangecrab: Fix r0.1 user_led mapping 
On r0.1, all three user_leds are mapped to the same pin.
Fix this by mapping them to the pins connected to the individual
channels of the RGB LED, to match the comments, the schematics, and the
spirit of r0.2.

Untested on real hardware (I have r0.2 only).

Fixes: c94cbae0c0 ("orangecrab: add user_led (RGB leds), DFUProg and --load support.")
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
 2020-09-25 10:33:21 +02:00