7fb225a162
Option --with-spi-flash for iCESugar-Pro
2021-12-19 15:50:52 +01:00
f18c1a033c
Efinix: ti60: add HyperRAM support
2021-12-17 10:23:10 +01:00
1c87c391c4
Initial release for Snickerdoodle
2021-12-14 16:00:42 -05:00
84f267e00c
Change bios-flash-offset for tinyFPGA
2021-12-14 19:10:03 +01:00
c2a840f777
Merge pull request #307 from fjullien/titanium_spi
...
Titanium spi
2021-12-14 08:21:15 +01:00
9608cae2ee
efinix: Ti60f225 change spi_flash module
2021-12-13 23:01:48 +01:00
be7dbf3b1b
exfinix: efinix_titanium_ti60_f225_dev_kit: fix typo
2021-12-13 22:53:50 +01:00
179e9090d1
Rename efinix_titanium_ti60_bga225_dev_kit to efinix_titanium_ti60_f225_dev_kit and also exclude it from tested platforms/targets.
2021-12-13 15:54:56 +01:00
e84f32b918
efinix: add titanium Ti60 dev kit
2021-12-13 09:37:14 +01:00
35e0026875
Merge pull request #303 from sergachev/master
...
sipeed_tang_nano_4k: add option to build with Gowin EMCU
2021-12-09 14:30:54 +01:00
14a8c50e97
sipeed_tang_nano_4k: connect Gowin EMCU UART, undo unnecessary changes
2021-12-09 00:17:48 +01:00
6274c4c425
sipeed_tang_nano_4k: connect Gowin EMCU UART
2021-12-09 00:12:31 +01:00
13c83ba532
sipeed_tang_nano_4k: add initial Gowin EMCU support
2021-12-08 23:50:14 +01:00
4287ab561e
sipeed_tang_nano_4k: allow non-vexriscv CPUs
2021-12-08 23:33:49 +01:00
9119250276
Merge pull request #300 from tilk/de1_soc
...
Better support for DE1-SoC
2021-12-08 06:18:25 +01:00
2b7587632f
Merge pull request #299 from gregdavill/butterstick-updates
...
Butterstick updates
2021-12-08 06:16:29 +01:00
8ad89881c2
fairwaves_xtrx: Add pcie_x2 definitions and switch to it.
2021-12-07 15:27:55 +01:00
cbeb2a3792
Add LedChaser to DE1-SoC
2021-12-05 20:16:10 +01:00
fd2ec534a7
butterstick: Add extra pins
2021-12-05 20:33:28 +10:30
c8a8e943b5
butterstick: add --sdram-device option
...
Set 64M16 as default sdram-device.
Related to #298
2021-12-04 17:07:06 +10:30
bf8b23c19f
trenz_tec0117: Update target.
2021-12-02 18:23:11 +01:00
efa1f46356
Merge pull request #297 from sergachev/master
...
Fix Sipeed Tang Nano 4k example compilation; adapt Gowin PLL class changes
2021-12-02 09:14:32 +01:00
666ef9dad3
sipeed_tang_nano_4k: use minimal vexriscv variant to fit into number of BSRAMs
2021-11-29 11:46:32 +01:00
2fb734a0f2
sipeed_tang_nano*: adapt Gowin PLL changes in litex
2021-11-29 11:45:13 +01:00
1829693877
fairwaves_xtrx: Integrate ICAP/SPIFlash (for update over PCIe).
2021-11-26 16:18:52 +01:00
fe14e16c1b
Merge branch 'master' into tang_primer
2021-11-23 19:04:09 +01:00
6954dd25eb
Set minimal core, since full does not work for some reason
2021-11-23 15:26:54 +01:00
0b7fabb864
FireAnt board support
2021-11-23 14:43:52 +01:00
2cc322e65d
Add initial support for Tang Primer board
2021-11-22 19:10:11 +01:00
70c0dbb185
targets/radiona_ulx3s: Remove SDRAM underflows debug pin.
2021-11-22 11:54:18 +01:00
60b769b624
efinix_trion_t120_bga576_dev_kit/ethernet: Disable software debug (RX now seems to be working fine).
2021-11-16 18:53:15 +01:00
996f5b2edd
efinix_trion_t120_bga576_dev_kit: Enable target1 port and also connect it to SoC.
2021-11-16 18:12:42 +01:00
7ce6c4cf79
efinix_trion_t120_bga576_dev_kit: Switch to ctrl_type = "none" (Also seems to work fine, avoid ddr_reset_sequencer dependency).
2021-11-16 17:50:47 +01:00
99f4f97f00
efinix_trion_t120_bga576_dev_kit: Use new InterfaceWriterBlock/InterfaceWriterXMLBlock and move PLL/DRAM blocks definition to target.
2021-11-16 17:41:26 +01:00
e16fa193fc
qmtech 10cl006: remove all options which won't fit into the device. use uartbone as default
2021-11-15 10:23:01 +07:00
138dc1467e
quicklogic_quickfeather: Fix build with GPIOIn when cpu-type=None (IRQ not supported).
2021-11-14 09:30:52 +01:00
ed67b91fcc
quicklogic_quickfeather: Simplify cpu_type switch between None/EOS-S3.
2021-11-14 09:26:29 +01:00
2d3422869c
quicklogic_quickfeather: Update clocking.
2021-11-14 09:19:19 +01:00
df468fcf85
quicklogic_quickfeather: Avoid add_csr calls (not required).
2021-11-14 08:54:49 +01:00
06bae58f48
efinix_trion_t120_bga576: Do a bit a of cleanup on LPDDR3 now that working.
2021-11-12 19:43:28 +01:00
86f6d7e66b
efinix_trion_t120_bga576_dev_kit: Remove test command.
2021-11-12 18:06:11 +01:00
4e03f66fad
efinix_trion_t120_bga576_dev_kit: Remove debug, integrate LPDDR3 as done on other targets.
...
Also lower sys_clk_freq since seems to cause issue with DRAM at 100MHz: Needs to be investigated.
2021-11-12 18:04:30 +01:00
77fffda9cd
efinix_trion_t120_bga576_dev_kit: Switch to UARTBone, Add LiteScope on Pseudo-AXI, fix addressing and do first successful LPDDR3 accesses :)
2021-11-12 16:41:42 +01:00
648d38da7e
quicklogic_quickfeather: add button and GPIOIn
...
Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
2021-11-12 13:21:00 +01:00
b6c5a85b98
Add initial Efinix Trion T20 MIPI Dev Kit support: CPU, ROM, RAM, UART and SPI Flash.
...
Tested with:
./efinix_trion_t20_mipi_dev_kit.py --with-spi-flash --build --load
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2021 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Nov 12 2021 08:37:48
BIOS CRC passed (2bec12a3)
Migen git sha1: 7507a2b
LiteX git sha1: f679992f
--=============== SoC ==================--
CPU: VexRiscv @ 100MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 128KiB
SRAM: 8KiB
FLASH: 4096KiB
--========== Initialization ============--
Initializing W25Q32JV SPI Flash @0x00400000...
Enabling Quad mode...
First SPI Flash block erased, unable to perform freq test.
Memspeed at 0x400000 (Sequential, 4.0KiB)...
Read speed: 2.6MiB/s
Memspeed at 0x400000 (Random, 4.0KiB)...
Read speed: 1.5MiB/s
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex>
2021-11-12 08:42:10 +01:00
d6fc4b412e
efinix_trion_t120/t20_dev_kit: Switch back to 100MHz (now that timings constraints are correctly applied).
2021-11-12 07:58:51 +01:00
7ce8567d9b
targets/efinix: Bitstreams now directly generated to gateware directory.
2021-11-11 11:19:39 +01:00
855fd7e3d7
efinix_trion_t120_bga576_dev_kit: Continue LPDDR3 integration...
2021-11-10 19:40:35 +01:00
224f527baa
efinix_trion_t120_bga576_dev_kit: Go a bit further in DRAM integration.
2021-11-10 12:07:30 +01:00
040e7b3104
quicklogic_quickfeather: Use initial EOS-S3 support/integration.
2021-11-09 18:59:37 +01:00
8ce83ce92f
efinix_trion_t120_bga576_dev_kit: Add inital LPDDR3 integration (not yet working).
2021-11-09 16:13:40 +01:00
9a7e5f40b4
efinix_trion_t120_bga576_dev_kit: Add Ethernet/Etherbone support.
...
Still not fully validated: TX seems OK but RX seems shifted/corrupted.
2021-11-09 11:32:32 +01:00
ccebae6f55
targets/hyperram: Update integration.
2021-11-08 16:39:49 +01:00
184f41e61a
sipeed_tang_nano: Use PLL and 48MHz sys_clk, switch to SoCMini, add UARTBone (at 1MBauds).
...
Working correctly on hardware with updated CH552 firmware & patched litex_server...
2021-11-08 09:23:44 +01:00
d6bf2fd00e
terasic_sockit: Use standard SDRAM module from litedram
2021-11-08 12:48:03 +07:00
a9847f15a7
qmtech_5cefa2: tuned the clock phase shift to be able to run the system at 105MHz
2021-11-06 09:58:10 +07:00
b2813cfb70
use the right DRAM chip for the QMTech Altera boards
2021-11-06 08:45:03 +07:00
6e7c76b71e
fairwaves_xtrx: Add clk60 (from USB PHY) as default Clk when no PCIe.
...
Fixes CI.
2021-11-05 15:22:55 +01:00
ceaaf67dfd
Add initial Fairwaves XTRX support (SoC with JTAG-UART and PCIe Gen2 X1).
2021-11-05 14:52:45 +01:00
01463a81a4
Merge pull request #287 from hansfbaier/qmtech-fixes
...
10cl006: add missing spiflash option
2021-11-05 07:11:27 +01:00
3a25af1c28
10cl006: add missing spiflash option
2021-11-05 09:57:04 +07:00
0edce3a176
Add support for QMTech 5CEFA2 board (Cyclone V)
2021-11-05 09:53:25 +07:00
a482d7f6de
targets/qmtech_xc7a35t: Use gpio_serial as serial when not mounted on daughterboard.
2021-11-04 18:52:36 +01:00
9543b5efae
marble/marble_mini: Add berkeleylab prefix.
2021-11-04 18:42:16 +01:00
5e5ae880a4
targets/litex_acorn_baseboard: Integrate WS2812/NeoPixel.
...
Tested with:
./litex_acorn_baseboard.py --cpu-type=None --uart-name=uartbone --with-ws2812 --build --csr-csv=csr.csv --load
litex_server --uart --uart-port=/dev/ttyUSBX
And test script: https://gist.github.com/enjoy-digital/c32c679a9ee4429d7f38a5ca5016a45a
2021-11-04 16:36:25 +01:00
808befec3b
Merge pull request #283 from yetifrisstlama/master
...
add Marble-board platform and target file
2021-11-04 15:20:11 +01:00
7aa639ac0f
QMTech boards: fix swapped RX/TX lines, remove double uart replacer
2021-11-02 09:34:25 +07:00
e645eb243b
add marble board platform and target file
2021-10-28 18:41:22 +02:00
207afb98fc
ego1: Switch to VideoTerminal (LiteVideo is no longer provided by default with LiteX).
2021-10-27 16:29:46 +02:00
91818bc5f0
targets/gsd_butterstick/BaseSoC: Set default device to 85F (consistency with default arguments).
2021-10-26 17:01:55 +02:00
c7a91f9eab
efinix: Enable identifier on SoC (issue fixed in LiteX).
2021-10-25 19:33:49 +02:00
4bcfde8882
efinix: Avoid no_we on ROM/RAMs (no longer required).
2021-10-25 19:10:03 +02:00
d13a8d54b8
efinix_trion_txy_dev_kit: Lower sys_clk_freq for now to 50MHz, enable QSPI on T120 BGA576 dev kit.
...
Now possible with recent LiteX changes to support Tristate IOs.
2021-10-25 18:35:35 +02:00
f230eaf9bc
efinix_trion_t120_bga576: Add Tristate test code.
2021-10-25 15:01:34 +02:00
0ac0f9e75d
efinix_xyloni_dev_kit: Switch to openFPGALoader to load bitstream.
2021-10-25 12:49:48 +02:00
fc05379929
efinix_xyloni_dev_kit: Use PLL.
2021-10-25 12:16:47 +02:00
394ea23b99
efinix_xyloni_dev_kit: Only force variant to minimal for Vexriscv.
2021-10-22 14:47:12 +02:00
75fd276dbe
efinix_xyloni_dev_kit: Increase similarities with others boards and make target very similar to iceBreaker/Fomu/TangNano4k.
2021-10-21 11:34:55 +02:00
dc1328f1a5
efinix_xyloni_dev_kit: Fix copyrights.
2021-10-21 10:12:46 +02:00
012c1d9705
efinix_trion_t20: Minor changes (move serial to platform, fix platform copyright).
2021-10-21 10:10:35 +02:00
0cf9793be5
Merge pull request #282 from AndrewD/master
...
efinix: xyloni dev board basic support
2021-10-21 10:06:25 +02:00
7525132907
litex_acorn_baseboard/video: Switch to 800x600@60Hz.
2021-10-19 16:34:28 +02:00
c548b1c1e2
efinix: xyloni dev board basic support
...
* This works: efinix_xyloni_dev_kit.py --cpu-type None --build --load --flash
* issues with SPIflash - wrong generation for tristates miso mosi for
some reason
2021-10-19 11:23:29 +11:00
a53f17380f
Merge pull request #271 from antmicro/add-data-center-board
...
WIP: boards: added datacenter DDR4 RDIMM tester board
2021-10-18 13:36:37 +02:00
a4d330dd2c
Merge pull request #279 from mmicko/efinix_t20_flash
...
Enable writing to flash for T20
2021-10-15 18:38:08 +02:00
3730d96709
litex_acorn_baseboard: Add SPIFlash support.
2021-10-15 18:22:08 +02:00
1f65d37121
Enable writing to flash for T20
2021-10-15 16:44:35 +02:00
d9638c40b8
Initial support for Efinix Trion T20 BGA256 Dev Kit
2021-10-15 12:26:15 +02:00
914e330a86
efinix_trion_t120_bga576_dev_kit: Add Flash support (Through openFPGALoader).
2021-10-15 09:38:43 +02:00
195bf176cf
efinix_trion_t120_bga576: Add SPIFlash support (X1 for now).
2021-10-14 19:16:01 +02:00
03c34e31cd
efinix_trion_t120_bga576: Add PLL to CRG and increase default sys_clk to 100MHz.
2021-10-14 15:45:26 +02:00
2ea803b7d1
efinix_trion_t120_bga576: Set no_we on integrated_main_ram.
...
To allow --integrated-main-ram-size use.
2021-10-14 10:19:18 +02:00
430918756d
efinix_trion_t120_bga576: Add PMODs connectors and use USB-UART/PMOD_E as Serial.
2021-10-14 10:10:42 +02:00
36897f4646
efinix_trion_t120_bga576: Disable Identifier (crashes design) and move no_we, working.
...
./efinix_trion_t120_bga576_dev_kit.py --build --load
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2021 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS CRC passed (b23a7321)
Migen git sha1: 7507a2b
LiteX git sha1: 8316fbf1
--=============== SoC ==================--
CPU: VexRiscv @ 40MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 128KiB
SRAM: 8KiB
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex>
2021-10-14 09:39:54 +02:00
ad773b6f2f
efinix_trion_t120_bga576: Fix argparse description.
2021-10-13 17:28:43 +02:00
6c17d76a92
targets/efinix_trion_t120_bga576: Switch to SoCCore (with CPU) and use button as reset (and AsyncResetSynchronizer).
2021-10-13 16:35:14 +02:00
a4d178a740
Add Efinix Trio T120 BGA576 Dev-Kit initial support (LedChaser).
2021-10-13 12:29:53 +02:00
83e64fbd64
targets/qmtech_10cl006: +x.
2021-10-13 12:16:41 +02:00
e29bcd30a6
litex_acorn_baseboard: Add some M2 signals and set devslp to 0.
2021-10-12 11:54:17 +02:00
a365362f5d
Rename litex_m2_baseboard to litex_acorn_baseboard and add link to repository.
2021-10-11 18:36:12 +02:00
fe08491e8d
litex_m2_baseboard: Add LCD.
2021-10-11 18:30:23 +02:00
393252ddc9
Merge pull request #277 from hansfbaier/master
...
Add support for QMTech 10CL006 board
2021-10-11 14:01:06 +02:00
79fe4a9199
Merge pull request #275 from alainlou/master
...
rz_easyfpga: cleanup and ease of use
2021-10-11 13:57:06 +02:00
2b2c7d3d68
trellisboard: Add PMOD GPIO support (for tests with MicroPython).
2021-10-11 11:33:13 +02:00
9e18d9bc34
gsd_butterstick: Remove ECLKBRIDGECS (not required).
2021-10-07 14:09:22 +02:00
d119b598c5
Add support for QMTech 10CL006 board
2021-10-05 12:06:41 +07:00
1b676f929a
cleanup and ease of use
...
- update README
- delete some unnecessary toolchain commands (copied from trenz boards)
- use minimal cpu_variant by default when vexriscv is selected
2021-10-03 13:21:45 -04:00
e8611794b4
Add initial QuickLogic QuickFeather support (Led Chaser).
...
Untested.
2021-10-01 10:58:26 +02:00
de4ad324cb
mnt_rkx7: Revert default sys_clk_freq to 100MHz.
2021-09-30 18:03:22 +02:00
1858273945
mnt_rkx7: Add SPI SDCard support.
2021-09-30 18:01:54 +02:00
05f3158311
mnt_rkx7: Increase default sys_clk_freq to 125MHz.
2021-09-30 16:22:18 +02:00
1217e94218
mnt_rkx7: Switch DDR3 to IS43TR16512B now added to LiteDRAM.
2021-09-30 15:45:40 +02:00
9bcae49629
mnt_rkx7: Add I2C (For the SiI9022A).
2021-09-30 15:33:53 +02:00
4f7c18a503
mnt_rkx7: Add Ethernet/Etherbone support.
2021-09-30 15:14:03 +02:00
84f0d715ff
mnt_rkx7: Add SDCard support.
2021-09-30 11:34:23 +02:00
31b404c42f
mng_rkx7: Add SPI Flash support.
2021-09-30 11:29:56 +02:00
df7fe5687e
Add initial MNT Reform Kintex-7 module (RKX7) support with Clk, UART and DDR3.
...
Compiles but untested on hardware.
2021-09-30 11:06:39 +02:00
82653cf66f
icebreaker/fomu: Fix SPRAM split.
2021-09-30 09:32:26 +02:00
5addd7f7d8
icebreaker/fomu: Split PSRAM in half: 64kB SRAM/64kB RAM).
...
Allows building bare metal demo and running it directly on these boards.
2021-09-29 19:33:22 +02:00
dfa572083a
Merge pull request #273 from ozbenh/wukong-v2
...
Wukong board improvements
2021-09-28 13:22:42 +02:00
228245075a
boards: added datacenter DDR4 RDIMM tester board
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-09-27 10:15:55 +02:00
4a52996106
Wukong board improvements
...
This adds support for v2 of the board via a --board-version argument
and a way to select the FPGA speed grade via a --speed-grade argument.
Note that the speed grade now defaults to -1. QMTech confirmed that
V1 of the board were made in two batches, one with -1 and one with -2,
while V2 of the board is all -1. So -1 is the safer default.
This also fixes the inversion of j10 and j11 and a typo in the pin
definition of jp3
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2021-09-24 12:13:56 +10:00
f18b10d1ed
Merge pull request #249 from Quiddle11/atlys
...
Initial Digilent Atlys support
2021-09-23 10:21:49 +02:00
921c300b50
digilent_atlys: Simplify/Remove entropy...
...
Build tested with ./digilent_atlys.py --with-ethernet --build.
2021-09-23 10:17:54 +02:00
1333f89ed6
rz_easyfpga: adjust SDRAM clk phase
...
- also add 1:2 rate
2021-09-22 00:26:28 -04:00
610e82d774
Add initial RZ-EasyFPGA support! ( #270 )
2021-09-21 09:55:22 +02:00
5190c9c869
sipeed_tang_nano_4k: Initial Video Out support.
...
With colorbars for now, need to free up BRAMS for Video Terminal (or finish HyperRAM support).
2021-09-20 09:32:20 +02:00
30756ce05e
targets: Update to VideoHDMIPHY.
2021-09-20 09:30:32 +02:00
7161ad18ec
sipeed_tang_nano_4k: Integrate new LiteX's GW1NSRPLL.
2021-09-20 08:40:19 +02:00
a5c5ba7652
sipeed_tang_nano_4k: Integrate HyperRam (not yet working).
2021-09-17 16:30:39 +02:00
376a836583
sipeed_tang_nano: Add SPI Flash, Enable CPU and use new external SPI Flash support from OpenFPGALoader.
...
./sipeed_tang_nano_4k.py --cpu-type=vexriscv --cpu-variant=lite --build --flash
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2021 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Sep 17 2021 15:54:08
BIOS CRC passed (6cc6de6d)
Migen git sha1: a5bc262
LiteX git sha1: 46cd9c5a
--=============== SoC ==================--
CPU: VexRiscv_Lite @ 27MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 64KiB
SRAM: 8KiB
FLASH: 4096KiB
--========== Initialization ============--
Initializing W25Q32 SPI Flash @0x80000000...
SPI Flash clk configured to 13 MHz
Memspeed at 0x80000000 (Sequential, 4.0KiB)...
Read speed: 1.3MiB/s
Memspeed at 0x80000000 (Random, 4.0KiB)...
Read speed: 521.9KiB/s
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex>
2021-09-17 15:57:55 +02:00
28571308bc
sispeed_tang_nano: Add simple UART loopback test... (Not working...)
2021-09-16 19:34:48 +02:00
5955a35372
Add initial Sipeed Tang Nano support (Clk/Leds/Buttons).
2021-09-16 19:22:30 +02:00
c0aed8a727
litex_m2_baseboard: Add Video Terminal support.
2021-09-16 18:54:50 +02:00
32a9256f3b
litex_m2_baseboard: Add SDCard support.
2021-09-16 18:17:34 +02:00
0854a5d234
litex_m2_baseboard: Add Ethernet/Etherbone support.
2021-09-16 18:02:55 +02:00
3ad0eb6992
Add initial LiteX M2 Baseboard support with Clk/Serial/Buttons.
2021-09-16 17:44:50 +02:00
26943959b5
Merge pull request #268 from trabucayre/runber_support
...
Add runber support
2021-09-15 08:32:05 +02:00
7ccae3332d
Add runber support
2021-09-15 06:50:57 +02:00
68fb163a27
targets: Remove spiflash mapping on targets where it's no longer useful.
2021-09-14 18:35:13 +02:00
db91eda899
linsn_rv901t.py: Update Ethernet and add Etherbone support.
2021-09-13 19:35:05 +02:00
b8373a361d
alchitry_mojo: new board
2021-09-10 02:40:31 -07:00
cacb76450f
Merge pull request #264 from teknoman117/alchitry-au
...
Add Alchitry Au as new board
2021-09-09 11:42:37 +02:00
8d91489756
tang_nano_4k: Add more IOs.
2021-09-09 11:23:20 +02:00
9bbdb87130
alchitry_au: new board
2021-09-09 00:03:19 -07:00
88534c6689
tang_nano_4k: Fix typo in sipeed.
2021-09-08 23:02:39 +02:00
ce52c8c5ed
beaglewire: Fix typo in qwertyembedded.
2021-09-08 21:29:29 +02:00
ecebe7e267
Add initial SiSpeed Tang Nano 4K support (Led blink only for now...).
...
./sispeed_tang_nano_4k.py --build --load
Build with Gowin EDA.
Load with OpenFPGALoader.
2021-09-08 19:36:46 +02:00
129b95f9b5
sqrl_acorn: Update pre_placement_commands with new XilinxVivadCommands.
2021-09-08 16:27:30 +02:00
7fa22a494b
arty: Switch SPI Flash rate to 1:2 (DDR) (Possible on Arty since SPI Flash's clk does not require use of STARTUPE2).
...
On the Digilent Arty, the SPI Flash's clk is connected to CCLK (that can be driven
through the STARTUPE2) but also to another generic IO that can be use to drive the
clock through DDR primitives.
2021-09-07 15:07:59 +02:00
aa2209729f
gsd_butterstick: Force uart_name to crossover when set to serial.
2021-09-02 15:23:05 +02:00
fddca1cd40
gsd_butterstick: Add SDCard (SPI & SD modes) support.
2021-09-02 14:06:09 +02:00
596f430326
gsd_butterstick: Add SPI Flash support.
2021-09-02 11:28:21 +02:00
55ea71bd01
gsd_butterstick: Add initial DDR3 support.
...
Validated with:
./gsd_butterstick.py --uart-name=crossover --with-etherbone --csr-csv=csr.csv --build --load
litex_server --udp
litex_term bridge
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2021 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Sep 1 2021 19:09:52
BIOS CRC passed (3d349845)
Migen git sha1: 27dbf03
LiteX git sha1: 315fbe18
--=============== SoC ==================--
CPU: VexRiscv @ 75MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 128KiB
SRAM: 8KiB
L2: 8KiB
SDRAM: 524288KiB 16-bit @ 300MT/s (CL-6 CWL-5)
--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Read leveling:
m0, b00: |01110000| delays: 02+-01
m0, b01: |00000000| delays: -
m0, b02: |00000000| delays: -
m0, b03: |00000000| delays: -
best: m0, b00 delays: 02+-01
m1, b00: |01110000| delays: 02+-01
m1, b01: |00000000| delays: -
m1, b02: |00000000| delays: -
m1, b03: |00000000| delays: -
best: m1, b00 delays: 02+-01
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
Write: 0x40000000-0x40200000 2.0MiB
Read: 0x40000000-0x40200000 2.0MiB
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
Write speed: 13.6MiB/s
Read speed: 15.6MiB/s
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex>
2021-09-01 19:21:16 +02:00
1f25a98476
butterstick: Add Ethernet/Etherbone support (UART crossover working over Etherbone).
2021-09-01 18:03:13 +02:00
1f149ece6b
Add intial ButterStick support (with just Clk, Buttons and Leds).
2021-09-01 17:33:54 +02:00
74c2178150
lattice_crosslink_nx_evn: don't set MASTER_SPI_PORT=SERIAL
...
Setting MASTER_SPI_PORT=SERIAL causes the SPI flash pins to be reserved
for use by the sysCONFIG logic, and prevents user logic from assigning
them. This made it impossible to have a Litex design which accesses the
SPI flash on this board.
Remove the setting, so that we get the default behaviour which permits
user logic to assign these pins. In the unlikely event that someone
needs the pins to stay reserved for sysCONFIG after configuration (I'm
not sure why this would be needed) they could explicitly add this
command in their design.
2021-09-01 18:47:17 +10:00
4731c500fb
Merge pull request #258 from danc86/clnexevn-device-arg
...
lattice_crosslink_nx_evn: allow specifying the FPGA device
2021-09-01 10:22:42 +02:00
ce254208ff
beaglewire: Review/Cleanup for consistency with other targets.
...
- Now uses regular UART.
- Build tested with: ./quertyembedded_beaglewire.py --cpu-type=serv --build
- Can still be build with Crossover UART with --uart-name=crossover+bridge.
2021-09-01 10:18:11 +02:00
35df77258a
beaglewire: Rename to quertyembedded_beaglewire.
2021-09-01 09:36:09 +02:00
1e1f6a476d
Merge pull request #254 from ombhilare999/master
...
beaglewire platform and target added
2021-09-01 09:33:07 +02:00
4a18951651
tul_pynq_z2: Fix copyrights, remove PS7 part for now.
2021-09-01 08:50:56 +02:00
54c777a49c
Merge pull request #252 from developandplay/PYNQ-Z2
...
WIP: Initial PYNQ Z2 support
2021-09-01 08:46:44 +02:00
8f1c15bdb8
ebaz4205: Remove PS7 support for now (since untested and we'll avoid the .xci in LiteX-Boards repository).
2021-08-31 18:56:47 +02:00
781d83bab6
Add support for EBAZ4205 'Development' Board
...
Usage:
```
./ebaz4205.py --cpu-type=vexriscv --build --load
```
```
$ pwd
litex-boards/litex_boards/targets
```
Tip: Use `GTKTerm` to connect to /dev/ttyUSB0 (usually) and interact
with the LiteX BIOS.
References:
- https://github.com/fusesoc/blinky#ebaz4205-development-board
- https://github.com/olofk/serv/#ebaz4205-development-board
- https://github.com/xjtuecho/EBAZ4205#ebaz4205
- https://github.com/nmigen/nmigen-boards/pull/180 (merged)
- https://github.com/olofk/corescore/pull/33
- The existing 'Zybo Z7' example
Note: The `PS7` stuff remains untested via LiteX for now.
2021-08-31 18:54:49 +02:00
b017a33f2b
targets: Fix SPI Flash mapping on target supporting --with-spi-flash.
2021-08-23 18:05:40 +02:00
cc9e39286a
lattice_crosslink_nx_evn: allow specifying the FPGA device
...
This board is documented as having the LIFCL-40-9BG400C part, but some
versions of the board exist which were fitted with LIFCL-40-8BG400CES,
an engineering sample part. The distinction is important because the
engineering sample requires a different device ID to be embedded in the
bitstream. If you try to build a bitstream for LIFCL-40-9BG400C and load
it onto LIFCL-40-8BG400CES the configuration fails (indicated by the red
"INITN" LED on this board).
Accept --device to allow the user to specify which FPGA part their board
has.
2021-08-17 18:30:03 +10:00
db9c98b28a
beaglewire platform and target added
2021-08-16 20:14:45 +05:30
22e823d756
Initial PYNQ Z2 support
2021-08-13 16:23:39 +02:00
b77b1514ce
Merge pull request #250 from david-sawatzke/fullmemwe
...
colorlight_5a_75x: Disable full_memory_we for l2 cache by default
2021-08-11 09:53:47 +02:00
9f5e8d4864
colorlight_5a_75x: Disable full_memory_we for l2 cache by default
...
Leads to an increase in DP16KD, first noticed in
https://github.com/enjoy-digital/liteeth/issues/70 .
With full_mem_we:
```
Info: DP16KD: 41/ 56 73%
```
Without:
```
Info: DP16KD: 29/ 56 51%
```
2021-08-08 14:37:46 +02:00
b81309401e
Initial Digilent Atlys support
2021-08-06 13:24:19 +02:00
615b97e205
tinyfpga_bx: Switch to LiteSPI.
2021-07-30 08:18:15 +02:00
90fcaec287
targets/radiona_ulx3s: Switch to LiteSPI.
2021-07-30 08:10:52 +02:00
fdf94b95c9
muselabe_icesugar/SPIFlash: Disable Master (to avoid wasting resources on this small FPGA).
2021-07-29 19:59:22 +02:00
218e830fbf
muselab_icesugar_pro: Switch to LiteSPI.
2021-07-29 19:58:13 +02:00
569c20ab86
muselab_icesugar: Switch to LiteSPI.
2021-07-29 19:55:32 +02:00
8df797c716
lattice_ice40up5k_evn: Switch to LiteSPI.
2021-07-29 19:50:36 +02:00
5e8c29d657
colorlight_i5: Switch to LiteSPI.
2021-07-29 19:47:41 +02:00
35ba3d9bc3
targets: Remove old call to add_spi_flash on targets now using LiteSPI (we'll find it with gitk is required).
2021-07-29 11:55:10 +02:00
54cee05986
#248 : Minor cleanup.
2021-07-28 18:20:42 +02:00
a41fbea5e6
Merge pull request #248 from JosephBushagour/jbushagour_fomu_spi_options
...
Add option for different Fomu SPI ICs.
2021-07-28 18:18:12 +02:00
99ff82c75a
xilinx_alveo_u280: Add more IOs and enable HBM2.
2021-07-28 18:11:49 +02:00
7b3dce65c1
Add option for different Fomu SPI chips.
...
Signed-off-by: Joey Bushagour <jbushagour@google.com>
2021-07-28 10:34:02 -05:00
401568c54e
digilent_arty_s7: Add SPI Flash.
2021-07-28 14:22:26 +02:00
64eadd8012
hackaday_hadbadge: Lower PLL's PFD Min from 10MHz to 8MHz.
...
This is now required since ECP5PLL now checks that PFD is in required range.
2021-07-28 12:25:17 +02:00
6ce5db1b90
qmtech_xc7a35t: Fix default build.
2021-07-28 12:23:24 +02:00
1f4383475a
decklink_intensity_pro_4k: Fix default build.
2021-07-28 12:23:12 +02:00
4e2b596ab3
digilent_arty/qmtech_xc7a35t: Rename --with-mapped-flash to --with-spi-flash.
2021-07-28 11:21:51 +02:00
fa3cc9b753
kosagi_fomu/spiflash: Switch to READ_1_1_4.
2021-07-28 11:10:34 +02:00
1118b09350
trenz_tec0117: Switch to LiteSPI.
2021-07-28 10:34:17 +02:00
9065cfa75d
kosagi_fomu: Switch to LiteSPI.
2021-07-27 19:55:04 +02:00
b3e7dbfd30
qmtech_xc7a35t: LiteSPI integration now provided by LiteX.
2021-07-27 19:39:50 +02:00
55ba0591df
targets: Remove SpiFlash imports (Obsolete since integration is provided by LiteX).
2021-07-27 19:35:19 +02:00
1c52e6b8fb
targets/digilent_arty/spiflash: LiteSPI integration now provided by LiteX.
2021-07-27 19:30:38 +02:00
15b5aec23f
1bitsquared_icebreaker_bitsy: Also switch to LiteSPI.
2021-07-27 19:27:28 +02:00
959780f372
1bitsquared_icebreaker: Switch to LiteSPI (with integration now done by LiteX).
...
Keep the old add_spi_flash call commented for now just in case we need to compare/test it.
2021-07-27 19:23:26 +02:00
533d25e845
1bitsquared_icebreaker: Enable LiteSPI Master but reduce FIFO depth to reduce resource usage.
...
Already better regarding resource usage:
Info: ICESTORM_LC: 2938/ 5280 55%
Info: ICESTORM_RAM: 2/ 30 6%
Info: SB_IO: 15/ 96 15%
Info: SB_GB: 8/ 8 100%
Info: ICESTORM_PLL: 1/ 1 100%
Info: SB_WARMBOOT: 0/ 1 0%
Info: ICESTORM_DSP: 0/ 8 0%
Info: ICESTORM_HFOSC: 0/ 1 0%
Info: ICESTORM_LFOSC: 0/ 1 0%
Info: SB_I2C: 0/ 2 0%
Info: SB_SPI: 0/ 2 0%
Info: IO_I3C: 0/ 2 0%
Info: SB_LEDDA_IP: 0/ 1 0%
Info: SB_RGBA_DRV: 0/ 1 0%
Info: ICESTORM_SPRAM: 4/ 4 100%
2021-07-27 17:38:25 +02:00
12fb315e09
1bitsquared_icebreaker: Disable LiteSPI Master.
...
Requires 80e9d2cea9
2021-07-27 17:00:55 +02:00
0f648ac4ef
1bitsquared_icebreaker: Add test code to use LiteSPI.
...
Both XiP from SPI(1X) or QSPI(4X) are working, but resource usage is currently
too high to be able to switch to it by default. We'll first try to reduce it.
Resource usage using SPI(1X) and actual LiteX SPI Flash core:
Info: Device utilisation:
Info: ICESTORM_LC: 2016/ 5280 38%
Info: ICESTORM_RAM: 2/ 30 6%
Info: SB_IO: 15/ 96 15%
Info: SB_GB: 8/ 8 100%
Info: ICESTORM_PLL: 1/ 1 100%
Info: SB_WARMBOOT: 0/ 1 0%
Info: ICESTORM_DSP: 0/ 8 0%
Info: ICESTORM_HFOSC: 0/ 1 0%
Info: ICESTORM_LFOSC: 0/ 1 0%
Info: SB_I2C: 0/ 2 0%
Info: SB_SPI: 0/ 2 0%
Info: IO_I3C: 0/ 2 0%
Info: SB_LEDDA_IP: 0/ 1 0%
Info: SB_RGBA_DRV: 0/ 1 0%
Info: ICESTORM_SPRAM: 4/ 4 100%
Resource usage using LiteSPI:
Info: Device utilisation:
Info: ICESTORM_LC: 3964/ 5280 75%
Info: ICESTORM_RAM: 2/ 30 6%
Info: SB_IO: 15/ 96 15%
Info: SB_GB: 8/ 8 100%
Info: ICESTORM_PLL: 1/ 1 100%
Info: SB_WARMBOOT: 0/ 1 0%
Info: ICESTORM_DSP: 0/ 8 0%
Info: ICESTORM_HFOSC: 0/ 1 0%
Info: ICESTORM_LFOSC: 0/ 1 0%
Info: SB_I2C: 0/ 2 0%
Info: SB_SPI: 0/ 2 0%
Info: IO_I3C: 0/ 2 0%
Info: SB_LEDDA_IP: 0/ 1 0%
Info: SB_RGBA_DRV: 0/ 1 0%
Info: ICESTORM_SPRAM: 4/ 4 100%
2021-07-27 16:50:18 +02:00
0ca203487b
pr243: Make led_chaser optional.
2021-07-27 15:00:18 +02:00
9835bd5f93
targets/muselab_icesugar_pro: +x.
2021-07-27 14:56:33 +02:00
2df3f9e664
pr243/platforms: Consistency with other platforms.
2021-07-27 14:55:19 +02:00
2418df9f2b
pr243: Add @tweakoz copyrights.
2021-07-27 12:21:23 +02:00
369d2cf49d
Merge pull request #243 from tweakoz/master
...
add FPGA Boards (Digilent CMOD A7, Digilent Nexys 4, Micronova Mercury2)
2021-07-27 12:17:04 +02:00
10bfd50e22
targets/1bitsquared_icebreaker: Revert to 128KB SPRAM.
2021-07-27 12:03:39 +02:00
4d20cfe5cd
Merge pull request #245 from racerxdl/feat/MuselabIceSugarPro
...
muselab_icesugar_pro: initial support
2021-07-23 14:34:57 +02:00
5852dbb88f
muselab_icesugar_pro: initial support
2021-07-22 11:26:27 -03:00
a3f479837c
digilent_arty: Allow exposing raw PMOD IOs (for tests with MicroPython).
2021-07-21 13:50:12 +02:00
a455713e0c
kosagi_fomu: Handle bios_flash_offset in flash function and make DFU flash offset explicit.
2021-07-21 11:41:35 +02:00
fbcecee1f8
Merge pull request #242 from tcal-x/fix-basys3-rst
...
Basys3: Invert reset button, so that the board is reset when btnc is pushed.
2021-07-20 19:47:53 +02:00
8c8e163eee
trenz_tec0117: Add SDCard (SPI and SD mode), move SPI Flash to 0x00000000 and use default l2_cache_min_data_width.
2021-07-20 17:25:51 +02:00
75cadf845f
add FPGA Boards
...
1. Digilent CMOD A7
https://reference.digilentinc.com/programmable-logic/cmod-a7/start
2. Digilent Nexys 4
https://reference.digilentinc.com/programmable-logic/nexys-4/start
3. MicroNova Mercury 2
https://www.micro-nova.com/mercury-2
2021-07-17 22:03:17 -06:00
5da2bdefb7
Invert reset button, so that board is reset when btn is pushed.
...
Signed-off-by: Tim Callahan <tcal@google.com>
2021-07-16 13:08:18 -07:00
4b48f15265
Merge pull request #236 from JosephBushagour/jbushagour_with_led_chaser
...
Add with_led_chaser argument to constructor of boards using LedChaser submodule.
2021-07-16 14:41:05 +02:00
6648b2f907
targets/trenz_tec0117: Switch SPI Flash to QSPI mode.
2021-07-15 09:15:34 +02:00
c369f4bb7f
trenz_tec0117: Get BIOS XiP from SPI Flash working, remove CPU variant force since can now fit default VexRiscv config.
2021-07-14 12:49:03 +02:00
132feaf3e8
trenz_tec0117: Prepare for 1:2 SDRAM rate (Not yet working at 1:2 but one step closer...).
2021-07-14 10:43:26 +02:00
ba8321a3ab
trenz_tec0117: Use new DDROutput to generate SDRAM Clk.
2021-07-14 10:02:58 +02:00
94b985ac56
trenz_tec0117: Use new integrated reset from GW1NPLL.
2021-07-14 09:55:00 +02:00
6e31d12fa9
trenz_tec0117: Avoid forcing CPU type (only force to lite variant when VexRiscv is selected=default).
2021-07-13 19:39:53 +02:00
1920db3535
Add with_led_chaser argument to constructor of boards using LedChaser submodule.
2021-07-06 16:39:37 -05:00
8c1e6c6a02
decklink_quad_hdmi_recorder: Remove WIP (SoC + DDR3 now working) and add build/use instructions.
2021-07-02 15:54:57 +02:00
2dff854b7a
decklink_quad_hdmi_recorder: Enable second DDR3 module.
2021-07-02 15:52:12 +02:00
a02855d105
decklink_quad_hdmi_recorder: Increase sys_clk to 200MHz.
2021-07-02 15:07:13 +02:00
b18f6a2c7f
decklink_quad_hdmi_recorder: Enable DRAM modules 0 and 1, fix pre placement constraints.
2021-07-02 14:32:53 +02:00
7442639a5e
targets/digilent_arty: Add default value for CRG's with_mapped_flash.
...
Otherwise break retro-compat on external design importing CRG without passing this new parameter.
2021-07-02 09:33:06 +02:00
1b65bad4c2
decklink_quad_hdmi: Add Clk IOs, use clk200 as primary clk and add JTAGBone.
2021-07-01 20:00:35 +02:00
e65308ee13
decklink_quad_hdmi_recorder: Add DDR3 SDRAM (only first module), building but untested.
2021-06-30 09:40:08 +02:00
84cb5d797d
decklink_intensity_pro_4k: Add WIP.
2021-06-30 09:06:00 +02:00
ebfb4fad57
Add initial Decklink Intensity Pro 4K support (with documented PCIe / Untested).
2021-06-24 19:55:40 +02:00
5f8560bf69
Add initial Decklink Quad HDMI Recorder support (with documented PCIe/HDMI In).
...
LitePCIe Gen3 X4 enumerating correctly.
2021-06-24 19:48:31 +02:00
8ec1435e65
targets/decklink_mini_4k: Fix typos.
2021-06-24 19:13:18 +02:00
87cd56d187
targets: Add new 1bitsquared_icebreaker_bitsy target
...
Most basic SoC ever but ... it runs
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2021-06-21 22:11:53 +02:00
caac75c7db
trenz_max1000: Review/Cleanup.
2021-06-16 18:04:55 +02:00
8ef138eaa0
added MAX1000 board
2021-06-16 17:55:06 +02:00
fa045e6fa4
enclustra_mercury_kx2: Comment user_led2/3 (Conflicting with DRAM pins).
2021-06-16 11:54:52 +02:00
588b430a0c
Merge pull request #217 from hansfbaier/master
...
QMTech EP4CE15: Add daughterboard support, small DECA addition
2021-05-25 10:15:26 +02:00
df10fc54ad
muselab_icesugar/trenz_cyc1000: +x.
2021-05-25 08:46:33 +02:00
1c4825e7c4
basys3: Review/Simplify and fix build.
2021-05-25 08:44:26 +02:00
25867c4dcb
Merge pull request #218 from helium729/master
...
Add digilent basys3 board support
2021-05-23 19:46:58 +02:00
dd5a4bdc92
CYC1000: Add initial support of CYC1000 board
2021-05-22 21:17:27 +02:00
bf123db20b
icebreaker/fomu: Update flashing and disconnect reset from SoC (will need proper support in iCE40PLL).
2021-05-20 09:14:54 +02:00
ce5b2a74a1
add digilent basys3 support
2021-05-17 16:39:16 +08:00
f01e0c02c9
qmtech ep4ce15: Add daughterboard support, add spiflash
2021-05-15 13:16:43 +07:00
c010b9a335
Merge pull request #215 from hansfbaier/qmtech-xc7a35t
...
Qmtech xc7a35t
2021-05-10 08:31:08 +02:00
df447ddc87
QMTech XC7A35T: fix argument parser description
2021-05-08 08:49:07 +07:00
e99272cb07
muselab_icesugar: Modify comments a bit.
2021-05-07 08:57:34 +02:00
5ae130661f
Merge pull request #213 from hansfbaier/icesugar
...
muselab_icesugar: first basic version which boots
2021-05-07 08:50:50 +02:00
2c2a9db3cc
Merge pull request #212 from hansfbaier/qmtech-xc7a35t
...
add QMTECH XC7A35T core board + daughter board
2021-05-07 08:32:16 +02:00
9e86c094c9
Merge pull request #211 from Acathla-fr/master
...
Lattice iCE40 UltraPlus Breakout board (iCE40UP5K-B-EVN) added
2021-05-07 08:30:01 +02:00
c2e0f6026e
muselab_icesugar: first basic version that boots
2021-05-07 11:50:28 +07:00
3bb84b0071
Add initial Blackmagic Decklink Mini 4K support (with UART, DDR3, PCIe, Video Out).
...
Mini Monitor 4K and Mini Recorder 4K are almost the same hardware with just changes on
the Video In/Out. For now tests have been done on the Mini Monitor 4K, but the aim is
support both boards in the same platform/target in the future, thus the mini_4k naming.
These boards could be used as affordable Artix7 dev boards for LiteX, to run Linux with
LiteX (512MB of RAM + a Video Framebuffer) or to create custom systems like a fast software
defined signal generator/recorder directly from a PC over PCIe, custom HDMI/SDI video
cards, etc... lots of possibilities :)
2021-05-06 09:47:01 +02:00
eec1078736
add QMTECH XC7A35T core board + daughter board
2021-05-06 05:50:48 +07:00
213d100860
Lattice iCE40 UltraPlus Breakout board (iCE40UP5K-B-EVN) added
2021-05-04 12:19:21 +02:00
026c623e17
Merge pull request #207 from hplp/master
...
Minor fixes for AU280 [work in progress]
2021-05-03 10:20:34 +02:00
2c5bf95f70
targets/trenz_tec0117: Switch to new GW1NPLL.
2021-04-30 11:32:24 +02:00
4f45462b95
Merge branch 'master' of https://github.com/litex-hub/litex-boards
2021-04-29 15:41:03 -04:00
9686db0ed3
targets: Update names in build descriptions.
2021-04-29 11:56:52 +02:00
6117b98049
siglent_sds1104xe: Avoid disabling hardware interface with BIOS ethernet reset.
2021-04-29 11:52:41 +02:00
c28a161392
siglent_sds1104xe: Expose ethphy (to allow correct .dts generation).
2021-04-29 11:02:13 +02:00
7d651a9a17
siglent_sds1104xe: Switch to VideoVGAPHY and adjust timings.
2021-04-29 10:41:19 +02:00
cfbcb8538d
siglent_sds1104xe: Use custom 800x480 video timings.
2021-04-28 16:59:09 +02:00
84e65d2113
Merge pull request #204 from hansfbaier/master
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terasic_sockit: fix: make video clock also optional as video terminal is optional
2021-04-28 09:42:13 +02:00
be6d08aff1
Merge pull request #205 from antmicro/jboc/lpddr4-tb-eth-delay
...
antmicro_lpddr4_test_board: fix ethernet rx delay issue
2021-04-28 09:41:11 +02:00
8ad91d9eb3
fix cmdltncy, with_led
2021-04-27 17:30:56 -04:00
f7ee3fa454
sds1104xe: Framebuffer fixes.
2021-04-27 19:32:03 +02:00
694608688d
terasic_sockit: fix: make video clock also optional as video terminal is optional
2021-04-27 08:52:11 +07:00
5bfeb999e4
targets/digilent_arty/flash: Simplify, use Quad mode and sys_clk (fast enough ~5MB/s).
2021-04-26 16:30:35 +02:00
2854df5028
Arty: move spiflash PHY do 4x faster clk domain
...
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2021-04-26 12:52:36 +02:00
84ae2b2bbc
arty: add option to use litespi QSPI controller
...
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2021-04-26 12:52:30 +02:00
2d2a10621f
antmicro_lpddr4_test_board: fix ethernet rx delay issue
2021-04-23 15:25:47 +02:00
228a9650d4
sqrl_acorn: Add flashing/reload support when used with PCIe, fix JTAG flash.
2021-04-21 17:00:40 +02:00
d2eabd112d
Add E-Elements Ego1 initial board support.
2021-04-12 08:20:46 +02:00
cd3d4c826e
Add Trenz te0725 initial board support.
2021-04-12 08:16:45 +02:00
5519c931f8
xilinx_alveo_u280: Fix DDR4 (tested with 8 modules on C0 and C1).
2021-04-12 08:07:16 +02:00
d5318dcb03
Qmtech Wukong: updates
...
fix ethernet clock (it's a GMII), add FB support over the HDMI connector (hdmi clock set from the resolution)
2021-04-10 16:26:25 +02:00
03accabc25
lpddr4_test_board: Add antmicro vendor prefix.
2021-03-31 09:48:23 +02:00
a834985e00
Add target for LPDDR4 Test Board
2021-03-30 14:50:02 +02:00
d5ce1901d8
targets/digilent_nexys_video: Add specific Video PLL to give more flexibility on supported Video Timings.
2021-03-30 10:17:50 +02:00
9417044584
targets: Minor cleanup, make sure all targets can be built with default settings.
2021-03-29 16:22:39 +02:00
1ca8ef97a1
targets/add_sdram: Specific size only when useful (ie for targets with > 1GB of RAM).
2021-03-29 16:03:19 +02:00
ba01776432
targets/add_sdram: Simplify call by removing useless arguments.
...
- main_ram mem_map is now directly used by add_sdram when origin is None.
- max_sdram_size/min_l2_data_width are no longer exposed as targets arguments this can
still be used enforced directly in the few cases it is useful.
2021-03-29 15:28:31 +02:00
58286ce29e
minispartan6: Change video resolution to 640x480, framebuffer working with Linux-on-LiteX-Vexriscv.
2021-03-29 14:36:34 +02:00
09700b28d0
ulx3s: Change video resolution to 640x480, framebuffer working with Linux-on-LiteX-Vexriscv.
2021-03-29 11:35:55 +02:00
73ce7f9df1
ztex213 fix; propagate variant from targets to platform
2021-03-27 11:04:51 +01:00
7c537748a0
colorlight_i5: Remove PRBS (too specific to application).
...
If useful for several boards, this should probably be provided directly by LiteX.
2021-03-27 09:31:48 +01:00
7737575b88
terasic_deca: Remove --integrated-ram-size parameter (--integrated-main-ram-size provides the same functionnality).
2021-03-27 08:58:49 +01:00
f714e1210a
terasic_deca: Remove enforced CPU variant/debug: --cpu-variant=imac or --cpu-variant=imac+debug can be used for this.
...
The default CPU/Variant is defined in LiteX, enforcing the variant on the target
prevent usage of the other CPUs and also complicate maintenance.
2021-03-27 08:56:46 +01:00
a48def1352
rhsresearchllc_litefury: Remove since already supported by ./acorn.py --variant=cle-101.
2021-03-26 23:54:56 +01:00
4329a69128
sqrl_acorn_cle_215: Rename to sqrl_acorn and add support for all variants (CLE-101, 215 and 215+).
2021-03-26 23:52:36 +01:00
87df45e625
siglent_sds1104xe: Allow build without Etherbone.
2021-03-26 23:25:42 +01:00
c6ced293d4
targets/siglent_sds1104xe: Integrate VideoTerminal/VideoFrameBuffer.
2021-03-26 22:55:25 +01:00
b54eed0859
terasic_sockit: Review/Cleanup for consistency with other boards.
2021-03-26 22:39:19 +01:00
53a767c85c
terasic_deca: Review/Cleanup for consistency with other boards.
2021-03-26 22:12:13 +01:00
be4965ca78
Merge pull request #192 from hansfbaier/deca_fixes
...
terasic_deca: fix cable name, ulpi, names, add gpio_serial
2021-03-26 21:52:31 +01:00
9fea5a7fc6
targets/digilent_nexys_video: Cleanup/Simplify #191 .
2021-03-26 21:49:22 +01:00
df58639916
nexys_video: choose VADJ value with arguments
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-03-26 14:50:05 +01:00
8c0ddd140b
terasic_deca: fix cable name, ulpi, names, add gpio_serial
2021-03-26 10:46:37 +07:00
e2de69496a
targets/lattice_crossing: Avoid direct override of SoCCore.mem_map (break default SoCore.mem_map with updated imports).
2021-03-25 22:41:26 +01:00
b284fe47c3
targets/terasic_sockit: Fix compilation.
2021-03-25 19:35:44 +01:00
22f167dde4
targets/sqrl_acorn_cle_215: Add missing false path constraints.
2021-03-25 18:19:20 +01:00
7d130d6981
targets/pcie: Cleanup.
2021-03-25 17:47:06 +01:00
333fb362ca
Move import Compat directly to litex_boards.__init__.py and simplify.
2021-03-25 16:47:47 +01:00
062b899e29
platforms/targets: Add mode Vendor prefixes.
2021-03-25 16:19:11 +01:00
7633eae360
targets/colorlight_i5: Remove l2-size args (already provided by soc_core_args.
2021-03-25 14:44:52 +01:00
5253a3c43e
test/ci: Fix/Update.
2021-03-25 14:21:13 +01:00
9a45c49918
targets/versa_ecp5: Also add Vendor prefix.
2021-03-25 14:13:32 +01:00
8a3cacae32
boards: Add Vendor prefix to platforms/targets name when useful and when multiple boards from the same vendor. (With Retro-Compat on the imports).
2021-03-25 14:11:17 +01:00
219067ed3a
Merge pull request #190 from kazkojima/colorlight_i5-video
...
colorlight_i5: Integrate Video Terminal and Video Framebuffer with ne…
2021-03-25 10:28:52 +01:00
47bdf5f759
targets: Use new CSR automatic allocation (self.add_csr will still work but is no longer required).
2021-03-25 10:11:24 +01:00
b3786c5e52
fomu/icebreaker: Update Up5KSPRAM import (litex.soc.cores.up5kspram deprecated, still supported for now but triggers a compat notice).
2021-03-24 17:22:55 +01:00
5995769b46
targets: Switch to soc_core_args/soc_core_argdict (instead of soc_sdram that is now deprecated, but still supported for now).
2021-03-24 17:22:51 +01:00
cb4e00c3f2
colorlight_i5: Integrate Video Terminal and Video Framebuffer with new VideoECP5HDMIPHY.
2021-03-20 07:56:59 +09:00
ddd46205aa
ulx3s: Integrate Video Terminal and Video Framebuffer with new VideoECP5HDMIPHY.
2021-03-18 15:06:35 +01:00
4330769add
minispartan6: Integrate Video Terminal and Video Framebuffer with new VideoS6HDMIPHY.
2021-03-18 14:10:42 +01:00
8b69ee57a6
arrow_sockit: get video terminal working on VGA
2021-03-16 12:31:41 +07:00
75f7120ff9
targets/Ultrascale: Fix build since idelay's reset is now handled by the PLL (with_reset=True).
2021-03-11 10:00:06 +01:00
8d3aaa8ea9
targets/nexys_video: Revert clk100 to avoid breaking Linux-on-LiteX-VexRiscv (we'll remove it when the switch the simple framebuffer will be done).
2021-03-11 09:48:26 +01:00
0e2d9a571e
alveo_u280: Fix copyrights (avoid too much cascading on Platforms/Targets) and generate reset on idelay clock domain (similarly to recent change on others Ultrascale+ boards).
2021-03-10 11:23:27 +01:00
f4ea3fb0d9
Merge pull request #168 from hplp/alveo_u280
...
Alveo U280 board
2021-03-10 11:16:32 +01:00
61f44739d7
Merge pull request #185 from stffrdhrn/arty-jtagbone
...
arty: Add an option to enable jtagbone
2021-03-10 11:12:20 +01:00
47faaf20d5
deca: Integrate Video Terminal (untested, resource issue).
2021-03-09 15:02:30 +01:00
8fb80053f7
targets/versa_ecp5: Fix LiteEthPHYRMGII tx/rx delays (need to be updated due to a bug fix in the ECP5RGMII PHY).
2021-03-08 17:39:13 +01:00
9cdcb8cb43
ecpix5: Add Etherbone (--with-etherbone).
2021-03-08 13:45:09 +01:00
52ce49cf0c
arty: Add an option to enable jtagbone
...
Then adds jtagbone for arty. I have tested with the following
litex_server and it seems to work fine.
litex_server --jtag --jtag-config openocd_xc7_ft2232.cfg
Note, the jtagbone and etherbone may be mutually exclusive, but I am not
sure how to define that in the args.
2021-03-08 07:05:54 +09:00
e280bff1ec
targets/video: Simplify/Cleanup integration.
2021-03-05 14:40:27 +01:00
ce669ac8cd
targets/nexys_video: Add optional VideoTerminal/VideoFramebuffer.
2021-03-05 14:33:22 +01:00
21207533b0
targets/Ultrascale(+): Generate Reset to idelay clock domain (to be sure to follow UG571 reset sequence).
2021-03-04 19:49:03 +01:00
71652e8d44
icebreaker: Lower VideoTerminal resolution to use default 24MHz sys_clk.
2021-03-04 18:29:21 +01:00
253d8129af
nexys4ddr: Integrate simple VideoFrameBuffer.
2021-03-03 20:00:31 +01:00
51a0bbfa65
platforms/targets: Harmonize VGA pins and use new Video Terminal on all targets with VGA support.
2021-03-03 18:05:24 +01:00
465a95d2a6
icebreaker/nexys4ddr: Use new LiteXSoC's add_video_terminal method to add the Video Terminal.
2021-03-03 17:47:20 +01:00
3af8ec0c8d
targets/nexys4ddr: Replace VGA terminal with new LiteX's VideoTerminal.
2021-03-03 17:10:22 +01:00
7e3b8ab3b5
icebreaker: Add optional DVI Video Terminal with new LiteX's VideoOut core.
...
Tested with: ./icebreaker.py --cpu-type=serv --with-video-terminal --build --flash
https://twitter.com/enjoy_digital/status/1365324823447171074
2021-03-03 16:21:04 +01:00
aa5c4f9e5a
Merge branch 'master' into arty-numato-sdcard-pmod
2021-02-25 09:37:34 +01:00
768c10c630
targets/arty: rebase/merge PR179, rename adaptor to adapter.
2021-02-25 09:36:26 +01:00
6f558a5d65
Add board support for Terasic/Arrow DECA board
2021-02-25 12:25:43 +07:00
98c80f0b2b
Merge pull request #177 from antmicro/arty-dynamic-ip
...
target/arty: add eth_ip_configurable switch
2021-02-24 09:29:55 +01:00
08ccf384aa
targets/arty: Allow selection of sdcard mod adaptor
...
The default stays with the Digilent/Antmicro layout, but the user can
optionally provide --sdcard-adaptor numato to use the Numato layout.
Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-02-24 14:59:50 +10:30
ae0d4dc0d8
target/arty: add eth_dynamic_ip switch
2021-02-23 21:01:27 +01:00
aad8154e3a
targets/sds1104xe: Enable both Ethernet/Etherbone with hybrid LiteEthMAC.
2021-02-23 15:27:50 +01:00
11405d9ee3
targets/sds1104xe/BaseSoC: Enable Etherbone by default also defaults to Crossover UART when kwargs is empty.
2021-02-18 19:30:05 +01:00
9a94e835c3
sockit: Add an option to plug in an UART via the GPIO daughter board
2021-02-10 14:52:19 +07:00
ea58ef94a7
Merge pull request #170 from hansfbaier/master
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arrow_sockit: add support for MiSTer XS SDRAM modules
2021-02-04 16:44:58 +01:00
38242b713f
Merge pull request #171 from antmicro/symbiflow_nexys_video_support
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nexys_video: enable symbiflow toolchain
2021-02-04 16:42:34 +01:00
e6d05001aa
use parameter for dram channel 0 or 1 and LedChaser
2021-02-03 17:29:30 -05:00
cdff5e3ca3
nexys_video: enable symbiflow toolchain
...
Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
2021-02-03 14:52:54 +01:00
c64e13f687
arrow_sockit: add support for MiSTer XS SDRAM modules
2021-02-03 09:37:03 +07:00
8692ed462f
targets/colorlight_i5: use .bit stream instead of .svf when loading.
2021-02-03 08:17:24 +09:00
31d7f810e7
use SDRAM C1 sysclk and constraints
2021-02-02 11:15:25 -05:00
f32c61d5d2
Merge pull request #163 from garytwong/friendly-incompatible-options
...
Be friendlier about incompatible options.
2021-02-02 08:51:46 +01:00
7c48af9b50
tec0117: get SDRAM working and increase sys_clk_freq to 25MHz.
...
./tec0117.py --build --load
Still some FIXMEs but validate use of the embedded SDRAM with LiteDRAM/LiteX:
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2020 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Feb 1 2021 13:09:35
BIOS CRC passed (5abceb2e)
Migen git sha1: 40b1092
LiteX git sha1: f324f953
--=============== SoC ==================--
CPU: VexRiscv_Lite @ 25MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 24KiB
SRAM: 4KiB
L2: 0KiB
SDRAM: 8192KiB 16-bit @ 25MT/s (CL-2 CWL-2)
--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2MiB)...
Write: 0x40000000-0x40200000 2MiB
Read: 0x40000000-0x40200000 2MiB
Memtest OK
Memspeed at 0x40000000 (2MiB)...
Write speed: 5MiB/s
Read speed: 6MiB/s
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex> mem_list
Available memory regions:
ROM 0x00000000 0x6000
SRAM 0x01000000 0x1000
SPIFLASH 0x80000000 0x1000000
MAIN_RAM 0x40000000 0x800000
CSR 0x82000000 0x10000
litex> mem_test 0x40000000 0x800000
Memtest at 0x40000000 (8MiB)...
Write: 0x40000000-0x40800000 8MiB
Read: 0x40000000-0x40800000 8MiB
Memtest OK
litex>
2021-02-01 13:32:01 +01:00
51c5d69586
targets/tec0117: use custom CPU/ROM/SRAM config to minimize resources.
2021-02-01 13:31:56 +01:00
538878ce13
tec0117: disable BIOS XIP from SPI Flash for now since not working (SPÏ Flash set to power down mode with bitstream?).
2021-02-01 13:31:51 +01:00
6cce07d9db
tec0117: add spiflash4x pins, rework flash function to flash both bitstream/bios.
2021-02-01 13:31:44 +01:00
0831b33285
tec0117: fix copyrights.
2021-02-01 13:31:39 +01:00
5e4b29c0b5
sockit: Fix cable name, default to jtag_atlantic
2021-02-01 11:48:06 +07:00
601c297c8f
Merge pull request #164 from rdolbeau/ztex213
...
Support file for the ZTEX USB-FPGA Module 2.13
2021-01-30 21:43:07 +01:00
31df53ef0a
Add flash to SPI flash support for board ECPIX5 (needs update to openfpgaloader.py from litex to work)
2021-01-30 13:19:08 +01:00
027e57b851
Support file for the ZTEX USB-FPGA Module 2.13
2021-01-30 05:19:18 -05:00
99e2f04ee5
Be friendlier about incompatible options.
...
Collect --with-ethernet/--with-etherbone, --with-spi-sdcard/--with-sdcard,
etc. into ArgumentParser.add_mutually_exclusive_group()s. That way, we
get pretty --help output, and appropriate error messages if somebody
tries to ask for something that doesn't make sense.
2021-01-29 18:08:38 -07:00
abccd12058
tec0117: add initial SDRAM support for the embedded SDRAM of the SIP.
...
Still a WIP but able to do the P&R with modifications on LiteX to generate
the IO_PORT constraints but not the IO_LOC for the SDRAM pins.
2021-01-29 22:28:40 +01:00
edb99797aa
targets/tec0117: minor cleanups.
2021-01-29 21:25:10 +01:00
3deeb69531
targets/fpc_iii: review/cleanup to increase similarities with others targets to ease maintenance.
2021-01-29 08:46:31 +01:00
4e5bb1bf1e
Add FPC-III board support.
...
FPC-III is the Free Permutable Computer; details on the board are
available from:
https://repo.or.cz/fpc-iii.git
2021-01-28 09:51:42 -07:00
9bd667720d
targets/ecpix5: add LedChaser with red leds.
...
Fits nicely LambdaConcept colors and Blue/Green leds are too bright and would need to be controlled through a PWM.
2021-01-28 14:29:07 +01:00
bd716d956f
netv2: add device variant to allow 100T as well
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-01-28 13:19:53 +01:00
aef78831c8
colorlight_i5: Use tx_delay=0 for LiteEthPHYRGMII instead of target specifig bios initialization
2021-01-27 18:19:27 +09:00
84656a9c2e
re-compare and adjust to u250
2021-01-26 23:03:09 -05:00
c3fa0eac8b
Add colorlight i5 board support
2021-01-27 11:44:59 +09:00
5fd04a97ea
targets/netv2/pcie: reduce max_pending_requests to 2 to reduce resource usage.
2021-01-26 11:01:51 +01:00
d256cc8bd6
camlink_4k: disable leds when serial is used (since pin is shared).
2021-01-25 12:19:29 +01:00
1e1bec10c4
orangecrab: remove dm_remapping workaround: we are now using Wihsbone/L2 path with VexRiscv-SMP on this board.
2021-01-25 11:52:59 +01:00
537f494cbb
arrow_sockit: review/harmonize with others boards.
2021-01-25 09:14:46 +01:00
bbaa2fdc98
Merge pull request #149 from hansfbaier/master
...
Add board support for Terasic/Arrow SocKit, Add connectors to de0-nano
2021-01-25 08:55:48 +01:00
45f538b1d3
Merge pull request #155 from blakesmith/add_spi_flash
...
ULX3S: Make spiflash optionally accessible from the SoC, and bootable
2021-01-24 21:22:35 +01:00
72985c72ca
Merge pull request #153 from Disasm/ecpix5-add-45f
...
ECPIX-5: add option to select ECP5 device
2021-01-24 21:14:14 +01:00
cae51c0c24
ULX3S: Make spiflash optionally accessible from the SoC, and bootable
2021-01-23 14:44:26 -06:00
c9f0745d54
sockit: add board definitions for Terasic SocKit
2021-01-23 20:17:38 +07:00
23760e2eae
orangecrab/CRGSDRAM: add missing rst signal (to reset from the SoC).
2021-01-22 22:55:02 +01:00
a678672fc9
ecpix5: add option to select ECP5 device
2021-01-19 01:22:52 +03:00
e71a4940c0
nexys4ddr: etherbone support
2021-01-15 12:14:40 -05:00
7a738245af
fix bitstream problem
2021-01-14 21:53:25 -05:00
5a73eb0b6d
initiate target and platform for alveo_u280 board
2021-01-14 18:35:43 -05:00
6a5f2f59a6
targets/orangecrab: use new ECP5DDRPHY's cmd_delay to add extra delay on DDR3's Clock/Commands.
...
This fixes https://github.com/enjoy-digital/litedram/issues/130 and has been tested
at 48/64/96MHz on MT41K64M16 and MT41K512M16 variants.
Also remove un-needed cd_sys2x_eb.
2021-01-12 18:57:22 +01:00
9ff90eb9fe
targets/c10lprefkit: fix default sys-clk-freq.
2021-01-12 16:15:52 +01:00
0a7443d273
targets/orangecrab: make usr_btn optional to fix compilation with revision 0.1.
2021-01-08 19:30:37 +01:00
ae5494d7b6
orangecrab: defaults to USB-ACM UART.
2021-01-08 19:01:41 +01:00
c6e75122d9
sds1104xe: defaults to Crossover UART.
2021-01-08 19:00:41 +01:00
ab72f69937
targets/ac701: rename --ethernet-phy to --eth-phy for consistency with others targets.
2021-01-08 18:50:01 +01:00
0ee62dd681
add etherbone ip address option for relevant boards
2021-01-08 18:44:31 +01:00
869cce2bba
targets/colorlight_5a_75x: rename etherbone-ip args to eth-ip.
...
eth-ip will also be used to configure Ethernet IP addresss.
2021-01-07 09:26:38 +01:00
c829a47c31
targets/colorlight_5a_75x: Automatically disable Led Chaser when serial is used.
2021-01-07 09:17:28 +01:00
adbcc81ecf
Merge pull request #145 from hansfbaier/master
...
colorlight: Add option for etherbone ip address and LED chaser
2021-01-07 09:08:43 +01:00
a6e867c691
Merge pull request #144 from gsomlo/gls-genesys2-sdcard
...
genesys2: LiteSDCard support
2021-01-07 08:12:24 +01:00
d73bd2f7ce
targets/xilinx: add comment on sys_clk to pll.clkin false path.
2021-01-07 08:01:54 +01:00
1ac1c6857f
targets/xilinx: add false path constraint between sys_clk and pll.clkin.
...
The SoC reset added recently creates a path between sys_clk and pll.clkin
clock domains that is reported by the tools but that can be safely ignored.
2021-01-07 00:02:46 +01:00
0d69cfa6b0
colorlight: make LEDs optional
2021-01-05 08:03:26 +07:00
4bec17e1a7
colorlight: Add option for etherbone ip address
2021-01-05 07:49:44 +07:00
2589d9f704
genesys2: add (spi-)sdcard build options
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2021-01-04 13:57:21 -05:00
fe67766fb7
targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl).
2021-01-04 11:38:07 +01:00
0e3c03f2f6
mercury_xu5: remove unneeded cmd_latency=0 (now defaulting to 0).
2021-01-04 10:48:34 +01:00
5cc49bafbd
orangecrab: Run reset_timer with por/48MHz clock domain (sys clock domain is now directly reseted on usr_btn press).
2021-01-04 09:42:05 +01:00
1fb24d4c71
orangecrab: Avoid usb clock domain reset on usr_btn press or SoC reset.
...
Allows the USB-ACM link to stay up during reset.
2021-01-04 09:05:19 +01:00
06cb49af37
targets/arty: add variant support through --variant args.
...
./arty.py --variant=a7-35 or a7-100
./arty_s7.py --variant=s7-50 or s7-25
2020-12-29 18:43:14 +01:00
02a81d54e2
targets/ecpix5/eth: set rx_delay to 0ns (tested with netboot on R01).
2020-12-29 16:01:12 +01:00
84098d2de5
targets/qmtech_wukong: submitted target was the platform file, update with target shared in #133 .
...
Build tested with /qmtech_wukong.py --with-sdcard --with-ethernet --integrated-rom-size=0x10000 --build.
2020-12-29 14:13:11 +01:00
e380f24655
targets/qmtech_wukong: +x.
2020-12-29 13:24:41 +01:00
4b721eded7
add QmTech Wukong board support.
2020-12-29 13:20:42 +01:00
9beaf25822
nexys4ddr: fix eth/int_n pin (B8) and use 4-bit on vga.blue.
2020-12-24 10:15:29 +01:00
2a04c5c74e
nexys4ddr: add support for litexvideo VGA Terminal
...
This commit adds VGA support for the Nexys A7/ Nexys 4 DDR.
The VGA is however limited to RGB443 instead of the full 12bit RGB444.
This is because IO D8 which is MSB for Blue, is also used for ETH int_n.
This makes the final output have a yellow tint.
2020-12-23 02:24:18 +05:30
f6a106cdf4
Fix orangecrab target
2020-12-20 01:07:43 +03:00
00fc2c5166
targets/orangecrab: use new DM remapping capability of LiteDRAM to fix LDM/UDM.
...
Required by VexRiscv-SMP that uses DMs on LiteDRAM interface.
2020-12-16 11:52:58 +01:00
bb58258fd4
Fix de10nano target
2020-12-14 15:27:33 +03:00
519f9449fa
targets/sds1104: litex_term now directly supports crossover uart.
2020-12-10 13:56:01 +01:00
18337cdf25
targets/arty: sync with litex repository
...
Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
2020-12-07 17:32:40 +01:00
8e5f955e4e
targets/orangecrab: Fix --sdram-device help text
...
Obviously --sdram-device takes the SDRAM device, not the ECP5 FPGA
device.
Fixes: bf3c9dc9bf
2020-12-04 14:34:01 +01:00
fe563baec7
targets/fomu: modification to ValentyUSB no longer required.
...
Following commits make it generic/portable while still using IOBuffers:
77b9d01058371526e432
2020-11-27 19:40:45 +01:00
5a4e28d47d
target/usb_acm: switch git clone to litex-hub/valentyusb repo (up to date with LiteX).
2020-11-27 18:53:45 +01:00
8d1095224f
add support for redpitaya14/16
2020-11-26 06:54:11 +01:00
11fa5c34ac
nexus: Allow selection of toolchain
...
Signed-off-by: David Shah <dave@ds0.me>
2020-11-25 09:45:25 +00:00
159a0c751c
targets/colorlight_5a_75x: update instructions and LiteEthPHYRGMII's tx_delay (required with LiteEth fixes).
2020-11-23 12:30:36 +01:00
03bb929f27
colorlight_5a_75x: add LedChaser.
2020-11-23 10:14:20 +01:00
ce38cff41d
mercury_xu5: reduce cmd_latency to fix problems with DRAM leveling
2020-11-20 15:31:47 +01:00
a2f3add24e
Merge pull request #123 from teknoman117/litefury
...
Support for the RHS Research LiteFury
2020-11-20 08:44:27 +01:00
389b623fe2
targets/litefury: new target
...
LiteFury is an Artix-7 development board in the M.2 form factor
for PCIe accelerator development. It's similar to the Aller but
with an xc7a100t rather than an xc7a200t and no TPM module.
https://rhsresearch.com/collections/rhs-public/products/litefury
2020-11-19 21:52:14 -08:00
49e1c34dfd
targets/acorn_cle_215: add SATA.
2020-11-18 19:14:18 +01:00
778ce53865
targets/xcu1525: add SATA.
2020-11-17 15:27:42 +01:00
27e19644f4
targets/kcu105: add SATA.
2020-11-16 18:44:18 +01:00
27f60b2e93
add initial Siglent SDS1104X-E support (Ethernet & DDR3 validated).
...
Pinout from https://github.com/360nosc0pe project.
2020-11-13 12:20:15 +01:00
d42af3ea19
targets: add --sys-clk-freq support to all targets.
2020-11-12 18:07:28 +01:00
72afb95329
targets: create platform on BaseSoC for all targets (consitency).
2020-11-12 16:57:31 +01:00
843e724e3d
targets/pcie: simplify using new LiteX's add_pcie method and enable it on all devices supported by LitePCIe.
2020-11-12 16:39:42 +01:00
9f11bfb0d1
qmtech_ep4ce15: convert name to lowercase, minor cleanup and add to test_targets.
2020-11-12 14:33:45 +01:00
31eb74dc2d
Merge pull request #122 from baselsayeh/master
...
add Qmtech EP4CE15 coreboard support
2020-11-12 14:27:49 +01:00
f3ccd140c2
targets/simple: add try/except on leds.
2020-11-12 14:26:00 +01:00
0fc67ddfdb
update copyright
2020-11-12 15:25:39 +02:00
7c6df67739
targets: add tinyfpga_bx target (based on icebreaker/fomu targets).
2020-11-12 14:09:25 +01:00
302e4ffdff
targets/simple: simplify (only keep minimal SoC + Leds) and add load argument.
...
ex of use:
./simple.py litex_boards.platform.ulx3s --build --load
./simple.py litex_boards.platform.trellisboard --build --load
./simple.py litex_boards.platform.arty --build --load
etc...
2020-11-12 13:54:30 +01:00
5cf7731f37
targets/netv2: add PCIe.
2020-11-12 12:16:01 +01:00
7a9f175450
targets/pcie: remove force of csr_data_width to 32 (this is now the default) but just add a check on the pcie block.
2020-11-12 12:08:20 +01:00
4401fec1e6
targets: remove add_csr("crg") (no longer needed).
2020-11-12 11:54:11 +01:00
bd4e92ad13
targets: cleanup, uniformize build arguments between targets.
2020-11-12 11:46:00 +01:00
1b1ed5ebf1
add Qmtech EP4CE15 coreboard support
2020-11-12 01:56:36 +02:00
5fbb176c2a
targets/crosslink_nx: update NXLRAM import.
2020-11-09 11:05:18 +01:00
afe44e2bd6
targets/crosslink_nx_evn: update NXPLL import.
2020-11-09 10:25:30 +01:00
39d979a9d3
targets/Ultrascale: add missing AsyncResetSynchronizer import.
2020-11-09 10:25:05 +01:00
97b64d16a6
Lattice NX PLL Support
2020-11-08 20:34:46 -06:00
2b17dc1b89
target: add rst signal to CRG to allow full reset of the SoC on reboot command.
2020-11-04 11:13:42 +01:00
aa6b9cab4a
targets/crosslink_nx_vip: +x.
2020-11-04 09:30:57 +01:00
ce14775dfb
targets/tec0117: move SerialFlashManager import to flash function.
2020-11-04 09:30:31 +01:00
c093d0d0fc
platforms: cleanup pass to uniformize comments/separators/orders.
2020-11-03 10:48:57 +01:00
8d26c241cd
kc705: revert sys_clk_freq to 125MHz.
2020-11-02 19:51:48 +01:00
babf638c2b
targets/nexys_video: add SATA support.
2020-11-02 19:43:25 +01:00
e950a4a588
targets/kc705: update sata pads.
2020-10-30 17:12:59 +01:00
a410e447e1
targets/kc705/sata: enable write support.
2020-10-30 14:51:40 +01:00
f9252fdd45
targets/kc705: simplify SATA using LiteX's add_sata integration method.
2020-10-29 10:16:40 +01:00
7da8628fba
targets/kc705: switch SATA to gen2.
2020-10-28 19:09:30 +01:00
931f6667ac
targets/kc705: add initial SATA support.
2020-10-26 15:15:24 +01:00
51934567fe
Merge pull request #118 from daveshah1/lifcl-vip
...
Add CrossLink-NX VIP board platform and target
2020-10-22 11:03:47 +02:00
a38c1e7062
mist: add copyrights.
2020-10-22 10:48:58 +02:00
20720693c4
crosslink_nx_vip: Add HyperRAM support
...
Signed-off-by: David Shah <dave@ds0.me>
2020-10-22 09:15:40 +01:00
b278d8bccc
Add CrossLink-NX VIP board platform and target
2020-10-22 09:15:35 +01:00
4541c39e94
Initial support for the MIST board ( https://github.com/mist-devel/mist-board/wiki )
2020-10-17 12:28:22 +02:00
814e7630e4
targets/xilinx: use generic name for idelay clk (avoid clk200, clk400, etc...) since we somtimes want to change it.
2020-10-13 12:10:29 +02:00
06137452d2
targets/xcu1525: use ddram_channel to select clk300.
2020-10-13 11:57:00 +02:00
c3ea04b6e9
targets/s7/us: update sdram (manual cmd_latency no longer needed).
2020-10-12 18:46:21 +02:00
ddf7038c78
ulx3s: add 1.7 and 2.0 revisions support.
2020-10-12 13:23:26 +02:00
5e67853a21
versa_ecp5: Add --eth-phy to select ethernet phy
...
This also simplifies the logic a bit.
2020-10-09 23:56:16 +02:00
477734ff06
versa_ecp5: Add etherbone support
...
Etherbone can be enabled with --with-etherbone
2020-10-09 00:53:08 +02:00
fff20f7532
targets/fomu: base it on iCEBreaker target + USB-ACM.
...
This uniformizes Fomu target with others, provide a simple example of LiteX SoC
on Fomu and will ease maintenance.
2020-10-06 11:39:30 +02:00
79ef091a06
Merge pull request #110 from pepijndevos/gowin
...
Add initial support for Trenz TEC0117 board
2020-10-05 19:50:09 +02:00
062fbd6c63
Merge pull request #108 from daveshah1/dave/nx-evn-doc
...
crosslink_nx_evn: Improve documentation on UART jumpers
2020-10-02 09:40:04 +02:00
18e5def9f2
don't verify erase, very slow
2020-10-01 08:41:16 +02:00
81e4f1f158
add initial support for Trenz TEC0117 board
2020-09-30 14:01:36 +02:00
de09b10726
targets/xcu1525: add ddram-channel selection and rewrite DRC workaround comment.
2020-09-24 18:19:49 +02:00
cc53206aff
targets/kcu105: create specific cd_eth for ethphy.
2020-09-24 10:25:55 +02:00
5b7288cfee
targets/kcu105: add Etherbone support.
2020-09-24 09:55:11 +02:00
77ba49f2bb
targets/pcie: update timing_constraints (now provided by the .xci).
2020-09-24 09:50:55 +02:00
e4cdbe0f7a
targets/ac701: reduce ddram pads to the first 4 modules.
2020-09-05 11:46:07 +02:00
8a9fd02768
crosslink_nx_evn: Improve documentation on UART jumpers
...
Signed-off-by: David Shah <dave@ds0.me>
2020-09-05 09:58:28 +01:00
76ac4a69a8
rename forest_kitten_33 platform/target to fk33.
2020-09-04 20:05:18 +02:00
979fee7517
forest_kitten_33: add pcie.
2020-09-04 20:02:43 +02:00
ad48728160
xcu1525: update headers (were still using old format).
2020-09-04 19:59:09 +02:00
ad4c483c32
Merge pull request #106 from daveshah1/dave/alveo_u250_pcie
...
alveo_u250: Add PCIe x4 support
2020-09-04 19:22:48 +02:00
a68c00e48e
Merge pull request #104 from DerFetzer/colorlight_5a_75e_v6_0
...
Add support for 5A-75E V6.0 board
2020-09-04 19:21:02 +02:00
ae6a052e57
alveo_u250: Add PCIe x4 support
...
Based on the implementation in xcu1525
Signed-off-by: David Shah <dave@ds0.me>
2020-09-04 14:20:04 +01:00
2eda9d0252
xcu1525: add DDR4 IOs for C1/C2/C3 and fix compilation (untested).
2020-09-04 11:34:33 +02:00
7b6b71d4e3
xcu1525: add initial DDR4 support in C0 (untested).
2020-09-03 19:48:23 +02:00
5a62a07b45
xcu1525: add initial PCIe support (untested).
2020-09-03 19:26:02 +02:00
51e881d1ff
add minimal xcu1525 support (VCU1525 or BCU1525 boards).
2020-09-03 19:06:43 +02:00
8bd736bd77
targets/colorlight_5a_75x: make Ethernet PHY selectable, cast sys_clk_freq to int for Wishbone
2020-09-02 22:08:45 +02:00
24b853c2db
targets/colorlight_5a_75x: force use of internal oscillator when using Ethernet with 5A-75E V6.0
2020-09-01 17:07:52 +02:00
8b1fee0e66
Add support for 5A-75E V6.0 board
2020-09-01 17:02:17 +02:00
9b6ed6bdf1
targets/orangecrab: add fallback to bootloader when usr_btn is pressed for 1 second.
2020-09-01 16:22:32 +02:00
b9ac72cf78
targets: simplify clocking on iCE40/ECP5 targets (AsyncResetSynchronizer now integrated in PLL).
2020-09-01 13:38:32 +02:00
9e2d301745
targets/icebreaker: simplify, update PLL/API and BIOS execution from SPI Flash.
2020-09-01 12:58:13 +02:00
beccecf59f
orangecrab: reduce DDR3 power consumption/heat and get back USB PLL to CRGSDRAM.
...
- disable DQ termination.
- disable RTT_NOM.
- drive VCCIO/GND pads.
Reduce current from 0.25A to 0.12A with: ./orangecrab.py --uart-name=usb_acm --sys-clk-freq=48e6.
Still working at 96MHz, 0.17A with: ./orangecrab.py --uart-name=usb_acm --sys-clk-freq=96e6.
See https://github.com/enjoy-digital/litedram/issues/216 .
2020-08-28 20:01:54 +02:00
63b65e278c
crosslink_nx_evn: update copyrights.
2020-08-24 22:33:58 +02:00
153326fa26
targets/icebreaker: update flash.
2020-08-24 17:19:15 +02:00
795e34aafd
add initial Crosslink-NX support.
2020-08-24 16:47:38 +02:00
84c19a6cdf
targets/de0nano: set sys2x_ps phase to 180° for sdram_rate=1:2.
2020-08-24 09:28:51 +02:00
70594a5305
ulx3s: simplify sdram constraints and increase phase to 180 for sdram_rate=1:2.
2020-08-24 09:05:58 +02:00
1781be166a
general: add SPDX License identifier to header and specify files are part of LiteX-Boards.
2020-08-23 15:00:17 +02:00
f328909578
Moved platform call inside of BaseSoC init for compatibility with linux-on-litex-vexriscv support. Added optional spi-sdcard support over P2 header.
2020-08-09 16:27:41 -04:00
45bb329b56
targets/colorlight_5a_75x: enable HalfRate SDRAM PHY.
2020-08-07 19:26:12 +02:00
b6a1ad5a9c
targets/orangecrab: add simple CRG when built without DDR3.
2020-08-07 18:10:03 +02:00
869ceadacb
targets: use platform.request_all on LedChaser.
2020-08-06 20:04:03 +02:00
ee28d7b5ec
targets/ulx3s/add_oled: simplify.
2020-08-04 12:31:15 +02:00
eba70377b7
add optional OLED peripheral to ULX3S target
2020-08-04 11:07:30 +02:00
5fd3e8dbcd
ecpix5: add SDCard.
...
Validated with Linux-on-LiteX-VexRiscv.
2020-07-28 17:45:49 +02:00
94ccf1dd3e
targets/trellisboard: simplify clocking when no DDR3, remove firmware_ram (was here for debug).
2020-07-27 16:31:46 +02:00
eb8a484032
targets/de10nano: fix typo.
2020-07-26 12:01:11 +02:00
2cef54a909
targets/colorlight_5a_75x: avoid sys_clk_freq of 125MHz with etherbone (no longer required).
...
This allows creating SoCs with CPU, SDRAM and Etherbone enabled all together.
2020-07-26 11:58:42 +02:00
760b8ff93a
arty: improve xy_pmod_io genericity (allow selecting the PMOD) and enable SDCard.
2020-07-24 16:29:35 +02:00
04fc98f834
de0nano/ulx3s: add sdram HalfRate support (untested).
2020-07-24 16:12:46 +02:00
d0ca1befa6
targets/de10nano/minispartan6: simplify HalfRate support, rename argument to sdram_rate.
2020-07-24 16:11:57 +02:00
89c5bf43cf
Merge pull request #92 from rob-ng15/master
...
Enable use of HalfRateGENSDRPHY on de10nano
2020-07-24 08:49:09 +02:00
1e1589a514
zybo_z7: demonstrate use of PS7 (with --cpu-type=zynq7000).
...
This uses a pre-generated .xci hosted on github, still need to figure out where the best location for it.
2020-07-23 17:45:21 +02:00
7cda143250
Allow use of HalfRateGENSDRPHY
2020-07-23 14:41:35 +01:00
8a3b453e2f
add Zybo Z7 minimal platform/targets: no PS7 support and USB-UART PMOD on JB.
2020-07-23 15:26:22 +02:00
19d0b95867
platforms/targets: keep in sync with litex.
2020-07-22 08:53:49 +02:00
02f53e6326
targets/minispartan6: add support for HalfRateGENSDRPHY
2020-07-14 11:01:09 +02:00
d9595a317e
targets/orangecrab: use user_btn as rst_n.
2020-07-06 17:49:05 +02:00
7b1bf9d74a
targets: remove sdcard specific clock domain (now generated by the PHY).
2020-07-03 20:09:30 +02:00
31e6997e70
sdcard: rename cd_sdcard to cd_sd to avoid unnecessary clock domain.
2020-07-01 12:58:48 +02:00
fe3ea805bc
targets/pcie: make pcie optional (--with-pcie) and avoid forcing uart to crossover.
2020-06-30 18:44:00 +02:00
7a48a61605
targets: add indentifier on all targets.
2020-06-30 18:11:04 +02:00
fc22e28fe9
targets: replace PCIeSoC with BaseSoC.
2020-06-30 17:41:57 +02:00
d28a0c4258
targets/pcie: remove DNA/XADC/ICAP that were only on PCIe targets.
...
DNA/XADC/ICAP are demonstrated in LitePCIe repository and should probably be added with
a add_xy method.
2020-06-30 17:37:24 +02:00
e91a5d6b82
targets/pcie: remove soft reset.
2020-06-30 17:28:13 +02:00
1356ebb416
targets/ecp5: update clocking on boards with DDR3 to use reset from ddrphy.init and use primary clock for Power on reset.
2020-06-29 16:42:53 +02:00
49973990f3
Merge pull request #85 from oskirby/logicbone
...
Add Logicbone ECP5 board
2020-06-29 16:24:15 +02:00
76a32ba8ec
Add Logicbone ECP5 board
...
The Logicbone is an Open Source development board for the Lattice ECP5
being developed at https://github.com/oskirby/logicbone
2020-06-27 03:32:47 -07:00
efe33c9764
targets/arty: add fixed sdcard clock and remove sys2x (use NETWORKING interface_type on DDR3).
2020-06-25 11:21:24 +02:00
6753a92296
targets: add fixed sdcard clock on boards with SDCard support.
2020-06-25 11:20:38 +02:00
04f6d4463a
versa_ecp5: simplify device (LFE5UM5G or LFE5UM) and adapt integrated_rom_size only for Microwatt.
2020-06-13 11:17:05 +02:00
90092164c8
Add device option for ECP5 Versa board
...
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
2020-06-12 18:39:43 -05:00
b1be5dcc23
Fix FTBFS from undersized BIOS ROM region with Microwatt
...
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
2020-06-12 18:39:43 -05:00
9b45ec0f35
de10lite: simplify vga terminal.
2020-06-11 19:59:32 +02:00
85cac7abc0
de10nano/Mister: review/simplify.
2020-06-11 19:54:55 +02:00
64372d7876
targets/orangecrab: add spi-sdcard and workaround for ValentyUSB.
2020-06-11 19:21:44 +02:00
c94cbae0c0
orangecrab: add user_led (RGB leds), DFUProg and --load support.
2020-06-11 19:21:40 +02:00
9aea2272eb
Merge pull request #80 from rob-ng15/master
...
Use 128mb sdram, uart via i/o port on i/o board and vga terminal via i/o board
2020-06-11 18:16:18 +02:00
45bd50b000
targets: rename colorlight_5a_75b to colorlight_5a_75x (since we are now also supporting the 75e).
2020-06-10 23:14:37 +02:00
ad1693a1ad
Merge pull request #82 from Disasm/colorlight-5a-75e
...
Add Colorlight 5A-75E V7.1 board
2020-06-10 23:09:26 +02:00
94861bbb9a
targets/orangecrab: uncomment MT41K512M16.
2020-06-10 19:30:07 +02:00
0c590abf12
Update colorlight_5a_75b target: add 5A-75E board support
2020-06-10 03:20:32 +03:00
485c242f24
Use 128mb sdram, uart via i/o port on i/o board and vga terminal via i/o board
2020-06-08 11:05:58 +01:00
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