7159237104
Fix csrrs/csrrc for xip registers
2019-03-23 18:11:26 +01:00
505bff6f45
CSR Plugin now implement interruptions as specified in the spec
2019-03-23 12:56:04 +01:00
3652ede130
Add mdeleg tests
2019-03-23 11:41:10 +01:00
9139b4d269
Restore all tests
2019-03-22 18:03:35 +01:00
597336b491
MMU sum/mxr tested and ok, all seem finen
2019-03-22 17:11:55 +01:00
f7b793b7bf
Add SSTATUS.SUM/MXR feature, need testing
2019-03-22 15:49:36 +01:00
e4cdc2397a
MMU pass all test, need to and SUM and MXR and it's all ok
2019-03-22 14:52:49 +01:00
2b458fc642
Added MMU superpage support, pass MMU tests
2019-03-22 12:23:47 +01:00
af2acbd46e
Got the new MMU design to pass simple tests #60
2019-03-22 01:10:17 +01:00
ea56481ead
Add supervisor CSR in the riscv golden model
2019-03-20 23:26:08 +01:00
7cbe399f1f
Fix some supervisor CSR access
2019-03-20 23:25:52 +01:00
6f2e5a0eb7
goldenmodel Implement some of the supervisor CSR
2019-03-20 20:28:04 +01:00
39b2803914
Fix some CsrPlugin flags issues
2019-03-20 20:27:47 +01:00
6c2fe934fd
Bring changes and fixies from @kgugala @daveshah1. Thanks guys !
2019-03-20 16:27:35 +01:00
130a69eeae
Pass regressions machinemode with CSR config including Supervisor
2019-03-20 14:14:59 +01:00
d205f88fb8
riscv golden model and RTL pass all current regressions
...
add RVC into the linux config
2019-03-20 12:17:43 +01:00
3c66f7c58a
goldenmodel now pass more machine mode CSR tests
2019-03-20 11:46:27 +01:00
ee402ec5dc
clearning
2019-03-20 01:16:39 +01:00
3a38fe4130
Add mmu regresion blank project
2019-03-20 01:13:05 +01:00
ccc3b63d7c
Enable golden model check for all regressions
...
Need to implement missing CSR of the golden model
2019-03-20 01:12:03 +01:00
8f22365959
Disable MMU in machine mode
2019-03-19 22:21:30 +01:00
3fbc2f4458
Fix generation
2019-03-19 20:29:28 +01:00
915db9d6c9
cleaning
2019-03-18 20:50:19 +01:00
001ca45c57
Add cachless dBus IBus access right checks
2019-03-18 12:52:22 +01:00
c490838202
Added MMU support into cacheless DBus IBus plugins (for testing purposes)
...
Probably full of bugs, need testing
2019-03-18 12:17:43 +01:00
ffa489d211
hardware refilled MmuPlugin wip
2019-03-17 21:06:47 +01:00
b63395435f
SimpleMul core.
2019-03-16 15:44:18 +00:00
5bc53c08ce
Merge branch 'master' of https://github.com/SpinalHDL/VexRiscv into MulSimple
2019-03-16 15:39:07 +00:00
9a61ff8347
Merge remote-tracking branch 'origin/dev'
2019-03-10 11:14:09 +01:00
bad60f39cd
Fix Decoding benchmark
2019-03-10 11:12:32 +01:00
434793711b
fix part of #59
2019-02-26 17:26:42 +01:00
e0c8ac01d2
Add custom external interrupts
2019-02-03 15:20:34 +01:00
11f55359c6
IBusCache can now avoid injectorStage in singleStage mode
2019-01-30 01:37:47 +01:00
56e3321394
cpp regresion now print the time of failure
2019-01-30 01:36:24 +01:00
f4598fbd0a
Add tightly coupled interface to the i$
2019-01-21 23:46:18 +01:00
b5caca54cd
restore all feature in TestsWorkspace
2019-01-16 15:25:50 +01:00
927ab6d127
Merge remote-tracking branch 'origin/master' into dev
2018-12-30 15:53:25 +01:00
dd42e30c61
Merge remote-tracking branch 'origin/master' into dev
2018-12-29 14:04:07 +01:00
d617bafb08
Roll back VexRiscvAvalonForSim to use caches
2018-12-25 00:15:23 +01:00
961abb3cf1
Avalon: Debug Clock Domain for JTAG
...
This change ensures that the clock domain for the JTAG interface
uses the debug plugin's domain. Otherwise, resetting the processor
will put the jtag debugger in to reset as well.
See SpinalHDL/VexRiscv#48
2018-12-22 07:58:59 -08:00
76ebfb2243
Fix machine mode to supervisor delegation
2018-12-10 13:15:03 +01:00
d9029c2efc
Fix #46 by filling missing return statements
2018-12-10 01:44:47 +01:00
281d61bbe1
regression fix hex << dec #46
2018-12-09 16:37:16 +01:00
1fbb81a4d9
regression fix delete [] #46
2018-12-09 15:40:02 +01:00
f121ce1ed5
add sanity asserts in regression #46
2018-12-08 14:10:18 +01:00
9330945623
fix regression makefile
2018-12-07 23:50:13 +01:00
52419fd7ad
Regression remove dplus stuff #46
2018-12-07 23:47:49 +01:00
68fdbe60cc
verilator regression fix missing fclose #46
2018-12-07 23:43:19 +01:00
eca54585b0
Fix hardware breakpoint
2018-12-04 16:57:24 +01:00
ac1ed40b80
Move things into SpinalHDL lib
2018-12-01 18:25:18 +01:00
3d71045159
DebugPlugin doesn't require memory/writeback stage anymore
2018-12-01 18:24:33 +01:00
58d7a4784d
move HexTools into SpinalHDL lib
2018-11-30 17:39:33 +01:00
b1b7da4f10
Rename SimpleBus into PipelinedMemoryBus
...
Move PipelinedMemoryBus into SpinalHDL lib
2018-11-30 17:37:17 +01:00
2f6a2dfccc
Add configs setup in SimpleBusInterconnect
2018-11-29 16:14:45 +01:00
7075e08d9f
Hazarplugin tell to branch plugin if the RS are hazardous in the execute stage
2018-11-24 13:38:54 +01:00
c2b9544794
Allow iBusCached plugin to be used when no memory stage is present
2018-11-24 13:37:53 +01:00
0086de9e36
Fix CsrPlugin catch illegalAccess
...
Add dhrystone optimized divider
cleaning
2018-11-20 19:39:17 +01:00
75d4d049d7
Add shadow regfile
...
various cleaning
2018-11-16 17:06:11 +01:00
cc48fc7403
add fenceiGenAsANop
2018-11-13 15:17:35 +01:00
0d92a5e5cd
Add many little options to reduce area
2018-11-12 14:14:34 +01:00
fb9ea11a5e
Allow VexRiscv to suppress the memory and the writeback stage, allowing to go downto a 2 stage CPU (FETCH_DECODE, EXECUTE)
2018-11-09 05:41:43 +01:00
b12e15b112
branch/csr/muldiv minor improvments
2018-11-07 19:27:49 +01:00
b7f3ee5e06
Fix CsrPlugin pipelined option
2018-11-05 16:22:41 +01:00
662d76e3aa
csrPlugin : avoid using ALU to get SRC1 (which was useless)
2018-11-03 11:29:30 +01:00
978232fd63
Optimise div iterative plugin done signal
2018-11-03 11:12:37 +01:00
c8ac214097
Optimize CSR
2018-10-28 02:18:27 +02:00
51de2b5820
SimpleBusInterconnect now adapte address width
2018-10-28 02:18:08 +02:00
00bf84b7f8
Add SimpleBusInterconnect
2018-10-25 23:47:05 +02:00
4ed4af6a3e
SrcPlugin add decodeAddSub option
2018-10-24 01:28:37 +02:00
372063582c
Improve CsrPlugin CombinatorialPaths
2018-10-23 19:07:08 +02:00
7096c63d50
Add more SimpleBus utilies
2018-10-23 17:46:31 +02:00
7c0f2dc713
Add SimpleBus object
2018-10-20 12:39:30 +02:00
85e696b286
CsrPlugin : Add mtvecModeGen
2018-10-16 14:53:41 +02:00
905abd5aaa
Add wfiGenAsWait and wfiGenAsNop
...
CsrPlugin cleaning
Much cleaning in general
Zephyr is running
2018-10-16 13:07:30 +02:00
f903df4b66
sync
2018-10-12 17:13:54 +02:00
2b29690010
Clean branch plugin lsb bit calculation
...
BranchPlugin doesn't try anymore to catch exception when RVC is on
2018-10-12 12:24:52 +02:00
eea92154ae
fetcher force PC LSB to be zero
2018-10-12 12:02:52 +02:00
0b8f6f6ed4
Fix broken C.LWSP reference_output
2018-10-12 12:02:02 +02:00
594f7a8bf2
Seem to pass all risc-v compliance tests, excepted the C.LWSP which is a broken test
2018-10-11 22:19:17 +02:00
8c25e73b9d
Fix DIV negative values divided by zero
2018-10-11 22:18:21 +02:00
c26b7e15cf
BranchPlugin exceptions are now risc-v compliance alligned
2018-10-11 17:56:49 +02:00
8b1a4a2717
Add RISCV compliance regression test, need to fix I-MISALIGN_JMP-01 mtval
2018-10-11 00:25:39 +02:00
40d85b8c70
Add fenceiGenAsAJump into BranchPlugin
2018-10-10 21:13:21 +02:00
68f1ff3222
Add CsrPlugin ebreak support
2018-10-10 19:23:04 +02:00
0662cc2797
Add GenMicro experiment to reduce ice40 area usage.
...
IBusSimplePlugin now require cmdFork parameters to be set (no default)
2018-10-03 22:08:57 +02:00
48bff80653
rework fetchPc to optionaly share the pcReg with the stage(1)
...
IBusSimplePlugin now implement cmdForkPersistence option
2018-10-03 16:24:10 +02:00
c61f17aea3
Fetcher/IBusSimplePlugin wip
2018-10-03 01:02:22 +02:00
0ada869b2d
regression golden ref regfile is now sync with trl boot's random values
...
wip
2018-10-01 16:14:21 +02:00
65a8d84d30
Introduce HAS_SIDE_EFFECT Stageable to solve sensitive instruction squeduling
...
(uncached DBus TODO)
2018-10-01 12:13:05 +02:00
7770eefa3b
wip
2018-09-30 12:57:08 +02:00
39c6bc11d6
Pass basic regression again
2018-09-29 19:04:20 +02:00
5ad7c39f47
wip
2018-09-29 12:04:58 +02:00
37a1970ad6
wip
2018-09-28 16:02:33 +02:00
9a3510f63d
Map all supervisor registers
2018-09-27 19:03:57 +02:00
acd1ca422a
wip
2018-09-27 18:24:40 +02:00
6dde73f97c
Murax demo with XIP is now fully defined in SpinalHDL
2018-09-27 00:55:30 +02:00
aff436ddcf
Sync with SpinalHDL head
...
Add mmu test into the dhrystone regression command
2018-09-24 18:31:33 +02:00
1e3b75ef1d
xip typo
2018-09-23 22:06:21 +02:00
86efb75f6a
rework fetcher
2018-09-23 22:05:53 +02:00
56fd73fbbc
Add missing bin files
2018-09-23 19:26:11 +02:00
bdc3246f5a
Fix xip gitignore
2018-09-23 19:23:43 +02:00
5024cc5616
Hardware breakpoint feature added
...
Murax XIP debugging passed tests
2018-09-20 13:11:20 +02:00
ff1d1072a7
XIP is physicaly working on murax
2018-09-19 00:09:14 +02:00
b51ac03a5e
murax xip flash integration wip
2018-09-18 16:53:26 +02:00
3e17461cc7
Add optional XIP to Murax
2018-09-16 11:00:56 +02:00
d7cba38ec2
move to SpinalHDL 1.1.7, add more default value for plugins parameters
2018-09-11 16:08:28 +02:00
791608f655
Move swing stuff into main test package
2018-08-29 14:55:25 +02:00
0255f51cc5
Add unpipelined Wishbone support for uncached version
2018-08-24 16:41:34 +02:00
7ed6835e97
Add C++ VexRiscv model to cross check the hardware simulation
2018-08-22 02:08:55 +02:00
38af5dbdd5
riscv emulator WIP (RVC missing)
2018-08-21 01:03:51 +02:00
dca1e5f438
revert RVC from murax
2018-08-17 23:12:45 +02:00
8ebb3af4fc
Merge remote-tracking branch 'origin/master' into reworkFetcher
...
Conflicts:
README.md
src/main/scala/vexriscv/TestsWorkspace.scala
src/test/scala/vexriscv/Play.scala
2018-08-17 20:56:51 +02:00
9c7e089329
Fix ExternalInterruptArrayPlugin CSR ids
2018-08-17 20:38:33 +02:00
1d3ac7830b
restore tests without CSR catch all
2018-08-17 19:33:41 +02:00
330ee14a23
final fetchRework commit ?
2018-08-17 19:13:23 +02:00
91773ec7d5
Sync, Seem to pass all except dynamic_o0 which is probably a freertos test setup issue
2018-08-14 11:51:53 +02:00
ae85698a2b
MulSimple
2018-08-09 22:15:26 -07:00
32fe1dcbd4
Add google cloud VM regressions scripts
2018-07-07 21:47:09 +02:00
3ea4f28354
wip
2018-07-07 11:39:42 +02:00
9c1a8ea219
Fix EPC
...
Fix Freertos binaries
wip
2018-07-03 23:17:32 +02:00
ffe5fa23f0
wip
2018-06-25 09:36:07 +02:00
d73aa9ce00
rework csr exception/interrupt handeling wip
2018-06-24 00:14:55 +02:00
dd47db9ad0
wip
2018-06-20 12:35:12 +02:00
8886f7e6d4
test wip
2018-06-19 16:15:42 +02:00
1090111a6f
TestIndividual is now fully random
2018-06-15 13:00:59 +02:00
b2cd8c5314
Fix exception pipelining
2018-06-15 13:00:26 +02:00
83864710a3
Fix IBusCached single cycle interaction with mmu bus
...
Add random test configs
2018-06-09 08:40:19 +02:00
08a1212fca
Add DBus simple/cached regressions
2018-06-07 02:31:18 +02:00
6bc5431fcd
Add iBusCached regressions
2018-06-07 00:57:26 +02:00
5e7dd02bf7
Fix relaxedPc/DYNAMIC_TARGET interaction
2018-06-06 18:30:30 +02:00
dc968020c4
Fix relaxedBusCmdValid pendingCmd overflow
2018-06-06 15:20:37 +02:00
7768f065e4
Add many cpu configs on regressions tests (some config are broken)
2018-06-06 02:23:07 +02:00
8729530a8d
Fix Dynamicfetch/!rvc config
2018-06-05 02:33:18 +02:00
930563291c
Allow RVC/dynamic_target/fetch bus latency > 1 all together
...
Fix freeretos rvc regressions
2018-06-05 02:21:05 +02:00
702db29edd
Fix dynamic prediction RVC allignement
2018-06-04 20:03:08 +02:00
fc835f370e
Fix DynamicPrediction with RVC missprediction between ret instruction and first instruction of the next function
2018-06-04 19:45:15 +02:00
52f1cdbca7
Fix some missing Barriel -> barriel fixes
2018-06-03 21:46:40 -07:00
9f0387350b
Add Freertos RVC binaries regression
2018-06-03 17:10:58 +02:00
e9bbbb3965
BarrielShifter -> BarrelShifter
2018-06-03 07:40:11 +00:00
7375855e58
DYNAMIC_PREDICTION used with RVC pass tests (1 cycle fetch)
2018-06-03 00:50:18 +02:00
98b68093f4
dynamic_prediction + RVC => instruction fetch stopped midair
2018-05-28 21:28:39 +02:00
863ac3f34d
dynamic prediction now use history from first aligned word of the instruction instead of the last one.
2018-05-28 11:03:13 +02:00
8a0c238bf3
dynamic prediction ok with rvc, todo dynamic_target with rvc
2018-05-28 10:59:22 +02:00
0335543309
More Unrolls
2018-05-28 07:20:26 +00:00
1613191779
Unrool -> Unroll
2018-05-28 07:18:13 +00:00
7493e70265
Merge remote-tracking branch 'origin/master' into reworkFetcher
2018-05-28 09:02:30 +02:00
5943ee727e
Fill travis, DhrystoneBench is now a Unit test
2018-05-28 09:02:01 +02:00
1752b5f184
Give name to inter stages registers
2018-05-27 23:39:49 +02:00
5704f22739
wip
2018-05-27 23:33:57 +02:00
346338f084
Better HexTools
2018-05-26 11:51:42 +02:00
6142b04603
Move HexTools into Spinal
2018-05-26 11:43:16 +02:00
c8677cca9b
Better HexTools
2018-05-26 11:32:36 +02:00
b0777bc646
Merge remote-tracking branch 'origin/master' into reworkFetcher
2018-05-24 14:05:35 +02:00
6004dcc365
Fix typo
2018-05-24 14:04:50 +02:00
9815763b7f
Merge remote-tracking branch 'origin/master' into reworkFetcher
...
Conflicts:
src/main/scala/vexriscv/plugin/PcManagerSimplePlugin.scala
src/test/cpp/regression/main.cpp
2018-05-24 14:04:01 +02:00
c4f33b30e2
Update SynthesisBench murax
2018-05-24 14:03:28 +02:00
485f35a1b5
IBusCachedPlugin default is two cycle cache with single cycle ram.
2018-05-24 13:46:31 +02:00
2f8ccc55b6
Fix branch plugin decode prediction exception by using the instruction decoder
2018-05-24 12:52:00 +02:00
a53f8fdc35
Clean configs
2018-05-23 16:57:32 +02:00
eb5bc4a791
Fix RVC decompressor (ALU immediats)
2018-05-22 17:23:20 +02:00
ff760a0bf0
DYNAMIC_TARGET branch prediction back for not compressed ISA (PASS)
2018-05-21 13:45:08 +02:00
7ffbfab312
Reintroduce MMU feature (pass tests)
2018-05-16 20:32:12 +02:00
c8cec59f1d
Update IBusCachedPlugin parameters
2018-05-16 12:11:53 +02:00
3b54ecf303
Restore two cycle instruction cache features
2018-05-15 23:03:33 +02:00
4e7152ae5a
IcestormFlow add ultraplus support
2018-05-14 20:18:53 +02:00
df3d9ccb13
rework IBusSimplePlugin parameters
2018-05-14 10:31:40 +02:00
c0271d382f
More assertion (csrPlugin)
2018-05-14 10:13:44 +02:00
9caa7163ae
IBusSimplePlugin add relaxedBusCmdValid feature
2018-05-14 10:04:19 +02:00
610bd01f3b
remove rspStageGen
2018-05-14 09:21:28 +02:00
7b37669a0f
Add exception catch to iBusSimplePLugin (pass)
2018-05-09 18:43:48 +02:00
acccbf40e2
RVC debug pass tets
2018-05-09 00:28:14 +02:00
0056da1342
DebugPlugin work
2018-05-08 02:01:34 +02:00
e65757e34c
wip before moving the fetchHalt
2018-05-06 16:38:00 +02:00
294293cb70
Reintroduce debug plugin (instruction injector need optimisations)
2018-05-05 23:05:32 +02:00
a50fbf0d7a
Fix IBusCachedPlugin Pass all dhrystone tests
2018-04-30 13:35:17 +02:00
558af595a1
Add ice40 synthesis results
2018-04-26 13:14:37 +02:00
bdcf3f6234
Add HexTools and add a Briey main which load the ram
2018-04-26 10:27:39 +02:00
cfc324aa0f
Allow csr mtvec to not have reset values
2018-04-24 23:33:48 +02:00
a9cbc48eb2
PcManagerPlugin is can now handle an external reset vector signal
2018-04-24 23:11:11 +02:00
978eb9b6b2
DBusCachedPlugin add CSR info
2018-04-22 11:46:01 +02:00
74f2a4194a
Add ExternalInterruptArrayPlugin
2018-04-20 17:56:21 +02:00
6598e82920
wishbone => word address, not byte address
2018-04-19 11:22:06 +02:00
455607b6b4
Fix dBus IO access
2018-04-18 14:11:59 +02:00
6e59ddcc73
Cached wishbone demo is passing regression tests
2018-04-18 13:51:33 +02:00
b37fc3fcc8
Add VexRiscv Wishbone demo for sim (generation ok)
2018-04-18 12:54:20 +02:00
a66efcb35b
Add wishbone support for i$ / d$ (not tested)
2018-04-17 23:56:44 +02:00
4440047fb6
ICache compressed is working
2018-04-16 10:34:18 +02:00
76352b44fa
wip
2018-04-13 12:51:27 +02:00
19d5d1ecf1
wip
2018-04-09 09:18:08 +02:00
4dd2997ad5
wip
2018-04-09 09:12:30 +02:00
e00c0750eb
wip
2018-04-03 18:37:05 +02:00
d9f2e03753
statuc prediction is fully funcitonnal
2018-04-02 17:43:58 +02:00
76ca852478
Static prediction is fully functionnal
2018-04-02 17:43:06 +02:00
0919308a8f
IBusSimplePlugin add relaxedPcCalculation
2018-03-23 22:49:32 +01:00
c48c7170e8
Added many pipelining option into IBusSimplePlugin
2018-03-23 19:07:03 +01:00
351ad10925
RVC Add dhrystone regressions (PASS)
2018-03-21 23:36:57 +01:00
0c7c2a1fba
IBusPlugin add support of bus error when using compressed instruction
2018-03-21 22:34:54 +01:00
31a464ffdc
VexRiscv now pass Riscv-test compressed stuff
2018-03-21 20:50:07 +01:00
af638e7bde
RV32IC is passing some of the compressed Riscv-test tests
2018-03-21 20:30:09 +01:00
f872d599e2
Add decodePcGen
2018-03-20 18:34:36 +01:00
1fb138de1f
IBusSimplePlugin fully functional Need to restore branch prediction
2018-03-20 00:01:28 +01:00
ac74fb9ce8
iBusSimplePlugin done, DebugPlugin need minor rework
2018-03-18 13:21:21 +01:00
64022557bf
Add synthesis attribut to the PcManagerSimplePlugin to optimize the pc calculation for vhdl
2018-03-15 18:56:25 +01:00
63c1b738ff
Add synthesis attribut to the PcManagerSimplePlugin to optimize the pc calculation inferation timings
2018-03-14 00:56:23 +01:00
d9b7426cde
undo InOutWrapper from Murax
2018-03-14 00:47:23 +01:00
91031f8d75
DivPlugin is now based MulDivIterativePlugin (Smaller)
2018-03-10 13:31:35 +01:00
e437a1d44e
Add division support in the MulDivInterativePlugin
2018-03-09 22:41:47 +01:00
36438bd306
iterative mul improvments
2018-03-09 20:00:50 +01:00
674ab2c594
experimental iterative mul/div combo
2018-03-09 19:07:26 +01:00
5228a53293
MuraxSim improve simulation Speed
2018-03-06 12:20:39 +01:00
9b2cd7b234
MuraxSim add switch
2018-03-06 12:17:15 +01:00
53970dd284
SpinalHDL 1.1.4
...
Now the CsrPlugin is waiting that the memory/writeback stages are empty before reading/writing things
2018-03-05 14:34:59 +01:00
ccad64def5
Pipeline CSR isWrite
2018-02-26 10:19:33 +01:00
2b6185b063
Decoding logic : Add primes duplication removal
2018-02-25 08:57:31 +01:00
2b6f43cef8
Fix Murax memory mapping range
2018-02-25 08:57:31 +01:00
5260ad5c35
Decoding lib cleaning
2018-02-25 08:57:31 +01:00
137b1ee32c
Briey testbench, fix io_coreInterrupt to zero to avoid external interrupt set by random boots values
2018-02-22 22:36:13 +01:00
d957934949
Fix ICache exception priority over miss reload
2018-02-19 22:44:46 +01:00
d0e963559a
Update readme with the new ICache implementation
2018-02-18 23:48:11 +01:00
93110d3b95
Add jump priority managment in PcPlugins
2018-02-16 14:27:20 +01:00
506e0e3f60
New faster/smaller/multi way instruction cache design.
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Single or dual stage
2018-02-16 02:21:08 +01:00
3853e0313b
SynthesisBench cleaning/experiments
2018-02-11 14:53:42 +01:00
0e6ae682b1
Add architecture section describing plugins in the readme
2018-02-09 00:44:27 +01:00
57ebfee2e6
Add more axi bridges
2018-02-08 21:39:22 +01:00
3ee111e100
Update readme (gcc stuff)
2018-02-05 16:34:10 +01:00
d4b05ea365
Remap Briey/Murax onChipRam to 0x80000000 to avoid having memory at the null pointer location
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Commit missing file
Update dhrystone hex to use GP. 1.44 DMIPS/Mhz
2018-02-05 16:16:27 +01:00
4729e46763
Add DummyFencePlugin
2018-02-03 12:28:53 +01:00
f13dba847c
Add custom csr gpio example
2018-02-02 11:14:55 +01:00
b7d8ed8a81
Add onWrite/onRead/isWriting/isReading on the CsrPlugin
2018-02-01 21:28:28 +01:00
4ee2482cbf
Fix custom_csr regression against random ibus stall
2018-01-31 18:33:21 +01:00
d2e5755df4
revert removed code by mistake
2018-01-31 18:29:30 +01:00
30b05eaf96
Add CsrInterface to allow custom CSR addition
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Add CustomCsrDemoPlugin as a show case
2018-01-31 18:13:42 +01:00
bdbf6ecf17
BranchPrediction DYNAMIC_TARGET add source PC tag to only consume entries on branch instructions
2018-01-29 14:52:31 +01:00
0d318ab6b9
Add DYNAMIC_TARGET branch prediction (1.41 DMIPS/Mhz)
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Add longer timeouts in the regressions tests
2018-01-29 13:17:11 +01:00
307c0b6bfa
Now mret and ebreak are only allowed in CSR machine mode
2018-01-28 16:34:55 +01:00
93da5d29bc
Fix dhrystone referance log
2018-01-28 16:34:55 +01:00
26732942e5
Update DMIPS/Mhz
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Add cached config with maximal performance settings
FullBarrielShifterPlugin can now be configured to do everything in the execute stage
2018-01-25 01:11:57 +01:00
3b3bbd48b9
SpinalHDL 1.1.3 => Now Verilog rom are emited into separated bin files
2018-01-20 18:29:33 +01:00
6a521a8d13
Better MuraxSim gui
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Add MuraxSim in the readme
2018-01-09 08:59:17 +01:00
9a89573942
SpinalHDL 1.1.2
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Add Murax setup with Mul Div Barriel
2018-01-06 22:09:42 +01:00
43d3ffd685
CsrPlugin : Now wait that the whole pipeline (including writeback) is empty before executing interruptions. This make the separation between context switching clear and avoid on atomic instructions failure
2018-01-04 17:37:23 +01:00
2b7465e5df
Add more atomic tests (PASS)
2018-01-04 16:16:22 +01:00
611f2f487f
Fix DataCache atomic integration into DBusCachedPlugin
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Atomic is passing basic tests
2018-01-04 15:24:00 +01:00
4637e6cb48
Fix DecodingSimplePlugin model building when reinvocation is done one a preexisting opcode.
...
add Atomic test flow
2018-01-04 14:43:30 +01:00
468dd3841e
Add Atomic LR SC support to the DBusCachedPlugin via reservation entries buffer
2018-01-04 13:16:40 +01:00
4ed19f2cc5
SpinalHDL 1.1.1
2017-12-30 03:36:57 +01:00
0d39e38906
SpinalHDL 1.1.0
2017-12-28 13:49:39 +01:00
3c0588eb4b
remove MuraxSim fixed path
2017-12-19 22:33:46 +01:00
7f2b2181c1
SpinalHDL 1.0.3
2017-12-19 21:21:16 +01:00
37849b7a66
Spinal 1.0.2 sim update
2017-12-19 00:40:52 +01:00
ebda7526b5
MuraxSim 1.0.0
2017-12-17 17:57:09 +01:00
dda5372a6c
Fix typo
2017-12-14 01:05:06 +01:00
d6e0761065
Fix led gui refresh rate
2017-12-14 01:04:31 +01:00
2259c9cb0f
Add SpinalHDL sim (1.0.0)
2017-12-14 00:57:12 +01:00
e1b86ea511
SpinalHDL 0.11.4 update
2017-12-01 11:19:23 +01:00
586d3ed286
Update formal VexRiscv to halt on missaligned dbus
2017-11-26 15:30:48 +01:00
4de0aac469
Merge branch 'formal'
2017-11-24 14:03:25 +01:00
b7f4f09814
Update verilator makefiles to support the last SpinalHDL changes (process merges)
2017-11-21 23:56:46 +01:00
9b9bbaa4ad
Add missing full config for the iBus
2017-11-21 00:09:02 +01:00
ce6fd6d0aa
Add VexRiscvAxi4 demo
2017-11-20 23:57:37 +01:00
7c19288648
Update Synthesis bench
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Update some synthesis results
2017-11-17 20:10:46 +01:00
290dbc106e
Fixes GPIO width mismatch
...
Adds explicit type to apbDecoder.slave to suppress IDE errors
2017-11-16 15:02:13 -05:00
6c3fed3505
SpinalHDL 0.11.1
2017-11-15 16:44:42 +01:00
be3d301eaf
Merge remote-tracking branch 'origin/spinalhdl_reworkDev'
2017-11-12 13:08:05 +01:00
838c13d68b
spinal.core.internals literals import
2017-11-10 13:14:30 +01:00
3060296b94
unsetRegIfNoAssignement -> allowUnsetRegToAvoidLatch
2017-11-10 11:33:04 +01:00
c3a7f4e58c
CSR unsetRegIfNoAssignement fix
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BranchPlugin doesn't emit the prediction cache when the STATIC setup is used
2017-11-10 00:59:31 +01:00
d6777ae8ec
usetRegIfNoAssign upgrade
2017-11-09 20:10:56 +01:00
a72c7fd0d1
Clean Murax toplevel by extracting integrated Area into dedicated components located in MuraxUtiles.scala
2017-11-07 22:19:33 +01:00
714d44d248
Add fixed bug into the FormalPlugin comments
2017-11-07 13:54:07 +01:00
200a73bea0
Fix FormalPlugin to pass liveness again.
2017-11-06 23:04:33 +01:00
8098a03a9b
with no bus stall, pass all tests except uniqueness
2017-11-06 20:26:45 +01:00
e2a432eb5e
add HaltOnExceptionPlugin
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wip
2017-11-05 20:13:27 +01:00
276f7895e7
Add FormalPlugin
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Add FormalSimple CPU configuration
2017-11-04 00:55:32 +01:00
ba42f71813
pass VexRiscv regressions
2017-10-30 14:29:25 +01:00
008a5b7309
updated main.cpp
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added missing using namespace std
2017-10-17 22:09:08 +00:00
2bf7ca24f2
Add VexRiscvAvalonWithIntegratedJtag
2017-10-16 11:52:17 +02:00
aa859aae6b
Update framework.h
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Add missing using namespace std;
2017-10-05 10:08:09 +02:00
09ba7c28da
Change some xx.input(REGFILE_WRITE_DATA) for xx.output(REGFILE_WRITE_DATA)
2017-08-27 15:21:44 +02:00
8168c9bf3a
Update simd_add makefile
2017-08-27 14:49:36 +02:00
2c6889e688
Murax mainBus now handle unmapped memory access allowing the debug to access unmapped area without locking the CPU
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Murax add dhrystone config
2017-08-10 22:48:00 +02:00
aa477b2b1c
DebugPlugin now prevent the CPU catching exception when debug instruction are pushed
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Fix DataCache locking when loading mem read rsp transaction has the flag set
Briey : Now the debug module reset the whole AXI system instead of only the CPU
Now in debug, you can access unmapped memory without crashing the CPU
2017-08-10 20:56:54 +02:00
1653548140
Better readme about custum instruction testing
2017-08-08 18:36:23 +02:00
54b06e6438
Add SIMD_ADD regression and config (show case)
2017-08-08 18:19:02 +02:00
3307d6c3b5
Briey move CPU and UART generics from to toplevel to the toplevel configuration object
2017-08-06 15:42:37 +02:00
671aa5050e
Move CPU and UART configs into the murax configuration object (in place of toplevel hardcoding)
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Add MuraxConfig.fast
2017-08-04 14:55:54 +02:00
ac59eebb8d
Add Murax configuration which integrate a boot programme :
...
Will blink led and echo UART RX to UART TX (in the verilator sim, type some text and press enter to send UART frame to the Murax RX pin)
2017-08-03 21:58:23 +02:00
58981c0e8e
Add Murax fast in synthesis bench
2017-08-01 21:14:09 +02:00
f44b345132
Add console TX in the Murax verilator
2017-07-31 21:04:41 +02:00
0c9a39d3ce
Connect the UART interruption to the CPU
2017-07-31 17:20:47 +02:00
c16a53c388
Refractoring of some arbitration signals
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Add UART into Murax
2017-07-31 13:34:25 +02:00
8708d2482f
Add more information about dependencies
2017-07-30 11:37:22 +02:00
de33128e01
Add Murax 0.55 DMIPS/Mhz
2017-07-30 02:42:14 +02:00
e8aa828744
PcPlugin change fastPcCalculation into relaxedPcCalculation
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relaxedPcCalculation relax timings on the IBusSimple address => better FMax when the CPU is integrated into a SoC
2017-07-29 21:36:30 +02:00
3b66d986a8
Fix cpu sending instruction memory request while being halted by the DebugPlugin
2017-07-29 18:20:22 +02:00
43253f61c1
Update Murax info
2017-07-29 02:52:57 +02:00
fa887d3830
Add pipelining option (hit 60 Mhz)
2017-07-29 02:52:03 +02:00
3bdf020c67
Add interrupts and timer to Murax
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8KB ram is the default now
2017-07-29 01:59:17 +02:00
823ac353ff
Add Murax SoC (very light, work on ice40)
2017-07-28 21:25:49 +02:00
1450077b70
Add Murax SoC (wip)
2017-07-28 14:16:30 +02:00
493f7721cb
All FreeRTOS tests are now passing
2017-07-28 00:07:51 +02:00
800e9e79a5
freertos regression now include O0 and O3 for rv32i and rv32im
2017-07-27 01:23:50 +02:00
6b3e2dbe7d
Add FreeRTOS test regression (FREERTOS=yes)
...
Multithreaded regression
2017-07-26 23:38:59 +02:00
10d282b2ef
Add DBusSimple early injection feature (better DMIPS)
2017-07-26 23:36:25 +02:00
6d117f5c81
Fix DataCache bug (interaction between the victim buffer and the memory read request in execute/memory stages)
...
freeRTOS pass
2017-07-23 22:58:26 +02:00
9fe4e1d54d
Package refractoring VexRiscv -> vexriscv Plugin -> plugin
2017-07-23 13:28:17 +02:00
4b5bf7d807
Briey Area down by 10% by spliting the memory system in two (System, Debug)
2017-07-23 01:11:33 +02:00
37c338ec98
Avalon add read response support.
...
Fix debug instruction injection and IBusSimplePlugin interraction
2017-07-21 20:39:54 +02:00
54f785b1a3
Add full avalon support (pass regression)
2017-07-21 17:40:45 +02:00
52f5020e64
Rename some regression commands
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Add Avalon regressions (PASS)
DebugModule read response is now 1 cycle latency
2017-07-21 14:32:49 +02:00
575a410786
Avalon regression (WIP)
2017-07-20 14:20:19 +02:00
570f0e1e3e
D$ remove the coupling between the mem.cmd.ready >> victim logic >> cpu halt by using halfPipe => Better practical FMax
2017-07-20 14:20:19 +02:00
8643086fc0
Add Briey area and timings into readme
2017-07-19 18:34:16 +02:00
42e546ecd9
Add fullNoMmuNoCache config
2017-07-17 16:45:06 +02:00
fcec6cba86
revert test changes
2017-07-17 15:26:37 +02:00
617861ee6c
Add smallAndProductive
2017-07-17 15:25:56 +02:00
99c3397243
readme, better plugin example
2017-07-17 14:19:28 +02:00
84bba3adf0
REG1/REG2 refractoring RS1/RS2
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Add CustomeInstruction example
2017-07-17 14:02:56 +02:00
708a8f66de
typo fixes
2017-07-17 14:01:35 +02:00
79c2972076
Update bench config with realistic embedded CSR
2017-07-16 14:34:42 +02:00
53300c4116
Add area and FMax in readme
...
Add Synthesis bench
2017-07-16 13:50:19 +02:00
37ea699c55
Add Synthesis bench
2017-07-16 03:29:50 +02:00
6930e76042
Remove mepc from smallest CSR config
...
Better readme
2017-07-16 00:44:23 +02:00
bc792a8655
Fix UartRx sim
2017-07-15 19:05:34 +02:00
74becb6633
Add VexRiscvAvalon QSysify
2017-07-15 09:41:39 +02:00
12d21a08e8
Add DebugPlugin avalon
2017-07-14 19:28:22 +02:00
d3dcfcec06
Add toAvalon bridge to cached bus
...
Add VexRiscvAvalon demo
2017-07-14 18:04:41 +02:00
f51f28164a
Fix info to flush data cache
...
Briey sim add VGA GUI (SDL2)
Add DE0-Nano Briey support
2017-07-09 01:00:46 +02:00
8d34c04425
Fix CsrPlugin case issue
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Better DBusSimplePlugin FMax with catch enables
SrcPlugin can now insert SRC1 and SRC2 in the execute mode for lower area usage and combinatorial path balancing
2017-06-27 19:37:46 +02:00
e9ab3d71d5
update readme
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add uart.elf binary for testing
2017-06-26 14:44:52 +02:00
4d7455f9c3
add retiming to the dataCache waysHit
...
Add exception catches in the default briey configuration
2017-06-26 14:02:25 +02:00
e9e7cf9e7a
Add briey tracing
...
Better debugPlugin implementation
Fix SimpleDBus/IBus into AXI bridge (cmd transaction removing)
Add SingleInstructionLimiterPlugin for debug purposes
2017-06-24 14:09:12 +02:00
edf1b4ed5a
Cleaning, better jtag perf
2017-06-18 16:10:27 +02:00
bc90331c49
Cleaning
2017-06-15 13:54:34 +02:00
88a2c4a603
Cleaning/Add documentation
2017-06-15 13:44:21 +02:00
835dd4ad50
Add CSR
2017-06-15 11:16:11 +02:00
f8678698fc
Briey improve AXI FMax
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Faster debugginPlugin regression
2017-06-11 11:52:59 +02:00
cbc770deb3
Improve TCP sockets latency
2017-06-10 19:38:42 +02:00
9b9d9e2582
Add Uart monitor in the briey testbench
2017-06-10 16:09:14 +02:00
11a63491bd
Add YAML feature to store CPU info
2017-06-09 16:06:18 +02:00
4b9668c063
Remove speed factor overriding when Trace
2017-06-09 08:41:12 +02:00
f46ec583d6
Briey is now working with DataCache on FPGA
2017-06-07 23:02:34 +02:00
8dcf5cf68a
Add missing import in Briey testbench
2017-06-07 16:56:29 +02:00
8da413dec3
Briey SoC is now working with openOCD TCP JTAG connection. (GDB OK)
...
Add SDRAM Verilator model
2017-06-07 04:19:35 +02:00
1e18daecc0
Add ICache and DCache axi bridges functions
...
Add StaticMemoryTranslationPlugin
2017-06-01 17:54:56 +02:00
ac16558b6b
Add haltItByOther
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Axi4, remove some pipelining
2017-05-30 17:49:29 +02:00
6b62d8da52
VexRiscv in Briey SoC is working on FPGA (including jtag debugging)
2017-05-29 21:17:14 +02:00
213e154b40
Fix regression test debugPlugin bus
2017-05-28 17:41:09 +02:00
8dddc7e334
GDB + openOCD successfully connect !
2017-05-25 13:36:54 +02:00
75f6b78daf
OpenOCD successfuly connected to target
2017-05-24 23:53:31 +02:00
1efed60307
Fix DebugPlugin
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Add DebugPlugin regression (PASS)
2017-05-22 19:23:11 +02:00
cc875d1c0b
Add TCP server socket to manage debug access from openOCD (as instance)
2017-05-22 00:42:19 +02:00
5cda2632df
Start implementing debugPlugin test infrastructures
2017-05-21 23:50:40 +02:00
9995c5109d
move tests
2017-05-21 16:53:48 +02:00
6c1d953647
DebugPlugin fully implemented
2017-05-20 18:15:15 +02:00
619739d33a
preliminary DebugPlugin
2017-05-20 15:16:45 +02:00
a5364ad001
Add flush support instruction into the instruction cache
2017-05-19 11:20:33 +02:00
736478ff1d
CsrPlugin now catch illegal CSR access (wrong address + to low privilege level)
2017-05-09 00:40:44 +02:00
fe184636dd
Improve CsrPlugin FMax
2017-05-08 22:59:05 +02:00
c69fdf7987
Add basics of the USER mode to CsrPlugin
2017-05-07 23:41:54 +02:00
579e93bb5a
Rename MachineCsr plugin into CsrPlugin
2017-05-07 22:26:17 +02:00
392f3a7d8c
Add PrivilegeService (User) (not implemented)
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Split caches from their plugins file
2017-05-07 20:16:41 +02:00
a51c27970b
Add opcode for clean/invalidate the datacache
...
Change mmu opcodes
2017-05-07 16:02:55 +02:00
4d6a6fbb02
Fix Instruction Data cache exceptions
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Pass all tests including CSR/FreeRTOS
2017-05-07 12:51:47 +02:00
ca1bc9cf69
DataCache plugin now support all exceptions
2017-05-07 10:44:41 +02:00
5ba8ab7947
DataCache add invalidate/clean/invalidateClean on a virtual address/way
2017-05-05 00:43:41 +02:00
48a5dc8e79
DCache move the exception bus outside the cache component
2017-05-04 21:01:08 +02:00
534a4c3494
mmu working for instruction and data bus (both tested)
2017-05-03 18:42:54 +02:00
c647ef8bb6
Rework constructors
2017-05-01 20:20:21 +02:00
889a040f90
Fix multi port MMU design
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Change machineCSR to handle exceptions from the writeBack stage
Change the DBusCachedPlugin to emit miss exception
2017-05-01 14:29:37 +02:00
2ed33106d6
MMU pass simple regression !
2017-04-29 19:58:17 +02:00
227772f19c
Add miss files
2017-04-28 16:41:44 +02:00
010ba568f0
MMU implemented
...
Datacached using MMU implemented
It compile, but nothing is tested
2017-04-28 16:41:23 +02:00
ba2ca77114
Two stage datacache now pass dhrystone benchmark without error
2017-04-23 23:15:38 +02:00
9040326273
WIP two stage DCache, nearly passed the dhrystone benchmark
2017-04-23 18:31:16 +02:00
e00bf028cb
Add HazardPessimisticPlugin for light and very good FMAX hazard tracking
2017-04-17 17:56:47 +02:00
024e14ae58
Smaller and faster single stage instruction cache
...
Add fast two stage instruction cache
Remove useless address == 0 checks in the HazardPlugin
2017-04-13 18:27:03 +02:00
c83a157c64
IBusCachedPlugin with twoStage config is now compatible with syncronous regfile
2017-04-09 11:59:09 +02:00
9a4c35d7b6
IBusCachedPlugin twoStage config fix
2017-04-08 18:34:44 +02:00
e3b9e671ec
IBusCachedPlugin add two stage cache option for better FMax and better scaling
2017-04-08 17:42:13 +02:00
5c594d6d2a
IBusCachedPlugin move memory access outside the pipeline
2017-04-07 13:27:47 +02:00
8f09867bda
Cleaning
2017-04-07 13:09:31 +02:00
efb27390a7
Better IntAluPlugin
...
Better SrcPlugin
Better DBusCachedPlugin
2017-04-06 01:28:52 +02:00
2e02a6f0e7
DBusCachedPlugin better write to read hazard logic (FMAX)
...
Add some TODO FMAX comments
2017-04-05 18:37:02 +02:00
179e7f7b4c
IBusCachedPlugin add asyncTagMemory option
2017-04-05 14:25:11 +02:00
2b24cbc8e1
Add pessimistic harzard options
...
Add separated add/sum option in srcPlugin
2017-04-04 00:25:39 +02:00
acb85a1fb8
Add some decoder comments
2017-04-03 01:33:54 +02:00
8ff05bd2a8
Much better decoder using Quine-Mc Cluskey
2017-04-02 21:05:25 +02:00
a9f7177181
Data cache pass dhrystone benchmark.
...
Data cache todo -> bus error handling
2017-04-01 17:06:59 +02:00
2f384364d8
Data cache WIP
...
refractoring
2017-03-31 15:20:51 +02:00
26597f78cd
cleaning
2017-03-31 11:06:40 +02:00
19fe998a52
Instruction cache is now able to catch bus errors
2017-03-30 17:34:24 +02:00
95585b4d9a
Add instruction cache plugin (tested)
2017-03-30 10:03:53 +02:00
32d32845bd
Add tests for iRsp, dRsp access faults
2017-03-28 20:25:58 +02:00
2cb0e90077
refractoring/cleaning
2017-03-28 01:53:37 +02:00
62a55c4cf4
Add IRsp/dRsp ready + error capabilities to stall the bus and to generate access error exceptions
2017-03-28 01:24:29 +02:00
eecc1e6b18
Add MachineCsr.mbadaddr logics
2017-03-27 18:35:27 +02:00
349d600182
Better readme
...
cleaning
2017-03-27 00:33:34 +02:00
91c52f4e46
Decoder now catch illegal instructions
2017-03-26 18:02:48 +02:00
c5520656e5
Now able to catch missaligned instruction/data addresses
...
Modify arbitration with an flushAll + isFlushed
2017-03-26 17:20:07 +02:00
4000191966
FreeRTOS tested
...
removeIt no more colapse bubbles
2017-03-25 16:44:42 +01:00
9bbf3ee3e7
MachineCsr fix csr set/clear with zero
...
MachineCsr pass external/timer interrupts test
2017-03-24 17:40:37 +01:00
72d65841d2
MachineCsr pass simple interrupt and exception tests
2017-03-23 23:12:44 +01:00
ed0660237f
MachineCsr wireing/logic done
2017-03-23 01:00:24 +01:00
de4c2470c8
MachineCsr add mcycle and minstret
2017-03-22 20:38:43 +01:00
94770f8e0b
Add MachineCsr (untested)
2017-03-22 18:29:34 +01:00
e9d3977737
Add Arbitration.flushIt
...
Add ExceptionService
Add unremovableStage
Add MachineCsr (untested)
2017-03-21 18:40:50 +01:00
c49373f3d1
Fix missing JAL, JALR encoding
2017-03-21 10:29:09 +01:00
787682d4f6
Add comments
...
Some refractoring
2017-03-20 14:49:49 +01:00
51058f851e
Renaming
2017-03-20 12:37:53 +01:00
ecf853f491
Add Static/Dynamic branch prediction
2017-03-20 12:37:20 +01:00
d569242124
Add Static branch prediction in decode stage
2017-03-19 23:27:35 +01:00
88dee6d2bc
Reduce area with reg[0] optimisation
2017-03-18 19:32:54 +01:00
fc1bb7249a
Add trace option to regresion
2017-03-18 14:06:42 +01:00
5e9da0f27a
Add self checked dhrystone test
2017-03-18 12:32:14 +01:00
31db6511dc
Fix performance of removed instruction which halt were halting the pipeline
2017-03-18 10:51:55 +01:00
20ca348707
Fix dCmd sent while the execute stage is removed
...
Pass dhrystone benchmark without error !
2017-03-17 21:26:42 +01:00
7517ac797d
Add MUL/DIV/REM support with plugins (pass Riscv-Tests)
2017-03-17 11:45:01 +01:00
52a524be06
Add light shifter plugin
2017-03-16 15:11:06 +01:00
401be6ca83
Reorganize project
2017-03-16 13:14:25 +01:00
bf5bebda08
PcManager now drive PC asyncronously (use 1 cycle less in jump)
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Fix bypass logic when read/write r0
Disable REGFILE_WRITE_VALID in decod stage when r0 is written
2017-03-15 21:10:44 +01:00
83232e9860
Faster pipeline arbitration logic (200 Mhz on cyclone IV c6)
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Branch plugin with jump in execute or memory stages (parameter)
2017-03-15 20:02:56 +01:00
c6610ea454
Fix halt arbitrations
2017-03-15 17:14:58 +01:00
11797fbb6e
Add sim performance print
2017-03-14 23:25:04 +01:00
70d910e7d7
Load/Store pass Riscv-Tests
2017-03-14 23:00:24 +01:00
7065ed5d93
All base instruction pass Riscv-Test (load/store not tested)
2017-03-14 20:13:35 +01:00
ad6964f0bb
Classify tests
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Riscv-test integration wip
2017-03-14 00:42:48 +01:00
df99a0d963
Better decoding
2017-03-13 18:30:37 +01:00
e36c90af03
Add decoder bench
2017-03-13 16:17:57 +01:00
9fc82c9736
Pass verilator simple literal, add, jump
2017-03-12 20:12:40 +01:00
ec4837a744
wip
2017-03-12 12:39:33 +01:00
cb1b73bc2b
Add branch
2017-03-11 19:07:08 +01:00
23abdb7f95
Add hazard tracking plugin
2017-03-11 16:45:04 +01:00
e58f28bc27
Add store/load
2017-03-11 15:35:56 +01:00
fcb70a333f
WIP
2017-03-11 00:34:49 +01:00
fc7e9a7730
wip
2017-03-09 01:07:55 +01:00
130ed6345c
boot
2017-03-08 22:17:48 +01:00
Dolu1990
Tom Verbeure
Brett Foster
Morard Dany
Dolu1990
Tony Kao
Ubuntu