2d75aee7e0
soc_core: ctrl: document registers
...
This adds a small amount of documentation to the three registers present
inside the `CTRL` module.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-01-02 15:37:45 +08:00
a251d71211
cores: timer: fix documentation formatting
...
The ReStructured Text used was not properly formatted, resulting in
confusing and broken output. This corrects the output and lets it
format correctly when using sphinx.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-01-02 15:36:35 +08:00
db7a48c05d
soc/cores/clock: also allow margin=0 on iCE40PLL and ECP5PLL
2020-01-01 13:24:06 +01:00
219bb7f294
add the possibility for a "precise" clock solution
...
If clocks and multipliers are planned well, we can have
a zero-error solution for clocks. Suggest to change < to <= in
margin comparison loop, so that a "perfect" solution is allowed
to converge.
2020-01-01 18:49:35 +08:00
9336fe1139
build/microsemi/libero_soc: update add_period_constraint behavior when clock is already constrainted.
2019-12-31 10:33:12 +01:00
3022f02b3f
build/xilinx/vivado: update add_period_constraint behavior when clock is already constrainted.
2019-12-31 10:32:09 +01:00
fe4eaf5860
build/lattice/icestorm/add_period_constraint: improve
...
- store period in ns.
- pass clocks to_build_pre_pack and do the convertion to MHz there.
- improve error message.
2019-12-31 10:30:09 +01:00
6b91e8827c
soc/integration/builder: avoid try/except on LiteDRAM import, just check if SoC has an sdram and do the import if so
2019-12-31 09:58:26 +01:00
2157d0f332
Merge pull request #327 from zakgi/master
...
moving RAM offsets outside of CSR_ETHMAC define
2019-12-31 09:49:53 +01:00
f0b5c67216
Allow specifying the same clock constraint multiple times.
...
(As long as the clock values actually match.)
2019-12-30 19:25:14 +01:00
8b955e6f69
Allow LiteX builder to be used without LiteDRAM.
2019-12-30 19:24:26 +01:00
a738739acd
Improve the invalid CPU type error message.
2019-12-30 16:10:57 +01:00
85ade2b3b3
build/xilinx/programmer: fix vivado_cmd when settings are sourced manually.
2019-12-30 10:07:08 +01:00
39ae230b83
moving RAM offsets outside of CSR_ETHMAC define
2019-12-29 22:56:42 -08:00
ffa7ca8f0b
Merge pull request #321 from gsomlo/gls-rocket-aximem-wide
...
cpu/rocket: variants with double (128b) and quad (256b) wide mem_axi
2019-12-21 21:31:04 +01:00
e754c0555a
Merge pull request #319 from DurandA/feature-integer-attributes
...
Add integer attributes
2019-12-21 21:30:09 +01:00
cd8feca574
cpu/rocket: variants with double (128b) and quad (256b) wide mem_axi
...
Various development boards' LiteDRAM ports may have native data
widths of either 64 (nexys4ddr), 128 (versa5g), or 256 (trellis)
bits. Add Rocket variants configured with mem_axi ports of matching
data widths, so that a point to point connection between the CPU's
memory port and LiteDRAM can be accomplished without any additional
data width conversion gateware.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-12-21 14:11:48 -05:00
585b50b292
soc_core: csr_alignment assertions
...
Enforce the condition that csr_alignment be either 32 or 64 when
requested explicitly when initializing SoCCore().
Additionally, if a CPU is specified, enforce that csr_alignment be
equal to the native CPU word size (currently either 32 or 64), and
warn the caller if an alignment value *higher* than the CPU native
word size was explicitly requested.
In conclusion, if a CPU is specified, then csr_alignment should be
assumed to equal 8*sizeof(unsigned long).
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-12-21 13:00:40 -05:00
b6818c205e
cpu/rocket: access PLIC registers via pointer dereference
...
Since the PLIC is internal to Rocket, access its registers
directly via pointer dereference, rather than through the
LiteX CSR Bus accessors (which assume subregister slicing,
and are therefore inappropriate for registers NOT accessed
over the LiteX CSR Bus).
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-12-21 12:59:19 -05:00
0e46913d52
cpu/microwatt: add initial software support
2019-12-20 23:32:21 +01:00
94e239ff13
Add integer attributes
2019-12-19 09:03:12 +01:00
f8c5821658
Revert "gen/fhdl/verilog: allow single element verilog inline attribute"
...
This reverts commit b845755995
2019-12-19 08:53:44 +01:00
f883f0c703
cpu/microwatt: add submodule
2019-12-18 19:07:08 +01:00
5da0bcbd7a
cpu/microwatt: set csr to 0xc0000000 (IO region)
2019-12-18 08:59:35 +01:00
39a8ebe70c
cpu/microwatt: fix add_source/add_sources
2019-12-18 08:56:36 +01:00
d74a7463e0
soc/cores/pwm: remove debug print(n)
2019-12-18 08:47:56 +01:00
bd15f07cf7
platforms/netv2: add xc7a100t support
2019-12-17 09:47:31 +01:00
76e57414c3
platforms/minispartan6: add assert on available devices
2019-12-17 09:47:12 +01:00
bfe0bf6402
cpu/microwatt: simplify add_sources
2019-12-17 09:41:46 +01:00
b9edde20de
cpu/microwatt: add io_regions and gcc_flags
2019-12-17 09:33:46 +01:00
16e7c6b634
cpu/microwatt: update copyright
2019-12-17 09:27:19 +01:00
3d79324fce
cpu/microwatt: drive stall signal (no burst support)
2019-12-16 12:37:27 +01:00
da3a178bc6
soc/cores/pwm: add clock_domain support
2019-12-16 11:13:10 +01:00
9da28c4ea5
build/xilinx/XilinxMultiRegImpl: fix n=0 case
2019-12-16 11:12:38 +01:00
ec7dc2d8f4
build/xilinx/ise: cleanup/simplify pass, remove mist support (not aware of anyone using it)
2019-12-14 22:47:07 +01:00
1b963bb2d5
soc/cores/cpu: add initial Microwatt gateware support
...
Implementation tested on arty:
cd litex/soc/cores/cpu/microwatt
git clone https://github.com/antonblanchard/microwatt
mv microwatt sources
cd litex/boards/targets
./arty --cpu-type=microwatt --no-compile-gateware
2019-12-14 00:00:13 +01:00
c34255d2ab
soc/cores/cpu/minerva: add self.reset to i_rst
2019-12-14 00:00:07 +01:00
a0dad1b071
soc_core: additional CSR safety assertions
...
Since csr_data_width=64 has probably never worked properly, remove
it as one of the possible options (to be fixed and re-added later).
Add csr_data_width=16, which has been tested and does work.
Additionally, ensure csr_data_width <= csr_alignment (we should not
attempt to create (sub)registers larger than the CPU's native word
size or XLen).
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-12-12 13:14:16 -05:00
fb6b0786b6
soc_core: remove static 16MB csr region allocation (use csr_address_width to allocate the correct size)
2019-12-12 12:41:47 +01:00
b1a1e5e227
soc_core: add sort of CSR regions by origin (allow csr.h/csr.csv to be ordered by origin)
2019-12-12 11:27:56 +01:00
061d593de3
cores/8b10b: use real Memory for 6b5b table (to improve timings on ECP5)
2019-12-09 19:25:38 +01:00
a0122f9863
build/xilinx/vivado: move build_script generation
2019-12-08 12:19:38 +01:00
18ff8f38d1
build/xilinx/vivado: cleanup/simplify
2019-12-08 12:08:17 +01:00
0931ccc919
build/lattice/icestorm: cleanup/simplify (and remove arachne-pnr support)
2019-12-07 22:11:17 +01:00
b1b920531a
build/xilinx/common/platform/programmer: cleanup pass
2019-12-06 22:23:04 +01:00
edaa66bbed
boards: add Lambdaconcept's PCIe Screamer (R02)
2019-12-06 18:20:59 +01:00
a8635c48a4
targets/versa_ecp5: fix compilation with diamond
2019-12-06 16:15:08 +01:00
30a18808ad
boards/targets: keep attributes are no longer needed since automatically added when applying constraints to signals.
2019-12-06 15:58:06 +01:00
23c33cfa99
build: automatically add keep attribute to signals with timing constraints.
...
Avoid having to specify it manually or eventually forget to do it and have a constraints that is not applied correctly.
2019-12-06 15:41:15 +01:00
4c9af635d2
build/altera/quartus: allow adding period constraints on nets and add optional additional sdc/qsf commands
...
Additional sdc/qsf commands can be added from the design like:
platform.sdc_additional_commands.append("create_clock ...")
platform.sdc_additional_commands.append("set_false_path ...")
2019-12-06 15:19:07 +01:00
22e6f5ac1d
build/lattice/trellis: nextpnr now handle LPF timing constraints and multiple clock domains, freq_constraint is no longer needed.
2019-12-06 12:57:59 +01:00
8fb3f9a90d
build/lattice: cleanup/simplify (no functional changes)
...
icestorm still need to be cleaned up
2019-12-06 12:54:52 +01:00
946478a71e
build/lattice: cleanup/simplify
2019-12-06 12:13:20 +01:00
60edca2345
build/microsemi: cleanup/simplify (no functional change)
2019-12-06 12:12:43 +01:00
50fdc5ce41
build/altera: cleanup/simplify (no functional change)
...
Altera build backend was a bit messy and needed some cleanup to ease future maintenance and new features.
2019-12-06 11:08:46 +01:00
b17dfafa55
Merge pull request #313 from mmicko/yosys_ise_flow_fix
...
Yosys - ISE flow fix
2019-12-05 19:05:44 -08:00
8d90f4e97b
build/xilinx/vivado: use VHDL 2008 as default
2019-12-03 15:27:20 +01:00
cfd17321e2
targets/nexys4ddr: remove MEMTEST_ADDR_SIZE limitation (no longer needed)
2019-12-03 10:11:15 +01:00
201d60f37a
targets/netv2: switch to MVP DDR3 (K4B2G1646F instead of MT41J128M16)
2019-12-03 09:05:52 +01:00
6b82064723
targets: uniformize, improve presentation
2019-12-03 08:58:01 +01:00
6de20f185a
soc/interconnect/csr: add fields support for CSRStorage's write simulation method
2019-12-02 09:44:44 +01:00
2567a0ae1d
soc/cores/gpio: add GPIO Tristate
2019-12-01 21:26:37 +01:00
f411d6d362
trellis: Support the CABGA256 package
2019-11-30 02:50:41 +01:00
783dfa508c
Properly select family for those currently supported
2019-11-29 19:11:22 +01:00
6560911df2
Integrate with latest yosys changes
2019-11-29 17:12:08 +01:00
581c23725e
spi_flash: correct documentation on SPI mode
...
The SPI mode is actually mode3, since the output value is updated on the
falling edge of CLK and the input value is updated on the rising edge.
This also clarifies some of the documentation based on experience with
the core.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-11-25 12:35:13 +08:00
de205d4a84
tools/remote/comm_udp: only use one socket
2019-11-22 15:28:35 +01:00
bdaca40fe4
build/generic_platform: avoid duplicate in GenericPlatform.sources
2019-11-22 15:28:07 +01:00
6883a43680
soc/cores/clock: change drp_locked to CSRStatus and connect it :)
2019-11-20 19:37:16 +01:00
36107cdfd7
soc/cores/clock: reset PLL/MMCM on all 7-series/Ultrascale with self.reset signal
2019-11-20 19:24:40 +01:00
e8e70b164a
Merge pull request #309 from antmicro/mmcm-fix
...
soc/cores/clock: add lock reg and assign reset
2019-11-20 19:20:15 +01:00
fd14b76594
soc/cores/clock: add lock reg and assign reset
...
It was necessary to add drp_locked CSR for reading LOCK signal from
MMCM. Additionally, input signal RESET from MMCM was not driven by
any signal to do a proper reset of MMCM module thus it was impossible
to perform entirely correct dynamic clock reconfiguration.
2019-11-20 16:22:49 +01:00
04017519c8
soc/interconnect/axi: add Wishbone2AXILite
2019-11-20 12:32:22 +01:00
d905521185
build/tools/get_migen/litex_git_revision: avoid git fatal error message is not installed as a git repository
2019-11-19 09:11:11 +01:00
02bfda5e38
Merge pull request #308 from gsomlo/gls-sdram-init
...
soc_sdram, bios/sdram: support sdram init for csr_data_width <= 32
2019-11-18 18:24:35 +01:00
3ef13fd27a
soc_sdram, bios/sdram: support sdram init for csr_data_width <= 32
...
Enable SDRAM to be initialized when csr_data_width > 8 bits.
Currently, csr_data_width up to 32 bits is supported.
Read leveling tested with csr_data_width [8, 16, 32] on the
ecp5-versa5g and trellisboard (using yosys/trellis/nextpnr),
and on the nexys4ddr (using Vivado).
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-11-18 09:00:19 -05:00
1efb18f1ea
soc/interconnect/packet/Depacketizer: another simplifcation pass
2019-11-18 09:06:56 +01:00
af52203c00
soc/interconnect/packet/Depacketizer: cleanup "ALIGNED-DATA-COPY" state
2019-11-17 11:57:14 +01:00
8272a00d6e
soc/interconnect/packet/Depacketizer: replace no_payload with sink_d.last
2019-11-17 11:50:09 +01:00
6059712794
test/test_packet: add randomness on ready output, fix corner-cases on Packetizer/Depacketizer
2019-11-16 14:39:18 +01:00
9642893371
test/test_packet: add randomness on valid input, fix corner-cases on Packetizer
2019-11-16 08:49:04 +01:00
888fd55bd8
Merge pull request #307 from sergachev/master
...
change >512 B CSR memory exception to a warning
2019-11-15 18:17:35 +01:00
2f2cfc9951
soc/interconnect/packet: fix synthesis (synthesis tools can do all sort of optimizations, but we still need to provide valid verilog :))
2019-11-15 16:19:05 +01:00
444ae951e9
change >512 B CSR memory exception to a warning
2019-11-15 15:34:12 +01:00
31661e9e2d
soc/interconnect/packet: connect error/last_be only present on both sink and source
2019-11-15 14:57:31 +01:00
2946581e50
soc/interconnect/packet: simplify/refactor Packetizer/Depacketizer to keep it simple
...
To avoid complex FSMs, let the synthesis tool do the simplifications when the FSM states are not reachable.
2019-11-15 14:39:55 +01:00
86662b54d0
soc/interconnect/packet: update copyright
2019-11-15 11:25:38 +01:00
5c19b133ac
soc/interconnect/packet: add > 8-bit support to Packetizer/Depacketizer
...
With high speed link (10gbps XGMII ethernet for example), stream data_width is generally
> 8-bit which make header/data un-aligned on bytes boundaries. The change allows the
Packetizer/Depacketizer to work on stream with a data_width > 8-bit.
2019-11-15 11:24:17 +01:00
5f151152ca
build/sim: cleanup run_as_root
2019-11-15 10:57:31 +01:00
446ae57b75
build/sim/modules: add XGMII 10Gbps ethernet module
...
Used to simulate SoCs with XGMII 10Gbps ethernet and to do LiteEth verification
2019-11-15 10:51:55 +01:00
56fbd2f250
sim/ethernet: remove trailing whitespaces
2019-11-15 10:39:49 +01:00
eb3888f68e
tools/litex_sim: cleanup/update (no functional change)
2019-11-14 11:19:23 +01:00
4798d6b750
tools/litex_term: remove automatic reboot when flashing and clear mem_regions to avoid re-flashing on next reboot(s)
2019-11-11 18:38:10 +01:00
a17e307acf
bios/flash: minor cleanup on serialboot flashing, add flash address support
2019-11-09 00:05:36 +01:00
2d6100bdbe
Merge pull request #305 from FrankBuss/master
...
adding support to flash an FBI image
2019-11-08 23:51:49 +01:00
05e8abfee3
soc_core: add integrated-rom-file parameter to allow initializing rom from command line
2019-11-08 23:32:10 +01:00
0a030fe17d
cores/code_8b10b/Decoder: add basic invalid symbols detection
...
Check that we have 4,5 or 6 ones in the symbol. This does not report all
invalid symbols but still allow detecting issues with the link.
2019-11-08 19:43:01 +01:00
9857d9d9d2
adding support to flash an FBI image
2019-11-08 17:16:28 +01:00
c96f31a9ad
software/bios: rename ef command to fe (for consistency)
2019-11-08 13:14:21 +01:00
4a12a92d62
software/libbase/spiflash: rename CHIP_ERASE_CMD to CE_CMD (for consistency)
2019-11-08 13:13:54 +01:00
7fb9cfeb64
Merge pull request #302 from FrankBuss/master
...
erase flash command added
2019-11-08 13:04:33 +01:00
db4739df81
soc_core: remove add_cpu method (when no real CPU but only wishbone masters, self.cpu is declared as CPUNone)
2019-11-08 12:55:29 +01:00
468df3c857
erase flash command added
2019-11-07 19:19:54 +01:00
f1714405c3
integration/export: do not include soc.h in csr.h when with_access_functions=False
...
Idealy we should have another parameter for that.
2019-11-07 09:02:31 +01:00
b52dcde9ba
soc_sdram/kcu105: add optional main_ram_size_limit and use it on KCU105 to limit to 1GB instead of 2GB.
...
CSR map will need to be updated to support the 2GB.
2019-11-07 09:00:54 +01:00
9053d0803a
soc_sdram: remove use_full_memory_we parameter (always used as True)
2019-11-07 08:56:52 +01:00
1b94699d12
soc_sdram: update copyrights
2019-11-07 08:44:34 +01:00
28708f4208
cpu/rocket: parameterize axi interface data width
...
Rocket variants can be configured with axi port data widths that
are multiples of the native word size (64 bits in our case). In
the future, we will add variants with mem_axi data width > 64 bit,
to match the native data width of the LiteDRAM controller on
various development boards (e.g., 128 bits on the ecp5versa, and
256 bits on the trellisboard).
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-11-01 08:55:27 -04:00
014db66444
soc_sdram: remove upper limit on usable main RAM
...
Revert commit #68a503174.
2019-11-01 08:55:15 -04:00
ec831f5b63
cpu/rocket, soc_sdram: Connect mem_axi to LiteDRAM, bypass WB bus
...
Connect Rocket's dedicated port for cached RAM accesses (mem_axi)
directly to the LiteDRAM data port, bypassing the shared LiteX
(Wishbone) bus.
When both Rocket's mem_axi and LiteDRAM's port have the same data
width, use a native point-to-point AXI connection.
Otherwise, convert both ends to Wishbone, and use the Wishbone
data width converter to bridge the gap.
FIXME: In the future, this part should be replaced with a native
AXI data width converter!
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-11-01 08:52:39 -04:00
9c3c43c94a
interconnect/csr_bus/SRAM: add mem_size check
...
Memory size is limited to 512 bytes:
- CSR region size is 0x800 (4096)
- default csr_data_width is 8
maximum size = 4096/8 = 512 bytes.
2019-11-01 11:33:50 +01:00
edb1731ef9
soc_core/soc_core_args: specify default cpu (vexriscv)
2019-11-01 11:30:50 +01:00
cc607f022a
lattice/diamond/tcl: always use / separators, even on windows
2019-11-01 10:11:12 +01:00
59acf0ea1c
cpu/minerva: elaborate minerva verilog to build directory
2019-11-01 09:59:13 +01:00
a762d29b19
soc/integration/builder: pass output_dir to platform, make sure gateware/software directory are created before finalizing
2019-11-01 09:59:06 +01:00
855d0e925d
cpu/minerva: generate minerva.v near core.py not in submodule
2019-10-31 21:16:27 +01:00
85d6607257
cpu/minverva: give more explicit error message when not able to elaborate cpu
2019-10-31 08:52:04 +01:00
4408dad9d2
Improve the error message on memory region conflict.
...
Before;
```
ValueError: Memory region conflict between rom and main_ram
```
After;
```
ValueError: Memory region conflict between rom (<SoCMemRegion 0x10000000 0x10000 cached>) and main_ram (<SoCMemRegion 0x0 0x20000000 cached>)
```
Fixes #296 .
2019-10-30 19:32:20 -07:00
607e1cc4f6
Fix file names for the mor1kx processor.
...
Fixes #292 .
2019-10-30 13:50:01 -07:00
a54b80b9b4
targets: use type="io" instead of io_region=True
2019-10-30 16:42:31 +01:00
a0c0a6fd05
integration/SoCMemRegion: use type instead of io_region/linker_region and export type to csv/json
...
Supported types: "cached", "io", "cached+linker", "io+linker", default="cached"
2019-10-30 16:42:26 +01:00
9fcf297387
soc_core: add check_regions_overlap method, add linker_region support (overlap is not checked on linker_regions)
2019-10-28 18:34:03 +01:00
4014fbffe1
soc_core/add_memory_region: fix memory overlap detection
2019-10-28 17:07:37 +01:00
ab8af28213
cpu/minerva: elaborate from nmigen sources during build, enable hardware multiplier
2019-10-28 10:23:08 +01:00
49372852da
build/lattice/trellis: optionally allow failure if p&r timing not met
...
When timing requirements are strict, allow the build process to fail upon
failure to meet timing. This facilitates running the build process from a
loop, repeatedly, until a "lucky" p&r solution is found, e.g.:
while true; do
litex/boards/targets/versa_ecp5.py --gateware-toolchain trellis \
--sys-clk-freq=60e06 --cpu-type rocket --cpu-variant linux \
--with-ethernet --yosys-nowidelut \
--nextpnr-timingstrict
if [ "$?" == "0" ]; then
echo "Success" | mail -s "Build Succeeded" your@email.here
break
fi
done
This augments commit #683e0668, which unconditionally forced p&r to
succeed, regardless of whether timing was met, via '--timing-allow-fail'.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-10-24 13:56:20 -04:00
b6d35c92ae
Merge pull request #283 from kbeckmann/kbeckmann/bios_increment_address
...
bios: Increment address when writing to flash
2019-10-20 15:30:22 +02:00
ef78ae951f
bios: Increment address when writing to flash
2019-10-19 22:58:24 +02:00
683e066812
build/lattice/trellis: use --timing-allow-fail to allow generating bistream when timings are not met
...
This is the default behaviour of the others tools and allow testing designs on hardware with small violations.
2019-10-18 14:12:01 +02:00
4cf346a1d4
soc/cores/icap/ICAPBitstream: always keep fifo.source.ready to 1
2019-10-18 10:27:37 +02:00
8b5da9c623
cores/icap/ICAPBitstream: add source ready signal.
2019-10-18 09:33:31 +02:00
626533ce9d
soc/integration/__init__: remove imports (not used and causing issues
2019-10-17 12:44:37 +02:00
675b455259
build: always use platform.add_source and avoid manipulate platform.sources directly
2019-10-17 12:17:36 +02:00
43f5d1ef13
build/generic_platform: replace set with list for sources/verilog_include_paths
...
Python does not have native OrderedSet and we need to be able to preserve the order of the sources
for some backends (Verilator for instance), so use list instead of set.
2019-10-17 09:52:49 +02:00
97a77b950c
cores/icap/ICAPBitstream: simplify, add icap_clk_div parameter, describe how to use it.
2019-10-16 15:00:58 +02:00
98c224be15
build/generic_platform: keep language to None if None after tools.language_by_filename
2019-10-15 12:14:37 +02:00
14dae8bd73
soc_core: fix default --uart_name
2019-10-14 22:15:02 +02:00
ba26441889
integration/soc_core: expose more SoC parameters
2019-10-14 09:12:25 +02:00
0e467168fd
picorv32: Fix minimal variant params
...
The param p_ENABLE_COUNTERS was misspelled.
2019-10-13 12:56:55 +02:00
ef504f62af
soc_core: fix soc_core_argdict
2019-10-12 23:05:53 +02:00
cd8213b988
cpu/lm32: add missing buses
2019-10-12 19:20:50 +02:00
5a0358754d
soc_core/soc_core_argdict: use inspect to get all parameters and simplify
2019-10-12 19:18:57 +02:00
96c369f3e4
integration: simplify cpu buses auto-conversion (always use Converter, thanks gsomlo)
2019-10-11 21:55:26 +02:00
29e51f5e97
interconnect/wishbone: fix Converter case when buses are identical
2019-10-11 21:49:11 +02:00
ae9c25b74f
platforms/versa_ecp5: add serdes refclk/sma
2019-10-11 19:51:38 +02:00
9a82933858
cpu/rocket: expose 64-bit buses (use automatic down-conversion of SoCCore)
2019-10-11 09:01:50 +02:00
ca81cc209b
soc_core: add automatic down-conversion of CPU buses to 32-bit (if needed)
2019-10-11 09:01:08 +02:00
03faf06c82
soc/interconnect/axi: re-align to improve readability
2019-10-11 08:41:05 +02:00
7dea9afd7d
software/bios: simplify banners
2019-10-11 08:38:12 +02:00
6bd1889330
cpu/picorv32: remove obsolete comment
2019-10-10 22:29:54 +02:00
28517d20ca
cpu/picorv32: use a single idbus
2019-10-10 22:02:04 +02:00
5daf1a2296
cpu: cleanup/re-align
2019-10-10 21:52:09 +02:00
467d35edee
cpu/rocket: rename ibus/dbus to mem_wb/mmio_wb and add size suffix
2019-10-10 21:40:29 +02:00
1045cda39e
cpu: add buses list and use it in soc_core to add bus masters
2019-10-10 21:35:06 +02:00
42ccc91f74
integration: move soc constants to soc.h of csr.h
...
software retro-compat with soc.h included in csr.h
2019-10-10 21:15:49 +02:00
ed3c53d7cd
build/generic_platform: only add sources if language is not None
2019-10-10 19:39:33 +02:00
f3ba078882
xilinx/vivado: replace "xy" == language with language == "xy"
2019-10-10 19:36:17 +02:00
17756f631b
Merge pull request #277 from railnova/feature/vivado_sysverilog_support
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[feature] Add SystemVerilog support for the Vivado builder
2019-10-10 19:31:09 +02:00
b25194826e
integration/soc_zynq: shadow_base no longer recommended (replace with io_regions)
2019-10-10 19:23:01 +02:00
496ba7e594
bios/main: use same banner than README (MiSoC cited in README/LICENSE)
2019-10-10 19:21:32 +02:00
840f01b6d5
software/bios: don't show peripherals init banner if nothing to init, add Ethernet init printf
2019-10-10 19:18:28 +02:00
f2369a4c9e
Add system Verilog support for the Vivado builder
2019-10-10 14:10:28 +02:00
f8f643a02f
cpu/rocket: swap main_mem and io regions
...
The total size of RAM (main_mem) can be expected to vary significantly,
and often exceed the size needed for MMIO allocations by a large margin.
As such, place Rocket's MMIO (io regions) below 0x8000_0000, and start
the RAM (main_mem) at 0x8000_0000, with nothing above it to limit its
future growth.
Also, bump the pre-built Rocket verilog submodule to an updated version,
which also comes with matching changes to the way MMIO and RAM accesses
are mapped and routed to their respective AXI interfaces.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-10-09 14:25:41 -04:00
b627a8fe71
cpu: add default io_regions to CPUNone (all address range can be used as IO)
2019-10-09 12:06:21 +02:00
a6b3aa3c62
soc_core: improve check_io_region error message
2019-10-09 10:47:19 +02:00
dc656d48c2
targets/sim: switch from shadow_base to io_regions
2019-10-09 10:38:22 +02:00
10146abf0a
cpu/rocket: move csr to IO region
2019-10-09 10:24:01 +02:00
7f1d4623ff
build/xilinx/vivado: fix default synth-mode
2019-10-09 10:19:18 +02:00
a4ef9b29b9
soc_core/cpu: add io_regions and deprecate shadow_base (with API retro-compat)
...
The shadow_base parameter has always been difficult to apprehend, replace it with
io_regions (uncached regions) defined user or the CPU.
The equivalent of a shadow_base parameter of 0x80000000 in the old API is:
io_regions = {0x80000000: 0x80000000} # origin, length
It's still possible to use shadow_base with retro-compat, but user is encouraged
to update and features will be removed in the future.
2019-10-09 10:15:42 +02:00
53777391e8
builder: use the SoC's existing shadow base with get_csr_header()
...
Both the SoC and get_csr_header() have independently set defaults
for the value of 'shadow_base'. If the SoC's value was modified,
ensure that get_csr_header() uses the modified value instead of
its own default.
Signed-off-by: Gabriel Somlo <somlo@cmu.edu>
2019-10-08 14:28:50 -04:00
92975b139e
targets/arty: allow setting synth-mode to yosys with command line: --synth-mode=yosys
2019-10-07 10:38:26 +02:00
4a1cefe946
build/xilinx/vivado: add vivado_build_args/vivado_build_argdict for yosys synthesis mode
2019-10-07 10:37:16 +02:00
3e22d4b9e6
xilinx/common: be sure language is not vhdl when yosys synthesis is used
2019-10-07 10:36:32 +02:00
975bd9be8b
cpu/vexriscv: use specific mem_map for linux variant
2019-10-07 08:50:03 +02:00
2dfe7441d6
Merge pull request #271 from gsomlo/gls-yosys-nowidelut
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RFC: optional '-nowidelut' flag for yosys synth_ecp5
2019-10-06 14:55:44 +02:00
6aa76b1df8
trellis, versa_ecp5: optional '-nowidelut' flag for yosys synth_ecp5
...
Passing '-nowidelut' to yosys' synth_ecp5 command improves area utilization
to the point where a (linux variant) rocket-chip based design will fit on a
versa_ecp5 board. Usually '-nowidelut' incurs a timing penalty, but that is
then mitigated by using DSP inference (enabled by default from yosys commit
8474c5b3).
Off by default, this flag can be enabled by adding '--yosys-nowidelut=True'
to the litex/boards/targets/versa_ecp5.py command line.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-10-06 08:37:43 -04:00
2f7bd97129
fix comments
2019-10-06 10:47:28 +02:00
960b25a541
Merge pull request #270 from gsomlo/gls-csr-upper
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soc/integration: ensure CSR constants are in uppercase
2019-10-01 21:40:56 +02:00
41ad08e8ef
soc/cores/icap: simplify ICAPBitstream (untested)
2019-10-01 21:30:14 +02:00
0c2993866c
soc/cores/icap: rename ICAP to ICAPBistream and revert old ICAP
2019-10-01 21:04:49 +02:00
4bb2827e05
Merge pull request #269 from antmicro/rework_icap
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soc: cores: support sending custom bitstream to ICAP
2019-10-01 20:55:28 +02:00
c8790d342a
soc/integration: ensure CSR constants are in uppercase
...
Fixup over commit 8be5824e
2019-10-01 12:15:25 -04:00
4423a46ba2
soc: cores: support sending custom bitstream to ICAP
...
This adds FIFO that can be used to send any
sequence of commands to the ICAP controller.
2019-10-01 13:44:45 +02:00
427d7af767
soc/interconnect: rename stream_packet to packet & cleanup (with retro-compat)
2019-09-30 23:41:07 +02:00
59bf04d965
soc/interconnect/stream: add separators, mode Actor modules just after Endpoint
2019-09-30 23:33:25 +02:00
59995c5359
soc_zynq: update get_csr_header
2019-09-30 16:00:11 +02:00
4d90058b18
soc/integration: move cpu_interface retro-compatibility to litex/__init__
2019-09-30 11:32:07 +02:00
8be5824e25
soc/integration: use dicts for constants/mem_regions/csr_regions to cleanup/simplify iterations on theses
2019-09-30 10:59:36 +02:00
7b72148c4e
cpu: remove initial SERV support (we'll work in a branch to experiment with it)
2019-09-30 08:35:18 +02:00
63a813af9c
soc_core: fix cpu_type=None case and add test for it
2019-09-30 08:26:38 +02:00
3d257d7266
soc_sdram: remove axi usecase, this was only useful to do some preliminary axi tests.
...
Proper AXI support will be added in the future for SoCs.
2019-09-29 17:33:16 +02:00
e8e57b4f87
soc_core: cleanup/re-align
2019-09-29 17:31:37 +02:00
334ae336bf
soc/integration: rename cpu_interface to export (with retro-compat), re-arrange a bit, add separators
2019-09-29 17:23:26 +02:00
48e5a1d140
soc/cores: uniformize (continue)
2019-09-29 17:04:21 +02:00
e9ed4761b5
soc/cores/gpio: uniformize with others cores
2019-09-29 16:10:44 +02:00
78cecbe36b
soc/cores: rename frequency_meter to freqmeter and uniformize with others cores
2019-09-29 16:08:39 +02:00
7575ecc6ad
soc/cores/ecc: improve readibility, uniformize with others cores
2019-09-29 16:02:04 +02:00
c6fe3f3145
soc/cores/clocks: improve readibility
2019-09-29 15:58:22 +02:00
6fcb12a98f
soc_core: use cpu.data_width to compute csr_alignment (and remove Rocket workaround)
2019-09-29 15:47:10 +02:00
b826c1705f
soc/cores/cpus: improve ident/align, uniformize between cpus
2019-09-29 15:41:36 +02:00
355072c285
soc/cores/cpu: add CPU class and make all CPU inheritate from it
...
Also rename reserved_interrupts to interrupts (empty dict is no reserved interrupts)
2019-09-29 15:27:41 +02:00
2c3ad3f96d
soc_sdram: move ControllerInjector to LiteDRAM (LiteDRAMCore)
2019-09-29 14:44:44 +02:00
101f1b1cef
soc/integration: add common.py and move helpers from soc_core to it
2019-09-29 14:22:26 +02:00
68ba1c60be
soc_core: avoid manual listing of support CPUs, just use CPU.keys()
2019-09-28 22:19:23 +02:00
9095b80e89
soc_core: remove add_cpu_or_bridge retro-compatibility (most of the designs have been updated since the change)
2019-09-28 19:01:41 +02:00
8dd2dc1ce8
integration/soc_core: remove csr_map_update (no longer used)
2019-09-28 18:59:30 +02:00
da91aa43f7
soc_core/cpu: move memory map override to CPUs, select reset_address after eventual memory map has override been done
2019-09-28 14:15:48 +02:00
8099b0beb6
soc/cores/cpu: add set_reset_address method and use it instead of passing reset_address as a parameter
2019-09-28 12:35:41 +02:00
7660dc22e1
soc/cores/cpu: do instance in do_finalize for all cpus (allow updating parameters until the design is generated)
2019-09-28 12:09:55 +02:00
a3816096a7
cores/cpu: define CPUS and simplify instance
2019-09-28 00:55:08 +02:00
9f6a2ae73e
soc_core/serv: use UART_POLLING (no interrupt support)
2019-09-28 00:42:00 +02:00
49594ed7d4
software/libbase/uart: add polling mode
2019-09-28 00:35:26 +02:00
3f95b9c0de
add SERV CPU initial support (not working)
2019-09-28 00:34:55 +02:00
015b65fe88
targets/ulx3s: revert to cl=2
2019-09-25 14:09:44 +02:00
a9d55b04c0
boards/netv2: switch to MVP, add spiflashx4 and hdmi in/out
2019-09-25 14:07:28 +02:00
1425a68d9e
wishbone2csr: refactor using FSM, reduce latency (make it asynchronous) and set csr.adr only when access is done (allow use of CSR/CSRBase we signal)
...
Making it asynchronous does not seem to deteriorate timing or resource usage, if it's the case for some designs, we'll add a register parameter.
2019-09-24 17:55:29 +02:00
ffd2be2ba0
csr: add we signal to CSR, CSRStatus
...
Doing actions on register read is generally not a good design practice (it's
better to do separate register write to trigger actions) but in some very
specific cases being able to know that register has been read can solve cases
that are difficult to do with the recommended practives and that can justify
doing an exception.
This commit add a we signal to CSR, CSRStatus and this allow the logic to know
when the CSR, CSRStatus is read.
2019-09-24 17:51:06 +02:00
47dc332498
build/xilinx/programmer: fix vivado_cmd
2019-09-24 14:40:48 +02:00
ed9bff2eb9
soc/integration/doc: replace "== None" by "is None"
2019-09-24 10:11:31 +02:00
836d5b88c5
Merge pull request #266 from xobs/add-moduledoc-autodoc
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Add ModuleDoc and AutoDoc
2019-09-24 10:09:22 +02:00
78fb0fb9dc
tools/litex_read_verilog: also delete yosys_v2j.ys
2019-09-24 08:49:00 +02:00
0ea7a1fd05
soc_core/sdram: Don't blow up if _wb_sdram_ifs or _csr_masters are empty
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For example a standalone controller with no exposed CSRs (probably not
a very useful configuration but I really don't like python backtraces)
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2019-09-24 08:41:59 +02:00
68cea8c32f
timer: inherit ModuleDoc
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With the new ModuleDoc class, we can inherit `ModuleDoc` and
automatically get module-level documentation.
This patch also corrects a typo in `timer` that causes an error in
sphinx.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-24 14:34:41 +08:00
131971986c
integration: add ModuleDoc and AutoDoc
...
It is important to be able to document modules other than CSRs.
This patch adds ModuleDoc and AutoDoc, both of which can be used
together to document modules.
ModuleDoc can be used to transform the __doc__ string of a class into a
reference-manual section. Alternately, it can be used to add additional
sections to a module.
AutoDoc is used to gather all submodule ModuleDoc objects in order to
traverse the tree of documentation.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-24 14:30:28 +08:00
742da31bc0
Merge pull request #264 from antmicro/mor1kx_linux
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Enable to run Linux on mork1x
2019-09-23 23:19:45 +02:00
06d0806494
soc_core: set csr to 0x00000000 when there is no wishbone
2019-09-23 15:57:14 +02:00
ad8830d977
soc_sdram: Don't add the L2 Cache when there's no wishbone bus
2019-09-23 15:53:07 +02:00
5844376d53
soc_core: adapt memory map for mainline Linux with mor1kx
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Mainline Linux expects it to be loaded at the physical address of 0x0.
Change the MAIN_RAM base address to 0x0 and update exception vector
during the booting process.
2019-09-23 15:34:52 +02:00
201218b2c3
boards/targets: increase integrated ROM size if EthernetSoC is used
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Currently section '.rodata' of the LiteX BIOS doesn't fit in the 'rom'
region if mor1kx is used with EthernetSoC. Increase the integrated ROM
size from 0x8000 to 0x10000 in EthernetSoC.
2019-09-23 15:34:34 +02:00
ae38fd4244
soc_core: revert wishbone2csr to __init__ but add with_wishbone parameter
2019-09-23 12:59:43 +02:00
8c979565a8
soc_sdram: change l2_size checks order
2019-09-23 10:15:27 +02:00
a9acab99b3
soc_core: move CSR bridge to finalize (only generate it if there is a wishbone master), revert default parameter when cpu_type is None (we have systems with cpu_type=None but that are using these peripherals)
2019-09-23 09:58:47 +02:00
dde6dd027b
integration/builder: avoid specific _generate_standalone_includes
2019-09-23 09:26:47 +02:00
735ea196dd
This will allow it to be built for microwatt out of tree
...
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2019-09-23 08:40:54 +02:00
c28086cde8
soc_core: When cpu_type is "None", let's not generate useless UART, timer, ROMs, wishbone to CSR bridge etc...
...
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2019-09-23 08:35:50 +02:00
f909e4d706
integration/builder: When the CPU is "None", we used to not generate any code.
...
With this change, we will now generate csr.h and sdram_phy.h, which
will be needed by the initialization code running on the host CPU.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2019-09-23 08:31:21 +02:00
1a6dddd57c
spi_flash: document register fields
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Document the various fields present in the SPI flash bitbang interface.
This adds documentation for the Single and DualQuad modules.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-20 12:42:43 +08:00
9ea11cf5ab
vivado just needs to be in the path for the programmer as well
2019-09-19 20:35:55 -07:00
60d8572c3e
csr_eventmanager: add `name` and `description` args
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Add `name` and `description` as optional arguments to the various
EventSource types. These default to `None`, so this should be a
backwards-compatible change.
Use the same trick as CSRs, where we default the `name` to be the
instantiated object name as read from the Migen `get_obj_var_name()`
call.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-19 17:23:03 +08:00
e2c78572a2
cores/timer: add general documentation on Timer implementation and behavior.
2019-09-19 09:27:24 +02:00
e97c1e36fb
soc_sdram: improve readibility and convert l2_size to minimal allowed if provided l2_size is lower
2019-09-19 05:36:57 +02:00
99ed0877ac
csr: add description to CSRStorage/CSRStatus attributes (thanks xobs)
2019-09-18 10:47:54 +02:00
f2e84a5800
soc/cores/timer: fix typo (thanks xobs)
2019-09-18 10:45:38 +02:00
28885064f7
soc/cores/timer/doc: rewrite a little bit, avoid some redundancy, change ident.
2019-09-18 10:14:47 +02:00
cb7d941aaa
timer: add documentation
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Now that CSRs have documentation support, add documentation to the basic
`Timer` module.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-18 15:06:20 +08:00
cca0478a5e
soc/cores/spi: use new CSRField (no functional change)
2019-09-16 17:02:55 +02:00
80b2bef387
soc/cores/bitbang: use new CSRField (no functional change)
2019-09-16 16:56:00 +02:00
9bda614a3e
csr: update copyrights
2019-09-16 08:49:00 +02:00
29134cc659
csr: more documentation
2019-09-16 08:45:29 +02:00
74e756aa30
csr/CSRStorage: remove storage_full (was only needed by alignment_bits)
2019-09-16 08:38:26 +02:00
5dc440e80d
csr: use IntEnum for CSRAccess
2019-09-16 08:36:25 +02:00
d2646f138e
csr/CSRStorage: remove alignment_bits: complexify too much code for the few use-cases it's really useful
2019-09-15 19:47:48 +02:00
8e14694eb5
csr/fields: document, add separators, 100 characters per line
2019-09-15 19:11:25 +02:00
4e84729cf9
csr/fields: add access parameter
2019-09-14 22:16:18 +02:00
23b01f8f02
csr/fields: add pulse mode support
2019-09-14 21:49:34 +02:00
8c080e5fb6
soc/interconnect/csr: add initial field support
2019-09-13 20:01:31 +02:00
c120f6d457
build/openocd: add set_qe parameter to flash
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QE bit is not set on blank SPI flashes and need to be set when SPI X4 is enabled in the bistream to load the FPGA.
2019-09-12 17:07:56 +02:00
6a0a1c9d87
tools/litex_term/upload: bufferize only chunks of the file instead of the entire file to speedup upload when used on embedded devices (RPI for example)
2019-09-12 10:21:37 +02:00
16b6b357ca
soc/integration/cpu_interface: don't raise OSError if we are not going to compile software and compilation toolchain is not found
2019-09-11 18:30:28 +02:00
62f53d5035
soc/integration/builder: call do_exit with vns when build is done.
2019-09-10 12:41:05 +02:00
cb5f1467cf
Merge branch 'master' of http://github.com/enjoy-digital/litex
2019-09-09 15:12:24 +02:00
004c96b508
soc/itnegration: update litedram
2019-09-09 15:12:08 +02:00
2400f0f43d
fix crc32
2019-09-09 13:19:43 +02:00
19f58dd971
interconnect/wishbone: add FlipFlop to allow UpConverter to be used
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Note: a test should be added for Converter and DownConverter/UpConverter should be cleaned up
2019-09-09 11:47:36 +02:00
bd6ec63be4
build/openocd: add stream method for JTAG UART
2019-09-06 11:57:18 +02:00
b356204f95
soc_core: add JTAG UART support (uart_name="jtag_uart)
2019-09-06 11:56:42 +02:00
d0ebbda4b3
soc/cores/jtag: add Xilinx JTAG TAPs support and simple JTAG PHY (can be used for JTAG UART)
2019-09-06 11:55:41 +02:00
2638393b53
soc_zynq: fix indent
2019-09-05 15:59:35 +02:00
9051cf97e4
soc_zynq: fix typo
2019-09-05 15:55:18 +02:00
67a09aef05
soc/interconnect/stream: add Monitor module
...
Generic module to monitor endpoints activity: tokens/overflows/underflows that
can be plugged on a endpoint. Can be useful for various purpose:
- endpoint bandwidth calculation.
- underflows/overflows detection.
- etc...
2019-09-05 11:54:14 +02:00
6f150a5626
Merge pull request #254 from mithro/crc-smaller
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Add @xobs' smaller CRC version
2019-09-03 07:23:32 +02:00
2a41f0d2a4
Use `SMALL_CRC` to enable smaller CRC versions.
...
@xobs created a smaller code size version of the CRC functions. Enable
these if someone uses the `SMALL_CRC` define.
2019-09-02 14:48:30 -07:00
083337441a
Remove extra whitespace.
2019-09-02 14:47:20 -07:00
c0e723868e
libbase: crc16: commit smaller version of crc16
...
Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-02 14:44:18 -07:00
a59d0efca0
libbase: crc32: add smaller version
...
Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-02 14:44:18 -07:00
3ff6a18a45
Only write file if contents will change.
2019-09-02 14:26:41 -07:00
a2938a7ae7
soc/cores: simplify JTAGAtlantic (only keep alt_jtag_atlantic instance), move to jtag and allow selecting it as uart with uart_name"jtag_atlantic"
2019-08-31 18:34:08 +02:00
19d3acfc71
Merge pull request #251 from micro-FPGA/master
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atlantic JTAG UART working module
2019-08-31 18:33:27 +02:00
fb00ee85a2
Create atlantic.py
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atlantic JTAG uart for Intel FPGA's, working and tested on Intel C10LP EK
2019-08-30 09:35:10 +02:00
41fe7cae0b
core/spi: add minimal SPISlave
2019-08-29 09:46:20 +02:00
b845755995
gen/fhdl/verilog: allow single element verilog inline attribute
2019-08-28 05:24:11 +02:00
5a7b4c3406
targets/nexys_video: generate clk100
2019-08-27 14:06:13 +02:00
c179741cf3
software/bios: switch to standard CRLF
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Avoid setting terminal to "implicit CR in every LF" mode.
2019-08-27 09:45:44 +02:00
0328ba7d6c
tools/litex_term: add automatic check to see if we need to insert LF or not
2019-08-26 18:17:43 +02:00
ffebd2076c
bios/tools: allow disabling CRC check on serialboot (to speedup debug/loading large images when only serial is available)
2019-08-26 17:15:01 +02:00
4842bdcf08
tools/litex_term: add sdl_payload_length
2019-08-26 12:10:11 +02:00
6d844a038a
software: use native toolchain for same host, target architectures
...
LiteX rightfully assumes that most often the target software must
be cross-compiled from an x86 host platform. However, LiteX can be
also built on a 'linux-riscv64' platform (e.g. Fedora's riscv64
port), where the software for riscv64 targets should be compiled
using the native toolchain.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-08-23 09:04:55 -04:00
92e5b4b2cd
Merge pull request #2 from enjoy-digital/master
...
update with hyperram and other changes
2019-08-16 14:36:59 +02:00
4990bf33c0
soc/core: simplify/cleanup HyperRAM core
...
- rename core to hyperbus.
- change layout (cs_n with variable length instead of cs0_n, cs1_n).
- use DifferentialOutput when differential clock is used.
- add test (python3 -m unittest test.test_hyperbus).
Usage example:
from litex.soc.cores.hyperbus import HyperRAM
self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
self.add_wb_slave(mem_decoder(self.mem_map["hyperram"]), self.hyperram.bus)
self.add_memory_region("hyperram", self.mem_map["hyperram"], 8*1024*1024)
2019-08-16 14:04:58 +02:00
f47e4978f2
libero enable enhanced constraints
...
Libero 12.0 does not support any more classic constraint flow
2019-08-16 10:31:53 +02:00
d1502d4195
soc/cores: add initial simple hyperram core
2019-08-16 09:48:17 +02:00
6e6fe83af3
build/altera/quartus: add add_ip method to use Quartus QSYS files
...
platform.add_ip("my_ip.qsys")
2019-08-15 13:45:29 +02:00
2899928aba
cpu_interface: add json csr map export, simplify csv csr map export using json
2019-08-15 09:27:33 +02:00
9d4b7cd515
bios/sdram: set init done after memtest (for standalone LiteDRAM controllers)
2019-08-14 19:09:58 +02:00
0cd4e45f48
build/xilinx/vivado: use "" for strings
2019-08-14 19:03:10 +02:00
8d161a47cf
build/xilinx/vivado: remove with_phys_opt
2019-08-14 19:02:01 +02:00
f6638ded13
Merge pull request #243 from sergachev/master
...
build/xilinx/vivado: improve directive support
2019-08-14 18:58:15 +02:00
861eea8a07
build/xilinx/vivado: improve directive support
2019-08-14 17:49:13 +02:00
db4c609a33
[fix] prevent Vivado from inferring DSP48 in AXIBurst2Beat
2019-08-14 11:30:39 +02:00
6d5fddc160
cores/spi_flash/S7SPIFlash: make cs_n optional in pads (when driven externally)
2019-08-14 07:35:45 +02:00
a5eaf172c5
more understandable error when missing a memory
2019-08-13 10:14:16 +02:00
6c298cb708
build/lattice/trellis: use abc9 techmapping pass with yosys
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-08-09 09:12:22 -04:00
31bfb54667
software/libbase/mdio: set data before clock, revert two cycle turnaround and test with different phys
2019-08-09 13:26:31 +02:00
e670cb9176
cores/cpu: add riscv-none-embed toolchain support to riscv32 cpus
2019-08-09 12:33:10 +02:00
6d94c07d70
software/libase/mdio: cleanup and reduce raw_turnaround by 1 cycle
2019-08-09 10:33:42 +02:00
0c287b11ba
cores/clock/S7PLL: fix -1/-3 speedgrade vco max freq swap
2019-08-09 09:27:32 +02:00
82cd557c24
software/bios: add Ethernet PHY MDIO read/write/dump commands
2019-08-09 09:26:41 +02:00
0ba9ab92b4
altera/common: fix AsyncResetSynchronizer polarity and simplify
2019-08-08 16:19:22 +02:00
124dff8f3f
build/xilinx/common: improve presentation
2019-08-08 16:08:55 +02:00
60873a5b73
microsemi/common: improve presentation
2019-08-08 16:06:40 +02:00
36d9d78c5e
build/altera/common: improve presentation
2019-08-08 16:02:34 +02:00
95953d2928
platforms/default_clk_period: use 1e9/freq
2019-08-07 08:36:04 +02:00
f1d8c70bd8
targets/minispartan6/crg: only keep S6PLL code
2019-08-07 08:29:59 +02:00
d3d0a6231c
cores/clock: juse use 1e9/freq instead of period_ns
2019-08-07 08:29:20 +02:00
a881817fb3
cores/clock/s6pll: add phase support
2019-08-07 08:18:54 +02:00
6b7ca0cff7
cores/clock/xilinx: change clkfbout_mult loop order to select highest vco_freq
2019-08-07 08:17:44 +02:00
1884649de1
litex_term: make sure to unconfigure console when board is unplugged
2019-08-06 08:46:25 +02:00
e052d7f645
soc/integration/builder: -x
2019-08-06 07:56:45 +02:00
236070fdcf
cores: -x on spi.py
2019-08-05 10:36:43 +02:00
a9fe2788a2
wishbone/SRAM: make read_only emited verilog code compatible with all tools
...
Quartus was not able to implement ROM correctly, see #228
2019-08-05 09:08:56 +02:00
ce5c58592b
soc/cores/uart: add FT245 FIFO mode support (sync & async)
2019-08-04 12:22:35 +02:00
a496760cb6
build/altera/quartus: use .bat on win32/cygwin
2019-08-02 10:27:38 +02:00
7e0ea07076
build/xilinx/vivado: change severity of Common 17-55 critical warning to warning
2019-08-01 21:03:05 +02:00
92d93ad221
cores/pwm: remove default CSR reset values.
2019-07-29 08:38:28 +02:00
25ca0a8b71
soc: generate git header and show migen/litex git sha1 in bios
2019-07-27 20:27:53 +02:00
fdb119cb7b
support vivado incremental implementation
2019-07-25 19:18:11 +02:00
932475a29b
cpu/vexriscv: bump submodule
2019-07-25 08:43:35 +02:00
bc7ab637dd
bios/sdram: fix compilation warning
2019-07-25 07:46:14 +02:00
1cfb36e1e4
soc_core: round memory regions size/length to next power of 2 (if not already a power of 2)
2019-07-23 20:35:28 +02:00
3e89c56468
cpu/vexriscv: bump submodule
2019-07-23 11:49:18 +02:00
e673fce445
bios/boot: fix default EMULATOR_RAM_BASE
2019-07-23 10:28:19 +02:00
0acacbaa82
cores/clock: cleanup
2019-07-23 09:54:30 +02:00
edf8aa8cfd
cores/clock: add initial iCE40 support
2019-07-23 09:27:20 +02:00
6d54335839
cores/spi_flash/add_clk_primitive: return if clk primitive is not needed
2019-07-22 21:55:07 +02:00
462d12bacc
bios/boot: define EMULATOR_RAM_BASE if not defined, add KERNEL_IMAGE_RAM_OFFSET
2019-07-22 21:54:24 +02:00
fc12961e7e
soc_core: fix cpu_variant definition
2019-07-22 12:46:39 +02:00
af61688d1d
bios/boot: fix booting rework
...
- keep emulator.bin in a specific ram (for now)
- print message when falling back to boot.bin
- print destination on tftp download (to ease debug)
2019-07-22 11:47:41 +02:00
4b686dbdb2
soc_core: fix cpu_variant config (we don't want the extension)
2019-07-22 11:44:32 +02:00
7d9cf1d2bd
Merge pull request #216 from antmicro/booting_vexriscv_linux
...
Rework booting Linux on VexRiscv
2019-07-22 11:44:20 +02:00
95cfd0b9e5
cores/spi_flash: add SpiFlashCommon and use it to add clk primitives (7-Series/ECP5 support for now)
2019-07-22 10:28:03 +02:00
bfdcf4b2a0
platforms/versa_ecp5: add spiflash pads
2019-07-22 10:25:55 +02:00
41eb21b343
soc_core: optimize mem_decoder
...
Non-optimized version was tested on 7-series and was additional resource usage
was not noticeable. This does not seems to be the case on iCE40 (see #220 ), so
hand optimize it. On 256MB aligned addresses, it should be equivalent to the
old decoder used by previously in LiteX.
The only requirement is that to have address aligned on size, which was already
the case. An assertion will trigger it this condition is not respected.
2019-07-22 08:53:54 +02:00
0eff65bb31
cores/up5ksram: optimize bus.adr decoding
2019-07-22 07:55:47 +02:00
bb99c4685a
cores/up5kspram: simplify and add support for all width/depth configurations
2019-07-21 19:28:31 +02:00
eaf84b8581
cores/pwm: remove clock_domain support (better to use ClockDomainsRenamer), make csr optional
2019-07-20 12:57:32 +02:00
ea619e3afe
cores/spi: rename add_control paramter to add_csr
2019-07-20 12:56:37 +02:00
ec411a6ac1
soc_core: add SoCMini class (SoCCore with no cpu, sram, uart, timer) for simple designs
2019-07-20 12:52:44 +02:00
8335f13fb1
bios/boot: rework netboot/flashboot for VexRiscv in linux variant
...
Get rid of NETBOOT_LINUX_VEXRISCV/FLASHBOOT_LINUX_VEXRISCV defines
and use information about CPU_TYPE and CPU_VARIANT instead.
Use common kernel/rootfs/device tree/emulator images layout
when booting over network and from flash.
2019-07-15 16:02:58 +02:00
a19bdd0e6a
soc_core: generate extra string-based config defines
...
C preprocessor does not allow to compare strings, so
the current defines are not usable at the compile time.
This adds new defines that can be ifdefed.
2019-07-15 15:58:54 +02:00
005c07769b
soc_core: include information about cpu variant in csv and headers
2019-07-15 15:58:54 +02:00
c6c743915a
soc: cores: fix name of EHXPLLL output clock in ECP5PLL
2019-07-14 12:27:28 -07:00
d3aaaf5e6c
cores/spi: fix/simplify loopback
2019-07-13 13:10:27 +02:00
769d15d433
cores/spi: move CSR control/status to add_control method, add loopback capability and simple xfer loopback test
...
Moving control/status registers to add_control method allow using SPIMaster directly with exposed signals.
Add loopback capability (mostly for simulation, but can be useful on hardware too).
2019-07-13 12:55:19 +02:00
ee8fec10ff
soc/cores: add ECC (Error Correcting Code)
...
Hamming codes with additional parity (SECDED):
- Single Error Correction
- Double Error Detection
2019-07-13 11:44:29 +02:00
7dbddb3a56
platforms/tinyfpga_bx: add serial extension
2019-07-13 11:43:16 +02:00
95796c5b29
Merge pull request #218 from railnova/zynq
...
[fix] Slave interface HP0 clk name
2019-07-12 18:00:03 +02:00
dcf55ad4f3
[fix] Slave interface HP0 clk name
2019-07-12 16:37:23 +02:00
dacec6aa86
spi: change CSR to CSRStorage
2019-07-12 14:12:51 +02:00
be280bed5e
soc_zynq: use zynq fabric reset as sys reset
2019-07-12 09:52:50 +02:00
220f43753b
soc_zynq: add missing axi hp0 clock
2019-07-10 16:51:08 +02:00
9c8c037108
soc_zynq: move axi gp0 clock connection to add_gp0 method
2019-07-10 16:50:06 +02:00
b0192e5f8b
soc_core: use fixed 16MB CSR address space
...
Using too small CSR address space cause a regression on PCIe SoC, this would
need to be understood if we want to reduce CSR address space under 16MB.
2019-07-10 10:39:00 +02:00
68a503174c
soc_sdram: limit main_ram to 512MB for now
...
Otherwise breaks linux-on-litex-vexriscv for targets with 1GB of ram, could
be removed when mem_map will be reworked on linux-on-litex-vexriscv.
2019-07-09 12:14:50 +02:00
21a5aaa4a6
soc_core: declare csr address size when registering csr, fixes #212
2019-07-08 22:58:07 +02:00
41b6fbde42
soc_cores: fix typos
2019-07-08 22:56:14 +02:00
e42f33ede1
soc_core: additional csr_alignment follow-up fixes
...
- Update a few additional places to use DFII_ADDR_SHIFT instead of
a hard-coded 4, which assumed 32-bit alignment.
- Force 64-bit alignment Rocket -- the only supported configuration!
This is a fixup for commit f4770219
2019-07-08 10:15:14 -04:00
f4770219fa
soc_core: add csr_alignment to allow 64-bit alignment with 64-bit CPUs
2019-07-08 10:20:51 +02:00
927b7c13a2
soc/integration: uniformize configuration constants declaration in SoCs (use self.config instead self.add_constant)
2019-07-08 08:57:05 +02:00
96f45bbd87
software/libbase/id: update code (length is now fixed to 256)
2019-07-06 17:18:34 +02:00
282ae96354
cores: add simple PWM (Pulse Width Modulation) module
2019-07-05 19:39:08 +02:00
77e7f9b3c1
core/spi: make cs_n optional (sometimes managed externally)
2019-07-05 19:18:52 +02:00
e726ad80ac
cores/spi_flash: add non-memory mapped S7SPIFlash modules based on SPIMaster (for design were we only want to re-program the bistream)
2019-07-05 19:01:55 +02:00
4c18c991bc
cores: add ICAP core (tested with reconfiguration commands)
2019-07-05 18:30:34 +02:00
6b82f23ce1
cores: add simple and minimal hardware SPI Master with CPOL=0, CPHA=0 and build time configurable data_width and frequency.
2019-07-05 15:50:58 +02:00
ada70e8c52
soc/cores/spi: remove too complicated and does not seem reliable in all cases.
2019-07-05 14:38:09 +02:00
7cd5c0f39b
cores: add bitbang class with minimal hardware for I2C/SPI software bit-banging
2019-07-05 14:26:10 +02:00
d29b841997
cores: remove nor_flash_16 (obsolete, most of the boards are now using SPI flash)
2019-07-05 13:13:31 +02:00
3f6bd266d9
cores/gpio: remove Blinker
2019-07-05 13:09:21 +02:00
4ee9c53f18
csr: add assert to ensure CSR size < busword (thanks tweakoz)
2019-07-03 13:44:15 +02:00
0116b2b708
soc_core: update default RocketChip mem_map
2019-06-28 23:40:01 +02:00
9d170b0944
soc_core: rearrange default mem_map
2019-06-28 23:27:23 +02:00
05b667bb95
bios/main: fix #ifdefs for fw command
2019-06-28 22:42:02 +02:00
37687579e0
libnet/tftp: fix compilation warning
2019-06-28 22:32:45 +02:00
9f3c8a9b8a
bios/main: fix spiflash compilation warnings
2019-06-28 22:18:24 +02:00
2da59b29e2
soc_sdram: allow main_ram_size > 256MB (limitation no longer exists)
2019-06-28 22:10:25 +02:00
b8d45af5c3
targets: use new prefered way to add wishbone slave
2019-06-28 22:10:20 +02:00
7618b84533
soc_core: use new way to add wisbone slave (now prefered)
2019-06-28 22:10:15 +02:00
740629ba53
soc_core: remove 256MB mem_map limitation
...
mem_map was limited to 8 256MB for simplicity but has become an issue for
complex SoCs. Default mem_map size is still 256MB (retro-compatibility) but
size can now be specified.
2019-06-28 22:10:02 +02:00
b65968c329
soc/core: remove #!/usr/bin/env python3
2019-06-28 21:37:52 +02:00
5a42dbf333
BIOS: TFTP: ASCII spinner progress indicator (cosmetic)
2019-06-27 10:31:33 -04:00
d5177d72ac
Merge pull request #204 from antmicro/write_to_flash
...
fw (flash write) command
2019-06-25 19:10:17 +02:00
cef2369015
core/spi_flash: re-integrate bitbang write support
2019-06-25 19:09:30 +02:00
2ee194b259
bios: add fw (flash write) command
2019-06-25 16:58:12 +02:00
dc03b7fab9
boards: community supported boards are now located at https://github.com/litex-hub/litex-boards
2019-06-24 12:05:02 +02:00
0af017e67c
liteeth: update mac imports (olds still works, but that's now the prefered way)
2019-06-24 11:45:01 +02:00
ecf999b8c7
soc/cores: add usb_fifo with FT245 USB FIFO PHY from LiteUSB, deprecate LiteUSB
...
LiteUSB was not up to date was not a real USB PHY but was just providing USB FIFO PHYs.
New true USB cores are now available: Daisho, ValentyUSB, so it's better using
then for true USB support. We only keep the FT245 FIFO PHY in LiteX that can be
useful to interface with USB2/USB3 USB FIFOs.
2019-06-24 10:58:36 +02:00
8f6e66ca52
make sure #!/usr/bin/env python3 is before copyright header
2019-06-24 07:29:24 +02:00
daa4307d9e
add CONTRIBUTORS file and add copyright header to all files
2019-06-23 23:23:56 +02:00
361f9d0dff
bios/sdram: set init_done/error when DDRCTRL is present (litedram_gen)
2019-06-22 10:55:15 +02:00
d8ac936206
Convert top level comment to a docstring.
2019-06-21 12:03:30 -07:00
7656f54d0a
soc: cores: add up5kspram module
...
The ICE40UP5K has 128 kB of SPRAM that's designed to be used
as memory for a softcore. This memory is actually 4 16-bit
chunks that we can gang together to give us either 64 kB or
128 kB.
Add a module that will allow us to use this memory in an ICE40.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-06-20 11:12:46 -07:00
73dbffe8f2
cores/frequency_meter: allow passing clk to be measured as a parameter
2019-06-20 09:03:30 +02:00
ab827d210d
tools/litex_sim: fix default endianness for mem_init
...
Initializing ROM and/or RAM content requires knowing the CPU
endianness before the SimSoC->SoCSDRAM->SoCCore constructor
sequence is invoked (before the SoC's self.cpu.endianness
could be accessed). Given that the majority of supported CPU
models use "little", set it as the new default, and override
only for the two models that use "big" endianness.
2019-06-18 16:55:58 -04:00
f75863fc31
cpu/rocket: add "linux" (MMU) and "full" (MMU & FPU) variants
2019-06-18 06:46:24 -04:00
c0df9e0823
cpu/rocket: update submodule
2019-06-18 09:44:13 +02:00
87118d509c
integration/soc_core: move cpu_variant checks/formating to cpu
2019-06-17 09:55:27 +02:00
f6b67a6dae
cpu/vexriscv: add "linux+no-dsp" variant
2019-06-17 09:54:17 +02:00
95b1b454f4
cpu/vexriscv: update
2019-06-17 09:24:57 +02:00
e46d287b64
targets/ulx3s: use CAS latency of 3 to be compatible with production boards
2019-06-17 09:20:21 +02:00
ca70ea91e4
bios: Fix build when ethphy is present but ethmac is not.
...
While testing my Ethernet DMA, I renamed the `ethmac` module to `ethmac_dma` so that it wouldn't be used from the BIOS, but I got an undefined reference to `eth_init` because `bios.c` checks different CSR defines than the code that defines `eth_init`.
2019-06-13 01:02:22 +02:00
33d7cc5fc8
Merge pull request #198 from TomKeddie/tomk_20190610_artyspi
...
boards/arty : Add directly connected spi clk pin
2019-06-11 15:50:02 +02:00
5346c3684f
boards/arty : Add directly connected spi clk pin to avoid need for STARTUPE2
2019-06-10 08:33:02 -07:00
243d7c7696
soc/cores: add PRBS (Pseudo Random Binary Sequence) Generator/Checker
...
Imported from LiteICLink. PRBS can be useful for different purposes, so is
better integrated in LiteX.
2019-06-10 16:05:36 +02:00
cfa952b062
tools/litex_term: exit on 2 consecutive CTRL-C
...
When running OS with LiteX and when LiteXTerm is use, we want to be able to
send CTRl-C to the OS. Ensure a specific sequence is sent to close the terminal.
2019-06-10 15:06:57 +02:00
1c34b4a015
cpu/vexriscv: update submodule
2019-06-10 12:57:21 +02:00
850b311d04
cpu/vexriscv: update submodule
2019-06-07 18:36:46 +02:00
755a2660ba
build/sim: allow configuring verilator optimization level
2019-06-07 12:28:20 +02:00
4b6ad8aa0d
build/sim: allow defining start/end cycles for tracing
2019-06-07 11:50:57 +02:00
ecb60f6e43
build/sim: use -O0 for verilator compilation
...
In most of the case, execution speed is already fast enough with -O0 and
with complex design -O0 is a lost faster to compile than -O3. In the future
we could add a switch to choose which optimization we want.
2019-06-07 11:16:39 +02:00
c64129dc69
soc/integration/soc_core: list rocket as supported CPU
2019-06-07 11:14:36 +02:00
ca4e7811e9
software/bios: change prompt to "litex" in green.
2019-06-07 11:13:36 +02:00
8d0f008a3b
integration/soc_core: improve readibility (add separators/comments)
2019-06-05 23:43:16 +02:00
e545b15f66
Merge pull request #196 from msloniewski/de10lite_support
...
De10lite support
2019-06-05 19:44:54 +02:00
04ce479035
boards/targets: add target for de10lite platform
2019-06-05 18:57:59 +02:00
f2a740d51d
boards/platforms: add de10lite Terasic platform support
2019-06-05 18:57:59 +02:00
a826aacac0
build/altera: Add possibility to turn off generation of .rbf file
...
For some FPGAs (e.g. MAX10) .rbf file cannot be generated.
Add possibility to turn off that feature for those chips.
2019-06-05 18:57:59 +02:00
93b61a65bf
integration/builder: generate flash_boot address to csv
2019-06-05 17:37:23 +02:00
d0b019b1f0
integration/builder: generate shadow_base address to mem.h and csv
2019-06-05 17:37:09 +02:00
f88b85a31c
software/libbase: memcpy: simple, arch-width agnostic implementation
...
Remove optimizations targeted specifically at rv32 architecture,
allowing memcpy to work on all word sizes.
Since this is "only" the BIOS, it is also arguably better to
optimize for size rather than performance, given that control
will be quickly handed over to some other program being loaded.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-06-04 14:48:51 -04:00
42e9d09755
Merge pull request #192 from sutajiokousagi/pr_c99_types
...
fix signed char type to be explicitly signed
2019-06-02 16:54:20 -07:00
ab0b2cac2e
fix signed char type to be explicitly signed
2019-06-03 06:01:13 +00:00
200d413def
update stdint.h to include c99 types
...
needed for some third party libraries to compile
2019-06-02 22:27:12 +00:00
db890736ea
fix csr_name in add_csr()
2019-06-02 20:56:02 +02:00
40cbe3a952
fix interrupt_name
2019-06-02 20:52:31 +02:00
220e2bdc6e
boards/platform/arty: add Arty A7-100 variant
2019-06-02 19:10:44 +02:00
8e6ecfb974
Merge pull request #189 from open-design/terasic-boards
...
Add support for Terasic DE2-115 and Terasic DE1-SoC boards
2019-06-02 18:40:57 +02:00
6cf1a814eb
boards: add Terasic DE2-115 initial support
...
See https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=502&PartNo=1
for board details.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
2019-06-02 11:33:10 +03:00
037259917a
boards: add Terasic DE1-SoC Board support
...
See https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=836
for board details.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
2019-06-02 11:26:21 +03:00
273a3ea15d
soc/integration/cpu_interface: improve code legibility
...
Factor out code appearing in both branches of an if/else.
2019-05-29 10:07:43 -04:00
08a811b1a5
soc/interconnect/gearbox: add msb_first/lsb_first order
2019-05-29 10:25:25 +02:00
675f78304e
boards/targets/arty: generate 25MHz ethernet clock with S7PLL
...
Allow ethernet to work when sys_clk_freq != 100MHz
2019-05-28 09:55:06 +02:00
26e6355fd6
litex/boards/targets: don't use tab for indentation
...
Fix pep8 E101 "indentation contains mixed spaces and tab" error.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
2019-05-26 12:00:03 +03:00
5109511259
soc/interconnect/axi: add round/robin arbitration between writes/reads
2019-05-25 10:02:31 +02:00
961101d809
bios/irc: remove compilation workaround
2019-05-25 09:24:48 +02:00
712977a0cf
software/bios/isr.c: workaround compilation issue (need to be fixed)
2019-05-24 10:18:50 +02:00
28ba8b3201
soc/integration/soc_core: revert default mem_map (do specific RocketChip remapping for now)
2019-05-24 10:18:32 +02:00
cf369c437c
boards/targets: revert default sys_clk_freq on nexys4ddr/versa_ecp5 (but add parameter to configure it)
2019-05-24 10:18:26 +02:00
019fd94005
fixup: generated-verilog submodule for experimental Rocket support
...
FIXME: This patch uses https://github.com/gsomlo/rocket-litex-verilog ,
however in the long term it would perhaps be better if enjoy-digital
hosted the generated-verilog repository.
Once that's in place, I'd be happy to re-spin (and squash) this patch
on top of its parent -- GLS
2019-05-23 18:22:37 -04:00
1a530cf27d
soc/cores/cpu/rocket: Support for 64-bit RocketChip (experimental)
...
Simulate a Rocket-based 64-bit LiteX SoC with the following command:
litex/tools/litex_sim.py [--with-sdram] --cpu-type=rocket
NOTE: Synthesizes to FPGA and passes timing at 50MHz on nexys4ddr
(with vivado) and ecp5versa (with yosys/trellis/nextpnr), but at
this time does not yet properly initialize physical on-board DRAM.
On ecp5versa, using '--with-ethernet', up to 97% of the available
TRELLIS_SLICE capacity is utilized.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-05-23 15:59:51 -04:00
e90caa8683
tools/litex_sim: restore functionality of '--with-sdram' option
...
After LiteDRAM commit #50e1d478, an additional positional argument
('databits') is required by the PhySettings() constructor.
The value used here (32) will generate a 64MByte simulated SDRAM.
2019-05-23 08:56:50 -04:00
014c950580
remote: usb: print "access denied" error
...
When we get an error with errno 13, it means that the user doesn't
have access to the USB device. Rather than silently eating this
error and returning -1, print out a message to aid in debugging.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-05-21 09:36:18 +08:00
faf6554c89
remote: usb: use 0x43/0xc3 for packet header
...
The previous value -- 0xc0 -- is used by Windows all the time to query
special descriptors. This was causing a conflict when using the USB
bridge on a Windows device.
Change the magic packet from "Vendor: Device" queries to "Vendor:
Other" by setting the bottom two bits.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-05-21 09:14:18 +08:00
10670e22ac
soc/cores/minerva: update to latest
2019-05-17 22:21:57 +02:00
5707bdc0a4
boards/nexys4ddr: ethernet support fix-up
...
Commit 5f6e7874
2019-05-17 10:06:12 -04:00
0a8699f1e6
Merge branch 'master' of http://github.com/enjoy-digital/litex
2019-05-16 15:15:30 +02:00
526ba1b165
soc_core: remove csr_expose and add add_csr_master method
...
This could be useful in specific case were we don't have a wishbone master
but just want to have a csr bus and allow the user to define it.
/!\ Since there is no arbitration on between the CSR masters, use this with
precaution /!\
2019-05-16 15:14:55 +02:00
1ea22d49b7
software/include/base/csr-defs.h: add specific CSR_IRQ_MASK/PENDING for Minerva
2019-05-15 22:40:32 +02:00
f25707012f
software/bios/boot: remove specific linux commands (not needed with device tree)
2019-05-14 11:45:16 +02:00
938d00c283
boards/targets/de0nano: reduce to 50MHz sys_clk, simplify CRG
2019-05-14 11:45:12 +02:00
11838bae20
platforms/de0nano: change serial pins (put then next to the GND pin)
2019-05-14 11:45:06 +02:00
eb6fa45833
cpu/vexriscv/core: update
2019-05-13 10:59:26 +02:00
0cad80e935
cpu/vexriscv: update submodule (new linux variant)
2019-05-13 10:59:03 +02:00
5f6e787494
boards/nexys4ddr: add ethernet support (RMII 100Mbps)
2019-05-13 10:18:23 +02:00
0ba1cb8756
boards/targets/netv2: +x
2019-05-11 12:39:02 +02:00
2f2b9b319f
soc/cores: remove cordic
...
Cordic is useful for DSP cores but not as a Soc building block.
2019-05-11 09:36:53 +02:00
6e4ac1c493
LICENSE: clarify
2019-05-11 09:26:51 +02:00
67159349d6
soc/interconnect: remove axi_lite
...
axi_lite code was defining AXI4Lite signals and doing a AXI4Lite bridge to the
CSR bus when LiteX was not having proper AXI support. LiteX now has proper AXI
support and it also cover what axi_lite was doing: To create a AXILite to CSR
bus, user can create an AXILite2Wishbone bridge and then connect the CSR bus
directly to the wishbone bus as done in the others non-AXI SoC.
2019-05-11 09:12:20 +02:00
745d83a332
boards: add initial NeTV2 support (clocks, leds, dram, ethernet)
2019-05-10 18:55:40 +02:00
a49d170a6d
soc/integration/soc_sdram: simplify/fix main_ram_size computation using new databits value of the phy
2019-05-10 15:46:22 +02:00
7445b9e2e0
soc/integration/soc_core: allow user to defined internal csr/interrupts
...
For some designs with different capabilities, we want to run the same software
and then have the CSRs/Interrupts defined to a specific location.
2019-05-10 11:05:34 +02:00
f333abcfcb
boards/targets: use new add_csr method
2019-05-09 23:50:43 +02:00
d76a2c7db2
tools/litex_sim: add uart csr (required when with_uart=False with new add_csr method)
2019-05-09 23:33:08 +02:00
b6be534cd6
soc/integration/soc_core: rework csr assignation/reservation
...
Similar refactor than on interrupts. Adds a add_csr method but still
retro-compatible with old way to declare CSRs.
2019-05-09 23:32:22 +02:00
3f09af6d6e
boards/targets: declare ethmac interrupt with new add_interrupt method
...
The previous way to define interrupt is still valid, but using add_interrupt
method will ease maintenance
2019-05-09 12:13:15 +02:00
2abb3e809c
Merge branch 'master' of http://github.com/enjoy-digital/litex
2019-05-09 11:57:19 +02:00
47dc87584f
integration/soc_core: rework interrupt assignation/reservation
...
The CPUs can now reserve specific interrupts with reserved_interrupts property.
User can still define interrupts in SoCCore.interrupt_map (old way) or use
add_interrupt method. Interrupts specific to SoCCore internal modules are
allocated automatically on the remaining free interrupt ids.
Priority for the interrupts allocation:
- 1) CPU reserved interrupts.
- 2) User interrupts.
- 3) SoCCore interrupts.
2019-05-09 11:54:22 +02:00
435cdad083
boards/targets: fix ulx3s/versa_ecp5 build
2019-05-09 11:48:32 +02:00
8caa38bc25
cpu: add `reserved_interrupts` property
2019-05-09 09:00:06 +02:00
c264a00964
soc/integration/cpu_interface: more arch-specific address size fixes
...
When generating arch-specific include files (generated/[mem|csr].h)
ensure address literal defines are suffixed by 'L', denoting their
'unsigned long' type. This inhibits compiler warnings when values
computed based on these constants are cast to pointers.
Also ensure csr_[read|write][b|w|l]() function declarations have
'unsigned long' address arguments.
Finally, restore the correct (32-bit, (unsigned *)) expected
behavior of the MMPTR() macro, inadvertently converted to an
arch-specific sized access (unsigned long *) by commit 5c2b8685
2019-05-08 16:03:36 -04:00
ff5179153c
boards/targets: make sys_clk_freq a parameter
...
Most of the targets can now generate an abritrary sys_clk_freq from onboard XO.
2019-05-07 18:44:03 +02:00
a8cbe4ad84
boards/targets/minispartan6: for now revert experimental s6pll clocking
2019-05-07 13:05:28 +02:00
6fcbf10eb9
boards/plarforms/minispartan6: default to xc6slx25
2019-05-07 12:48:36 +02:00
b7e3713388
bios/boot/ update linux memory mapping
2019-05-07 11:59:28 +02:00
190ff89aaa
tools/litex_term: add json support to load images to memory, allow passing speed as float
...
example json file (serialboot.json):
{
"binaries/Image": "0xc0000000",
"binaries/rootfs.cpio": "0xc2000000",
"binaries/rv32.dtb": "0xc3000000",
"emulator/emulator.bin": "0x20000000"
}
example command:
lxterm --images=serialboot.json /dev/ttyUSBX
2019-05-06 23:56:33 +02:00
a048ba47c4
vexriscv: Fix some floating signals
...
Signed-off-by: David Shah <dave@ds0.me>
2019-05-04 17:27:21 +01:00
fcd518b5d0
bios/boot: add specific flash_boot for linux with vexriscv
2019-05-04 11:27:01 +02:00
1ba1ad9a00
bios/boot: rename MM_RAM to EMULATOR_RAM
2019-05-03 19:47:36 +02:00
fbb24720f0
soc/get_mem_data: add direct support for regions
...
We now support passing filename (offset=0), json file and regions
2019-05-03 13:24:06 +02:00
0714816f31
soc/interconnect/axi: add AXI2AXILite converter and use it in AXI2Wishbone
2019-05-03 11:59:06 +02:00
c6d0d23445
soc/interconnect/axi: add AXI Lite definition
2019-05-03 09:43:12 +02:00
9fab4752c4
soc/interconnect/axi: add comment on axi signas that are present but not used
2019-05-03 09:30:59 +02:00
5989076346
cores/cpu/vexriscv: add VexRiscvTimer and use it for the linux variant
2019-05-03 09:30:26 +02:00
21bf10383d
bios/boot: add liftoff banner just before booting
2019-05-02 18:26:35 +02:00
8f4685b3b1
bios/boot/netboot: only get boot.bin as default, add linux_vexriscv netboot config
2019-05-02 16:34:41 +02:00
6cf1ff091c
soc/interconnect/axi: connect axi.ar/aw when selecting write or read
2019-05-02 09:58:55 +02:00
6affc56a09
soc/interconnect/axi: wishbone address shift is not always 2, make it generic
2019-05-02 09:35:07 +02:00
698bc88296
soc/interconnect/wishbone: allow setting adr_width (default to 30)
2019-05-02 09:34:30 +02:00
4dccb8a9eb
soc/interconnect/axi/AXI2Wishbone: add buffer on axi command to be sure command is accepted before response is sent
2019-05-01 12:59:04 +02:00
9f8f0eb18e
build/sim: update tapcfg
2019-05-01 12:34:12 +02:00
5c2b8685fc
software: use "unsigned long" for address values, also 8-byte alignment
...
Enable future support for 64-bit CPU models.
2019-04-29 15:03:38 -04:00
5c1d980540
soc/interconnect/axi: add burst support to AXI2Wishbone
2019-04-29 16:49:20 +02:00
6de2713524
soc/interconnect/axi: add capabilities to AXIBurst2Beat and simplify/optimize
2019-04-29 14:02:05 +02:00
305b8879de
integration/soc_core: use cpu name as cpu-type for all cpus (mor1kx was instanciated with or1k)
...
Keep or1k retro-compatibility for now but add a warning
2019-04-29 10:14:30 +02:00
4e50f36b72
build/tools: add deprecated_warning
2019-04-29 10:12:54 +02:00
b40d1b73c4
cpu_interface: default to gcc for all cpus unless told otherwise (mor1kx default was clang)
2019-04-29 10:00:04 +02:00
dbb71af189
cpu: use property methods to return name, endianness, gcc triple/flags, linker output format
2019-04-29 09:58:51 +02:00
d828c3a596
cpu: integrate nmigen version of Minerva, add submodule
2019-04-28 23:40:33 +02:00
bf27869ad9
fix vexriscv build
2019-04-28 11:10:20 +02:00
2d5bae3def
Merge pull request #175 from mithro/cpu-docs
...
Standardizing `cpu_variants` and adding lots of documentation
2019-04-27 21:24:06 +02:00
5cbc5bc199
Adding testing of cpu variants.
2019-04-26 18:57:49 -05:00
71a837315a
Work with no `cpu_variant` provided.
2019-04-26 17:44:36 -05:00
39c579baa2
Standardize the `cpu_variant` strings.
...
Current valid `cpu_variant` values;
* minimal (alias: min)
* lite (alias: light, zephyr, nuttx)
* standard (alias: std) - Default
* full (alias: everything)
* linux
Fully documented in the [docs/Soft-CPU.md](docs/Soft-CPU.md) file
mirrored from the
[LiteX-BuildEnv Wiki](https://github.com/timvideos/litex-buildenv/wiki ).
Also support "extensions" which are added to the `cpu_variant` with a
`+`. Currently only the `debug` extension is supported. In future hope
to add `mmu` and `hmul` extensions.
2019-04-26 17:44:30 -05:00
3a2e283613
.gitmodules: use our VexRiscv-verilog
2019-04-27 00:00:55 +02:00
78c09125be
soc/integration/soc_core: fix get_mem_data when not file is not multiple of 4 bytes
2019-04-25 23:43:10 +02:00
0175f86cb2
soc/integration/soc_core: fix get_mem_data for json files
2019-04-25 18:36:47 +02:00
4443b5075b
soc/integration/soc_core: add integrated_sram_init
2019-04-25 17:30:03 +02:00
f27084c6c0
soc/integration/cpu_interface: fix banner in get_mem_header
2019-04-24 22:44:37 +02:00
d21cba2f17
build: handle exceptional case when litex/migen not deployed as git repo
2019-04-24 12:50:47 -04:00
27fbb814ab
tools/remote/csr_builder: allow comments in csv file and cleanup
2019-04-24 12:25:49 +02:00
e8f3c49127
software/libnet/microudp: rearrange send_packet, add comments and remove txlen padding
2019-04-24 11:32:40 +02:00
44e0cdda9a
software/libnet/microudp: speed-up ARP by changing timeout/tries
...
First ARP request does not seem to be transmitted (the link is probably not
fully established). Reduce the timeout between tries and increase number of
tries.
2019-04-24 09:55:41 +02:00
3ee78a5b70
build/tools: fix typo
2019-04-23 18:10:51 +02:00
9ded2eb20b
tools/litex_term: change TERM prompt to LXTERM
2019-04-23 17:46:02 +02:00
475deb51ac
build: add migen and litex git revision to generated file
2019-04-23 17:40:24 +02:00
8b5cf29542
build/tools: git_revision is not doing what we want, return "--------" for now
2019-04-23 17:15:43 +02:00
0f60ec35e2
tools/litex_server: fix comms import
2019-04-23 14:25:27 +02:00
68f12495cf
soc/integration: also add sha-1/date to generated software files
2019-04-23 13:17:54 +02:00
425741226c
build: add sha-1/date to generated verilog, change git_version to git_revision
2019-04-23 12:59:25 +02:00
818dfae1e8
boards/platforms/ulx3s: fix default clock
2019-04-23 11:37:29 +02:00
17b6164cd9
boards/platforms/sp605: apply same simplifications than on others platforms
2019-04-23 11:21:55 +02:00
24bf02934e
boards/platforms: add SP605
2019-04-23 11:15:42 +02:00
10cf0fdea3
cores/cpu/vexriscv: fix wrong revert
2019-04-23 11:13:29 +02:00
d2ad14417a
targets/ac701: cleanup and make it similar to others targets.
...
Still supports EthernetSoC with RGMII and 1000BaseX.
2019-04-23 11:10:35 +02:00
a24bf72fc7
targets/xilinx: remove keep attribute on clock going to idelayctrl
...
Causes P&R issues with Vivado.
2019-04-23 10:51:36 +02:00
ea8dbff86e
boards/platform/ac701: add proper copyright, cleanup to be similar to others platforms
2019-04-23 10:50:19 +02:00
0122982e09
boards/platforms/kc705: provide only one default programmer as others platforms
2019-04-23 10:00:52 +02:00
89a590263f
boards: Xilinx ac701 dev board support
2019-04-23 09:48:16 +02:00
88b882c7e0
build/xilinx/ise.py: write .v file for post synthesis sim
2019-04-23 09:22:48 +02:00
7396ebbb38
build/xilinx/programmer: cleanup XC3SProg position parameter
2019-04-23 09:20:59 +02:00
f579cbc603
build/xilinx/programmer: add position parameter to XC3SProg
2019-04-23 09:16:42 +02:00
535d86727a
targets/minispartan6: use S6PLL in CRG
2019-04-23 06:44:29 +02:00
40342404f2
cores/clock: add divclk_divide_range on S6PLL/S6DCM
2019-04-23 06:43:48 +02:00
0d282f38f9
cores/clock: use common XilinxClocking class for all Xilinx clocking modules
2019-04-23 06:35:39 +02:00
83699ea0a5
cores/clock: add initial Spartan6 PLL/DCM support
2019-04-23 06:23:00 +02:00
eff141da2d
build: add git version (sha-1) used to create the scripts
2019-04-23 06:03:12 +02:00
cc141a64b9
build: scripts are generated by LiteX
2019-04-23 05:38:33 +02:00
115c842ef0
build/xilinx/vivado: cleanup pull request #170
2019-04-23 05:33:56 +02:00
fda18fd6ef
build/xilinx/vivado: only try Xilinx setup if vivado is not already in the path
...
Only affects the non-Windows code path.
Uses python distutils, already used elsewhere.
2019-04-22 15:42:31 -07:00
7d278854d5
global: switch to VexRiscv as the default CPU
...
VexRiscv can now replace LM32 for almost all usecases and we now have better
software support with RISC-V.
2019-04-22 09:41:07 +02:00
8c78997089
boards/platforms: add separators, cleanup imports
2019-04-21 00:44:23 +02:00
cb8c26d1b8
boards/platforms: provide only one default programmer per platform.
...
create_programmer is not really longer used, so try to keep it simple.
2019-04-21 00:17:03 +02:00
e1d202df02
boards/platforms/kc705: only keep Vivado support
...
There is no reason still using ISE on 7-Series.
2019-04-21 00:04:56 +02:00
53c7be6e46
boards: always define timing constraints the same way (1e9/freq_mhz)
2019-04-20 23:56:27 +02:00
02ffbed5e3
boards/targets/ulx3s: allow running test_targets on it
2019-04-20 23:47:05 +02:00
5a1925df2e
boards/targets: add keep attribute directly in crg
...
This makes it systematic and avoid having to add it later.
2019-04-20 23:43:44 +02:00
f71b8d4f57
litex_server: check socket flags exist before using them
...
Some flags are only available on certain platforms. Verify these flags
exist prior to using them when opening a socket.
See
https://stackoverflow.com/questions/14388706/socket-options-so-reuseaddr-and-so-reuseport-how-do-they-differ-do-they-mean-t
for more information
Signed-off-by: Sean Cross <sean@xobs.io>
2019-04-20 17:28:26 +08:00
9ee6c35b42
tools: move from litex.soc.tools to litex.tools and fix usb.core import
2019-04-20 10:44:53 +02:00
49fd93ae83
Merge pull request #165 from xobs/vexriscv-cpu-reset-address
...
Vexriscv cpu reset address
2019-04-19 19:16:16 +02:00
ca6065a6a1
Merge pull request #164 from xobs/litex-usb-server
...
Litex usb server support
2019-04-19 19:14:15 +02:00
c69183648f
utils: litex_server: add usb support
...
Add `--usb` and associated arguments to create a litex bridge over
USB. This makes use of the new CommUSB module.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-04-19 18:02:42 +01:00
9dd59d6301
tools: remote: add usb communications protocol
...
This adds a USB communications protocol to the suite of litex-supported
wishbone bridge protocols.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-04-19 17:29:50 +01:00
9cbed91b3e
soc/interconnect/axi: add AXIBurst2Beat
...
Converts AXI bursts commands to AXI beats.
2019-04-19 12:13:16 +02:00
5a8115d9e1
soc/interconnect/avalon: add description
2019-04-19 11:43:15 +02:00
c780fb22b7
Merge branch 'master' of https://github.com/enjoy-digital/litex
2019-04-19 16:47:55 +08:00
fa95608694
soc/integration/soc_zynq: fix HP0 connections
2019-04-19 10:21:56 +02:00
a78ca2de92
build/xilinx/vivado: only set library for vhdl files (not supported for verilog/system-verilog)
2019-04-19 09:18:25 +02:00
e2cf45b8a9
cpu: vexriscv: allow cpu_reset_address to be overridden
...
Allow the cpu_reset_address value to be overridden, for example allowing
it to be a signal. That way the reset address can be modified after
synthesis, in dual-core or debug situations.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-04-19 13:04:57 +08:00
a92e90b215
soc/interconnect: add avalon with converters to/from native streams
2019-04-18 18:42:29 +02:00
d860eeea4f
Merge pull request #162 from antmicro/full-conf-vexriscv
...
Add full and full_debug CPU variant of VexRiscv
2019-04-17 19:01:55 +02:00
e1683078ec
build/sim/core: Initialize Verilator commandArgs
...
Required when DUT is using plusargs. Prevents Verilator simulation
from crashing with "Verilog called $test$plusargs or $value$plusargs
without testbench C first calling Verilated::commandArgs(argc,argv)".
2019-04-17 10:39:35 -04:00
40de01bcb0
vexriscv: Add full and full_debug CPU variant
2019-04-17 09:09:35 +02:00
017147c623
build/altera: switch to sdc constraints, add add_false_path_constraints method
2019-04-16 16:57:23 +02:00
1275e2f150
build/xilinx/vivado: set quiet property on MultiReg/AsyncResetSynchronizer constraints
...
MultiReg/AsyncResetSynchronizer are not necessarily present in all design, set
quiet property to avoid generating false warnings.
2019-04-15 16:48:47 +02:00
c252972bef
soc/cores/clock: add divclk_divide/vco_margin support on S7/Ultrascale
2019-04-15 11:36:42 +02:00
f986974d60
soc/cores/clock: improve presentation
2019-04-15 10:57:00 +02:00
538ca59ab6
build/xilinx/vivado: round period constraints to lowest picosecond
...
Vivado will do the opposite if we don't do it, with this change we ensure the applied period constraints will always be >= to the requested constraint.
2019-04-15 10:51:17 +02:00
a2bc4bb777
litex_server: set socket.SO_REUSEPORT to avoid waiting 60s in case of unclean termination
2019-04-15 08:23:27 +02:00
be99083e2b
litex_server: add message and exit when mandarory arguments are missing.
2019-04-14 14:00:35 +02:00
db11aec961
litex_server: allow setting bind port, remove auto-incrementing on bind_port
2019-04-14 12:48:49 +02:00
76bc57851b
litex_server: refactor parameters and to allow setting bind address
...
In some cases, it can be useful to bind to "0.0.0.0" instead of "localhost".
While adding bind address support, parameters passing has also been refactored
to ease adding parameters in the future.
2019-04-14 09:00:08 +02:00
13a76ec7fb
software/libnet/microudp: simplify txbuffer managment
2019-04-12 18:47:31 +02:00
3441eb05cb
software/libnet/microudp: cleanup eth_init
2019-04-12 17:15:09 +02:00
92a79c6dc1
software/libnet/microudp: simplify rxbuffer managment
2019-04-12 17:14:07 +02:00
fdeff7f64f
software/libnet/microudp: set raw frame size to ETHMAC_SLOT_SIZE
2019-04-12 17:09:50 +02:00
1569e2e0cf
software/libnet: remove use of ethmac_mem.h
2019-04-12 17:08:29 +02:00
c7ac96761c
bios/sdram: add __attribute__((unused)) on cdelay
2019-04-11 22:26:58 +02:00
792245f196
boards/targets/kcu105: add Ethernet (with 1Gbps SFP adapter)
2019-04-10 16:36:49 +02:00
f8dcdb70d2
software/libnet: add #ifdef on eth_init
2019-04-10 16:16:47 +02:00
04939990ac
litex/build/altera/quartus: changes to make top level assigment in .qsf file with build name
2019-04-08 14:07:10 +03:00
8558065fca
litex/build/altera/common: added reset synchronizer
2019-04-08 14:06:24 +03:00
866fa34493
integration/soc_zynq: fix missing SoCCore.do_finalize
...
Signed-off-by: Florent Kermarrec <florent@enjoy-digital.fr>
2019-04-01 14:44:37 +02:00
794c3c5860
integration/soc_zynq: add add_hp0 method
2019-04-01 11:10:35 +02:00
38d404c3cb
integration/soc_zynq: use add methods to add optional peripherals
2019-04-01 10:50:04 +02:00
7375856bec
integration/soc_zynq: connect axi signals that were missing
2019-04-01 10:31:33 +02:00
b15fd9d834
interconnect/axi: add missing axi signals
2019-04-01 10:23:25 +02:00
1f0b3f8124
Add ifdef check for MAIN_RAM_SIZE
2019-03-31 10:33:39 -05:00
dd214d2d21
bios/main: align SoC info, show CPU speed on CPU line, show L2
2019-03-30 11:49:39 +01:00
6599f7bb50
bios/main: move sdrinit
2019-03-30 10:56:17 +01:00
b92b89ab92
bios/main: print boot sequence only if sdr_ok
2019-03-30 10:19:00 +01:00
f4369c8fb2
bios/main: remove csr functions (not used and only supported by lm32), improve help presentation
2019-03-29 19:40:24 +01:00
66dffb7071
software/bios: improve readibility, add soc informations
2019-03-29 00:51:16 +01:00
449632e430
soc/interconnect/axi: data/address length cleanup
...
Instead of hard-coding data and address width to 32, assert that
the AXI and Wishbone interfaces have *matching* address and data
widths.
2019-03-27 16:52:52 -04:00
552b0243b3
soc/interconnect/axi: remove dead code (thanks gsomlo)
2019-03-27 21:15:14 +01:00
b682dacdd7
Merge pull request #154 from daveshah1/yosys_xilinx_edif
...
build/xilinx: Update Yosys write_edif parameters
2019-03-22 17:43:40 +01:00
57e1ccd5f8
build/xilinx: Update Yosys write_edif parameters
2019-03-22 16:06:52 +00:00
fd7ed6c1ec
utils/litex_sim: fix main_ram_size
2019-03-16 21:25:02 +01:00
3f386dad7d
soc_core/get_mem_data: add json support
...
example of json file:
{
"vmlinux.bin": "0x00000000",
"vmlinux.dtb": "0x01000000",
"initramdisk.gz": "0x01002000"
}
2019-03-16 21:23:36 +01:00
7bc13ba841
build/microsemi/libero_soc: add linux build script support
2019-03-16 09:33:16 +01:00
7b88980d06
vexriscv: allow user to use an external variant
2019-03-15 18:16:25 +01:00
b04a756abb
vexriscv/core: fix min variant
2019-03-15 17:49:39 +01:00
a549f0941b
utils/litex_sim: handle cpu_endianness for rom-init/ram-init
2019-03-13 10:56:09 +01:00
411bca790a
utils/litex_sim: increase default integrated_main_ram_size to 256MB, automatically boot on main_ram when ram_init is specified
2019-03-13 10:42:10 +01:00
7ec3ed4d89
Merge pull request #153 from railnova/fix_utils
...
[fix] utils was omitted when installed from pip
2019-03-07 21:12:00 +01:00
aed2e9b4b5
[fix] utils was not installed from pip
2019-03-07 09:40:58 +01:00
b014c7194b
build/lattice/trellis: also generate bitstream in svf format
...
Before being able to program the board (e.g., with openocd), one
would have to convert the bitstream file to .svf using a python
script included with the source trellis distribution. However,the
trellis 'ecppack' utility can also generate .svf bitstream files
directly.
2019-03-06 16:29:18 -05:00
317dba8314
software/bios/sdram: use specific ERR_DDRPHY_BITSLIP/NMODULES computation
...
In the future, the PHYs should generated these constants.
2019-03-05 18:03:24 +01:00
7de1fe519a
targets/versa_ecp5: update ECP5DDRPHY on BaseSoC, add EthernetSoC
2019-03-05 13:27:11 +01:00
ca63db4040
bios/sdram: use burstdet detection for ECP5DDRPHY init
2019-03-05 13:27:06 +01:00
ebe8f600e1
lattice/common: Fix tristate buses with Trellis
...
Signed-off-by: David Shah <dave@ds0.me>
2019-03-04 10:50:56 +00:00
935f3a5337
boards/ulx3s: add device selection parameter
...
ULX3S can be populated with LFE5U-45F (default) or LFE5U-85F
2019-03-04 09:40:14 +01:00
e6f97e08d2
targets/ulx3s: use AsyncResetSynchronizer and derivate sys_clk/sys_clk_ps constraints from clk25
...
Now supported by Trellis/Nextpnr.
2019-03-04 09:27:31 +01:00
5ef28bdf75
build/lattice/trellis: add package support
2019-03-01 15:20:02 +01:00
1b34c07da9
build/lattice/trellis: basecfg now integrated in nextpnr
2019-03-01 14:20:00 +01:00
7e995eb418
boards/targets/ulx3s: allow building with diamond or trellis
2019-03-01 13:59:28 +01:00
4bf789eab9
soc/software/bios/boot: add vexriscv workaround
...
Flushing icache was working correctly on previous version of Vexriscv, understand
why it's no longer the case.
2019-03-01 09:16:48 +01:00
1fd81c2882
soc/integration: add initial SoCZynq SoC
2019-02-27 22:39:35 +01:00
3c527dcbdf
soc/interconnect: add initial axi code with bus definition and AXI2Wishbone
2019-02-27 22:26:57 +01:00
ed2578799b
test: add test_axi_lite (with test code from soc/interconnect/axi_lite lightly modified)
2019-02-27 22:24:56 +01:00
4aa07f2ae9
soc/interconnect: rename axi to axi_lite
2019-02-27 22:11:09 +01:00
c9f9e237d9
Merge pull request #149 from daveshah1/versa_trellis
...
Add trellis build option to versa_ecp5 and bring trellis support up to date
2019-02-25 19:26:07 +01:00
ff7e0fab6a
versa_ecp5: Add option to build with Trellis
2019-02-25 18:02:04 +00:00
024b41c5b2
trellis: Add LPF frequency constraints and remove -nomux
2019-02-25 18:01:35 +00:00
e38dfd99e8
soc/software/sdram: fix compilation on ultrascale
2019-02-25 16:12:21 +01:00
5f29a12ee7
targets/versa_ecp5: integrate DDR3
2019-02-25 15:27:08 +01:00
3dd529e40b
soc/software/bios/sdram: add ECP5 support
2019-02-25 14:41:33 +01:00
2fd6d0e7e1
soc/software/bios/sdram: improve write_level robustness
2019-02-25 14:38:24 +01:00
36772b75f6
soc/software/bios/sdram: improve sdrlevel readibility
2019-02-25 14:37:31 +01:00
6a980781d3
soc/software/bios/sdram: add helpers for rst/inc of delays
2019-02-25 14:36:47 +01:00
321dd8fcf6
versa_ecp5: Remove negative diff IO pins
...
In Lattice FPGAs only the positive side of differential pairs should
be specified (unlike Xilinx)
These are a warning on Diamond (which trims unused IO) and an error
with Yosys/nextpnr (which doesn't so they conflict when the positive
pin is 'expanded').
Already this is the case for the clock input, this commit performs
the same change for the DDR3 pins.
2019-02-22 12:12:10 +00:00
c03b1ad13a
platforms/versa_ecp5: add ddram pins
2019-02-20 22:45:19 +01:00
ff155a474d
soc/tools/remote/comm_uart: be sure to flush in waiting bytes before read and write
2019-02-16 00:08:24 +01:00
d3ecdd9995
soc/cores/clock: add actual clk_freqs to config
2019-02-14 10:41:27 +01:00
af52842fbb
soc_sdram: add use_full_memory_we parameter to allow disabling vivado workaround on small l2 caches
2019-02-12 12:12:40 +01:00
32543430c0
build/lattice/common/LatticeECXTrellisImpl: add support for nbits == 1
2019-02-11 19:41:12 +01:00
aabf042d38
soc_sdram: don't generate sdram initialization error message when integrated_main_ram is used
2019-02-11 09:23:39 +01:00
f51ad43607
build/lattice/common: add LatticeiCE40DDROutput
2019-02-07 16:23:55 +01:00
22ccf9ddf1
platforms/nexys_video: add LPC transceivers pins
2019-02-01 23:39:17 +01:00
1d9c55888f
build/sim: add jtagremote module (thanks LamdaConcept)
2019-01-30 14:01:19 +01:00
57b8bdd530
soc/integration/soc_core: allow disabling wishbone timeout
2019-01-29 12:47:11 +01:00
05dcb5cadc
soc/interconnect/wishbone: increase bus error timeout to 1e6 cycles
2019-01-27 08:28:01 +01:00
02708d3b0f
boards/platform/kc705: add sfp pins (both tx and rx)
2019-01-23 08:40:47 +01:00
8344a6a4ef
soc/cores/clock: add USIDELAYCTRL
2019-01-22 12:50:05 +01:00
7e0dd37616
soc/integration/soc_sdram: round port.data_width/l2_size to nearest power of 2 when it's not the case
...
With ECC configurations, native port data_width is not necessarily a power of 2.
2019-01-22 09:08:35 +01:00
871b958f85
boards/targets: improve presentation
2019-01-21 10:40:41 +01:00
a318343afb
boards/platforms/kcu105: add si570_refclk
2019-01-21 10:40:37 +01:00
48312890e5
boards/platforms/kc705: use vivado as default programmer
2019-01-21 10:40:32 +01:00
1b23890e0d
soc/cores/clock: allow ClockSignal to be used for clkin
2019-01-16 22:05:52 +01:00
387ee04130
build/sim/core: fix coverage
2019-01-11 15:01:58 +01:00
482abf9b43
build/sim/core: set -Wno-BLKANDNBLK (prevent blocking/non-blocking assigns on a same structure in system verilog)
2019-01-11 13:51:15 +01:00
9c5f654773
build/sim/core: set unroll-count to 256 to prevent Error-BLKLOOPINIT
2019-01-11 13:39:09 +01:00
f132012de1
build/sim: disable Warning-WIDTH
2019-01-10 16:03:09 +01:00
7c67bac723
soc/cores/cpu/vexriscv: set default variant to None in add_sources
2019-01-09 10:28:24 +01:00
648015d78e
soc/cores/cpu/vexriscv: move verilog variant selection to add_sources
2019-01-09 09:19:40 +01:00
2b5a6f1058
targets/kcu105: use USMMCM
2019-01-08 14:14:28 +01:00
86e19e6232
targets: pass speedgrade to S7PLL/S7MMCM
2019-01-08 13:50:12 +01:00
2581a00380
soc/cores/clock: add Xilinx Ultrascale PLL/MMCM
2019-01-08 13:21:53 +01:00
68e1dfca28
boards: avoid duplicating platforms that can be found in migen/litex-buildenv
...
The platforms that are kept are the ones used for litex development.
2019-01-06 19:01:19 +01:00
041bf41226
soc/integration/cpu_interface: generate name for Memories in get_csr_header
2019-01-05 10:57:37 +01:00
9f5d0cef6b
utils/litex_server: allow specify uart_baudrate as float
2019-01-03 10:38:14 +01:00
2c43f6f7dc
targets/ulx3s: use pll for phase shift, enable refresh, memtest ok
2018-12-28 15:58:28 +01:00
5ef4d09caa
targets/versa_ecp5: use pll for phase shift, enable refresh, memtest ok
2018-12-28 15:39:20 +01:00
9c801fbe50
soc/cores/clock/ECP5PLL: add basic phase support
2018-12-28 15:03:12 +01:00
a7b5b9d212
litex_sim: simplify, change sdram module and enable sdram refresh.
2018-12-27 20:36:50 +01:00
2deffd8c8a
build/sim/verilator: compile sim just before running and not when building.
2018-12-21 09:59:34 +01:00
291843ee76
Merge pull request #144 from mithro/nextpnr-migen-update
...
Integrate latest migen changes for lattice/icestorm.
2018-12-20 11:35:42 -08:00
53731b792b
Integrate latest migen changes for lattice/icestorm.
...
Integrated up to 37db6bb52532b6d1c6bc8b724c2e8c6a38546c2a.
2018-12-20 11:33:19 -08:00
180912a7a3
build/sim: handle verilog $finish and if coverage is enabled, write report at the end of the simulation.
2018-12-20 10:38:40 +01:00
b6c98cab0d
platforms/kcu105: change internal vref to 0.84v (recommended value for ddr4)
2018-12-19 11:33:32 +01:00
ebe0d567f8
bios/sdram: only show read delays when they are valid.
2018-12-19 11:19:47 +01:00
67a2590235
bios/sdram: reduce write leveling scan range
2018-12-19 11:18:19 +01:00
fe5cef4294
soc/cores/clock: remove return on S7PLL.create_clkout
2018-12-19 09:14:26 +01:00
eda1a83ea9
platforms/kcu105: set internal vref on ddr4 banks
2018-12-18 21:38:23 +01:00
a27b5a3be1
update Ultrascale DDRPHY
2018-12-18 11:25:21 +01:00
1c1c1bd122
Merge pull request #141 from mithro/xst-fix
...
Fix `-vlgincdir` for xst.
2018-12-17 21:24:15 -08:00
8b2abc7e89
Fix `-vlgincdir` for xst.
...
The command line is of the form;
```
-vlgincdir {"path1" "path2"}
```
Fixes the following error;
```
WARNING:Xst:3164 - Option "-vlgincdir" found multiple times in the command line. Only the first occurence is considered.
```
2018-12-17 21:11:14 -08:00
f8f3683aaa
bios/sdram: reduce scans verbosity on ultrascale
2018-12-17 16:00:44 +01:00
efce434aa9
bios/sdram: use ddrphy_half_sys8x_taps_read() for KUSDDRPHY
2018-12-17 11:43:21 +01:00
22d454efcd
Hack to fix #136 .
2018-12-16 14:40:10 -08:00
fa6fef1e15
Merge pull request #135 from mithro/icestorm-ice40up5k
...
Add uwg30 package and up3k part.
2018-12-16 14:04:19 -08:00
9481781d1c
Add uwg30 package and up3k part.
2018-12-16 14:03:29 -08:00
e9f1049200
soc/cores/cpu/vexriscv: add add_debug method for debug variants
2018-12-12 10:01:49 +01:00
35155e5172
soc/cores/cpu/vexriscv: add support for the new variants.
2018-12-12 09:39:30 +01:00
2ace45e6f8
soc/cores/cpu/vexriscv: update submodule
2018-12-12 09:38:53 +01:00
6d6c2b4c45
soc/cores/cpu/lm32: add submodule/rtl to include path (needed for lm32_include.v)
2018-12-12 09:38:10 +01:00
584fd51c01
build/sim/verilator: add support for plaform.sources, some cleanup
2018-12-12 09:37:24 +01:00
c9915f89ce
build/microsemi/libero_soc: fix typos
2018-12-12 09:34:43 +01:00
99578bc68c
gen/sim/core: add args support on Display
2018-12-09 09:46:10 +01:00
fa260f5b42
gen/fhdl: add simulation Display, Finish support.
...
In some simulation cases, it's easier to add debug traces directly in the code
than in the verilog/Migen testbench. This adds support for verilog $display in
Migen code.
Being able to terminate a simulation from the code is also useful, this also
add support for verilog $finish.
2018-12-09 09:45:17 +01:00
92a6169d2a
build/sim: add coverage parameter to enable code coverage
2018-12-09 08:10:50 +01:00
0c687bc29e
soc/interconnect/stream: add support for buffered async fifo
2018-12-08 01:24:08 +01:00
bf3b4eec34
gen: integrate migen changes
2018-12-04 21:06:51 +01:00
96527b5a3a
soc/interconnect/stream/gearbox: remove bit reversing by changing words order
2018-11-30 23:12:30 +01:00
1c8c2426b9
Merge branch 'master' of http://github.com/enjoy-digital/litex
2018-11-27 17:45:07 +01:00
8887fc24c4
build/xilinx/vivado: disable xpm by default (can be enabled by passing enable_xpm=True to build).
...
Old version of Vivado don't have XPM support and enable it break the build.
Enabling XPM is only useful in some cases, we can do it manually.
2018-11-27 17:42:39 +01:00
cc4ba65659
Merge pull request #130 from jfng/master
...
litex_sim: add --trace argument
2018-11-27 17:35:03 +01:00
ec46beeb47
targets/ulx3s, versa_ecp5: use ECP5PLL
2018-11-27 17:31:53 +01:00
71398e0155
litex_sim: add --trace argument
2018-11-27 17:26:32 +01:00
18048eb454
cores/clock: test and fix ECP5PLL, phase still not implemented.
2018-11-27 17:24:22 +01:00
20dd95c541
boards/platforms/ulx3s: add gpios 0-3
2018-11-27 14:15:35 +01:00
909cff1940
bios/sdram: flush l2 cache only when present
2018-11-26 18:37:45 +01:00
2ad83778bf
bios: allow testing main_ram at init when using an external controller
2018-11-26 15:21:00 +01:00
cdfe0454bb
build/microsemi/libero_soc: small cleanup
2018-11-26 11:35:06 +01:00
4592e3235b
Merge pull request #128 from mithro/small-fix
...
Two small fixes
2018-11-26 09:48:10 +01:00
4f565c5179
stream.Endpoint: Pass extra arguments to superclass.
2018-11-25 12:57:11 -08:00
3b9e4c4df6
wishbone.SRAM: Support non-32bit wishbone widths.
2018-11-25 12:56:37 -08:00
515c06219a
cores/clock: add ECP5PLL
2018-11-24 00:47:38 +01:00
7623b5dd96
soc/interconnect/stream/gearbox: inverse bit order
2018-11-23 18:34:24 +01:00
d32e393033
soc/cores/spi_flash: add missing endianness parameter
2018-11-23 18:33:53 +01:00
c954943e02
platforms/avalanche: add IOStandard on ddram pins
2018-11-23 12:47:45 +01:00
09a1cda943
build/microsemi/libero_soc: associate timings constraints with synthesis/place&route/timing verification
2018-11-23 09:30:13 +01:00
a98e1ad689
build/microsemi/libero_soc: add additional_timing_constraints
2018-11-23 09:04:42 +01:00
b166882308
build/microsemi/libero_soc: use die/package/speed from platform.device and add tcl_name helper
2018-11-23 08:26:31 +01:00
9df75d7d63
platforms/avalanche: add package/speed to platform.device
2018-11-23 08:24:29 +01:00
953b1f70df
build/microsemi/libero_soc: remove previous impl directory if exists
2018-11-23 08:11:57 +01:00
18d513a146
build/microsemi/libero_soc: give better names to pdc files: io/fp
2018-11-23 08:03:55 +01:00
4f092dbe35
build/microsemi/libero_soc: add additional_constraints
2018-11-22 18:40:19 +01:00
206c9a4697
platforms/avalanche: fix ddram dq7
2018-11-22 18:13:33 +01:00
f003407776
build/microsemi/libero_soc: add {} around port name.
2018-11-22 17:37:03 +01:00
beeca856e5
utils/litex_read_verilog: fix generated indent on instance
2018-11-22 17:33:46 +01:00
1fe7d09fb5
soc/integration/soc_core: add csr_map_update function
2018-11-21 08:39:52 +01:00
89c702187a
libbase/crt0-picorv32: Add support for .data sections.
2018-11-21 00:13:13 -05:00
80bdae0e55
build/sim/verilator: add trace parameter to enable tracer
2018-11-20 18:54:22 +01:00
7359a99bf9
soc_core: convert cpu_type="None" string to None
2018-11-20 17:45:11 +01:00
5805d63013
build/microsemi/libero_soc: only associate timings constraint to timing check (otherwise we loose io constraints...), use default settings for place & route
2018-11-19 16:36:30 +01:00
85f7666207
build/microsemi/common: add async reset synchronizer (using DFN1P0)
2018-11-19 15:35:59 +01:00
e3c6bd5846
build/microsemi/libero_soc: pass timing constraints to synthesis, place & route and timing verification tools
2018-11-19 12:50:07 +01:00
4c966114f8
build/microsemi/libero_soc: add timing constraints support
2018-11-19 09:40:16 +01:00
60faae490a
boards/platforms/avalanche: fix swapped serial pins
2018-11-19 08:45:55 +01:00
52396add5d
boards/platforms/avalanche: rename rst to rst_n (active low reset)
2018-11-19 08:14:46 +01:00
8e07e1a099
build/microsemi/libero_soc: associate .pdc to place and route tool.
...
For constraint to be applied, we also to associate them with the tool that will use it.
2018-11-19 08:07:36 +01:00
a5ed42ec68
soc/interconnect/stream: add Gearbox
2018-11-17 17:29:45 +01:00
a25645afa6
utils: add litex_read_verilog utility
...
generate Migen's modules from verilog files
2018-11-16 16:09:44 +01:00
a538d36268
create utils directory and move the litex utils to it
2018-11-16 14:37:19 +01:00
45ec78e93a
build/microsemi/libero_soc: able to generate design script (tcl) and design constraint (pdc) for libero soc / avalanche board.
2018-11-16 12:19:03 +01:00
4cb6583b4e
build: add microsemi template for polarfire fpgas support
2018-11-15 18:21:41 +01:00
b1425ba85f
lattice/icestorm: Add toolchain_path so it doesn't end up kwargs.
...
Fixes the following error;
```
make[1]: Leaving directory `/home/travis/build/mithro/litex-buildenv/build/ice40_hx8k_b_evn_base_lm32.lite/software/stub'
Traceback (most recent call last):
File "./make.py", line 164, in <module>
main()
File "./make.py", line 148, in main
vns = builder.build(**dict(args.build_option))
File "/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/soc/integration/builder.py", line 171, in build
toolchain_path=toolchain_path, **kwargs)
File "/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/soc/integration/soc_core.py", line 389, in build
return self.platform.build(self, *args, **kwargs)
File "/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/build/lattice/platform.py", line 29, in build
return self.toolchain.build(self, *args, **kwargs)
File "/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/build/lattice/icestorm.py", line 139, in build
v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
File "/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/build/lattice/platform.py", line 26, in get_verilog
**kwargs)
File "/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/build/generic_platform.py", line 368, in get_verilog
create_clock_domains=False, **kwargs)
TypeError: convert() got an unexpected keyword argument 'toolchain_path'
```
2018-11-13 16:18:08 -08:00
af25bf2bc0
soc_core: check for cpu before checking interrupt
2018-11-13 16:17:49 +01:00
b4bdf2a023
cores/clock/S7: just reset the generated clock, not the PLL/MMCM
2018-11-13 14:47:04 +01:00
86fd945bc3
bios/main: fix typo on mor1kx
2018-11-13 11:16:06 +01:00
af95028574
cpu/mor1kx: use clang only for linux variant
2018-11-13 11:09:39 +01:00
04523bc28a
xilinx/vivado: fix migen merge
2018-11-12 16:31:51 +01:00
Sean Cross
Florent Kermarrec
bunnie
Tim 'mithro' Ansell
Giammarco Zacheo
Gabriel Somlo
Arnaud Durand
Konrad Beckmann
Miodrag Milanovic
Pawel Czarnecki
Ilia Sergachev
Vamsi K Vytla
fb@frank-buss.de
Jan Kowalewski
Martin Cornil
Benjamin Herrenschmidt
Filip Kokosinski
Antti Lukats
chmousset
Daniel Kucera
Ilia Sergachev
Mateusz Holenko
Francis Lam
Ilia Sergachev
William D. Jones
Ambroz Bizjak
Tom Keddie
msloniewski
Antony Pavlov
David Shah
Kurt Kiefer
Michael Betz
Vamsi K Vytla
Larry Doolittle
Joanna Brozek
vytautasb
Caleb Jamison
David Shah
Jean-François Nguyen