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1660 commits

Author SHA1 Message Date
Florent Kermarrec
3deeb69531 targets/fpc_iii: review/cleanup to increase similarities with others targets to ease maintenance. 2021-01-29 08:46:31 +01:00
Florent Kermarrec
6c6d8a1393 platforms/fpc_iii: review/cleanup to increase similarities with others platforms and ease maintenance. 2021-01-29 08:41:10 +01:00
Sergiu Mosanu
1916677dc9 use VREF constraint for DDR4 C0 2021-01-28 19:58:38 -05:00
Gary Wong
4e5bb1bf1e Add FPC-III board support. 
FPC-III is the Free Permutable Computer; details on the board are
available from:

    https://repo.or.cz/fpc-iii.git
 2021-01-28 09:51:42 -07:00
Florent Kermarrec
9bd667720d targets/ecpix5: add LedChaser with red leds. 
Fits nicely LambdaConcept colors and Blue/Green leds are too bright and would need to be controlled through a PWM.
 2021-01-28 14:29:07 +01:00
Florent Kermarrec
aa20fca1f1 ecpix5: reorder rgb_leds to have ld7:0, ld8:1, ld5:2, ld6:3. 2021-01-28 14:25:16 +01:00
enjoy-digital
691bfd8b70
Merge pull request #159 from euryecetelecom/master 
Add ECPIX5 board components and pinouts (sata/spiflash/PMOD) + review openocd IDs
 2021-01-28 14:01:01 +01:00
Alessandro Comodi
bd716d956f netv2: add device variant to allow 100T as well 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-01-28 13:19:53 +01:00
Guillaume REMBERT
9beba7209d Add ECPIX5 components and pinouts (pmod/sata/spiflash) + review IDs from ECPIX5 openocd configuration 2021-01-28 12:00:28 +01:00
Kaz Kojima
aef78831c8 colorlight_i5: Use tx_delay=0 for LiteEthPHYRGMII instead of target specifig bios initialization 2021-01-27 18:19:27 +09:00
Sergiu Mosanu
84656a9c2e re-compare and adjust to u250 2021-01-26 23:03:09 -05:00
Kaz Kojima
c3fa0eac8b Add colorlight i5 board support 2021-01-27 11:44:59 +09:00
Florent Kermarrec
5fd04a97ea targets/netv2/pcie: reduce max_pending_requests to 2 to reduce resource usage. 2021-01-26 11:01:51 +01:00
Florent Kermarrec
d256cc8bd6 camlink_4k: disable leds when serial is used (since pin is shared). 2021-01-25 12:19:29 +01:00
Florent Kermarrec
1e1bec10c4 orangecrab: remove dm_remapping workaround: we are now using Wihsbone/L2 path with VexRiscv-SMP on this board. 2021-01-25 11:52:59 +01:00
Florent Kermarrec
537f494cbb arrow_sockit: review/harmonize with others boards. 2021-01-25 09:14:46 +01:00
Florent Kermarrec
4adc1b14c4 platforms/de0nano: use separator for connectors. 2021-01-25 08:58:12 +01:00
enjoy-digital
bbaa2fdc98
Merge pull request #149 from hansfbaier/master 
Add board support for Terasic/Arrow SocKit, Add connectors to de0-nano
 2021-01-25 08:55:48 +01:00
enjoy-digital
45f538b1d3
Merge pull request #155 from blakesmith/add_spi_flash 
ULX3S: Make spiflash optionally accessible from the SoC, and bootable
 2021-01-24 21:22:35 +01:00
enjoy-digital
8132f9f65b
Merge pull request #154 from euryecetelecom/master 
Fix SDCard issue when no SDCard inserted in ECPIX5 board.
 2021-01-24 21:14:58 +01:00
enjoy-digital
72985c72ca
Merge pull request #153 from Disasm/ecpix5-add-45f 
ECPIX-5: add option to select ECP5 device
 2021-01-24 21:14:14 +01:00
Blake Smith
cae51c0c24 ULX3S: Make spiflash optionally accessible from the SoC, and bootable 2021-01-23 14:44:26 -06:00
Hans Baier
aa771e9ff4 de0-nano: add connectors 2021-01-23 20:18:15 +07:00
Hans Baier
c9f0745d54 sockit: add board definitions for Terasic SocKit 2021-01-23 20:17:38 +07:00
Florent Kermarrec
23760e2eae orangecrab/CRGSDRAM: add missing rst signal (to reset from the SoC). 2021-01-22 22:55:02 +01:00
Guillaume REMBERT
b386ee5059 Fix SDCard issue when no SDCard inserted in ECPIX5 board. Now enable to detect SDCard presence. 
https://github.com/litex-hub/linux-on-litex-vexriscv/issues/171
 2021-01-20 18:02:13 +01:00
Vadim Kaushan
a678672fc9
ecpix5: add option to select ECP5 device 2021-01-19 01:22:52 +03:00
Gabriel Somlo
e71a4940c0 nexys4ddr: etherbone support 2021-01-15 12:14:40 -05:00
Sergiu Mosanu
7a738245af fix bitstream problem 2021-01-14 21:53:25 -05:00
Sergiu Mosanu
5a73eb0b6d initiate target and platform for alveo_u280 board 2021-01-14 18:35:43 -05:00
Florent Kermarrec
6a5f2f59a6 targets/orangecrab: use new ECP5DDRPHY's cmd_delay to add extra delay on DDR3's Clock/Commands. 
This fixes https://github.com/enjoy-digital/litedram/issues/130 and has been tested
at 48/64/96MHz on MT41K64M16 and MT41K512M16 variants.

Also remove un-needed cd_sys2x_eb.
 2021-01-12 18:57:22 +01:00
Florent Kermarrec
9ff90eb9fe targets/c10lprefkit: fix default sys-clk-freq. 2021-01-12 16:15:52 +01:00
Florent Kermarrec
0a7443d273 targets/orangecrab: make usr_btn optional to fix compilation with revision 0.1. 2021-01-08 19:30:37 +01:00
Florent Kermarrec
ae5494d7b6 orangecrab: defaults to USB-ACM UART. 2021-01-08 19:01:41 +01:00
Florent Kermarrec
c6e75122d9 sds1104xe: defaults to Crossover UART. 2021-01-08 19:00:41 +01:00
Florent Kermarrec
ab72f69937 targets/ac701: rename --ethernet-phy to --eth-phy for consistency with others targets. 2021-01-08 18:50:01 +01:00
Hans Baier
0ee62dd681 add etherbone ip address option for relevant boards 2021-01-08 18:44:31 +01:00
Florent Kermarrec
869cce2bba targets/colorlight_5a_75x: rename etherbone-ip args to eth-ip. 
eth-ip will also be used to configure Ethernet IP addresss.
 2021-01-07 09:26:38 +01:00
Florent Kermarrec
c829a47c31 targets/colorlight_5a_75x: Automatically disable Led Chaser when serial is used. 2021-01-07 09:17:28 +01:00
enjoy-digital
adbcc81ecf
Merge pull request #145 from hansfbaier/master 
colorlight: Add option for etherbone ip address and LED chaser
 2021-01-07 09:08:43 +01:00
enjoy-digital
a6e867c691
Merge pull request #144 from gsomlo/gls-genesys2-sdcard 
genesys2: LiteSDCard support
 2021-01-07 08:12:24 +01:00
enjoy-digital
d2d17e00a2
Merge pull request #142 from geertu/master 
platforms/ecp5: Fix slewrate configuration
 2021-01-07 08:11:30 +01:00
Florent Kermarrec
d73bd2f7ce targets/xilinx: add comment on sys_clk to pll.clkin false path. 2021-01-07 08:01:54 +01:00
Florent Kermarrec
1ac1c6857f targets/xilinx: add false path constraint between sys_clk and pll.clkin. 
The SoC reset added recently creates a path between sys_clk and pll.clkin
clock domains that is reported by the tools but that can be safely ignored.
 2021-01-07 00:02:46 +01:00
Hans Baier
0d69cfa6b0 colorlight: make LEDs optional 2021-01-05 08:03:26 +07:00
Hans Baier
4bec17e1a7 colorlight: Add option for etherbone ip address 2021-01-05 07:49:44 +07:00
Gabriel Somlo
2589d9f704 genesys2: add (spi-)sdcard build options 
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2021-01-04 13:57:21 -05:00
Gabriel Somlo
4eb0026a69 genesys2: add "rst" and "cd" signals to (spi-)sdcard records 
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2021-01-04 13:10:13 -05:00
Geert Uytterhoeven
4a95b94dbf platforms/ecp5: Fix slewrate configuration 
When building linux-on-litex-vexriscv for OrangeCrab:

    Warning: IOBUF 'spisdcard_clk' attribute 'SLEW' is not recognised (on line 207)
    Warning: IOBUF 'spisdcard_mosi' attribute 'SLEW' is not recognised (on line 210)
    Warning: IOBUF 'spisdcard_cs_n' attribute 'SLEW' is not recognised (on line 214)
    Warning: IOBUF 'spisdcard_miso' attribute 'SLEW' is not recognised (on line 218)

Platforms using litex.build.lattice.LatticePlatform seem to support only
"SLEWRATE", not "SLEW".  Fix the few offenders in the LogicBone and
OrangeCrab platform definitions.

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
 2021-01-04 17:08:51 +01:00
Florent Kermarrec
fe67766fb7 targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl). 2021-01-04 11:38:07 +01:00
Florent Kermarrec
0e3c03f2f6 mercury_xu5: remove unneeded cmd_latency=0 (now defaulting to 0). 2021-01-04 10:48:34 +01:00
Florent Kermarrec
5cc49bafbd orangecrab: Run reset_timer with por/48MHz clock domain (sys clock domain is now directly reseted on usr_btn press). 2021-01-04 09:42:05 +01:00
Florent Kermarrec
1fb24d4c71 orangecrab: Avoid usb clock domain reset on usr_btn press or SoC reset. 
Allows the USB-ACM link to stay up during reset.
 2021-01-04 09:05:19 +01:00
Florent Kermarrec
06cb49af37 targets/arty: add variant support through --variant args. 
./arty.py --variant=a7-35 or a7-100
./arty_s7.py --variant=s7-50 or s7-25
 2020-12-29 18:43:14 +01:00
Florent Kermarrec
02a81d54e2 targets/ecpix5/eth: set rx_delay to 0ns (tested with netboot on R01). 2020-12-29 16:01:12 +01:00
Florent Kermarrec
93779ecb95 platforms/colorlight_5a_75b: revert toolchain args. 
Useful to do tests with Diamiond.
 2020-12-29 14:22:42 +01:00
enjoy-digital
f2985f1e71
Merge pull request #141 from la6m/Colorlight_v8.0 
add colorlight v8.0 PCB
 2020-12-29 14:20:29 +01:00
Florent Kermarrec
84098d2de5 targets/qmtech_wukong: submitted target was the platform file, update with target shared in #133. 
Build tested with /qmtech_wukong.py --with-sdcard --with-ethernet --integrated-rom-size=0x10000 --build.
 2020-12-29 14:13:11 +01:00
Florent Kermarrec
b67b18caad qmtech_wukong: review/cleanup platform. 2020-12-29 14:10:49 +01:00
la6m
3e6b934961 add colorlight v8.0 PCB 2020-12-29 13:52:13 +01:00
Florent Kermarrec
e380f24655 targets/qmtech_wukong: +x. 2020-12-29 13:24:41 +01:00
Shinken Sanada
4b721eded7 add QmTech Wukong board support. 2020-12-29 13:20:42 +01:00
Florent Kermarrec
9beaf25822 nexys4ddr: fix eth/int_n pin (B8) and use 4-bit on vga.blue. 2020-12-24 10:15:29 +01:00
Sahaj Sarup
2a04c5c74e nexys4ddr: add support for litexvideo VGA Terminal 
This commit adds VGA support for the Nexys A7/ Nexys 4 DDR.

The VGA is however limited to RGB443 instead of the full 12bit RGB444.
This is because IO D8 which is MSB for Blue, is also used for ETH int_n.
This makes the final output have a yellow tint.
 2020-12-23 02:24:18 +05:30
Vadim Kaushan
f6a106cdf4
Fix orangecrab target 2020-12-20 01:07:43 +03:00
Florent Kermarrec
00fc2c5166 targets/orangecrab: use new DM remapping capability of LiteDRAM to fix LDM/UDM. 
Required by VexRiscv-SMP that uses DMs on LiteDRAM interface.
 2020-12-16 11:52:58 +01:00
Vadim Kaushan
bb58258fd4
Fix de10nano target 2020-12-14 15:27:33 +03:00
Florent Kermarrec
ec4ccc9fa5 platforms/xcu1525: fix ddram 1/2/3 pinout. 
DDR4 now validated successfully with LiteDRAM on the 4 channels.
 2020-12-11 13:58:26 +01:00
Florent Kermarrec
519f9449fa targets/sds1104: litex_term now directly supports crossover uart. 2020-12-10 13:56:01 +01:00
Robert Winkler
18337cdf25 targets/arty: sync with litex repository 
Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
 2020-12-07 17:32:40 +01:00
Alessandro Comodi
f66860c201 zybo_z7: fix clock pin constraint 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-12-07 16:46:20 +01:00
Geert Uytterhoeven
8e5f955e4e targets/orangecrab: Fix --sdram-device help text 
Obviously --sdram-device takes the SDRAM device, not the ECP5 FPGA
device.

Fixes: bf3c9dc9bf ("orangecrab: Add sdram selection option")
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
 2020-12-04 14:34:01 +01:00
Florent Kermarrec
fe563baec7 targets/fomu: modification to ValentyUSB no longer required. 
Following commits make it generic/portable while still using IOBuffers:
77b9d01058
371526e432
 2020-11-27 19:40:45 +01:00
Florent Kermarrec
5a4e28d47d target/usb_acm: switch git clone to litex-hub/valentyusb repo (up to date with LiteX). 2020-11-27 18:53:45 +01:00
Gwenhael Goavec-Merou
8d1095224f add support for redpitaya14/16 2020-11-26 06:54:11 +01:00
David Shah
11fa5c34ac nexus: Allow selection of toolchain 
Signed-off-by: David Shah <dave@ds0.me>
 2020-11-25 09:45:25 +00:00
Florent Kermarrec
159a0c751c targets/colorlight_5a_75x: update instructions and LiteEthPHYRGMII's tx_delay (required with LiteEth fixes). 2020-11-23 12:30:36 +01:00
Florent Kermarrec
03bb929f27 colorlight_5a_75x: add LedChaser. 2020-11-23 10:14:20 +01:00
Florent Kermarrec
d18deef10d colorlight_5a_75x: switch prog to FT232 based programmer (ex: JTAG HS2). 2020-11-23 10:13:57 +01:00
Jędrzej Boczar
ce38cff41d mercury_xu5: reduce cmd_latency to fix problems with DRAM leveling 2020-11-20 15:31:47 +01:00
enjoy-digital
a2f3add24e
Merge pull request #123 from teknoman117/litefury 
Support for the RHS Research LiteFury
 2020-11-20 08:44:27 +01:00
Nathaniel R. Lewis
389b623fe2 targets/litefury: new target 
LiteFury is an Artix-7 development board in the M.2 form factor
for PCIe accelerator development. It's similar to the Aller but
with an xc7a100t rather than an xc7a200t and no TPM module.

https://rhsresearch.com/collections/rhs-public/products/litefury
 2020-11-19 21:52:14 -08:00
Florent Kermarrec
49e1c34dfd targets/acorn_cle_215: add SATA. 2020-11-18 19:14:18 +01:00
Florent Kermarrec
778ce53865 targets/xcu1525: add SATA. 2020-11-17 15:27:42 +01:00
Florent Kermarrec
27e19644f4 targets/kcu105: add SATA. 2020-11-16 18:44:18 +01:00
Florent Kermarrec
27f60b2e93 add initial Siglent SDS1104X-E support (Ethernet & DDR3 validated). 
Pinout from https://github.com/360nosc0pe project.
 2020-11-13 12:20:15 +01:00
Florent Kermarrec
d42af3ea19 targets: add --sys-clk-freq support to all targets. 2020-11-12 18:07:28 +01:00
Florent Kermarrec
72afb95329 targets: create platform on BaseSoC for all targets (consitency). 2020-11-12 16:57:31 +01:00
Florent Kermarrec
843e724e3d targets/pcie: simplify using new LiteX's add_pcie method and enable it on all devices supported by LitePCIe. 2020-11-12 16:39:42 +01:00
Florent Kermarrec
9f11bfb0d1 qmtech_ep4ce15: convert name to lowercase, minor cleanup and add to test_targets. 2020-11-12 14:33:45 +01:00
enjoy-digital
31eb74dc2d
Merge pull request #122 from baselsayeh/master 
add Qmtech EP4CE15 coreboard support
 2020-11-12 14:27:49 +01:00
Florent Kermarrec
46e8a957fe platforms/zybo_z7: fix default_clk typo. 2020-11-12 14:26:36 +01:00
Florent Kermarrec
ac075f18c7 platforms/crosslink_nx_evn/vip: add default_clk. 2020-11-12 14:26:17 +01:00
Florent Kermarrec
f3ccd140c2 targets/simple: add try/except on leds. 2020-11-12 14:26:00 +01:00
Basel Sayeh
0fc67ddfdb
update copyright 2020-11-12 15:25:39 +02:00
Florent Kermarrec
7c6df67739 targets: add tinyfpga_bx target (based on icebreaker/fomu targets). 2020-11-12 14:09:25 +01:00
Florent Kermarrec
302e4ffdff targets/simple: simplify (only keep minimal SoC + Leds) and add load argument. 
ex of use:
./simple.py litex_boards.platform.ulx3s --build --load
./simple.py litex_boards.platform.trellisboard --build --load
./simple.py litex_boards.platform.arty --build --load
etc...
 2020-11-12 13:54:30 +01:00
Florent Kermarrec
a4d05522d4 platforms/ice40/ecp5: add toolchain parameter with default to trellis (ECP5) or icestorm (iCE40). 
Required to simplify simple.py target and use trellis/icestorm as default toolchain.
 2020-11-12 13:33:30 +01:00
Florent Kermarrec
5cf7731f37 targets/netv2: add PCIe. 2020-11-12 12:16:01 +01:00
Florent Kermarrec
7a9f175450 targets/pcie: remove force of csr_data_width to 32 (this is now the default) but just add a check on the pcie block. 2020-11-12 12:08:20 +01:00
Florent Kermarrec
4401fec1e6 targets: remove add_csr("crg") (no longer needed). 2020-11-12 11:54:11 +01:00
Florent Kermarrec
bd4e92ad13 targets: cleanup, uniformize build arguments between targets. 2020-11-12 11:46:00 +01:00
Basel Sayeh
1b1ed5ebf1
add Qmtech EP4CE15 coreboard support 2020-11-12 01:56:36 +02:00
Florent Kermarrec
5fbb176c2a targets/crosslink_nx: update NXLRAM import. 2020-11-09 11:05:18 +01:00
Florent Kermarrec
afe44e2bd6 targets/crosslink_nx_evn: update NXPLL import. 2020-11-09 10:25:30 +01:00
Florent Kermarrec
39d979a9d3 targets/Ultrascale: add missing AsyncResetSynchronizer import. 2020-11-09 10:25:05 +01:00
davidcorrigan714
97b64d16a6 Lattice NX PLL Support 2020-11-08 20:34:46 -06:00
Florent Kermarrec
1f52fbaca6 xcu1525: fix last ddram channel numbering. 2020-11-06 10:48:26 +01:00
Florent Kermarrec
2b17dc1b89 target: add rst signal to CRG to allow full reset of the SoC on reboot command. 2020-11-04 11:13:42 +01:00
Florent Kermarrec
aa6b9cab4a targets/crosslink_nx_vip: +x. 2020-11-04 09:30:57 +01:00
Florent Kermarrec
ce14775dfb targets/tec0117: move SerialFlashManager import to flash function. 2020-11-04 09:30:31 +01:00
Florent Kermarrec
2da4eabffe platforms/icebreaker: fix refactoring typo. 2020-11-04 09:30:01 +01:00
Florent Kermarrec
c093d0d0fc platforms: cleanup pass to uniformize comments/separators/orders. 2020-11-03 10:48:57 +01:00
Florent Kermarrec
8d26c241cd kc705: revert sys_clk_freq to 125MHz. 2020-11-02 19:51:48 +01:00
Florent Kermarrec
babf638c2b targets/nexys_video: add SATA support. 2020-11-02 19:43:25 +01:00
Kevin Mehall
d1c9cc7553 Add LFE5U-12F device for ULX3S 2020-11-01 23:45:32 +00:00
Florent Kermarrec
e950a4a588 targets/kc705: update sata pads. 2020-10-30 17:12:59 +01:00
Florent Kermarrec
a410e447e1 targets/kc705/sata: enable write support. 2020-10-30 14:51:40 +01:00
Florent Kermarrec
d626861e95 platforms/acorn_cle_215: add serial_io (on P2). 2020-10-29 12:10:12 +01:00
Florent Kermarrec
f9252fdd45 targets/kc705: simplify SATA using LiteX's add_sata integration method. 2020-10-29 10:16:40 +01:00
Florent Kermarrec
7da8628fba targets/kc705: switch SATA to gen2. 2020-10-28 19:09:30 +01:00
Florent Kermarrec
931f6667ac targets/kc705: add initial SATA support. 2020-10-26 15:15:24 +01:00
enjoy-digital
51934567fe
Merge pull request #118 from daveshah1/lifcl-vip 
Add CrossLink-NX VIP board platform and target
 2020-10-22 11:03:47 +02:00
Florent Kermarrec
a38c1e7062 mist: add copyrights. 2020-10-22 10:48:58 +02:00
David Shah
20720693c4 crosslink_nx_vip: Add HyperRAM support 
Signed-off-by: David Shah <dave@ds0.me>
 2020-10-22 09:15:40 +01:00
David Shah
b278d8bccc Add CrossLink-NX VIP board platform and target 2020-10-22 09:15:35 +01:00
YanekJ
4541c39e94 Initial support for the MIST board (https://github.com/mist-devel/mist-board/wiki) 2020-10-17 12:28:22 +02:00
Florent Kermarrec
814e7630e4 targets/xilinx: use generic name for idelay clk (avoid clk200, clk400, etc...) since we somtimes want to change it. 2020-10-13 12:10:29 +02:00
Florent Kermarrec
06137452d2 targets/xcu1525: use ddram_channel to select clk300. 2020-10-13 11:57:00 +02:00
Florent Kermarrec
982cfd5ad5 platforms/xcu1525: fix ddram constraints, add clk300 constraints for all channels. 2020-10-13 11:50:36 +02:00
Florent Kermarrec
c3ea04b6e9 targets/s7/us: update sdram (manual cmd_latency no longer needed). 2020-10-12 18:46:21 +02:00
Florent Kermarrec
ddf7038c78 ulx3s: add 1.7 and 2.0 revisions support. 2020-10-12 13:23:26 +02:00
enjoy-digital
204d22c62b
Merge pull request #115 from BryanJacobs/master 
platforms/ulx3s: Update ULX3S SD pins for revision 2.0
 2020-10-12 12:55:17 +02:00
Bryan Jacobs
3b11e60fb1 Update ULX3S SD pins for revision 2.0 2020-10-11 14:17:48 +11:00
Konrad Beckmann
5e67853a21 versa_ecp5: Add --eth-phy to select ethernet phy 
This also simplifies the logic a bit.
 2020-10-09 23:56:16 +02:00
Konrad Beckmann
477734ff06 versa_ecp5: Add etherbone support 
Etherbone can be enabled with --with-etherbone
 2020-10-09 00:53:08 +02:00
Florent Kermarrec
55da8b867a platforms/zedboard: minor cleanups to uniformize with other platforms. 2020-10-07 11:25:20 +02:00
Michael Betz
e225cbd28f add zedboard platform to CI 2020-10-06 11:35:03 -07:00
Michael Betz
8ee20a3f30 clean up imports 2020-10-06 11:24:34 -07:00
Michael Betz
865c2bd98c zedboard platform: clean up 
* remove unused code
  * remove oled integration code
  * openocd = default programmer
 2020-10-06 11:00:36 -07:00
Michael Betz
94ef096e77 Merge branch 'master' of https://github.com/litex-hub/litex-boards into HEAD 2020-10-06 10:05:34 -07:00
Florent Kermarrec
fff20f7532 targets/fomu: base it on iCEBreaker target + USB-ACM. 
This uniformizes Fomu target with others, provide a simple example of LiteX SoC
on Fomu and will ease maintenance.
 2020-10-06 11:39:30 +02:00
Michael Betz
12aed44577 add zedboard platform 2020-10-06 00:28:54 -07:00
enjoy-digital
79ef091a06
Merge pull request #110 from pepijndevos/gowin 
Add initial support for Trenz TEC0117 board
 2020-10-05 19:50:09 +02:00
enjoy-digital
2ee32f2a15
Merge pull request #109 from geertu/orangecrab-Fix-r0.1-user_led-mapping 
orangecrab: Fix r0.1 user_led mapping
 2020-10-02 09:40:41 +02:00
enjoy-digital
062fbd6c63
Merge pull request #108 from daveshah1/dave/nx-evn-doc 
crosslink_nx_evn: Improve documentation on UART jumpers
 2020-10-02 09:40:04 +02:00
Pepijn de Vos
18e5def9f2 don't verify erase, very slow 2020-10-01 08:41:16 +02:00
Pepijn de Vos
81e4f1f158 add initial support for Trenz TEC0117 board 2020-09-30 14:01:36 +02:00
Geert Uytterhoeven
b2e34f5faf orangecrab: Fix r0.1 user_led mapping 
On r0.1, all three user_leds are mapped to the same pin.
Fix this by mapping them to the pins connected to the individual
channels of the RGB LED, to match the comments, the schematics, and the
spirit of r0.2.

Untested on real hardware (I have r0.2 only).

Fixes: c94cbae0c0 ("orangecrab: add user_led (RGB leds), DFUProg and --load support.")
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
 2020-09-25 10:33:21 +02:00
Florent Kermarrec
de09b10726 targets/xcu1525: add ddram-channel selection and rewrite DRC workaround comment. 2020-09-24 18:19:49 +02:00
Florent Kermarrec
cc53206aff targets/kcu105: create specific cd_eth for ethphy. 2020-09-24 10:25:55 +02:00
Florent Kermarrec
5b7288cfee targets/kcu105: add Etherbone support. 2020-09-24 09:55:11 +02:00
Florent Kermarrec
77ba49f2bb targets/pcie: update timing_constraints (now provided by the .xci). 2020-09-24 09:50:55 +02:00
Florent Kermarrec
c6610b4a3f platforms/xcu1525: update ddram1/2/3 pinout. 
Using https://github.com/d953i/Custom_Part_Data_Files/blob/master/Boards/Xilinx_BCU1525/BCU1525_DIMMx.xdc
 2020-09-20 21:07:00 +02:00
Florent Kermarrec
e5a144e9cd platforms/xcu1525: update ddram0 pinout. 
Using https://github.com/d953i/Custom_Part_Data_Files/blob/master/Boards/Xilinx_BCU1525/BCU1525_DIMM0.xdc.
 2020-09-19 23:28:34 +02:00
Florent Kermarrec
8ffb86c0dc platforms/fk33/xcu1525: define pcie_x2/x4/x8/x16. 2020-09-19 22:37:05 +02:00
Florent Kermarrec
e4cdbe0f7a targets/ac701: reduce ddram pads to the first 4 modules. 2020-09-05 11:46:07 +02:00
David Shah
8a9fd02768 crosslink_nx_evn: Improve documentation on UART jumpers 
Signed-off-by: David Shah <dave@ds0.me>
 2020-09-05 09:58:28 +01:00
Florent Kermarrec
76ac4a69a8 rename forest_kitten_33 platform/target to fk33. 2020-09-04 20:05:18 +02:00
Florent Kermarrec
979fee7517 forest_kitten_33: add pcie. 2020-09-04 20:02:43 +02:00
Florent Kermarrec
ad48728160 xcu1525: update headers (were still using old format). 2020-09-04 19:59:09 +02:00
enjoy-digital
ad4c483c32
Merge pull request #106 from daveshah1/dave/alveo_u250_pcie 
alveo_u250: Add PCIe x4 support
 2020-09-04 19:22:48 +02:00
enjoy-digital
a68c00e48e
Merge pull request #104 from DerFetzer/colorlight_5a_75e_v6_0 
Add support for 5A-75E V6.0 board
 2020-09-04 19:21:02 +02:00
David Shah
ae6a052e57 alveo_u250: Add PCIe x4 support 
Based on the implementation in xcu1525

Signed-off-by: David Shah <dave@ds0.me>
 2020-09-04 14:20:04 +01:00
Florent Kermarrec
2eda9d0252 xcu1525: add DDR4 IOs for C1/C2/C3 and fix compilation (untested). 2020-09-04 11:34:33 +02:00
Florent Kermarrec
7b6b71d4e3 xcu1525: add initial DDR4 support in C0 (untested). 2020-09-03 19:48:23 +02:00
Florent Kermarrec
5a62a07b45 xcu1525: add initial PCIe support (untested). 2020-09-03 19:26:02 +02:00
Florent Kermarrec
51e881d1ff add minimal xcu1525 support (VCU1525 or BCU1525 boards). 2020-09-03 19:06:43 +02:00
DerFetzer
8bd736bd77 targets/colorlight_5a_75x: make Ethernet PHY selectable, cast sys_clk_freq to int for Wishbone 2020-09-02 22:08:45 +02:00
DerFetzer
cc78574297 targets/colorlight_5a_75x: fix rx_data pin order for Ethernet PHY 0 2020-09-02 22:04:23 +02:00
DerFetzer
24b853c2db targets/colorlight_5a_75x: force use of internal oscillator when using Ethernet with 5A-75E V6.0 2020-09-01 17:07:52 +02:00
DerFetzer
8b1fee0e66 Add support for 5A-75E V6.0 board 2020-09-01 17:02:17 +02:00
Florent Kermarrec
9b6ed6bdf1 targets/orangecrab: add fallback to bootloader when usr_btn is pressed for 1 second. 2020-09-01 16:22:32 +02:00
Florent Kermarrec
b9ac72cf78 targets: simplify clocking on iCE40/ECP5 targets (AsyncResetSynchronizer now integrated in PLL). 2020-09-01 13:38:32 +02:00
Florent Kermarrec
9e2d301745 targets/icebreaker: simplify, update PLL/API and BIOS execution from SPI Flash. 2020-09-01 12:58:13 +02:00
Florent Kermarrec
beccecf59f orangecrab: reduce DDR3 power consumption/heat and get back USB PLL to CRGSDRAM. 
- disable DQ termination.
- disable RTT_NOM.
- drive VCCIO/GND pads.

Reduce current from 0.25A to 0.12A with: ./orangecrab.py --uart-name=usb_acm --sys-clk-freq=48e6.
Still working at 96MHz, 0.17A with: ./orangecrab.py --uart-name=usb_acm --sys-clk-freq=96e6.

See https://github.com/enjoy-digital/litedram/issues/216.
 2020-08-28 20:01:54 +02:00
Florent Kermarrec
63b65e278c crosslink_nx_evn: update copyrights. 2020-08-24 22:33:58 +02:00
Florent Kermarrec
153326fa26 targets/icebreaker: update flash. 2020-08-24 17:19:15 +02:00
Piense
795e34aafd add initial Crosslink-NX support. 2020-08-24 16:47:38 +02:00
Florent Kermarrec
84c19a6cdf targets/de0nano: set sys2x_ps phase to 180° for sdram_rate=1:2. 2020-08-24 09:28:51 +02:00
Florent Kermarrec
70594a5305 ulx3s: simplify sdram constraints and increase phase to 180 for sdram_rate=1:2. 2020-08-24 09:05:58 +02:00
Florent Kermarrec
1781be166a general: add SPDX License identifier to header and specify files are part of LiteX-Boards. 2020-08-23 15:00:17 +02:00
Florent Kermarrec
83d8b8d1b4 platforms/acorn_cle_215: integrated sdcard ios as extension. 2020-08-22 22:11:51 +02:00
connorwk
f328909578 Moved platform call inside of BaseSoC init for compatibility with linux-on-litex-vexriscv support. Added optional spi-sdcard support over P2 header. 2020-08-09 16:27:41 -04:00
Florent Kermarrec
45bb329b56 targets/colorlight_5a_75x: enable HalfRate SDRAM PHY. 2020-08-07 19:26:12 +02:00
Florent Kermarrec
b6a1ad5a9c targets/orangecrab: add simple CRG when built without DDR3. 2020-08-07 18:10:03 +02:00
Florent Kermarrec
869ceadacb targets: use platform.request_all on LedChaser. 2020-08-06 20:04:03 +02:00
Pawel Sagan
d2cd6d4c0e arty: Change USB-uart and I2S Pmod configuration 
This makes it compatible with the Arty A7 expansion board by Antmicro
(https://github.com/antmicro/arty-expansion-board).
 2020-08-05 11:54:25 +02:00
Florent Kermarrec
ee28d7b5ec targets/ulx3s/add_oled: simplify. 2020-08-04 12:31:15 +02:00
Pepijn de Vos
eba70377b7 add optional OLED peripheral to ULX3S target 2020-08-04 11:07:30 +02:00
Florent Kermarrec
929e55d7e6 platforms/trellisboard: add SDCard PMOD pins. 2020-07-29 09:07:55 +02:00
Florent Kermarrec
5fd3e8dbcd ecpix5: add SDCard. 
Validated with Linux-on-LiteX-VexRiscv.
 2020-07-28 17:45:49 +02:00
Florent Kermarrec
94ccf1dd3e targets/trellisboard: simplify clocking when no DDR3, remove firmware_ram (was here for debug). 2020-07-27 16:31:46 +02:00
Florent Kermarrec
eb8a484032 targets/de10nano: fix typo. 2020-07-26 12:01:11 +02:00
Florent Kermarrec
2cef54a909 targets/colorlight_5a_75x: avoid sys_clk_freq of 125MHz with etherbone (no longer required). 
This allows creating SoCs with CPU, SDRAM and Etherbone enabled all together.
 2020-07-26 11:58:42 +02:00
Florent Kermarrec
760b8ff93a arty: improve xy_pmod_io genericity (allow selecting the PMOD) and enable SDCard. 2020-07-24 16:29:35 +02:00
Florent Kermarrec
04fc98f834 de0nano/ulx3s: add sdram HalfRate support (untested). 2020-07-24 16:12:46 +02:00
Florent Kermarrec
d0ca1befa6 targets/de10nano/minispartan6: simplify HalfRate support, rename argument to sdram_rate. 2020-07-24 16:11:57 +02:00
Florent Kermarrec
9730c6f722 platforms/de10nano: use additional sdram constraints required for HalfRate. 2020-07-24 12:27:36 +02:00
Florent Kermarrec
7399d13cef paltforms/de10nano/sdram: enable fast input/output on dq. 2020-07-24 11:27:25 +02:00
Florent Kermarrec
b4b1ab8621 paltforms/de10nano: simplify IO constraints (for consistency with others platforms). 2020-07-24 09:03:35 +02:00
enjoy-digital
89c5bf43cf
Merge pull request #92 from rob-ng15/master 
Enable use of HalfRateGENSDRPHY on de10nano
 2020-07-24 08:49:09 +02:00
Florent Kermarrec
1e1589a514 zybo_z7: demonstrate use of PS7 (with --cpu-type=zynq7000). 
This uses a pre-generated .xci hosted on github, still need to figure out where the best location for it.
 2020-07-23 17:45:21 +02:00
rob-ng15
7cda143250
Allow use of HalfRateGENSDRPHY 2020-07-23 14:41:35 +01:00
rob-ng15
cf9839307f
Add Misc 
Add Misc("") arguments to various inputs/outputs for stability. Allows de10nano to use HalfRateGENSDRPHY for sdram
 2020-07-23 14:40:04 +01:00
Florent Kermarrec
8a3b453e2f add Zybo Z7 minimal platform/targets: no PS7 support and USB-UART PMOD on JB. 2020-07-23 15:26:22 +02:00
Florent Kermarrec
e723bef49a platforms/arty: add usb_uart_pmod_io (USB-UART PMOD on JA) to ease debug with a second UART (for UARTbone/LiteScope). 
Also use pmod connector names in i2s_pmod and sdcard_pmod.
 2020-07-22 14:41:09 +02:00
Florent Kermarrec
19d0b95867 platforms/targets: keep in sync with litex. 2020-07-22 08:53:49 +02:00
Florent Kermarrec
0ee4b215b9 trellisboard/ulx3s: fix sdcard slewrate. 2020-07-21 15:23:08 +02:00
Florent Kermarrec
7efa1c37a1 platforms/arty: add missing pullups on sdcard. 2020-07-21 15:22:39 +02:00
Florent Kermarrec
2ce24df76d platforms/genesys2: add internal_vref to 0.750v on bank 34 (DDR3). 2020-07-18 22:18:41 +02:00
Florent Kermarrec
135c387155 platforms/ulx3s: add assertion for supported devices. 2020-07-17 12:04:06 +02:00
Florent Kermarrec
851378f0a9 platforms/trellisboard: move ddram_vtt_en. 2020-07-17 12:03:37 +02:00
enjoy-digital
165f9eacde
Merge pull request #91 from antmicro/jboc/gensdrphy 
targets/minispartan6: add support for HalfRateGENSDRPHY
 2020-07-15 08:22:57 +02:00
Jędrzej Boczar
02f53e6326 targets/minispartan6: add support for HalfRateGENSDRPHY 2020-07-14 11:01:09 +02:00
Vamsi K Vytla
44ad902aad platforms/kc705.py: LPC DP0_M2C/C2M diff pair 2020-07-13 10:26:17 -07:00
Greg Davill
a461f5ac59 orangecrab: add usb, rst_n signals for r0.1 
- fix standard io extensions
 - Use newly assigned code for orangecrab 1209:5af0
 2020-07-09 19:56:32 +09:30
enjoy-digital
f3d02d8fca
Merge pull request #87 from antmicro/arty_i2s 
arty: Add configuration of I2S pins
 2020-07-07 17:22:10 +02:00
Pawel Sagan
df54b93db3 arty: Add configuration of I2S pins 2020-07-07 15:25:10 +02:00
Florent Kermarrec
d9595a317e targets/orangecrab: use user_btn as rst_n. 2020-07-06 17:49:05 +02:00
Florent Kermarrec
40fbbbbebc platforms/orangecrab: add sdcard pins on r0_2. 2020-07-06 17:48:48 +02:00
Florent Kermarrec
7b1bf9d74a targets: remove sdcard specific clock domain (now generated by the PHY). 2020-07-03 20:09:30 +02:00
Florent Kermarrec
31e6997e70 sdcard: rename cd_sdcard to cd_sd to avoid unnecessary clock domain. 2020-07-01 12:58:48 +02:00
Florent Kermarrec
fe3ea805bc targets/pcie: make pcie optional (--with-pcie) and avoid forcing uart to crossover. 2020-06-30 18:44:00 +02:00
Florent Kermarrec
7a48a61605 targets: add indentifier on all targets. 2020-06-30 18:11:04 +02:00
Florent Kermarrec
fc22e28fe9 targets: replace PCIeSoC with BaseSoC. 2020-06-30 17:41:57 +02:00
Florent Kermarrec
d28a0c4258 targets/pcie: remove DNA/XADC/ICAP that were only on PCIe targets. 
DNA/XADC/ICAP are demonstrated in LitePCIe repository and should probably be added with
a add_xy method.
 2020-06-30 17:37:24 +02:00
Florent Kermarrec
e91a5d6b82 targets/pcie: remove soft reset. 2020-06-30 17:28:13 +02:00
Florent Kermarrec
1356ebb416 targets/ecp5: update clocking on boards with DDR3 to use reset from ddrphy.init and use primary clock for Power on reset. 2020-06-29 16:42:53 +02:00
enjoy-digital
49973990f3
Merge pull request #85 from oskirby/logicbone 
Add Logicbone ECP5 board
 2020-06-29 16:24:15 +02:00
Owen Kirby
76a32ba8ec Add Logicbone ECP5 board 
The Logicbone is an Open Source development board for the Lattice ECP5
being developed at https://github.com/oskirby/logicbone
 2020-06-27 03:32:47 -07:00
Florent Kermarrec
efe33c9764 targets/arty: add fixed sdcard clock and remove sys2x (use NETWORKING interface_type on DDR3). 2020-06-25 11:21:24 +02:00
Florent Kermarrec
6753a92296 targets: add fixed sdcard clock on boards with SDCard support. 2020-06-25 11:20:38 +02:00
Florent Kermarrec
782c856619 platforms/genesys2: add usb_fifo. 2020-06-23 18:02:53 +02:00
Florent Kermarrec
936ba5b279 platforms/genesys2: add openocd specific configuration (channel 1 used for JTAG). 2020-06-23 11:55:50 +02:00
Florent Kermarrec
55ed9fbf02 platforms/kcu105: add sdcard/spisdcard. 2020-06-23 11:44:40 +02:00
Florent Kermarrec
eee00ebd0a platforms/genesys2: add sdcard/spisdcard. 2020-06-23 11:44:26 +02:00
Florent Kermarrec
6568c8a3ae platforms/netv2: add spisdcard. 2020-06-23 11:44:10 +02:00
Florent Kermarrec
7de7c4be5c platforms/kc705: rename mmc to sdcard and make it similar to other boards. 2020-06-23 10:56:31 +02:00
Florent Kermarrec
0ecb8609b3 platform/arty: also update spisdcard. 2020-06-16 20:15:12 +02:00
Florent Kermarrec
7a8b0b743d platforms/pano_logic_g2: -x. 2020-06-16 19:53:46 +02:00
Kamil Rakoczy
f70655d1ac Change sdcard Pmod from JB to JD 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-06-15 12:01:46 +02:00
Florent Kermarrec
04f6d4463a versa_ecp5: simplify device (LFE5UM5G or LFE5UM) and adapt integrated_rom_size only for Microwatt. 2020-06-13 11:17:05 +02:00
Raptor Engineering Development Team
90092164c8 Add device option for ECP5 Versa board 
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
 2020-06-12 18:39:43 -05:00
Raptor Engineering Development Team
b1be5dcc23 Fix FTBFS from undersized BIOS ROM region with Microwatt 
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
 2020-06-12 18:39:43 -05:00
Florent Kermarrec
9b45ec0f35 de10lite: simplify vga terminal. 2020-06-11 19:59:32 +02:00
Florent Kermarrec
85cac7abc0 de10nano/Mister: review/simplify. 2020-06-11 19:54:55 +02:00
Florent Kermarrec
64372d7876 targets/orangecrab: add spi-sdcard and workaround for ValentyUSB. 2020-06-11 19:21:44 +02:00
Florent Kermarrec
c94cbae0c0 orangecrab: add user_led (RGB leds), DFUProg and --load support. 2020-06-11 19:21:40 +02:00
enjoy-digital
9aea2272eb
Merge pull request #80 from rob-ng15/master 
Use 128mb sdram, uart via i/o port on i/o board and vga terminal via i/o board
 2020-06-11 18:16:18 +02:00
Florent Kermarrec
45bd50b000 targets: rename colorlight_5a_75b to colorlight_5a_75x (since we are now also supporting the 75e). 2020-06-10 23:14:37 +02:00
enjoy-digital
ad1693a1ad
Merge pull request #82 from Disasm/colorlight-5a-75e 
Add Colorlight 5A-75E V7.1 board
 2020-06-10 23:09:26 +02:00
enjoy-digital
b312c65eb9
Merge pull request #81 from Disasm/fix-5a-75b 
Update J4 pin 5 on Colorlight 5A-75B V7.0
 2020-06-10 23:07:33 +02:00
Florent Kermarrec
94861bbb9a targets/orangecrab: uncomment MT41K512M16. 2020-06-10 19:30:07 +02:00
Florent Kermarrec
b6df166f5a platforms/arty: add spisdcard to _sdcard_pmod_io. 2020-06-10 17:38:16 +02:00
Florent Kermarrec
00c8e40d02 platforms/ulx3s: add sdcard pins. 2020-06-10 17:37:50 +02:00
Vadim Kaushan
0c590abf12
Update colorlight_5a_75b target: add 5A-75E board support 2020-06-10 03:20:32 +03:00
Vadim Kaushan
1acdb962a5
Add 5A-75E V7.1 board 2020-06-10 03:07:20 +03:00
Vadim Kaushan
939f05fea4
Update J4 pin 5 on Colorlight 5A-75B V7.0 2020-06-10 02:49:18 +03:00
rob-ng15
485c242f24
Use 128mb sdram, uart via i/o port on i/o board and vga terminal via i/o board 2020-06-08 11:05:58 +01:00
rob-ng15
e52d6aca5f
Use 128mb sdram, uart via i/o port on i/o board and vga terminal via i/o board 2020-06-08 11:05:36 +01:00
Gabriel Somlo
f9a8edb973 targets/trellisboard: add initial LiteSDCard support 
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-06-03 13:41:57 -04:00
Florent Kermarrec
d87a11a9cb targets/pcie: use generate_litepcie_software on all targets with PCIe. 2020-06-03 08:30:54 +02:00
Florent Kermarrec
9f83b6e3cf targets/acorn_cle_215: use new generate_litepcie_software functions and add --driver argument to generate driver. 2020-06-03 08:20:43 +02:00
Florent Kermarrec
091ec846a1 targets/acorn_cle_215: automatically copy software from litepcie and generate headers in kernel directory. 2020-06-02 20:09:45 +02:00
Florent Kermarrec
06edf48897 targets: rename gateware-toolchain parameter to toolchain. 2020-06-02 13:45:05 +02:00
Florent Kermarrec
0b11aba8a1 platforms/nexys_video: add spisdcard pins. 2020-05-29 19:37:04 +02:00
Florent Kermarrec
76df4e39c8 targets: simplify Ethernet/Etherbone integration on targets with both. 2020-05-29 19:20:27 +02:00
Florent Kermarrec
2e1a816d1f pano_logic_g2: switch to LiteEthPHY and simplify Ethernet/Etherbone. 2020-05-29 10:41:35 +02:00
enjoy-digital
33fe308ef0
Merge pull request #78 from antmicro/jboc/spd-read 
ZCU104: add I2C
 2020-05-27 14:56:31 +02:00
Jędrzej Boczar
e5578a1ae8 zcu104/platform: change I2C number to 0 2020-05-27 14:31:22 +02:00
Jędrzej Boczar
ac1f1cd6a7 zcu104: add I2C 2020-05-27 12:47:43 +02:00
Florent Kermarrec
71f220a24d colorlight_5a_75b: remove unnecessary parenthesis. 2020-05-27 10:13:44 +02:00
Florent Kermarrec
2f3817cba9 pano_logic_g2: add ethernet (build but not functional yet) and use user_btn_n as sys_rst. 2020-05-27 10:13:12 +02:00
Florent Kermarrec
f19bc36813 pano_logic_g2: add revision support (b and c, c as default) and add OpenOCD programmer. 
Tested with:
./pano_logic_g2.py --uart-name=jtag_uart --build --load
./litex_jtag_uart.py --config=openocd_xc6_ft232.cfg
lxterm /dev/pts/X
 2020-05-27 08:58:40 +02:00
Florent Kermarrec
d6518c7dc2 prog/openocd: fix openocd_xc6 cfgs. 2020-05-27 08:48:16 +02:00
Florent Kermarrec
22f18f618e pano_logic_g2: move gmii_rst_n to _CRG. 2020-05-26 08:36:06 +02:00
Skip Hansen
0648c04158 Updated comment, added link to clocking documentation. 2020-05-25 14:48:24 -07:00
Skip Hansen
1ab46562bd Take Ethernet PHY out of reset so default clock is 125 Mhz (and baud rate is 115,200) 2020-05-25 10:11:03 -07:00
Florent Kermarrec
9b572ece0e forest_kitten_33: add minimal target and use es1. 
Tested with:
./forest_kitten_33.py --uart-name=jtag_uart --build --load
litex/tools/litex_jtag_uart.py
lxterm /dev/pts/X
 2020-05-25 12:26:52 +02:00
Gabriel Somlo
435913f7d8 platforms/nexys4ddr: add option to build with spi-mode sdcard support 2020-05-24 19:09:25 -04:00
Florent Kermarrec
0d549a8c89 platforms: add forest_kitten_33 initial platform suppport. 2020-05-24 11:22:02 +02:00
Florent Kermarrec
12b54a7a7f platforms/alveo_u250: add clk300 clock constraints. 2020-05-24 11:18:30 +02:00
Florent Kermarrec
46f78b5002 nexys_video: add usb_fifo pins. 2020-05-22 14:28:55 +02:00
Florent Kermarrec
445338e2e7 platforms/nexys_video: add specific openocd cfg (use channel 1). 2020-05-22 14:12:45 +02:00
Florent Kermarrec
5aeb7d85e6 targets/acorn_cle_215: fix typo in description. 2020-05-21 10:18:06 +02:00
Florent Kermarrec
eeba64d7b2 targets: use soc.build_name in load/flash bitstream. 2020-05-21 09:12:29 +02:00
Florent Kermarrec
76551dec4c platforms/nexys_video: add sdcard pins, move clk/rst to top. 2020-05-20 13:05:18 +02:00
Florent Kermarrec
83457b8791 platforms/arty: add _sdcard_pmod_io. 2020-05-20 12:09:43 +02:00
Florent Kermarrec
8158d94ae7 targets/c10lprefkit: switch to litehyperbus. 2020-05-19 15:48:19 +02:00
Florent Kermarrec
587caf7584 paltforms/marblemini: add break_off_pmod. 2020-05-19 15:42:53 +02:00
Florent Kermarrec
c2cd863658 platforms/ecp5_evn: rename spiflash1x to spiflash, rewrite hardware/configuration description and remove make_spiflash. 
The Platform file should not contain import code related to cores, this has to be done in the target.
 2020-05-19 15:29:25 +02:00
enjoy-digital
3f0f12011b
Merge pull request #70 from ilya-epifanov/ecp5-evn-spi1x-and-flash-params 
ECP5-EVN SpiFlash parameters
 2020-05-19 15:16:25 +02:00
Florent Kermarrec
b9ee3a797a alveo_u250: re-organize the auto-generated IOs, add build/load parameters. 2020-05-16 11:47:14 +02:00
Florent Kermarrec
c0b7afc739 targets/alveo_u250: +x. 2020-05-16 11:13:01 +02:00
Florent Kermarrec
67d2a4940e tools/extract_xdc_pins: +x. 2020-05-16 11:12:46 +02:00
Florent Kermarrec
482d7a6b95 targets/pcie: use 128-bit datapath and 8 max_pending_requests on pcie_x4 configurations. 2020-05-14 15:34:00 +02:00
Florent Kermarrec
2bb7fce5e3 targets/acorn_cle_215: add minimal instructions to reproduce the results. 2020-05-13 17:55:52 +02:00
enjoy-digital
6757c4e298
Merge pull request #71 from daveshah1/alveo_u250 
[WIP] Add Alveo U250 platform and target
 2020-05-13 09:10:22 +02:00
Florent Kermarrec
c7404e356f targets/acorn_cle_215: switch to MT41K512M16 (Acorn has a 1GB DDR3 vs 512MB on NiteFury). 2020-05-09 16:39:17 +02:00
Florent Kermarrec
d05b10fd76 target/camlink_4k: add missing import. 2020-05-09 12:27:07 +02:00
Florent Kermarrec
4faa91c7f2 platforms/marblemini: review/cleanup. 
- add copyrights.
- add link to documentation.
- reindent code.
- rename some IOs (for consistency with the others platforms).
- add pullup on clk20_vcxo_en.
- set clk20_vcxo as default clock.
- remove ununnecessary eth constraints. (we are using IO primitives).
- move PMODS to connectors (for consistency with others platforms).
 2020-05-09 10:16:42 +02:00
enjoy-digital
4ffdcb5ea9
Merge pull request #75 from jersey99/marblemini 
Marblemini [https://github.com/berkeleylab/marble-mini/]
 2020-05-09 09:39:40 +02:00
Vamsi K Vytla
e4ccfcfad1 platforms/marblemini.py: Cleanup. Add openocd for programming marblemini 2020-05-08 17:20:14 -07:00
Florent Kermarrec
6f22f082ff targets: add LedChaser on platforms with user_leds. 
Default to Chaser mode and similar user interface than GPIOOut.
 2020-05-08 22:16:13 +02:00
enjoy-digital
b9a0f2363c
Merge pull request #74 from tommythorn/master 
targets/orangecrab.py: propagate command arguments
 2020-05-08 07:28:05 +02:00
Vamsi K Vytla
a7d6de78ae Merge branch 'master' into marblemini 2020-05-07 12:19:47 -07:00
Vamsi K Vytla
5f7f087cba community/platforms/marblemini.py: Added marblemini from https://github.com/berkeleylab/marble-mini/ 2020-05-07 12:17:42 -07:00
Florent Kermarrec
19b12fd984 targets/panol_logic_g2: replace with a minimal target. 2020-05-07 16:36:04 +02:00
Florent Kermarrec
99c04358bf platforms/pano_logic_g2: simplify/cleanup. 2020-05-07 16:35:34 +02:00
Florent Kermarrec
6b5492a707 pano_logic_g2: add copyrights. 2020-05-07 15:24:03 +02:00
Florent Kermarrec
6ddd859309 add pano_logic_g2 from litex-buildenv. 2020-05-07 15:22:22 +02:00
Florent Kermarrec
27c242b2ca targets/pcie: switch to PCIe X4 on all boards that support it. 2020-05-07 12:18:39 +02:00
Florent Kermarrec
f9939532b6 targets/pcie: update LitePCIe constraints. 2020-05-07 12:15:52 +02:00
Tommy Thorn
6335717eca targets/orangecrab.py: propagate command arguments 
The parsed args are stripped off by soc_core_argdict() (called from
soc_sdram_argdict() so we have to pass them explicitly (or pass the
original "args", but this mimics the rest of the code in the repo).

This fixes #72
 2020-05-06 18:24:11 -07:00
Florent Kermarrec
d34c3baf15 prog: use different openocd config files for FT232/FT2232. 2020-05-06 16:14:51 +02:00
Florent Kermarrec
117d1a1c75 prog: add colorlight_5a_75b openocd config. 2020-05-06 16:01:59 +02:00
Florent Kermarrec
e500d90bcc platforms/ecpix5: set pullups on rx_data to advertise as RGMII mode. 2020-05-06 16:00:46 +02:00
Florent Kermarrec
59e8c2cd30 acorn_cle_215: add .bin generation and --flash argument, working on hardware :). 2020-05-06 12:27:07 +02:00
Florent Kermarrec
a049fa6856 add Acorn CLE 215+ platform/target. 2020-05-06 07:53:55 +02:00
Florent Kermarrec
da61aabc5b targets: remove USDDRPHY_DEBUG and set cmd_latency to on all Kintex7/Ultrascale targets. 2020-05-05 16:32:10 +02:00
Florent Kermarrec
b58b9b9e6a platforms: fix CI. 2020-05-05 16:01:43 +02:00
Florent Kermarrec
2d9543b65e targets: add build/load parameters on all targets. 2020-05-05 15:11:47 +02:00
Florent Kermarrec
19eb5708de platforms: make sure all traditional platforms have a create_programmer method. 2020-05-05 13:34:57 +02:00
Florent Kermarrec
84468c2a63 targets/CRG: platforms are now automatically constraining the input clocks. 2020-05-05 11:51:57 +02:00
Florent Kermarrec
1f88a9d5ec platforms: make sure clocks inputs are constraints on all platforms. 
Also use new loose lookup_request to simplify constraints.
 2020-05-05 11:45:41 +02:00
Florent Kermarrec
86648ec7d8 platforms/vcu118: rename ddram_second_channel to ddram:1. 2020-05-05 09:54:11 +02:00
Florent Kermarrec
e1820c7831 platforms/ac701: indent HPC. 2020-05-05 09:49:59 +02:00
Florent Kermarrec
2129b67779 platforms: make sure all plarforms have separators. 2020-05-05 09:47:55 +02:00
Florent Kermarrec
ea0eda9f75 platforms: make sure all Xilinx/Altera platforms have a create_programmer method, use OpenOCD on Spartan6 and 7-Series. 2020-05-05 09:42:34 +02:00
Florent Kermarrec
588bbac719 add prog directory with some Xilinx OpenOCD configurations files. 2020-05-05 09:11:06 +02:00
Florent Kermarrec
78b5727774 targets: rename usb_cdc to usb_acm. 
As discussed recently on Discord.
 2020-04-30 21:48:10 +02:00
David Shah
088cceca8b Add Alveo U250 platform and target 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-29 12:31:16 +01:00
Ilya Epifanov
0ba8045789 Added spiflash1x pins, a method to create an SpiFlash instance and a note on a second UART channel of FT2232H 2020-04-28 21:56:33 +02:00
Florent Kermarrec
2213d73b89 targets/kcu105: use cmd_latency=1. 2020-04-25 12:13:49 +02:00
Florent Kermarrec
a8a42c55c9 targets/kc705: manual DDRPHY_CMD_DELAY adjustment no longer needed. 2020-04-25 11:08:05 +02:00
Florent Kermarrec
865b01ec75 ecpix5: add ethernet. 2020-04-22 20:21:59 +02:00
Florent Kermarrec
6fe4c4ea62 ecpix5: add DDR3 (working) 2020-04-22 17:03:22 +02:00
Florent Kermarrec
efb13bc118 add mininal ECPIX-5 board support (Clk/Rst/Leds/UART), BIOS working. 2020-04-22 16:31:07 +02:00
Florent Kermarrec
4154bdf034 targets/PCIe: add PCIe software reset. 2020-04-20 12:30:09 +02:00
Florent Kermarrec
4ad6042e07 platforms/de0nano: swap serial tx/rx to ease use of cheap FT232 based cables. 2020-04-18 11:36:18 +02:00
Florent Kermarrec
4185a019f5 targets: manual define of the SDRAM PHY is no longer needed. 2020-04-16 11:25:59 +02:00
Florent Kermarrec
cb95962850 targets/ulx3s and colorlight_5a_75b: cleanup USB ACM addition and only keep USB ACM changes. 
- remove update in loading/flashing: we need to thinks how to integrate this.
- remove specific README: documentation is moved to the files, link to more complete project can
be added if maintained externally, as done for the iCEBreaker for example.
- revert default freq on ULX3S to 50MHz and instantiate a second PLL as done on the colorlight.
 2020-04-14 16:14:18 +02:00
Dave Marples
f79a010a29 Addition of flash for colorlight board 2020-04-14 14:37:56 +01:00
Dave Marples
389e8aa13a Addition of USB ACM for ECP5 2020-04-14 13:53:46 +01:00
Florent Kermarrec
a12faae0fb targets/colorlight_5a_75b: increase sys_ps phase (fixes memtest). 2020-04-14 11:24:16 +02:00
Florent Kermarrec
52c9648176 arty_s7: fix copyrights, rename to arty_s7, various minor changes to make it similar to others targets. 2020-04-13 15:20:36 +02:00
Staf Verhaegen
bbb1ded9f8 Added Arty S7 board 
As the pin-out is totally different from the A7 board I did put this
in a separate class and not as a variant of the Arty board.
Used migen Arty S7 board file and Digilent xdc file as reference.
 2020-04-12 21:48:25 +02:00
Florent Kermarrec
188d4a45d6 targets: use DDROutput on sdram_clock and similar configuration for all SDRAM targets. 2020-04-10 14:43:04 +02:00
Florent Kermarrec
ca197af2be targets/simple: use CRG from litex.build. 2020-04-10 10:26:19 +02:00
Florent Kermarrec
b8a648d499 litex.build: update from migen.genlib.io litex.build.io. 2020-04-10 09:23:33 +02:00
Florent Kermarrec
4d7135f167 platforms/versa_ecp5: remove LatticeProgrammer (no longer used since we can now use OpenOCD). 2020-04-09 23:06:57 +02:00
Florent Kermarrec
2cf3c3e845 platforms: cosmetic cleanups. 2020-04-09 23:05:13 +02:00
Florent Kermarrec
df5de8816d platforms/ulx3s: cleanup, fix user_leds, add PULLMODE/DRIVE constraints on SDRAM. 2020-04-09 18:53:06 +02:00
Florent Kermarrec
467b14a0ad colorlight_5a_75b: minor comment changes. 2020-04-09 08:14:17 +02:00
David Sawatzke
15a27d40fa targets/colorlight_5a_75b: Change baudrate to work on v6.1 
There seems to be some capacitance on KEY+, so the usual 115200 don't work
 2020-04-09 05:08:23 +02:00
David Sawatzke
4fc9df8414 colorlight_5a_75b/v6.1: Add eth_clock & serial pins 2020-04-09 05:06:08 +02:00
David Sawatzke
4ddde31429 colorlight_5a_75b/v6.1: Fix bank activate pin 2020-04-09 05:05:29 +02:00
enjoy-digital
9b3f16af1e
Merge pull request #62 from ilya-epifanov/ecp5-evn-button1-and-spi-flash-ios 
ECP5-EVN board: Added BUTTON_1 and SPI flash pins to IOs
 2020-04-08 09:00:12 +02:00
Florent Kermarrec
db67dff0ea targets/de10lite: use Max10PLL, remove 50MHz limitation. 2020-04-08 08:55:30 +02:00
Florent Kermarrec
8ccab03358 targets/c10lprefkit: use Cyclone10LPPLL, remove 50MHz limitation. 2020-04-08 08:34:59 +02:00
Florent Kermarrec
4cdc121327 targets/de10nano: use CycloneVPLL, remove 50MHz limitation. 2020-04-08 08:11:04 +02:00
Florent Kermarrec
2d8a4ef9ec targets/de1_soc: use CycloneVPLL, remove 50MHz limitation. 2020-04-08 08:07:37 +02:00
Florent Kermarrec
cec4cbb6dc targets/de2_115: use CycloneIVPLL, remove 50MHz limitation. 2020-04-08 08:03:41 +02:00
Florent Kermarrec
1fac6077fb targets/de0nano: use CycloneIVPLL, remove 50MHz limitation. 2020-04-07 17:01:58 +02:00
Florent Kermarrec
5f629c203b targets/vcu118: fix clk500 typo. 2020-04-07 13:53:22 +02:00
Florent Kermarrec
a7fbe0a724 colorlight_5a_75b: add SoC with regular UART (on J19). 2020-04-03 10:28:53 +02:00
Florent Kermarrec
19e5366ad1 targets/colorlight_5a_75b: update sys/sys_ps phases. 2020-03-31 18:18:45 +02:00
Florent Kermarrec
9ae8a0cc11 colorlight_5a_75b/v7.0: add spiflash pins. 2020-03-31 16:18:12 +02:00
Ilya Epifanov
a43072ac40 ECP5-EVN board: Added BUTTON_1 and SPI flash pins to IOs 2020-03-28 13:08:46 +01:00
enjoy-digital
ccfc021c1a
Merge pull request #61 from ilya-epifanov/ecp5-evn-programming 
programming the ECP5-EVN flash through the OpenOCD JTAG-SPI proxy
 2020-03-28 12:59:19 +01:00
Ilya Epifanov
8afc9a5b03 programming the ECP5-EVN flash through the OpenOCD JTAG-SPI proxy 2020-03-28 11:27:34 +01:00
Florent Kermarrec
89dd00d3a2 platforms/aller: rename pcie to pcie_x4 (for consistency with others platforms). 2020-03-27 13:01:36 +01:00
Piotr Binkowski
d2edf54ab3 zcu104: add fully working SO-DIMM config 2020-03-26 16:37:11 +01:00
Florent Kermarrec
3b91e96c42 targets/add_constant: avoid specifying value when value is None (=default) 2020-03-26 09:47:22 +01:00
Florent Kermarrec
555bf6c4dc targets/Ultrascale(+): enable USDDRPHY_DEBUG. 2020-03-26 09:17:09 +01:00
Florent Kermarrec
4053c02d7e targets/orangecrab: add USB PLL for USB CDC with ValentyUSB. 2020-03-25 19:38:36 +01:00
Florent Kermarrec
85f38876c2 targets: update PCIe on Numato targets. 
Should be compatible with software from: https://github.com/enjoy-digital/netv2.
 2020-03-25 11:53:52 +01:00
Florent Kermarrec
6e6b6dac55 platforms/orangecrab: add spisdcard pins. 2020-03-25 10:21:57 +01:00
Florent Kermarrec
87fd4dc059 platforms/minispartan6: add spisdcard pins. 2020-03-25 09:53:04 +01:00
Florent Kermarrec
24033e331c targets: update SDRAM to use new GENSDRPHY and new ECP5PLL phase support. 2020-03-24 19:59:42 +01:00
Florent Kermarrec
92f793f9c5 platforms: remove versa_ecp3 (ECP3 no longer supported). 2020-03-24 19:58:12 +01:00
Greg Davill
eb35ec92ba orangecrab: combine revisions in target 2020-03-23 09:20:01 +10:30
Greg Davill
159360da2c orangecrab: Add r0.2 support 2020-03-22 21:04:07 +10:30
Greg Davill
bf3c9dc9bf orangecrab: Add sdram selection option 2020-03-22 20:41:12 +10:30
Greg Davill
88d3f1d63e orangecrab: r0.1 OrangeCrab fixes 2020-03-22 20:14:29 +10:30
Florent Kermarrec
78224b1e56 targets/colorlight_5a_75b: add SDRAM. 2020-03-21 22:11:47 +01:00
Florent Kermarrec
a95a4eed3f targets/colorlight_5a_75b: switch to add_ethernet/add_etherbone methods. 2020-03-21 21:50:05 +01:00
Florent Kermarrec
7bba5caab0 targets/c10prefkit: remove keep attributes (no longer needed, added automatically). 2020-03-21 21:44:44 +01:00
Florent Kermarrec
6c31933e89 targets: switch to add_etherbone method. 2020-03-21 21:40:45 +01:00
Florent Kermarrec
159386e3d3 targets: always use sys_clk_freq on SDRAM modules. 2020-03-21 20:00:56 +01:00
Florent Kermarrec
3fb3ba18e8 targets: switch to add_ethernet method instead of EthernetSoC. 2020-03-21 18:29:52 +01:00
Florent Kermarrec
83e6fb29f8 targets: switch to SoCCore/add_sdram instead of SoCSDRAM. 2020-03-21 12:43:39 +01:00
enjoy-digital
33bf1d3ee2
Merge pull request #58 from gsomlo/gls-trellisboard-spisdcard 
Move trellisboard target to SoCCore, add SPI-mode SDCard support
 2020-03-20 19:07:00 +01:00
Florent Kermarrec
fb1cab857a targets/arty: use new ISERDESE2 MEMORY mode. 2020-03-20 18:59:17 +01:00
Gabriel Somlo
f021c1de5f targets/trellisboard: add '--with-spi-sdcard' build option 
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-03-20 07:14:13 -04:00
Gabriel Somlo
69a78c8c66 targets/trellisboard: switch to SoCCore, use add_ethernet() method 
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-03-19 18:09:37 -04:00
Gabriel Somlo
396b0383c8 platforms/trellisboard: fix "sdcard" pads, add "spisdcard" pads 
Add support for SPI-mode SDCard interface. Also, add pull-up and
slew constraints to the standard sdcard interface.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-03-19 18:09:37 -04:00
Florent Kermarrec
d0d047dfa4 platforms/ulx3s: add spisdcard pins. 2020-03-19 15:14:05 +01:00
Florent Kermarrec
6ab13a0661 de10nano/MiSTer: rename SPI SD CARD pins to spisdcard and remove SPI SD Card integration from target. 2020-03-19 11:09:48 +01:00
enjoy-digital
db9d5489ec
Merge pull request #56 from rob-ng15/master 
de10nano add in support for MiSTer secondary sd card
 2020-03-19 11:07:40 +01:00
Florent Kermarrec
57bcadb5b4 platforms/nexys4ddr: add spisdcard pins. 2020-03-19 11:04:11 +01:00
Florent Kermarrec
f3d7f5880f platforms/kcu105: fix pcie tx0 p/n swap. 2020-03-18 19:09:52 +01:00
rob-ng15
bc6ef0bc48
Allow access to secondary sd card via hardware spi bitbanging 2020-03-18 12:13:37 +00:00
rob-ng15
a6f80694cb
Add in support for secondary sd card via spi hardware bitbanging 2020-03-18 12:11:57 +00:00
Florent Kermarrec
a99d258411 targets/icebreaker: use simplified version closer to the others targets. 
Add description of the board, link to the crowdsupply campaign and to the more complete example.
 2020-03-13 09:43:43 +01:00
Florent Kermarrec
74a5ffb9ef targets/Ultrascale+: use 500MHz IDELAYCTRL reference clock. 
The minimum is 300MHz on Ultrascale+ vs 200MHz on Ultrascale.
 2020-03-10 16:58:30 +01:00
Florent Kermarrec
e2a66090ee targets/Ultrascale(+): simplify CRG using USIDELAYCTRL. 2020-03-10 16:55:22 +01:00
Florent Kermarrec
cf58550bba targets/Ultrascale+: use USPDDRPHY. 2020-03-10 16:06:48 +01:00
enjoy-digital
ce922613a7
Merge pull request #55 from antmicro/jboc/mercury-xu5 
platforms/mercury_xu5: fix sdram timing issues
 2020-03-10 15:30:12 +01:00
Jędrzej Boczar
90de99eb46 platforms/mercury_xu5: fix sdram timing issues 2020-03-10 15:03:31 +01:00
Florent Kermarrec
75286f8a9b platforms/zcu104: add missing INTERNAL_VREF on bank 64 (DQ0-31) 2020-03-10 14:57:39 +01:00
Florent Kermarrec
95e1a05bf1 platforms/Ultrascale: avoid unnecessary {{}} on INTERNAL_VREF. 2020-03-09 09:29:49 +01:00
Florent Kermarrec
3f191c8561 mercury_xu5: set INTERNAL_VREF to 0.84. (similar to others Ultrascale boards with DDR4). 2020-03-09 09:28:25 +01:00
Florent Kermarrec
f4ae21a7a2 zcu104: fix copyrights. 2020-03-09 09:24:06 +01:00
Florent Kermarrec
5031c11d57 mercury_xu5: add missing copyrights. 2020-03-09 09:23:08 +01:00
Florent Kermarrec
8c535d15f2 platforms/mercury_xu5: replace ' with ". 2020-03-09 09:21:27 +01:00
enjoy-digital
dc1371108d
Merge pull request #52 from antmicro/jboc/mercury-xu5 
add Enclustra Mercury XU5 board
 2020-03-09 09:11:15 +01:00
Florent Kermarrec
2b1b9684de targets/icebreaker: simplify CRG, just use a 12MHz sys_clk and por_clk for reset. 2020-03-07 18:25:26 +01:00
Florent Kermarrec
9416ddd84a targets/icebreaker: simplify arguments and make it closer to others targets. 2020-03-07 18:13:02 +01:00
Florent Kermarrec
992f7066fa targets/icebreaker: simplify leds. 2020-03-07 18:12:59 +01:00
Florent Kermarrec
682316214c targets/icebreaker: use specific method to set Yosys/Nextpnr settings. Rename argument to nextpnr-xxyy. 2020-03-07 18:12:52 +01:00
Florent Kermarrec
f777d4b08c targets/icebreaker: +x 2020-03-05 23:11:35 +01:00
Florent Kermarrec
6f517ad1d6 targets/ecp5: make sure all BaseSoC/EthernetSoc default to trellis. 2020-03-05 10:57:59 +01:00
Jędrzej Boczar
d002059e0b add Enclustra Mercury XU5 board 2020-03-05 10:52:32 +01:00
Piotr Esden-Tempski
745c99ba14 icebreaker: Updated to build on newer litex. Disabled bios building. 2020-03-05 00:12:18 -08:00
Piotr Esden-Tempski
3ac9d927a9 targets: icebreaker: Minor style fixes. 2020-03-05 00:12:18 -08:00
Sean Cross
738967176c targets: icebreaker: set the boot address to point to SPI flash 
Signed-off-by: Sean Cross <sean@xobs.io>
 2020-03-05 00:12:18 -08:00
Sean Cross
093e4913c4 targets: icebreaker: hack to get boot working 
Signed-off-by: Sean Cross <sean@xobs.io>
 2020-03-05 00:12:18 -08:00
Sean Cross
77b780eb4b targets: icebreaker: switch to single SPI 
The Icebreaker doesn't have the QE/ bit set in config, so default to
using single SPI.

Signed-off-by: Sean Cross <sean@xobs.io>
 2020-03-05 00:12:18 -08:00
Sean Cross
e6dcdc31ed targets: icebreaker: fix cpu and add spi flash 
Signed-off-by: Sean Cross <sean@xobs.io>
 2020-03-05 00:12:18 -08:00
Sean Cross
0185095782 targets: icebreaker: fix argument parsing for cpu 
Signed-off-by: Sean Cross <sean@xobs.io>
 2020-03-05 00:12:18 -08:00
Sean Cross
f0dd31f6c8 target: targets: add crg and begin getting it working 
Signed-off-by: Sean Cross <sean@xobs.io>
 2020-03-05 00:12:18 -08:00
Piotr Esden-Tempski
ce9b67e2ee Added icebreaker platform and target. 
Target is heavily based on Fomu.
 2020-03-05 00:12:18 -08:00
Tom Keddie
7b4ca20ff4 platforms.colorlight_5a_75b: add J1-J8 connectors 2020-02-28 06:09:44 -08:00
Florent Kermarrec
be5ed35871 targets: default to trellis toolchain on all ECP5 targets (now able to build all supported targets). 2020-02-28 09:46:54 +01:00
Florent Kermarrec
b44885d222 vc707: fix copyrights (Michael Betz is the initial author) 2020-02-28 08:39:52 +01:00
Florent Kermarrec
b89af28a05 targets/kc705: use DDRPHY_CMD_DELAY to center write leveling. 2020-02-27 12:58:52 +01:00
Florent Kermarrec
aaa10c69eb platforms/colorlight_5a_75b: add default_clk_name/period 2020-02-27 11:16:49 +01:00
Florent Kermarrec
d8de4fbdfb platforms/targets: keep in sync with LiteX 2020-02-27 11:06:53 +01:00
Florent Kermarrec
18f65a7f9d platforms/kc705: cleanup ddram. 2020-02-27 11:06:35 +01:00
Florent Kermarrec
d4460c11a5 platforms/kcu105/vcu118: remove PRE_EMPHASIS/EQUALIZATION on dm. 2020-02-27 10:43:41 +01:00
Florent Kermarrec
58f588f69e platforms/zcu104/ddram: add PRE_EMPHASIS/EQUALIZATION settings 2020-02-27 10:43:01 +01:00
Florent Kermarrec
d87b8b3c66 zcu104: add separate ddram_32/64 definitions and use ddram_32 for now. 
Ease switching between ddram_32 and ddram_64.
 2020-02-27 10:05:17 +01:00
Florent Kermarrec
8ecfb13f3c zcu104: add copyrights 2020-02-27 09:57:26 +01:00
enjoy-digital
22b0449509
Merge pull request #47 from antmicro/zcu104 
Add support for ZCU104 board
 2020-02-27 09:51:54 +01:00
Piotr Binkowski
608541d5b8 add ZCU104 board 2020-02-26 13:53:21 +01:00
Florent Kermarrec
e516ff3452 vcu118/ddram: use similar IO settings than Xilinx's MIG, comment unused pins. 2020-02-26 10:16:51 +01:00
Florent Kermarrec
9d2ca50c5f kcu105/ddram: use similar IO settings than Xilinx's MIG, comment unused pins. 2020-02-26 10:16:35 +01:00
Florent Kermarrec
83d2c71099 platforms/vcu118: add missing Internal Vref configuration on DDR4 C1/C2 banks 2020-02-25 18:32:42 +01:00
Florent Kermarrec
4a84e9b08a targets/colorlight_5a_75b: add instruction to build/load and use bitstream with wishbone-tool 2020-02-25 12:47:08 +01:00
Florent Kermarrec
f279fe9d33 vc707: cleanup platform/targets, remove Ethernet support (no Ethernet pads defined) 2020-02-25 10:35:18 +01:00
Florent Kermarrec
3581df5af6 vc707: cleanup platform/targets, remove Ethernet support (SGMII is not currently supported) 2020-02-25 09:41:53 +01:00
Florent Kermarrec
88a1f80db1 vc707/vcu118: use proper copyrights 2020-02-25 09:03:52 +01:00
Fei Gao
373e74f435 add new board files for VC707 and VCU118, only specified limited ports for VCU118, including clock, reset and DDR4 2020-02-24 14:20:47 -05:00
Gwenhael Goavec-Merou
2cf4e084ec platforms/colorlight_5a_75b.py: fix sdram_clock and sdram a pins 2020-02-23 10:01:41 +01:00
Sean Cross
f72e7bd314
Merge pull request #41 from lromor/fix-wrong-import 
Changed wrong imports for fomu board.
 2020-02-12 18:48:13 +07:00
Leonardo Romor
ec30cc05c3
Changed wrong imports for fomu board. 2020-02-12 12:40:07 +01:00
Florent Kermarrec
c94360c2e0 targets: avoid direct use of mem_decoder. 2020-02-11 21:59:42 +01:00
Florent Kermarrec
4edf196911 targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC) 2020-02-11 17:45:35 +01:00
Florent Kermarrec
8211aca2e8 Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets. 
We initially wanted to provide different level of support for the platforms/targets, mainly
to avoid too much maintenance and let each contributor update its contributed platforms and
targets, but it's easier to update all platforms/targets all-together when LiteX evolves or
changes (and that's what has been done on litex-boards since the creation of the repository).
So let just simplify things and avoid this differentiation.
 2020-02-03 09:36:30 +01:00
Sean Cross
7a24406b2e targets: fomu: fix compatibility for when a cpu is added 
Things weren't quite right for adding a CPU.  This fixes that by
correcting the placer arguments, memory map, and USB type.

Signed-off-by: Sean Cross <sean@xobs.io>
 2020-02-03 08:58:54 +08:00
Florent Kermarrec
0627f55dca de10nano: cleanup a bit, rename SDRAMSoC to MiSTerSDRAMSoC and argument to --with-mister-sdram to make it clear that it's using the MiSTer SDRAM extension board. 2020-01-31 09:29:02 +01:00
Florent Kermarrec
cf9a9ff91b de10nano: update copyrights, remove trailing whitespaces 2020-01-31 09:13:36 +01:00
Paul Sajna
36e1f1fe75 rename sw to user_sw 2020-01-30 05:01:46 -08:00
Paul Sajna
1631b071c3 finish up sdram, passes memtest 2020-01-30 03:41:44 -08:00
Paul Sajna
5091a1b40a WIP sdram module option 2020-01-29 13:59:57 -08:00
Paul Sajna
3a6a9258ce add de10 nano board 
add iostandard to hdmi
 2020-01-29 00:21:51 -08:00
Florent Kermarrec
2ec6bc0bdc colorlight_5a_75b: add disclaimer 2020-01-23 14:13:13 +01:00
Florent Kermarrec
55c0b781e4 colorlight_5a_75b: revert rx_delay to 2ns, improve comment (thanks @tnt) 2020-01-23 13:16:36 +01:00
Florent Kermarrec
4fb89fc9c5 colorlight_5a_75b: set RGMII tx/rx_delay to 0ns in the FPGA (added by PCB/PHY) 2020-01-23 09:39:48 +01:00
Florent Kermarrec
dcc65b347d targets/colorlight_5a_75b: switch to SoCCore, CPU and Etherbone working :) 
Tested with:
./colorlight_5a_75b.py --cpu-type=picorv32 --uart-name=crossover --with-etherbone --csr-csv=csr.csv

Load with following script:
#!/usr/bin/env python3

# Load ---------------------------------------------------------------------------------------------

def load():
    import os
    f = open("openocd.cfg", "w")
    f.write(
"""
interface ftdi
ftdi_vid_pid 0x0403 0x6011
ftdi_channel 0
ftdi_layout_init 0x0098 0x008b
reset_config none
adapter_khz 25000
jtag newtap ecp5 tap -irlen 8 -expected-id 0x41111043
""")
    f.close()
    os.system("openocd -f openocd.cfg -c \"transport select jtag; init; svf soc_etherbonesoc_colorlight_5a_75b/gateware/top.svf; exit\"")
    exit()

if __name__ == "__main__":
    load()


Then start lxserver:
lxserver --udp

And run following script:

#!/usr/bin/env python3

import sys

from litex import RemoteClient

wb = RemoteClient()
wb.open()

# # #

while True:
    if wb.regs.uart_xover_rxempty.read() == 0:
        print(chr(wb.regs.uart_xover_rxtx.read()), end="")
        sys.stdout.flush()

# # #

wb.close()
 2020-01-22 15:57:52 +01:00
Florent Kermarrec
c07e4a6b3a colorlight_5a_75b: fix rst_n 2020-01-22 14:57:48 +01:00
Florent Kermarrec
8da8ed7a0e colorlight_5a_75b/v7.0: update eth_clocks/rx pinout, remove FIXME 2020-01-22 14:56:17 +01:00
Florent Kermarrec
bb805999cb platforms/colorlight_5a_75b: fix 6.1 used_led_n/user_btn_n thanks @smunaut 2020-01-22 12:43:37 +01:00
Florent Kermarrec
43badd162e colorlight_5a_75b/v6.1: add led/btn and remove FIXME on sdram now that clarified 2020-01-22 11:05:08 +01:00
Florent Kermarrec
1d9e349093 partner: add colorlight_5a_75b initial support 2020-01-22 09:51:00 +01:00
Florent Kermarrec
07067301d5 targets/linsn_rv901t: cleanup arguments 2020-01-22 09:04:28 +01:00
Florent Kermarrec
8113b491db aller/nereid/tagus: update litepcie 2020-01-21 21:26:23 +01:00
Florent Kermarrec
684c1640bb add Linsn RV901T support 2020-01-18 21:40:04 +01:00
Florent Kermarrec
0e4569a48a platforms/camlink_4k: remove #!/usr/bin/env python3 2020-01-18 21:35:18 +01:00
Florent Kermarrec
e72cd1468c platforms/ac701: fix eth indent 2020-01-18 21:34:50 +01:00
Florent Kermarrec
908539d49f targets/nexys4ddr: fix typo 2020-01-17 13:15:22 +01:00
Florent Kermarrec
bb99a8dd0c targets/kcu105: remove main_ram_size_limit 2020-01-17 12:09:53 +01:00
Florent Kermarrec
eca9bf10ae mimas_v7: cleanup, make it similar to others boards 2020-01-16 11:24:09 +01:00
Florent Kermarrec
54f39b600a mimas_a7: fix copyrights 2020-01-16 11:02:11 +01:00
enjoy-digital
8d298951a8
Merge pull request #37 from feliks-montez/master 
Add Mimas A7 board support
 2020-01-16 11:00:32 +01:00
Florent Kermarrec
f9619c4a8f aller/tagus/nereid: use crossover UART, rename SoC to PCIe SoC and pass soc_sdram_argdict to PCIeSoC 2020-01-16 10:51:35 +01:00
Florent Kermarrec
fd1e655700 targets: cleanup EthernetSoC 2020-01-16 10:28:09 +01:00
Feliks
206ec34551 platforms/mimas_a7: add support 2020-01-14 23:31:03 -05:00
Feliks
9f1c3305b6 targets/mimas_a7: add support 2020-01-14 23:30:49 -05:00
Florent Kermarrec
50d550c911 kx2: cleanup, fix copyright 2020-01-13 17:22:33 +01:00
enjoy-digital
3811b58f32
Merge pull request #36 from Marrkson/master 
ADD: KX2 and DDR3 support
 2020-01-13 17:07:16 +01:00
Florent Kermarrec
c109b36fb9 travis: update/fix 2020-01-13 17:00:01 +01:00
Florent Kermarrec
028d4a78aa targets: use default integrated rom/ram size passed with **kwargs from default soc_core_args 2020-01-13 15:20:37 +01:00
Mark
13e5ca03a5 ADD: KX2 and DDR3 support 2020-01-13 14:21:54 +01:00
Florent Kermarrec
beccf670e5 hadbadge: fix _CRG 2020-01-11 10:46:23 +01:00
Florent Kermarrec
15f3457aea platforms/de0nano/serial: add gpio names in comment 2020-01-10 18:53:52 +01:00
Florent Kermarrec
94ba343daf targets/ac701: cpu_reset is active high 2020-01-10 18:53:14 +01:00
Florent Kermarrec
ab01f70e5c platforms/ac701: set internal vref to 0.750v on DDR3 banks, use IN_TERM=UNTUNED_SPLIT_50 on dq 2020-01-09 21:56:01 +01:00
Florent Kermarrec
7afe3dc674 platforms/targets: sync with litex 2020-01-09 21:10:59 +01:00
Florent Kermarrec
4192b20f09 targets: cleanup Altera CRGs 2020-01-09 19:46:39 +01:00
Florent Kermarrec
9e9fc5ef78 platforms: always use 1e9/clk_freq for default_clk_period 2020-01-09 19:28:50 +01:00
enjoy-digital
fe23881348
Merge pull request #33 from msloniewski/master 
targets/de10lite: use external clock for sys directly
 2020-01-09 19:23:55 +01:00
Marcin Sloniewski
aaf8d54c6a targets/de10lite: use AsyncResetSynchronizer for clock domains 
At the start output of the pll is not stabilized, which
caused malfunctions when used for sys clock domain.
Use AsyncResetSynchronizer to start clock domains
on pll locked signal.
 2020-01-09 18:47:13 +01:00
Gabriel Somlo
d08dfdb808 platforms/nexys4ddr: add sdcard pins (sync w. litex commit #e99740e8) 2020-01-09 09:25:19 -05:00
Florent Kermarrec
babbc676eb targets: cleanup ECP5 CRGs 2020-01-09 14:24:18 +01:00
Florent Kermarrec
82601ff700 hadbadge: remove speed_grade workaround, now passed to trellis from device. 2020-01-08 19:44:35 +01:00
Florent Kermarrec
1f300bb03e add initial camlink_4k support 2020-01-08 09:56:37 +01:00
Florent Kermarrec
c0e4578bea targets/hadbadge: cleanup/simplify (keep things similar to ulx3s) and add copyrights 2020-01-07 10:29:58 +01:00
Florent Kermarrec
85c4f76eba platform/hadbadge: cleanup/simplify and add copyrights 2020-01-07 10:29:01 +01:00
enjoy-digital
829898d652
Merge pull request #31 from pdp7/master 
add the Hackaday Supercon ECP5 badge
 2020-01-07 09:48:15 +01:00
Arnaud Durand
ab41cf5b79
Update ecp5_evn.py 2020-01-07 01:55:59 +01:00
Drew Fustini
b3f175c064 add the Hackaday Supercon ECP5 badge 
Add the Hackaday Supercon 2019 badge which has an ECP5 FPGA:
https://hackaday.io/project/167255-2019-hackaday-superconference-badge

These changes are from Michael Welling's fork:
https://github.com/mwelling/linux-on-litex-vexriscv

During Supercon, we trying two approaches:
- use the built-in 16MB QSPI SRAM
- use add-on cartiridge with 32MB SDRAM by Jacob Creedon

We were not able to get the QSPI SRAM working so I've removed
those changes, and I have just added the changes that are needed
to boot Linux with the 32MB SDRAM.

Thanks to Jacob Creedon, Greg Davill and Tim Ansell who helped debug.

KiCad design files for the SDRAM cartridge are available at:
https://github.com/jcreedon/dram-cart/

The SDRAM cartridge PCB is shared at:
https://oshpark.com/shared_projects/IQSl2lid

More information in this blog post:
https://blog.oshpark.com/2019/12/20/

The Hackaday Supercon badge PCB design is here:
https://github.com/Spritetm/hadbadge2019_pcb
 2020-01-06 16:59:15 +01:00
Tim Ansell
f8f2301a3e
Merge pull request #30 from mithro/fomu-update 
Updating the templates for Fomu.
 2020-01-03 08:40:18 +00:00
Tim 'mithro' Ansell
250706b98c Updating the templates for Fomu. 2020-01-02 13:55:09 +00:00
Florent Kermarrec
2b43a18a3c platforms/pipistrello: cleanup, remove extra stuff specific to litex-buildenv 2019-12-31 18:18:56 +01:00
Florent Kermarrec
c96e7c8fb9 platforms/pipistrello: cleanup, remove extra stuff specific to litex-buildenv 2019-12-31 18:07:18 +01:00
Florent Kermarrec
2259042383 pipistrello: add copyrights 2019-12-31 17:44:24 +01:00
enjoy-digital
6324433e1c
Merge pull request #28 from zakgi/master 
Adding initial support for Saanlima's Pipistrello LX45 board
 2019-12-31 17:33:25 +01:00
Florent Kermarrec
980b0ebda0 targets/de10lite: rename VideoSoC to VGASoC (to avoid confusion with VideoSoC as used on Video designs with framebuffer) 2019-12-31 17:30:23 +01:00
Florent Kermarrec
10e5248bda targets/de10lite: minor cleanup on import/_CRG 2019-12-31 17:26:09 +01:00
msloniewski
9c5a4f757f targets/de10lite: add VideoSoC with VGA peripheral 
Add VideoSoC build option, based on Frank Buss example.
 2019-12-30 23:25:43 +01:00
msloniewski
cace17e162 targets/de10lite: refactor setting up clock domains 
Use PLL to generate clock for both sys clock domain and clock domain
for sdram. Additionally set up clock domain for VGA periph.
 2019-12-30 23:25:43 +01:00
msloniewski
9ed68d129f platforms/de10lite: add additional configuration 
Use single image with memory initialization
to make more space for SoC ROM sector.
 2019-12-30 23:23:44 +01:00
msloniewski
28753a2c04 platforms/de10lite: remove UART pins from GPIO resource 
V10 and W10 pins were used in UART periph, causing error
when gpio_0 were requested.
 2019-12-30 23:06:58 +01:00
Tim 'mithro' Ansell
359918c2a2 Comment out template overrides for now. 2019-12-30 19:23:05 +01:00
Florent Kermarrec
1f32dcf662 partner: rename orange_crab to orangecrab 2019-12-30 12:07:34 +01:00
Florent Kermarrec
8965b01347 partner/orange_crab: cleanup, make it similar to others targets and only keep BaseSoC 2019-12-30 11:54:53 +01:00
Greg Davill
e77afaaef0 partner: add OrangeCrab support (https://github.com/gregdavill/OrangeCrab) 2019-12-30 11:54:45 +01:00
Giammarco Zacheo
39e428581f Adding initial support for Saanlima's Pipistrello LX45 board 2019-12-29 18:29:11 -08:00
Florent Kermarrec
48476be9e2 aller/nereid/tagus: LitePCIeWishboneBridge's shadow_base replace with base_address 2019-12-14 22:10:04 +01:00
Florent Kermarrec
7184032555 aller/neired/tagus: fix gateware/software build directory 2019-12-14 11:29:15 +01:00
Derek Kozel
4334ba9527 partner/aller, nereid, tagus: Remove deprecated param 
get_csr_header parameter with_shadow_base
removed/deprecated in litex 2a8d8c8f. New default
behavior matches the desired behavior in these targets.
 2019-12-14 01:04:28 +00:00
Derek Kozel
3012cf75fe partner/aller, nereid, tagus: Use updated csr APIs 
litex commit 8be5824e258b84df240d34636aaa539124b92c65 simplified the handling
of csr regions and constants.
 2019-12-14 01:00:52 +00:00
Florent Kermarrec
d91458c3e6 targets/versa_ecp5: fix compilation with diamond 2019-12-06 16:16:19 +01:00
Florent Kermarrec
30ea463b41 targets: keep attributes are no longer needed since automatically added when applying constraints to signals. 2019-12-06 16:01:59 +01:00
Florent Kermarrec
8fa3f09226 partner/c10prefkit: apply ethernet constraints on nets as done on Xilinx devices. 2019-12-06 15:22:40 +01:00
Florent Kermarrec
0a56d86b1a partner/c10lprefkit: remove FAMILY platform_command (not needed) 2019-12-06 15:21:48 +01:00
Florent Kermarrec
5193f7155a partner/aller,nereid & tagus: fix compilation 2019-12-03 09:37:18 +01:00
Florent Kermarrec
f7fbfb4639 partner/community/targets: uniformize, improve presentation 2019-12-03 09:33:08 +01:00
Florent Kermarrec
1b1370d086 official/targets: uniformize, improve presentation 2019-12-03 09:07:09 +01:00
Sean Cross
4e13b7fdab targets: fomu: move SoCCore import definition 
The SoCCore definition used to be available under litex.soc.integration,
however it was removed in
626533ce9d

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-11-25 12:46:21 +08:00
Sean Cross
0da263fa75 platforms: fomu: add spiflash4x definition 
Fomu Hacker supports dual spi, so add a "spiflash4x" definition.
The litex spi_flash module will run this flash in dual mode, because the
`dq` array is only two signals wide.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-11-24 21:56:57 +08:00
Sean Cross
45b847b466 fomu: add documentation to crg 
This documentation can be fetched using a package such as lxsocdoc.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-11-23 12:55:26 +08:00
Sean Cross
2c82e02df9 fomu: pvt: swap miso and mosi 
These pins were swapped in the definition, which made them not work so
well.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-11-22 18:57:26 +08:00
Florent Kermarrec
4231d59901 platforms/target: only catch ModuleNotFoundError exceptions to improve error reporting (thanks mwelling) 2019-11-16 09:40:30 +01:00
Florent Kermarrec
2a0fbcadd2 ac701: add pcie_x1 pins 2019-11-06 09:29:55 +01:00
Florent Kermarrec
5bd8c4d74f targets/trellisboard: use ECLKBRIDGECS to allow ECLK to reach all DDR banks (fixes Diamond build) 2019-11-01 10:52:56 +01:00
Florent Kermarrec
1ae26dd499 targets: use type="io" instead of io_region=True 2019-10-30 16:35:32 +01:00
Gabriel Somlo
8878c0a84a versa_ecp5, trellisboard: add trellis toolchain specific arguments 
Sync up with Litex commit #49372852d.
 2019-10-29 12:32:41 -04:00
Gabriel Somlo
5f80633154 targets: increase integrated ROM size if EthernetSoC used 
Sync up with litex commit #201218b2c.
 2019-10-29 12:32:41 -04:00
Gabriel Somlo
c83e10d9f3 official/platforms/versa_ecp5: add serdes refclk/sma 
Sync up with litex commit #ae9c25b74.
 2019-10-29 12:32:41 -04:00
Florent Kermarrec
91083f99a8 ulx3s: simplify SDRAM module selection 2019-10-13 21:15:22 +02:00
enjoy-digital
6f3b194bd3
Merge pull request #20 from lolsborn/ulx3s-target 
memory device selection for ulx3s
 2019-10-13 20:59:16 +02:00
Steven Osborn
abf6f7b09a memory device selection for ulx3s 2019-10-13 09:27:33 -07:00
enjoy-digital
53d5ed1226
Merge pull request #19 from lolsborn/ulx3s-target 
add sys clock freq flag, uses same method as current versa code
 2019-10-13 10:32:43 +02:00
Steven Osborn
34507eb431 add sys clock freq flag, uses same method as current versa code 2019-10-13 00:44:07 -07:00
Sean Cross
92cfd629df partners: fomu-evt: add "dbg" connector 
This connector is for the six "debug" pins on the Raspberry Pi header.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-10-11 21:39:19 +08:00
Sean Cross
09a55d20c1 partners: fomu-evt: fix spiflash4x pin mapping 
The D3 and D4 pins were swapped around, leading to interesting issues.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-10-11 21:38:50 +08:00
Florent Kermarrec
785909ac5f targets: switch from shadow_base to io_regions 2019-10-09 11:09:59 +02:00
Sean Cross
19e2a12266
Merge pull request #18 from xobs/fomu-cpu-updates 
Fomu cpu updates
 2019-09-27 16:55:27 +08:00
Sean Cross
c20c489d66 fomu-evt: add i2c pins 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-09-27 11:26:23 +08:00
Florent Kermarrec
48cd1208df targets: sync with litex targets 2019-09-25 14:09:25 +02:00
Florent Kermarrec
0ead12bae8 targets/ulx3s: revert to cl=2 2019-09-25 13:58:45 +02:00
Sean Cross
c8e8f254ca targets: fomu: add USBSoC and default to heap placer 
The heap placer is important enough that we should just make it the
default.

Also, add a `USBSoC` that includes the required interrupt table, as this
must be specified prior to calling `__init__()`.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-09-17 17:08:05 +08:00
Sean Cross
218bd353c1 targets: fomu: use memory array for sram address 
Use the memory array to find the address for the sram bank.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-09-17 17:07:26 +08:00
Sean Cross
348677598d targets: fomu: support building with a cpu 
Allow the user to specify a CPU.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-09-17 17:06:23 +08:00
Florent Kermarrec
e94c6c8f27 partner/netv2: switch to MVP (K4B2G1646F instead of MT41J128M16) 2019-09-12 09:52:13 +02:00
Florent Kermarrec
91feb59f49 Merge branch 'master' of http://github.com/litex-hub/litex-boards 2019-09-11 23:02:44 +02:00
Florent Kermarrec
a92ce32f91 targets/netv2: add clk100 (for framebuffer) 2019-09-11 23:02:21 +02:00
Florent Kermarrec
ec97d01feb platforms/netv2: add spiflashx4, hdmi in/out 2019-09-11 23:01:58 +02:00
Antti Lukats
91a1520655 add initial Trenz Cyclone 10 LP RefKit support with SDRAM/HyperRAM/Ethernet 2019-09-10 11:32:29 +02:00
Florent Kermarrec
c6bb34d78a partner/targets/nereid: MT8KTF51264 now in LiteDRAM 2019-09-09 08:50:06 +02:00
Florent Kermarrec
b4eefa6c33 import: allow importing directly from litex_boards.platforms or litex_boards.targets 2019-09-03 15:30:20 +02:00
Florent Kermarrec
ec5540454b partner: aller/nereid/tagus fix copyright (Rohit Singh as main author), do some cosmetic 2019-09-02 11:43:30 +02:00
enjoy-digital
cd527f0fcb
Merge branch 'master' into master 2019-09-02 11:29:22 +02:00
Florent Kermarrec
d78965ffb2 partner/targets/fomu fix copyright & mode 2019-09-02 11:23:43 +02:00
Sean Cross
bdbd2ec1c0 partner: add fomu target 
This adds the Fomu target back in.  The default BaseSoC supports
various USB methods, and will be updated as more become available.

The debug bridge may optionally be added.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-09-02 14:18:09 +08:00
Florent Kermarrec
e704014b36 targets/__init__: comment targets import until we found a way to avoid litedram/liteeth dependecies for targets no using them. 2019-09-01 11:43:21 +02:00
Rohit Singh
346621b9fc partner: add platforms and targets for aller, tagus and nereid boards 2019-09-01 03:02:04 -05:00
Florent Kermarrec
1131af05af nexys_video: generate clk100 2019-08-27 14:05:07 +02:00
Florent Kermarrec
f661ee0ec9 targets: fix import 2019-08-26 11:00:12 +02:00
Florent Kermarrec
ac58d57a83 targets: import platforms from litex_boards.platforms 2019-08-26 09:09:40 +02:00
Florent Kermarrec
b84308cb58 list all platforms/targets in platforms.py, targets.py to ease import 2019-08-26 09:07:07 +02:00
Arnaud Durand
618f41bb1e
Update ecp5_evn.py 
The system clock was driven directly while it should be driven by the PLL.
 2019-08-22 02:27:50 +02:00
DurandA
1abca7dcff Turn litex_boards.community into module 2019-08-12 00:17:26 +02:00
enjoy-digital
ad21f15782
Merge pull request #10 from DurandA/ecp5-evn 
Add ECP5 Evaluation Board
 2019-08-09 12:37:36 +02:00
DurandA
c90950e319 Default to 60 Mhz system clock on ECP5 Evaluation Board 
Exact PLL clock can be derived from U1 12 Mhz or X5 50 Mhz clock.
 2019-08-09 11:58:30 +02:00
DurandA
9e6dccc277 Remove ECP5 Evaluation Board programmer 2019-08-09 11:54:49 +02:00
DurandA
4126ed21d5 Add X5 clock and PLL to ECP5 Evaluation Board 2019-08-09 11:54:38 +02:00
DurandA
c7444fe19c Add ECP5 Evaluation Board 2019-08-09 09:45:13 +02:00
Florent Kermarrec
2596b20982 partner/targets/fomu: remove for now since only has a CRG (we'll add one later with a real design) 2019-08-07 09:08:11 +02:00
Florent Kermarrec
0c1fa7f4a8 partner/platform/fomu: cleaup, make it similar to others platforms 2019-08-07 09:04:31 +02:00
Florent Kermarrec
9f3ed82097 keep up to date with LiteX 
- use 1e9/freq for default_clk_period
- add default serial on tinyfpga_bx
- use S6PLL on minispartan6
- add SPIFlash pins on versa_ecp5
 2019-08-07 08:47:08 +02:00
Florent Kermarrec
bbf0e770e9 partner/targets/trellisboard: cleanup/update 2019-07-12 19:39:12 +02:00
Florent Kermarrec
a792502756 targets: make sure all targets have copyrights & #!/usr/bin/env python3 2019-07-12 19:36:49 +02:00
Florent Kermarrec
e470b55d2b fomu, trellisboard: +x 2019-07-12 19:24:08 +02:00
Florent Kermarrec
a88970a67f move trellis board from community to partner 2019-07-12 19:23:21 +02:00
Florent Kermarrec
82d73b8359 Merge branch 'master' of http://github.com/litex-hub/litex-boards 2019-07-12 19:19:31 +02:00
Florent Kermarrec
debafd7c17 official/partner: update 2019-07-12 19:19:01 +02:00
David Shah
a07e88d761 community: Add TrellisBoard 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-09 15:52:28 +01:00
DurandA
adcc34b528 Turn litex_boards.partner into module 2019-07-01 19:36:34 +02:00
Florent Kermarrec
325b6399a2 add test/test_targets (only test platforms with simple target for now) 2019-06-24 12:38:58 +02:00
Florent Kermarrec
aeddb93729 add copyright header to all files, udpate. 2019-06-24 12:13:54 +02:00
Sean Cross
49ffc94e85 partner: platforms: fomu_evt: rename rgb_led_n -> rgb_led 
The evt platform has a different naming scheme from the other two
versions of Fomu.

This harmonises the naming of the rgb_led pads between all of the Fomu
variants.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-06-19 19:21:15 -07:00
Sean Cross
d01711fdf9 partner: targets: add fomu target 
The `fomu` target represents a generic target that supports the Fomu
48 MHz crystal, with or without a PLL.

It does not yet include a BaseSoC, since that requires USB and
up5kspram, neither of which are present yet.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-06-19 12:58:13 -07:00
Florent Kermarrec
482a00aa76 fomu: move to right location 2019-06-12 19:50:46 +02:00
Florent Kermarrec
44d01edab9 dispatch platforms/targets by level of support 2019-06-10 18:59:49 +02:00
Florent Kermarrec
4213c75e48 init repo with litex official boards 2019-06-10 17:11:36 +02:00