Florent Kermarrec
6f8f0d2346
litex_setup: add litehyperbus and remove hyperbus core/test.
2020-05-19 15:49:25 +02:00
Florent Kermarrec
109fd2674a
integration/builder: simplify default output_dir to "build/platform".
...
All SoC are now based on the same base class and naming was too complicated.
2020-05-19 13:59:56 +02:00
Florent Kermarrec
7192397ab4
software/libbase: remove linker-sdram (unused).
2020-05-18 23:35:48 +02:00
Florent Kermarrec
b4b84def3c
software/bios: mode spisdcard code to liblitesdcard.
2020-05-18 23:33:34 +02:00
Florent Kermarrec
21e2a34c3f
software/bios: rename commands to cmds and update with libs' names.
2020-05-18 23:26:51 +02:00
Florent Kermarrec
33f6ce7431
software/bios: move hw flags definitions to respective libs, remove hw/flags.h.
2020-05-18 23:09:31 +02:00
Florent Kermarrec
403355a8ed
software: create liblitescard and move sdcard init/test code to it.
2020-05-18 22:49:12 +02:00
Florent Kermarrec
920d0ee536
software: create liblitedram and move sdram init/test code to it.
2020-05-18 22:42:23 +02:00
Florent Kermarrec
c95084e5c6
bios/software: rename cmd_dram/cmd_sdcard/cmd_spi_flash to cmd_litedram/cmd_litesdcard/cmd_spiflash.
2020-05-18 22:24:24 +02:00
Florent Kermarrec
573a881529
software/bios/commands: rename cmd_mdio to cmd_liteeth.
2020-05-18 22:16:20 +02:00
Florent Kermarrec
ff8d9e61bf
software/bios: move mdio to libliteeth.
2020-05-18 21:09:41 +02:00
Florent Kermarrec
70a67ce7ed
software/bios: rename libnet to libliteeth and move all ethernet files to it.
2020-05-18 21:04:54 +02:00
Florent Kermarrec
56b8723b72
software/bios: rename cmd_mem_access to cmd_mem.
2020-05-18 19:59:28 +02:00
Florent Kermarrec
a02077d547
cpu/microwatt/add_sources: add use_ghdl_yosys_synth parameter to convert microwatt to verilog using GHDL-Yosys-plugin and use converted verilog for build.
2020-05-18 17:30:42 +02:00
Florent Kermarrec
b5352f403c
cpu/microwatt: update microwatt_wraper.vhdl
2020-05-18 16:38:08 +02:00
Florent Kermarrec
be25500e91
uptime: rework and integrate it in Timer to ease software support.
2020-05-17 11:05:14 +02:00
Florent Kermarrec
d6549ff8f1
bios: add uptime command and rewrite cmd_bios comments.
2020-05-16 10:02:31 +02:00
Florent Kermarrec
fc0e55be32
soc: improve uptime comments.
2020-05-16 10:01:39 +02:00
enjoy-digital
840679add6
Merge pull request #526 from rprinz08/master
...
Make booting from SD-Card to behave same as from SPI flash
2020-05-15 16:03:37 +02:00
Florent Kermarrec
82364de57f
soc/SoCController: add uptime since start (disabled by default) and allow features to be enabled/disabled.
2020-05-15 15:00:04 +02:00
rprinz08
3f649077b1
Make booting from SD-Card to behave same as from SPI flash
2020-05-15 12:07:52 +02:00
Florent Kermarrec
3391398a5f
bios/sdram: always show bitslip on two digits to keep scan aligned.
2020-05-14 15:20:52 +02:00
Benjamin Herrenschmidt
1e35b0e705
csr: Rework accessors
...
Have all the new compound accessors be written in terms of the simple
ones and fix how CSR_ACCCESORS_DEFINED can be used to override the
simple ones but keep the definitions of the other ones around.
This *should* also also fix incorrect multiple accesses done
by 64-bit CPUs to 32-bit CSR busses, and make the accessors not
depend on CONFIG_CSR_ALIGNMENT being the same as sizeof(unsigned long)*8
In addition, the generated csr.h now will include system.h
always when with_access_functions is True. This guarantees that the
higher level accessors are defined. The extern prototypes for the
simple accessors when CSR_ACCCESORS_DEFINED are removed and system.h
is responsible for providing them. It is also added to hw/common.h
This allows system.h to set CSR_ACCCESORS_DEFINED when necessary, in
which case it's responsible for both declaring and defining the simple
accessors. That way, it can make them inline rather than forcing them
to be extern which at least on microwatt saves spaces.
One can continue to use -DCSR_ACCCESORS_DEFINED but in that case a system.h
will have to be provided with at least the extern definitions.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-14 21:38:19 +10:00
enjoy-digital
a51c7a7bac
Merge pull request #518 from enjoy-digital/csr_base
...
export: add define of CSR_BASE if not already defined and use it for …
2020-05-14 08:02:37 +02:00
Arnaud Durand
9d9e7d54cd
Update litex_term help
...
Specify the use of kernel address with flash flag.
2020-05-13 22:50:09 +02:00
Florent Kermarrec
2e59dc329d
platforms/nexys4ddr: add card detect pin to sdcard.
2020-05-13 19:11:46 +02:00
Florent Kermarrec
51742be2bb
integration/soc: review/simplify interconnect and add logger.info.
2020-05-13 18:29:12 +02:00
Benjamin Herrenschmidt
1ed6869110
soc: Revive generation of a PointToPoint interconnect
...
When there's only one master, one slave, and that slave is at 0
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-14 00:06:53 +10:00
Florent Kermarrec
748ef1add3
export: add define of CSR_BASE if not already defined and use it for CSRs definitions/accesses.
...
This will allow more flexibility when integrating standalone cores.
2020-05-13 15:56:20 +02:00
Florent Kermarrec
9d1443c1a8
cpu/soc_core: automatically set csr mapping to 0x00000000 when using CPUNone, remove csr_base parameter that was used for that.
2020-05-13 09:31:20 +02:00
Florent Kermarrec
5ea3bae036
bios/boot: review/fix #503 .
...
- copy_image_from_flash_to_ram is now used by all CPUs.
- copy_image_from_flash_to_ram already show the flash address, no need to duplicate it.
2020-05-13 08:44:17 +02:00
enjoy-digital
bf7857f553
Merge pull request #503 from rprinz08/master
...
BIOS boot firmware from SPI with address offset
2020-05-13 08:36:43 +02:00
Dave Marples
d2d82dacf2
Bios linker edits to prevent inappropriate optimisation
2020-05-12 23:32:49 +01:00
rprinz08
1f55fcf449
fixed bug in BIOS spi flash "fw" command
2020-05-12 16:58:42 +02:00
rprinz08
f062c0c44b
removed FLASH_BOOT_OFFSET, replaced memcyp with copy_image_from_flash_to_ram
2020-05-12 16:57:21 +02:00
Florent Kermarrec
3fb99b7d33
cores/spi_flash: add back old SpiFlashDualQuad and rename new one as SpiFlashQuadReadWrite.
2020-05-12 16:51:47 +02:00
enjoy-digital
2a5a7536b8
Merge pull request #478 from antmicro/extended_spi_flash
...
Extended SPI flash support
2020-05-12 16:42:01 +02:00
enjoy-digital
7d79da8eda
Merge pull request #510 from mubes/colorlight_usb
...
Colorlight usb
2020-05-12 16:35:29 +02:00
Florent Kermarrec
3a6dd95d6f
integration/soc: review/simplify changes for standalone cores.
...
- do the CSR alignment update only if CPU is not CPUNone.
- revert PointToPoint interconnect when 1 master and 1 slave since this will
break others use cases and will prevent mapping slave to a specific location.
It's probably better to let the synthesis tools optimize the 1:1 mapping directly.
- add with_soc_interconnect parameter to add_sdram that defaults to True. When
set to False, only the LiteDRAMCore will be instantiated and interconnect with
the SoC will not be added.
2020-05-12 16:18:26 +02:00
Dave Marples
8499733289
Fix dumb missing line
2020-05-12 14:40:11 +01:00
enjoy-digital
0d5eb13359
Merge pull request #511 from ozbenh/standalone-cores
...
Improve standalone cores
2020-05-12 14:55:44 +02:00
Florent Kermarrec
873d95e517
interconnect/wishbonebridge: refresh/simplify.
...
This should also improve Wishbone timings.
Tested on iCEBreaker:
./icebreaker.py --cpu-type=None --uart-name=uartbone --csr-csv=csr.csv --build --flash
With the following script:
#!/usr/bin/env python3
import sys
from litex import RemoteClient
wb = RemoteClient()
wb.open()
# # #
print("scratch: 0x{:08x}".format(wb.regs.ctrl_scratch.read()))
errors = 0
for i in range(2):
for j in range(32):
wb.write(wb.mems.sram.base + 4*j, i + j)
for j in range(32):
if wb.read(wb.mems.sram.base + 4*j) != (i + j):
errors += 1
print("sram errors: {:d}".format(errors))
# # #
wb.close()
2020-05-12 13:40:28 +02:00
Benjamin Herrenschmidt
f628ff6b47
WB2CSR: Use CSR address_width for the wishbone bus
...
Currently, we create a wishbone interface with the default address
width (30 bits) for the bridge. Instead, create an interface that
has the same number of address bits as the CSR bus.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-12 21:37:36 +10:00
Benjamin Herrenschmidt
520c17e96d
soc_core: Add option to override CSR base
...
When creating standalone IP cores such as standalone LiteDRAM without
a CPU, the CSR are presented externally via a wishbone with just enough
address bits to access individual CSRs (14), and no address decoding
otherwise. It is expected that the design using such core will have
its own address decoder gating cyc/stb.
However, such a design might still need to use LiteX code such as
the sdram init code, which relies on the generated csr.h. Thus we
want to be able to control the CSR base address used by that generated
csr.h.
This could be handled instead by having the "host" code provide
modified csr_{read,write}_simple() that include the necessary base
address. However, such an approach would make things complicated
if the design includes multiple such standalone cores with separate
CSR busses (such as LiteDRAM and LiteEth).
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-12 21:35:12 +10:00
Benjamin Herrenschmidt
ecbd40284a
soc: Don't update CSR alignment when there is no CPU
...
The alignment specified by the standalone core config should
be honored.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-12 21:31:23 +10:00
Benjamin Herrenschmidt
f28f247130
soc: Don't create a wishbone slave to LiteDRAM with no CPU
...
When creating a standalone LiteDRAM core with no CPU, there is
no need to create a wishbone slave to LiteDRAM interface.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-12 21:30:19 +10:00
Dave Marples
33e202edd4
Bring into line with master
2020-05-12 12:28:09 +01:00
Benjamin Herrenschmidt
dcc881db92
soc: Don't create a share intercon with only one master and one slave
...
This creates a lot of useless churn in the resulting verilog. Instead
use a point to point interconnect in that case.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-12 20:58:19 +10:00
enjoy-digital
c136113a9b
Merge pull request #506 from scanakci/blackparrot_litex
...
Update README and core.py for Blackparrot and change vivado command for systemverilog
2020-05-12 11:41:25 +02:00
Dave Marples
dc1d452008
Addition of boot address parameter for trellis builds
2020-05-12 09:41:37 +01:00
Kamil Rakoczy
0db3506997
Update Litex bios to handle updated litesdcard.
2020-05-12 10:07:16 +02:00
sadullah
aed1d514ab
Update README.md and core.py for BlackParrot
2020-05-12 03:06:38 -04:00
sadullah
5e4a436089
Vivado Command Update for Systemverilog
...
Add BlackParrot to LiteX setup file
2020-05-12 03:05:41 -04:00
enjoy-digital
3ce9010083
Merge pull request #505 from DurandA/patch-3
...
Enable 1x mode on SPI flash
2020-05-11 22:53:31 +02:00
Florent Kermarrec
e2176cefc2
soc: remove with_wishbone (a SoC always always has a Bus) and expose more bus parameters.
2020-05-11 22:39:17 +02:00
Arnaud Durand
2c40967b5a
Enable 1x mode on SPI flash
2020-05-11 22:12:40 +02:00
Florent Kermarrec
1e610600f6
build/lattice/diamond/clock_constraints: review and improve similarities with the others build backends.
2020-05-11 10:52:39 +02:00
enjoy-digital
ebcf67c10f
Merge pull request #502 from shuffle2/master
...
diamond: project generation improvements
2020-05-11 09:55:52 +02:00
enjoy-digital
13db89ebd2
Merge branch 'master' into rdimm_bside_init
2020-05-11 09:42:35 +02:00
Florent Kermarrec
c9e36d7fdd
lattice/icestorm: add ignoreloops/seed support (similar to trellis) and icestorm_args.
2020-05-11 09:33:26 +02:00
Florent Kermarrec
ea7fe383a3
lattice/trellis: simplify seed support and add it to trellis_args.
2020-05-11 09:26:12 +02:00
enjoy-digital
5ee01c9460
Merge pull request #484 from ilya-epifanov/lattice-trellis-toolchain-seed
...
Can now pass `--seed` to `nextpnr-ecp5` via `TrellisToolchain` `kwargs`
2020-05-11 09:13:26 +02:00
enjoy-digital
c5f74a5aa7
Merge branch 'master' into cpu-imac-config-for-vexriscv
2020-05-11 08:58:20 +02:00
Florent Kermarrec
59d88a880c
integration/soc/add_adapter: rename is_master to direction.
2020-05-11 08:47:50 +02:00
Ilia Sergachev
e4fa4bbcf7
integration/soc: fix add_adapter for slaves
2020-05-10 11:32:34 +02:00
Benjamin Herrenschmidt
2d70220b80
bios: Fix warning on 64-bit
...
This fixes an incorrect printf format specifier
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-09 19:44:43 +02:00
rprinz08
ea232fc53a
BIOS boot firmware from SPI with address offset
2020-05-09 19:20:32 +02:00
Shawn Hoffman
eeee179dd8
diamond: close project when done
...
Avoids ".recovery file is present" prompt.
2020-05-09 02:28:00 -07:00
Shawn Hoffman
9b782bd7da
diamond: clock constraint improvements
...
Specify NET or PORT for freq constraints
Add equivalent timing closure check that diamond ui uses,
and default to asserting check has passed
2020-05-09 02:28:00 -07:00
Florent Kermarrec
fbbbdf03b5
core/led: simplify LedChaser (to have the same user interface than GPIOOut).
2020-05-08 22:13:47 +02:00
Florent Kermarrec
05869beb72
cores/led: add LedChaser (now that LiteX is running on FPGA mining boards let's use fancy led blinks :))
2020-05-08 13:18:12 +02:00
Florent Kermarrec
90c485fcc8
integration/soc: add clock_domain parameter to add_etherbone.
...
To allow using a sys_clk < 125MHz with a 1Gbps link.
2020-05-08 13:16:26 +02:00
Florent Kermarrec
f1a50a2138
integration/soc: add add_uartbone method (to add a UARTBone aka UART Wishbone bridge).
2020-05-08 11:54:51 +02:00
Florent Kermarrec
79ee135f56
bios/sdram: fix lfsr typo.
2020-05-07 12:11:59 +02:00
enjoy-digital
162d32603d
Merge pull request #500 from mubes/fixups
...
Fixups
2020-05-07 11:55:58 +02:00
Florent Kermarrec
d74f8fc93d
build/xilinx: add disable_constraints parameter to Platform.add_ip.
...
When integrate .xci, we don't necessarily want to apply the default timing/loc
constrants generated by Vivado but our custom ones. Setting disable_constraints
to True allow disabling .xdc generated by the IP.
2020-05-07 11:34:26 +02:00
Dave Marples
2a37b97d9f
Merge branch 'master' of https://github.com/enjoy-digital/litex into fixups
2020-05-07 09:36:41 +01:00
Dave Marples
967e38bb57
Small fixups to address compiler warnings etc.
2020-05-07 09:26:46 +01:00
Florent Kermarrec
84841e1d58
bios/sdram: fix merge typo in lfsr (thanks Benjamin Herrenschmidt).
2020-05-07 08:21:57 +02:00
Benjamin Herrenschmidt
99c5b0fca1
bios/sdram: Use an LFSR to speed up pseudo-random number generation
...
This speeds up the memory test by an order of magnitude, esp. on
cores without a hardware multiplier by getting rid of the
multiplication in the loop.
The LFSR implementation comes from microwatt's simple_random test
project.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-06 21:56:10 +02:00
Florent Kermarrec
8b9aa16d2e
boards/platforms: update xilinx programmers.
2020-05-06 16:16:41 +02:00
Florent Kermarrec
3c34039b73
build/xilinx/vivado: ensure Vivado process our .xdc early.
...
When generating the LitePCIe PHY wrappers from the .xci, Vivado is locking the
PCIe lanes to default locations that do not necessarily match the ones used in
the design.
Processing our constraints earlier makes Vivado use our constraints and not the
ones from the generated wrapper.
2020-05-06 13:13:01 +02:00
Florent Kermarrec
b057858071
gen/fhdl/verilog: explicitly define input/output/inout wires.
...
When integrating designs which set `default_nettype none, the top also needs
to explicitly define the type of the signals.
2020-05-05 16:58:33 +02:00
Florent Kermarrec
0aa3c339cc
targets/genesys2: set cmd_latency to 1.
2020-05-05 16:33:14 +02:00
Florent Kermarrec
95b57899cd
bios: remove usddrphy debug (we'll use a specific debug firmware to fix the usddrphy corner cases).
2020-05-05 16:27:21 +02:00
Florent Kermarrec
98d1b45157
platforms/targets: fix CI.
2020-05-05 15:55:09 +02:00
Florent Kermarrec
22bcbec03a
boards: keep in sync with LiteX-Boards, integrate improvements.
...
- create_programmer on all platforms.
- input clocks automatically constrainted.
- build/load parameters.
2020-05-05 15:27:56 +02:00
Florent Kermarrec
28f85c7403
build/lattice/programmer: add UJProg (for ULX3S).
2020-05-05 13:31:58 +02:00
Florent Kermarrec
85ac5ef133
build/lattice/programmer: make OpenOCDJTAGProgrammer closer to OpenOCD programmer.
2020-05-05 12:17:12 +02:00
Florent Kermarrec
9a7f9cb87b
build/generic_programmer: catch 404 not found when downloading config/proxy.
2020-05-05 12:16:29 +02:00
Florent Kermarrec
d0b8daa005
build/platform: allow doing a loose lookup_request (return None instead of ConstraintError) and allow subname in lookup_request.
...
In the platforms, insead of doing:
self.lookup_request("eth_clocks").rx
we can now do:
self.lookup_request("eth_clocks:rx")
This allows some try/except simplifications on constraints.
2020-05-05 11:23:46 +02:00
Florent Kermarrec
b8f9f83a8f
build/openocd: add find_config method to allow using local config file or download it if not available locally.
2020-05-05 09:56:13 +02:00
Florent Kermarrec
9bef218ad6
cpu/microwatt: fix integration/crt0.S (thanks Benjamin Herrenschmidt).
...
Tested on Arty A7:
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2020 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on May 4 2020 17:15:13
BIOS CRC passed (0adc4193)
Migen git sha1: 5b5e4fd
LiteX git sha1: 6f24d46d
2020-05-04 17:30:50 +02:00
Gabriel Somlo
edfed4f068
software/*/Makefile: no need to copy .S files from CPU directory
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-05-04 09:16:52 -04:00
shuffle2
ee413527ac
diamond: quiet warning about missing clkin freq for EHXPLLL
...
FREQUENCY_PIN_CLKI should be given in mhz
2020-05-04 01:10:09 -07:00
Florent Kermarrec
2112703181
cpu/microwatt: add powerpc64le-linux-gnu to gcc_triple.
...
It seems to be what most distros cross-comiplers are using.
2020-05-04 08:51:38 +02:00
Florent Kermarrec
c06a127909
cpu/microwatt: add pythondata and fix build with it.
2020-05-04 08:46:25 +02:00
Florent Kermarrec
45377d9faa
cpus: use a common definition of gcc_triple for the RISC-V CPUs, reorganize CPU by ISA/Data-Width.
2020-05-03 21:29:54 +02:00
Florent Kermarrec
7c69a6dbba
bios/cmd_mdio.c: fix missing <base/mdio.h> import.
2020-05-03 10:54:35 +02:00
Florent Kermarrec
b02053357c
cpu/vexriscv: fix flush_cpu_icache, remove workaround on boot.c.
2020-05-02 20:07:52 +02:00
Florent Kermarrec
97e534d0b6
cpus: add nop instruction and use it to simplify the BIOS.
2020-05-02 12:52:25 +02:00
Florent Kermarrec
4efc783534
cpus: add human_name attribute and use it to simplify the BIOS.
2020-05-02 11:52:58 +02:00
Florent Kermarrec
d81f171c8a
software/libbase/system.c: remove unused includes.
2020-05-02 11:27:22 +02:00
enjoy-digital
999b93af0a
Merge branch 'master' into blackparrot_litex
2020-05-02 11:16:33 +02:00
enjoy-digital
705d388745
Merge pull request #474 from fjullien/term_hist_auto_compl
...
Terminal: add history and auto completion
2020-05-02 10:45:12 +02:00
Sadullah Canakci
0c770e0683
Update README.md
2020-05-02 02:51:41 -04:00
sadullah
19bb1b9b8c
update to comply with python-data layout
2020-05-01 23:44:20 -04:00
sadullah
3eb9efd64f
BP fpga recent version
2020-05-01 16:27:30 -04:00
sadullah
bf864d335b
Fix memory transducer bug, --with-sdram for BIOS works, memspeed works
2020-05-01 16:27:27 -04:00
sadullah
cf01ea65f3
rebased, minor changes in core.py
2020-05-01 16:25:01 -04:00
sadullah
b7b9a1f0fb
Linux works, LiteDRAM works (need cleaning, temporary push)
2020-05-01 16:24:58 -04:00
Sadullah Canakci
74140587c8
Create GETTING STARTED
...
Rename GETTING STARTED to GETTING STARTED.md
Update GETTING STARTED.md
Update GETTING STARTED.md
Update GETTING STARTED.md
2020-05-01 16:20:35 -04:00
enjoy-digital
e853cac6b6
Merge pull request #483 from ilya-epifanov/lattice-openocd-jtag-programmer-erase-flag-and-quiet-output
...
Lattice OpenOCD JTAG programmer: removed erase flag and made progress output less noisy
2020-05-01 21:18:09 +02:00
enjoy-digital
a6779b9d61
Merge pull request #491 from gsomlo/gls-spisd-clusters
...
software: spisdcard: cosmetic: avoid filling screen with cluster numbers
2020-05-01 21:17:38 +02:00
Florent Kermarrec
bd8a410047
cpu/minerva: add pythondata and use it to compile the sources.
2020-05-01 20:12:02 +02:00
Gabriel Somlo
c8e3bba4b7
software: spisdcard: cosmetic: avoid filling screen with cluster numbers
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-05-01 09:49:16 -04:00
Florent Kermarrec
3c70c83f9b
cpu/software: move flush_cpu_icache/flush_cpu_dcache functions to CPUs.
2020-05-01 12:41:14 +02:00
Franck Jullien
74dc444b02
bios: add auto completion for commands
2020-05-01 12:12:35 +02:00
Franck Jullien
fc2b8226c5
bios: switch command handler to a modular format
...
Command are now described with a structure. A pointer to this
structure is placed in a dedicated linker section.
2020-05-01 12:12:35 +02:00
Franck Jullien
86cab3d362
bios: move helper functions to their own file
2020-05-01 12:12:35 +02:00
Franck Jullien
bc5a1986e2
bios: add terminal history
...
Terminal history and characters parsing is done in readline.c.
Passing TERM_NO_HIST disable terminal history.
Passing TERM_MINI use a simple terminal implementation in order to save
more space.
2020-05-01 12:12:07 +02:00
Franck Jullien
e764eabda1
builder: add a parameter to pass options to BIOS Makefile
2020-05-01 12:10:50 +02:00
Florent Kermarrec
bb70a2325a
cpu/software: move CPU specific software from the BIOS to the CPU directories.
...
This simplifies the integration of the CPUs' software, avoid complex switches in the code,
and is a first step to make CPUs fully pluggable.
The CPU name is no longer present in the crt0 files (for example crt0-vexriscv-ctr.o
becomes crt0-ctr.o) so users building firmwares externally will have to update their
Makefiles to remove the $(CPU) from crt0-$(CPU)-ctr.o.
2020-05-01 11:04:54 +02:00
Florent Kermarrec
0abc7d4f0b
cpu/Minerva: Clone the repository locally for now, we need to create a pythondata repository.
2020-05-01 11:03:07 +02:00
Florent Kermarrec
b82b3b7ecf
integration/soc: rename usb_cdc to usb_acm.
...
As discussed on Discord recently.
2020-04-30 21:45:53 +02:00
Florent Kermarrec
0a1afbf66f
litex/__init__.py: remove retro-compat > 6 months old.
2020-04-30 21:31:58 +02:00
Florent Kermarrec
3531a64173
soc: allow passing custom CPU class to SoC.
...
Useful to experiment with custom CPU wrappers and a first step to make CPUs plugable.
2020-04-29 20:12:23 +02:00
David Shah
64b505156e
Add RDIMM side-B inversion support
...
Signed-off-by: David Shah <dave@ds0.me>
2020-04-29 12:28:53 +01:00
Ilya Epifanov
83f4dcb2c6
Added imac config for CPUs which implements the most basic working riscv32imac feature set, implemented for VexRiscv
2020-04-28 22:27:35 +02:00
Ilya Epifanov
ac1e968351
Can now pass --seed to nextpnr-ecp5 via TrellisToolchain kwargs
2020-04-28 22:25:57 +02:00
Ilya Epifanov
a11f1c39b7
Removed erase flag and made progress output less noisy
2020-04-28 22:22:33 +02:00
bunnie
17b766546b
propose patch to not break litex for python 3.5
2020-04-29 00:34:19 +08:00
Jakub Cebulski
00f973ea35
spi_flash: extend non-bitbanged flash support
...
This commit adds support for memory mapped writes
in the same configuration as memory mapped reads
are currently supported.
It also adds support for accessing registers
and erasing sectors in non-bitbanged single SPI
mode.
2020-04-28 15:02:55 +02:00
Florent Kermarrec
6d0896de1d
cpu/serv: switch to pythondata package instead of local git clone.
2020-04-28 10:34:39 +02:00
enjoy-digital
4d86ab9ded
Merge pull request #399 from mithro/litex-sm2py
...
Converting LiteX to use Python modules.
2020-04-28 08:34:19 +02:00
Florent Kermarrec
5ef869b9eb
soc/cpu: add memory_buses to cpus and use them in add_sdram.
...
This allows the CPU to have direct buses to the memory and replace the Rocket specific code.
2020-04-27 23:53:52 +02:00
Florent Kermarrec
467fee3e23
soc/cpu: rename cpu.buses to cpu.periph_buses.
2020-04-27 23:08:15 +02:00
enjoy-digital
317ea7edd1
Merge branch 'master' into litex-sm2py
2020-04-27 22:24:10 +02:00
shuffle2
f71014b9fb
diamond: fix include paths
...
include paths given via tcl script need semicolon separators and forward slash as directory separator (even on windows)
2020-04-27 11:14:18 -07:00
Florent Kermarrec
4dece4ce24
soc/cpu: simplify integration of CPU without interrupts (and automatically use UART_POLLING mode in this case).
2020-04-27 19:06:16 +02:00
enjoy-digital
c5ef9c7356
Merge pull request #473 from fjullien/memusage
...
bios: print memory usage
2020-04-27 18:24:43 +02:00
Franck Jullien
3892d7a90a
bios: print memory usage
...
Print memory usage during the compilation of bios.elf.
2020-04-27 16:33:34 +02:00
Florent Kermarrec
9460e048ec
tools/litex_sim: use similar analyzer configuration than wiki.
2020-04-27 16:10:41 +02:00
enjoy-digital
443cc72d0a
Merge pull request #476 from enjoy-digital/serv
...
Add SERV support (The SErial RISC-V CPU)
2020-04-27 13:59:28 +02:00
Florent Kermarrec
1d1a4ecd28
software/irq: cleanup and make explicit that irqs are not supported with Microwatt and SERV, fix compilation warning.
2020-04-27 13:47:13 +02:00
Florent Kermarrec
fb9e369a19
serv: connect reset.
2020-04-27 13:26:45 +02:00
Florent Kermarrec
c4c891dec5
build/icestorm: add verilog_read -defer option to yosys script (changes similar the ones applied to trellis).
2020-04-27 13:17:53 +02:00
Greg Davill
642c4b3036
build/trellis: add verilog_read -defer option to yosys script
2020-04-27 20:10:25 +09:30
Florent Kermarrec
71778ad226
serv: update copyrights (Greg Davill found the typos/issues).
2020-04-27 10:27:44 +02:00
Florent Kermarrec
1f9db583fd
serv/cores: fix verilog top level (use serv_rf_top instead of serv_top), working :).
2020-04-26 21:05:47 +02:00
Florent Kermarrec
2efd939d06
serv: fix ibus/dbus byte/word addressing inconsistency, add missing ibus.sel (thanks @GregDavill).
2020-04-26 16:26:57 +02:00
Florent Kermarrec
96e7e6e89a
bios/sdram: reduce number of scan loops during cdly scan to speed it up.
2020-04-25 12:51:33 +02:00
Florent Kermarrec
43e1a5d67d
targets/kcu105: use cmd_latency=1.
2020-04-25 12:12:27 +02:00
Florent Kermarrec
85a059bf77
bios/sdram: add some margin on cdly ideal_delay, do the read_leveling even if write_leveling is not optimal.
...
We need to provide enough information to ease support and understand the issue. The write leveling/read leveling
are doing there best to calibrate the DRAM correctly and memtest gives the final result.
2020-04-25 12:11:10 +02:00
Florent Kermarrec
038e1bc048
targets/kc705: manual DDRPHY_CMD_DELAY no longer needed.
2020-04-25 11:03:04 +02:00
Florent Kermarrec
aaed4b9475
bios/sdram: review/cleanup Command/Clock calibration, set window at the start instead of middle.
...
Working on KC705 that previously required manual adjustment.
2020-04-25 11:00:21 +02:00
enjoy-digital
33c7b2ce6b
Merge pull request #472 from antmicro/jboc/sdram-calibration
...
bios/sdram: add automatic cdly calibration during write leveling
2020-04-25 09:59:08 +02:00
enjoy-digital
4608bd1864
Merge pull request #470 from antmicro/jboc/sdram-eeprom-timings
...
litex_sim: add option to create SDRAM module from SPD data
2020-04-25 08:27:00 +02:00
Jakub Cebulski
a344e20b5e
spi_flash: fix building without bitbang
2020-04-24 17:45:17 +02:00
Jędrzej Boczar
ab92e81e31
bios/sdram: add automatic cdly calibration during write leveling
2020-04-24 14:00:42 +02:00
Florent Kermarrec
22c3923644
initial SERV integration.
2020-04-23 08:18:41 +02:00
Florent Kermarrec
0b3c4b50fa
soc/cores/spi: add optional aligned mode.
...
In aligned mode, MOSI and MISO bits are located on the LSBs and first transmitted MOSI bit is length - 1 bit.
2020-04-22 13:15:51 +02:00
Florent Kermarrec
6bb22dfe6b
cores/spi: simplify.
2020-04-22 12:20:23 +02:00
Florent Kermarrec
fc434af949
build/lattice/common: add specific LatticeiCE40SDROutputImpl/LatticeiCE40SDRTristateImpl (thanks @tnt).
2020-04-22 12:01:23 +02:00
Florent Kermarrec
1457c32052
xilinx/common: use a common SDRTristate implementation for Spartan6, 7-Series and Ultrascale.
2020-04-22 10:42:06 +02:00
Florent Kermarrec
69462e6669
build/xilinx/common: add 7-Series/Ultrascale SDROutput/Input.
2020-04-22 10:33:22 +02:00
Florent Kermarrec
65e6ddc6cd
lattice/common: add LatticeECP5DDRInput.
2020-04-22 10:13:28 +02:00
Florent Kermarrec
2031f28057
lattice/common: cleanup instances, simplify tritates.
2020-04-22 09:07:38 +02:00
Florent Kermarrec
2d25bcb09c
lattice/common: add LatticeiCE40DDRInput, LatticeiCE40SDROutput and LatticeiCE40SDRInput.
2020-04-22 09:07:33 +02:00
Florent Kermarrec
56e1528455
platforms/de0nano: swap serial tx/rx to ease use of cheap FT232 based cables.
2020-04-18 11:38:24 +02:00
Florent Kermarrec
08e4dc02ec
tools/remote/etherbone: update import.
2020-04-17 21:30:33 +02:00
Jędrzej Boczar
b0f8ee9876
litex_sim: add option to create SDRAM module from SPD data
2020-04-17 14:52:53 +02:00
Florent Kermarrec
19f983c420
targets: manual define of the SDRAM PHY no longer needed.
2020-04-16 11:26:59 +02:00
Florent Kermarrec
c0f3710d66
bios/sdram: update/simplify with new exported LiteDRAM parameters.
2020-04-16 10:42:01 +02:00
Florent Kermarrec
3915ed9760
litex_sim: add phytype to PhySettings.
2020-04-16 10:22:43 +02:00
Florent Kermarrec
c0c5ae558a
build/generic_programmer: move requests import to do it only when needed.
2020-04-16 08:44:36 +02:00
Florent Kermarrec
c9ab593989
bios/sdram/ECP5: set ERR_DDRPHY_BITSLIP to 4.
...
Bitslip software control is now used on ECP5 to move dqs_read.
2020-04-15 19:30:28 +02:00
Florent Kermarrec
5e149ceda2
build/generic_programmer: add automatic search/download of flash_proxy in repositories if not available locally.
2020-04-15 08:59:03 +02:00
Mateusz Holenko
77a05b78e8
soc_core: Fix region type generation
...
Include information about being a linker region.
2020-04-14 21:45:32 +02:00
Florent Kermarrec
d44fe18bd9
stream/AsyncFIFO: add default depth (useful when used for CDC).
2020-04-14 17:35:19 +02:00
Florent Kermarrec
ded10c89dc
build/sim/core/Makefile: add -p to mkdir modules.
2020-04-14 12:38:02 +02:00
enjoy-digital
c323e94c83
Merge pull request #464 from mithro/litex-sim-fixes
...
Improve the litex_sim Makefiles
2020-04-14 12:16:21 +02:00
Tim 'mithro' Ansell
97d0c525ee
Remove trailing whitespace.
2020-04-12 10:29:13 -07:00
Florent Kermarrec
4fe31f0760
cores: add External Memory Interface (EMIF) Wishbone bridge.
...
Useful to interface Processors/DSPs with LiteX. EMIF is generally used on Texas Instrument DSPs.
2020-04-12 16:34:33 +02:00
Rangel Ivanov
c57e438df6
boards/targets/ulx3s.py: Update --device option help message
...
Signed-off-by: Rangel Ivanov <rangelivanov88@gmail.com>
2020-04-12 12:01:31 +03:00
Rangel Ivanov
f4b345ecd7
build/lattice/trellis.py: Add 12k device
...
nextpnr adds the --12k option which is the same like
the --25k but with the correct idcode for the 12k devices
Signed-off-by: Rangel Ivanov <rangelivanov88@gmail.com>
2020-04-12 11:46:44 +03:00
Tim 'mithro' Ansell
1f35669508
litex_sim: Find tapcfg from pythondata module.
2020-04-11 18:38:15 -07:00
Tim 'mithro' Ansell
ebcb2a4406
Rename litex-data-XXX-YYY to pythondata-XXX-YYY
2020-04-11 18:37:06 -07:00
Tim 'mithro' Ansell
e618d41ffb
Fixing mor1kx data finding.
2020-04-11 18:37:06 -07:00
Tim 'mithro' Ansell
2e3b7f20c7
Fix typo in error message.
2020-04-11 18:37:06 -07:00
Tim 'mithro' Ansell
83b2581331
Fix the libcompiler_rt path.
2020-04-11 18:37:06 -07:00
Tim 'mithro' Ansell
1c1c5bcbda
Remove submodules.
2020-04-11 18:37:06 -07:00
Tim 'mithro' Ansell
c96d1e6672
Fix import for data.
2020-04-11 18:37:06 -07:00
Tim 'mithro' Ansell
69367f8d4e
Make litex a namespace.
2020-04-11 18:37:06 -07:00
Tim 'mithro' Ansell
d5a21a7522
Converting litex to use Python modules.
2020-04-11 18:37:06 -07:00
Tim 'mithro' Ansell
5a0bb6ee01
litex_sim: Rework Makefiles to put output files in gateware directory.
2020-04-11 18:37:03 -07:00
Tim 'mithro' Ansell
a0658421cc
litex_sim: Better error messages on failure to load module.
2020-04-11 18:35:39 -07:00
Florent Kermarrec
b95e0a19b1
altera/common: add DDROutput, DDRInput, SDROutput, SDRInput.
2020-04-10 15:50:35 +02:00
Florent Kermarrec
40f43efcf6
targets: use DDROutput on sdram_clock and similar configuration for all SDRAM targets.
2020-04-10 14:41:01 +02:00
Florent Kermarrec
292d6b75b6
build/xilinx/common: add Spartan6 specialized DDRInput, SDROutput, SDRInput and SDRTristate.
2020-04-10 14:38:22 +02:00
Florent Kermarrec
88dc5158c1
build/io: add SDR Tristate (with infered version) and remove multi-bits support on SDRIO.
2020-04-10 14:37:29 +02:00
Florent Kermarrec
fdadbd868b
build/lattice/common: remove multi-bits support on SDRInput/Output.
2020-04-10 14:36:13 +02:00
Florent Kermarrec
8159b65bee
litex/build/io: also import CRG (since using DifferentialInput).
2020-04-10 10:25:21 +02:00
Florent Kermarrec
79913e8614
litex.build: update from migen.genlib.io litex.build.io.
2020-04-10 09:49:45 +02:00
Florent Kermarrec
8e014f76da
litex/build: move io.py from litex/gen and re-import DifferentialInput/Output, DDRInput/Output contributed to Migen.
...
This will make things easier and more consistent, all special IO primitives are now in LiteX.
2020-04-10 08:47:07 +02:00
Florent Kermarrec
2e270cf28c
platforms/versa_ecp5: remove Lattice Programmer (no longer used since we can now use OpenOCD).
2020-04-09 23:08:59 +02:00
Florent Kermarrec
deebc49ab0
boards/platforms: cosmetic cleanups.
2020-04-09 23:04:29 +02:00
Florent Kermarrec
3c0ba8ae62
boards/plarforms/ulx3s: cleanup, fix user_leds, add spisdcard, add PULLMODE/DRIVE on SDRAM pins.
2020-04-09 18:55:01 +02:00
Florent Kermarrec
6c429c9995
build/lattice: add ECP5 implementation for SDRInput/SDROutput.
2020-04-09 16:24:05 +02:00
Florent Kermarrec
72c8d590fa
litex/gen: add io with SDRInput/SDROutput (if not overrided, register is supposed to be infered).
2020-04-09 16:23:27 +02:00
Florent Kermarrec
8f57321f30
tools/litex_sim: remove LiteSPI support for now since breaking Travis-CI of others sub-projects.
...
LiteSPI is not mature enough to be integrated in LiteX sim directly. (will case trouble is things are refactored).
This could be re-introduced later when more mature. For now simulation with LiteX Sim
could be tested directly in LiteSPI with a custom simulation.
2020-04-09 11:14:19 +02:00
Florent Kermarrec
9afd017a3a
tools/litex_term: increase workaround delay for usb_fifo. (validated on Minispartan6 and MimasA7).
...
Still needs to be fixed properly.
2020-04-09 10:52:15 +02:00
David Sawatzke
d69b4443b3
Add riscv64-none-elf triple
2020-04-09 05:36:10 +02:00
Florent Kermarrec
14bf8b8190
soc/cores/clock: add Max10PLL.
2020-04-08 08:54:12 +02:00
Florent Kermarrec
2470ef5096
soc/cores/clock: add Cyclone10LPPLL.
2020-04-08 08:33:57 +02:00
Florent Kermarrec
f8d6d0fda8
soc/cores/clock/CycloneVPLL: fix typos.
2020-04-08 08:25:46 +02:00
Florent Kermarrec
970c8de4c2
soc/cores/clock: rename Altera to Intel.
2020-04-08 08:16:37 +02:00
Florent Kermarrec
383fcd36d6
soc/cores/clock: add CycloneVPLL.
2020-04-07 17:24:12 +02:00
Florent Kermarrec
ab4906ea3b
targets/de0nano: use CycloneIVPLL, remove 50MHz limitation.
2020-04-07 17:00:45 +02:00
Florent Kermarrec
0f17547c5b
soc/cores/clock: add initial AlteraClocking/CycloneIV support.
2020-04-07 16:59:53 +02:00
Florent Kermarrec
0f352cd648
soc/cores: use reset_less on datapath/configuration CSRStorages.
2020-04-06 13:17:14 +02:00
Florent Kermarrec
a67ab41835
interconnect/csr: add reset_less parameter.
...
In cases CSRStorage can be considered as a datapath/configuration register and does not need to be reseted.
2020-04-06 13:15:08 +02:00
Florent Kermarrec
05b1b7787b
interconnect/csr, wishbone: use reset_less on datapath signals.
2020-04-06 13:11:50 +02:00
Florent Kermarrec
b95965de73
cores/code_8b10b: set reset_less to True on datapath signals.
...
Reset is only required on control signals.
2020-04-06 11:35:18 +02:00
Florent Kermarrec
a35df4f7d1
stream: set reset_less to True on datapath signals.
...
Reset is only required on control signals.
2020-04-06 11:33:49 +02:00
kessam
fb532f5e92
Fix timing constraints
2020-04-05 17:56:29 +02:00
Florent Kermarrec
6043108376
soc/cores/clock/ECP5PLL: add CLKI_DIV support.
2020-04-03 11:14:57 +02:00
enjoy-digital
27f00851d0
Merge pull request #447 from antmicro/spi-xip
...
Add initial support for the new LiteSPI core
2020-04-01 16:51:29 +02:00
Piotr Binkowski
81be74a7b1
targets: netv2: add LiteSPI
2020-04-01 16:20:36 +02:00
Piotr Binkowski
946cb16429
platform: netv2: update SPI flash pinout
2020-04-01 16:20:36 +02:00
Piotr Binkowski
31fceb0a10
litex_sim: add LiteSPI
2020-04-01 16:20:36 +02:00
Florent Kermarrec
91981b960c
soc/cores/uart: use reset_less on accumulator, reg, bitcount to reduce.
...
This reduces logic a bit. It does not make large difference on usual design with
only 1 UART, but is interesting on designs with hundreds of UARTs used to "document"
FPGA boards :) (similar to https://github.com/enjoy-digital/camlink_4k/blob/master/ios_stream.py )
2020-03-31 16:54:38 +02:00
Florent Kermarrec
87160059d3
soc/cores/spi_flash: add ECP5SPIFlash (non-memory-mapped).
2020-03-31 16:17:12 +02:00
enjoy-digital
e3445f6cd9
Merge pull request #444 from ilya-epifanov/openocd-jtag-programmer
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Added openocd jtagspi programmer, to be used with ECP5-EVN board
2020-03-28 12:58:08 +01:00
Ilya Epifanov
351551a041
Added openocd jtagspi programmer, to be used with ECP5-EVN board
2020-03-28 11:20:30 +01:00
Gabriel Somlo
8473ed567a
software/bios: add spisdcardboot() to boot_sequence()
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-27 15:24:09 -04:00
Gabriel Somlo
e9054ef65a
software/libbase/spisdcard: add delay to goidle loop
...
In `spi_sdcard_goidle()`, insert a `busy_wait()` into the CMD55+ACMD41
loop to avoid exhausting the retry counter before the card has a chance
to be ready (required on the trellisboard, also tested OK on nexys4ddr).
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-27 15:24:09 -04:00
Gabriel Somlo
c6b6dee2e7
software/bios: factor out busy_wait() function
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-27 15:24:09 -04:00
Gabriel Somlo
540218b2d8
software/libbase/spisdcard: fix width of address parameter
...
Host address parameter types should match CPU word width, so
use `unsigned long` to be correct on both 32 and 64 bit CPUs.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-27 15:24:09 -04:00
Florent Kermarrec
2e48ab568b
soc/cores/spi: make dynamic clk divider optional (can be enabled with add_clk_divider method) and only use it in add_spi_sdcard.
2020-03-27 18:44:48 +01:00
Florent Kermarrec
4abb3715d9
targets/add_constant: avoid specifying value when value is None (=default).
2020-03-26 09:45:19 +01:00
Florent Kermarrec
73b4347587
software/libbase/spisdcard: add USE_SPISDCARD_RECLOCKING define to easily disable reclocking.
2020-03-26 07:46:32 +01:00
Florent Kermarrec
b509df8bb6
integration/soc/add_uart: add USB CDC support (with ValentyUSB core).
2020-03-25 19:07:06 +01:00
Florent Kermarrec
76872a7afb
tools/litex_sim: simplify using uart_name=sim.
2020-03-25 19:06:37 +01:00
Florent Kermarrec
09a3ce0ee5
integration/soc/add_uart: add Model/Sim.
2020-03-25 18:56:58 +01:00
Florent Kermarrec
3f43c6a223
integration/soc/add_uart: cleanup.
2020-03-25 18:54:29 +01:00
Florent Kermarrec
5bcf730c77
build/tools: add replace_in_file function.
2020-03-25 16:36:53 +01:00
Florent Kermarrec
ffe83ef0f3
tools/litex_term: use 64 bytes as default payload_lengh (work for all confniguration) and add small delay between frames for FT245 FIFO.
...
The delay still need to be investigated.
2020-03-25 09:31:51 +01:00
Florent Kermarrec
8f2e36927d
bios/boot: update comments.
2020-03-25 09:21:28 +01:00
enjoy-digital
1746b57a1b
Merge pull request #437 from feliks-montez/bugfix/fix-serialboot-frames
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flush rx buffer when bad crc and fix frame payload length
2020-03-25 09:18:31 +01:00
Florent Kermarrec
8d999081e3
boards/targets: update SDRAM to use new GENSDRPHY and new ECP5PLL phase support.
2020-03-24 20:04:18 +01:00
Florent Kermarrec
3eb08c7dd8
boards/platforms: remove versa_ecp3 (ECP3 no longer supported).
2020-03-24 20:02:57 +01:00
Florent Kermarrec
eb64169521
build/lattice/diamond: remove ECP3 support. (ECP3 is not used and no longer interesting now that ECP5 has an open-source toolchain).
2020-03-24 19:36:57 +01:00
Florent Kermarrec
bba5f1828b
cores/clock/ECP5PLL: add phase support.
2020-03-24 19:09:05 +01:00
Florent Kermarrec
0123ccc893
build/lattice/common: change LatticeECPXDDROutputImpl from ECP3 to ECP5.
2020-03-24 19:08:38 +01:00
bunnie
5a402264d0
Fix off-by-one error on almost full condition for prefetch
...
This causes a DRC error on the Xilinx tools when the prefetch
lines setting is 1. Don't know why this wasn't caught earlier,
but it just popped up in CI.
2020-03-24 08:04:35 +01:00
Feliks
ebdc38fc91
flush rx buffer when bad crc and fix frame payload length
2020-03-23 23:04:36 -04:00
Florent Kermarrec
d62ef38c4b
soc/doc/csr: allow CSRField.reset to be a Migen Constant.
2020-03-23 18:47:41 +01:00
Florent Kermarrec
4adac90d88
cpu/vexriscv/mem_map_linux: move main_ram to allow up to 1GB.
2020-03-23 15:35:33 +01:00
Florent Kermarrec
63ab2ba40c
software/bios/boot/linux: move emulator.bin to main_ram and allow defining custom ram offsets.
2020-03-23 15:06:32 +01:00
Florent Kermarrec
d998475498
targets: remove Etherbone imports.
2020-03-21 21:39:34 +01:00
Florent Kermarrec
3b04efbcae
targets: switch to add_etherbone method.
2020-03-21 19:55:00 +01:00
Florent Kermarrec
5ad7a3b7df
integration/soc: add add_etherbone method.
2020-03-21 19:54:36 +01:00
Florent Kermarrec
d6b0819e4c
integration/soc/add_ethernet: add name parameter (defaults to ethmac).
2020-03-21 19:36:31 +01:00
Florent Kermarrec
930679efd7
targets: always use sys_clk_freq on SDRAM modules.
2020-03-21 19:36:06 +01:00
Florent Kermarrec
ae6ef923af
targets: fix typos in previous changes.
2020-03-21 18:26:58 +01:00
enjoy-digital
c547b2cc29
Merge pull request #436 from rob-ng15/master
...
Reclock spi sdcard access after initialisation
2020-03-21 09:26:25 +01:00
enjoy-digital
011773af8d
Merge pull request #435 from enjoy-digital/spi_master_clk_divider
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soc/core/spi: add Clk Divider CSR (defaults to sys_clk_freq/spi_clk_f…
2020-03-21 09:25:37 +01:00
rob-ng15
2bf31a31da
Reclock spi sdcard access after initialisation
...
Depends upon https://github.com/enjoy-digital/litex/pull/435
After initialising the card, reclock the card, aiming for ~16MHz (divider is rounded up, as slower speed is safer), but a maximum of half of the processor speed.
Tested with the card being clocked to 12.5MHz on de10nano
2020-03-21 07:37:21 +00:00
Florent Kermarrec
f03d862c06
targets: switch to add_ethernet method instead of EthernetSoC.
2020-03-20 23:46:15 +01:00
Florent Kermarrec
4e9a8ffe9c
targets: switch to SoCCore/add_sdram instead of SoCSDRAM.
2020-03-20 22:02:36 +01:00
Florent Kermarrec
61c9e54a90
soc/core/spi: add Clk Divider CSR (defaults to sys_clk_freq/spi_clk_freq).
2020-03-20 19:49:42 +01:00
Florent Kermarrec
dd7718b4fe
targets/arty: use new ISERDESE2 MEMORY mode.
2020-03-20 18:58:31 +01:00
Florent Kermarrec
fca52d110d
Merge branch 'master' of http://github.com/enjoy-digital/litex
2020-03-20 18:54:51 +01:00
rob-ng15
f3c233776e
Use <stdint.h> to provide structure sizes
2020-03-20 11:35:05 +00:00
rob-ng15
c2ebbcbf6c
Use <stdint.h> for structure sizes
2020-03-20 11:34:24 +00:00
Florent Kermarrec
ccf7363932
integration/soc: add add_spi_flash method to add SPI Flash support to the SoC.
2020-03-20 10:24:31 +01:00
Florent Kermarrec
ec3e068669
targets/nexys4ddr: use LiteXSoC's add_spi_sdcard method.
2020-03-20 09:58:09 +01:00
Florent Kermarrec
d276036f24
integration/soc: add add_spi_sdcard method to add SPI mode SDCard support to the SoC.
2020-03-20 09:57:37 +01:00
enjoy-digital
6044570928
Merge pull request #433 from gsomlo/gls-rocket-spisdcard
...
Support SPI-mode SDCard booting on Litex+Rocket (64bit) configuration
2020-03-20 09:41:56 +01:00
Gabriel Somlo
b960d7c574
targets/nexys4ddr: add '--with-spi-sdcard' build option
2020-03-19 21:51:44 -04:00
Gabriel Somlo
7a7b8905b7
platforms/nexys4ddr: add spisdcard pins.
...
Synchronize with litex-boards commit #57bcadb.
2020-03-19 21:51:44 -04:00
Gabriel Somlo
af4de03fad
targets/nexys4ddr: make sdcard reset conditional
2020-03-19 21:51:44 -04:00
Gabriel Somlo
a33916bc6b
software/libbase/spisdcard: fix 4-byte FAT fields on 64-bit CPUs
...
On 64-bit architectures (e.g., Rocket), 'unsigned long' means
eight (not four) bytes. Use 'unsigned int' wherever a FAT data
structure requires a four-byte field!
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-19 21:51:44 -04:00
Piotr Esden-Tempski
279886721b
Don't let python convert lane number to float.
...
While at it also:
* Don't multilane for reg >= 8 bit width.
* Only check if we should switch to multilane after finding min field width.
2020-03-19 18:12:41 -07:00
Gabriel Somlo
1f90abea8e
bios: make SPI SDCard boot configs other than linux-on-litex-vexriscv
...
When NOT on linux-on-litex-vexriscv, we load 'boot.bin' to MAIN_RAM_BASE,
and jump to it.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-19 19:37:47 -04:00
Gabriel Somlo
c2938dc973
bios/boot.c: cosmetic: re-indent spisdcardboot() for consistency
2020-03-19 19:37:47 -04:00
enjoy-digital
dd07a0ad2f
Merge pull request #431 from antmicro/hybrid-mac
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litex_sim: add support for hybrid mac
2020-03-19 22:10:33 +01:00
Florent Kermarrec
37f25ed37a
software/libbase/bios: rename spi.c/h to spisdcard.h, also rename functions.
2020-03-19 11:02:15 +01:00
Florent Kermarrec
939256340f
software/bios/main: revert USDDRPHY_DEBUG (merge issue with SPI SD CARD PR).
2020-03-19 10:47:28 +01:00
enjoy-digital
8fe9e72f7b
Merge pull request #429 from rob-ng15/master
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SPI hardware bitbanging from SD CARD
2020-03-19 10:41:09 +01:00
Piotr Binkowski
96a265a408
litex_sim: add support for hybrid mac
2020-03-19 10:04:08 +01:00
Gabriel Somlo
b2103f4ad8
bios/sdcard: provide sdclk_set_clk() stub for clocker-less targets
...
Targets which lack an adjustable clocker will not expose the required
registers. Provide a stub sdclk_set_clk() routine for those situations.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-18 15:11:23 -04:00
Florent Kermarrec
e865162904
platforms/kcu105: fix pcie tx0 p/n swap.
2020-03-18 19:05:54 +01:00
rob-ng15
27720409ce
SPI hardware bitbanging from SD CARD
2020-03-17 09:51:11 +00:00
rob-ng15
d45dda731a
SPI hardware bitbanging from SD CARD
2020-03-17 09:50:45 +00:00
rob-ng15
50b6db6a6b
SPI hardware bitbanging from SD CARD
2020-03-17 09:50:16 +00:00
Florent Kermarrec
2c4b89639f
soc/cores/clock: make sure specific clkoutn_divide_range is only used as a fallback solution.
2020-03-16 11:44:39 +01:00
Piotr Esden-Tempski
57576fa8fc
Add bit more logic to decide when to switch to multilane CSR documentation.
...
Now we only generate multilane bitfield documentation when the CSR has
fields, and the smallest field is less than 8bit long. As this is when
we start running into space problems with the field names.
2020-03-13 14:48:56 -07:00
Piotr Esden-Tempski
dda7a8c5f3
Split CSR documentation diagrams with more than 8 bits into multiple lanes.
...
In cases when each CSR bit has a name and we use CSR with more than 8
bits, the register diagram quickly becomes crowded and hard to read.
With this patch we split the register into multiple lanes of 8 bits
each.
2020-03-13 14:48:23 -07:00
Florent Kermarrec
aec1bfbeb4
cores/clock: simplify Fractional Divide support on S7MMCM.
...
Specific clkoutn_divide_range can now be provided by specialized XilinxClocking classes.
When provided, the specific range will be used. Floats are also now supported in the
range definition/iteration.
2020-03-13 15:56:39 +01:00
enjoy-digital
f34593a17d
Merge pull request #421 from betrusted-io/clk0_fractional
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add fractional division options to clk0 config on PLL
2020-03-13 14:15:24 +01:00
Florent Kermarrec
eb9f54b2bc
test: add initial (minimal) test for clock abstraction modules.
...
Also fix divclk_divide_range on S6DCM.
2020-03-13 12:38:23 +01:00
Florent Kermarrec
c304c4db27
targets/icebreaker: add description of the board, link to crowdsupply campagin and to the more complete example.
2020-03-13 09:37:42 +01:00
Piotr Esden-Tempski
d063acb767
Updating the vendored wavedrom js files.
2020-03-12 22:35:04 -07:00
Florent Kermarrec
a27385a79c
soc/intergration: rename mr_memory_x parameter to memory_x.
2020-03-12 12:20:48 +01:00
Piotr Esden-Tempski
4d02263223
Add --mr-memory-x parameter to generate memory regions memory.x file.
...
This file is used by rust embedded target pacs.
2020-03-11 18:12:18 -07:00
Florent Kermarrec
e9f0ff68ce
Merge branch 'master' of http://github.com/enjoy-digital/litex
2020-03-11 12:57:29 +01:00
Florent Kermarrec
979f98ea31
software: revert LTO changes (Disable it).
...
It seems LTO is not yet fully working with all configurations, so it's better
reverting the changes for now.
- cause issues with LM32 available compilers.
- seems to cause issues with min/lite variant of VexRiscv.
- seems to cause issues with some litex-buildenv configurations. (see https://github.com/enjoy-digital/litex/issues/417 ).
2020-03-11 12:57:00 +01:00
Sean Cross
01b6969375
Merge pull request #422 from xobs/core-doc-fixes
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Core doc fixes
2020-03-11 19:38:42 +08:00
enjoy-digital
4ccf62afc1
Merge pull request #423 from gsomlo/gls-ethmac-fixes
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integration/soc: add_ethernet: honor self.map["ethmac"], if present
2020-03-11 12:33:50 +01:00
Florent Kermarrec
bb8905fa5d
cores/gpio: add CSR descriptions.
2020-03-11 12:06:15 +01:00
Florent Kermarrec
4dabc5a625
cores/icap: add CSR descriptions.
2020-03-11 11:04:42 +01:00
Florent Kermarrec
77132a48b0
cores/spi: add CSR descriptions.
2020-03-11 10:58:32 +01:00
Florent Kermarrec
6d861c6e57
cores/pwm: add CSR descriptions.
2020-03-11 10:38:28 +01:00
Florent Kermarrec
cbc1f5949d
cores/xadc: add CSR descriptions.
2020-03-11 10:05:14 +01:00
Gabriel Somlo
a904034811
integration/soc: add_ethernet: honor self.map["ethmac"], if present
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-10 19:49:34 -04:00
Florent Kermarrec
846a2720b7
targets/kcu105: move cd_pll4x.
2020-03-10 17:02:28 +01:00
Florent Kermarrec
c97fabb285
targets/kcu105: simplify CRG using USIDELAYCTRL.
2020-03-10 16:48:07 +01:00
Florent Kermarrec
3c0b97eec8
cores/clock/USIDELAYCTRL: use separate reset/ready counters and set cd_sys.rst internally.
...
This is the behaviour that was duplicated in each target. Integrating it here
will allow simplifying the targets.
2020-03-10 16:46:54 +01:00
Sean Cross
a2f61b4e80
soc/cores/spi_opi: documentation fixes
...
The ModuleDoc-generated documentation for the spi_opi module produced
slightly invalid output due to ambiguities in how rst assigns headers.
As a result, sections from the spi_opi document would appear as full
sections.
This cleans up these errors so that it parses properly under sphinx.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-03-10 20:40:04 +08:00
Sean Cross
d2f6139dc7
soc/cores/i2s: fix rst parsing errors
...
The ModuleDoc-generated documentation for the i2s module produced
slightly invalid output due to ambiguities in how rst assigns headers.
As a result, sections from the i2s document would appear as full
sections.
This cleans up these errors so that it parses properly under sphinx.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-03-10 20:37:55 +08:00
Florent Kermarrec
bcbf558b6b
bios: add more Ultrascale SDRAM debug with sdram_cdly command to set clk/cmd delay.
2020-03-10 13:08:49 +01:00
bunnie
5b92bf2d57
add fractional division options to clk0 config on PLL
...
S7 MMCMs allow fractional divider on clock 0. Add a fallback
to try fractional values on clock 0 if a solution can't be found.
This is necessary for e.g. generating both a 100MHz and 48MHz
clock from a 12MHz source with margin=0
2020-03-10 18:48:30 +08:00
enjoy-digital
c4ce6da6c8
Merge pull request #419 from gsomlo/gls-ultra-sdram-fixup
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software/bios: fixup for Ultrascale SDRAM debug
2020-03-10 11:43:23 +01:00
Florent Kermarrec
b509068790
cores/clock: add logging to visualize clkin/clkouts and computed config.
2020-03-10 11:13:16 +01:00
Florent Kermarrec
04b8a91255
integration/soc: add FPGA device and System clock to logs.
2020-03-10 11:10:23 +01:00
Florent Kermarrec
02cba41d64
targets/icebreaker: create CRG after SoC.
2020-03-10 11:09:56 +01:00
Gabriel Somlo
4d15e1f7f8
software/bios: fixup for Ultrascale SDRAM debug
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Keep CSR accesses independent of csr_data_width and csr_alignment.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-09 15:32:08 -04:00
Florent Kermarrec
ba2f31d43d
integration/soc: set use_rom when cpu_reset_address is defined in a rom region.
2020-03-09 19:36:47 +01:00
Florent Kermarrec
8808c884c5
boards/platforms/icebreaker: cleanup a bit.
2020-03-09 19:16:02 +01:00
Florent Kermarrec
4656b1b2ad
software/common: fix LTO checks.
2020-03-09 19:08:27 +01:00
Florent Kermarrec
2a91deadcb
soc/cores/clock/iCE40PLL: add SB_PLL40_PAD support.
2020-03-09 19:03:05 +01:00
Florent Kermarrec
38d7f8a6e6
build/lattice/icestorm: add timingstrict parameter and default to False. (similar behavior than others backends)
2020-03-09 19:02:23 +01:00
Florent Kermarrec
1e9aa64387
targets/icebreaker: simplify, use standard VexRiscv, add iCE40PLL and run BIOS from SPI Flash.
2020-03-09 19:01:16 +01:00
Florent Kermarrec
197bdcb026
lattice/icestorm: enable DSP inference with Yosys and avoid setting SPI Flash in deep sleep mode after configuration which prevent running ROM CPU code from SPI Flash.
2020-03-09 16:51:18 +01:00
Florent Kermarrec
37869e38b8
boards: add initial icebreaker platform/target from litex-boards.
2020-03-09 11:56:55 +01:00
Florent Kermarrec
72af1b39eb
software/bios: add Ultrascale SDRAM debug functions.
2020-03-09 10:55:31 +01:00
Florent Kermarrec
6480d1803e
boards/platforms/kcu105: avoid unnecessary {{}} on INTERNAL_VREF.
2020-03-09 09:37:31 +01:00
Florent Kermarrec
b02c23391a
integration/soc/SoCRegion: add size_pow2 and use this internally for checks since decoder is using rounded size to next power or 2.
2020-03-08 19:17:31 +01:00
Florent Kermarrec
e801dc0261
soc: allow creating SoC without BIOS.
...
By default the behaviour is unchanged and the SoC will provide a ROM:
./arty.py
Bus Regions: (4)
rom : Origin: 0x00000000, Size: 0x00008000, Mode: R, Cached: True Linker: False
sram : Origin: 0x01000000, Size: 0x00001000, Mode: RW, Cached: True Linker: False
main_ram : Origin: 0x40000000, Size: 0x10000000, Mode: RW, Cached: True Linker: False
csr : Origin: 0x82000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False
The integrated rom can be disabled with:
./arty.py --integrated-rom-size=0
but the SoC builder will check for a user provided rom, and if not provided will complains:
ERROR:SoC:CPU needs rom Region to be defined as Bus or Linker Region.
When a rom is provided, the CPU will use the rom base address as cpu_reset_address.
If the user just wants the CPU to start at a specified address without providing a rom,
the cpu_reset_address parameter can be used:
./arty.py --integrated-rom-size=0 --cpu-reset-address=0x01000000
If the provided reset address is not located in any defined Region, an error will
be produced:
ERROR:SoC:CPU needs reset address 0x00000000 to be in a defined Region.
When no rom is provided, the builder will not build the BIOS.
2020-03-06 20:05:27 +01:00
Florent Kermarrec
ecca3d801d
integration/builder: rename software methods to _prepare_rom_software/_generate_rom_software/_initialize_rom_software.
2020-03-06 14:53:59 +01:00
Florent Kermarrec
69ffafd81d
integration/builder: generate csr maps before compiling software.
2020-03-06 14:20:32 +01:00
Florent Kermarrec
e2dab06386
Add SVD export capability to Builder (csr_svd parameter) and targets (--csr-svd argument) and fix svd regression.
...
This allows generating SVD export files during the build as we are already doing for .csv or .json.
Use with Builder:
builder = Builder(soc, csr_svd="csr.svd")
Use with target:
./arty.py --csr-svd=csr.svd
2020-03-06 14:12:58 +01:00
Florent Kermarrec
e124aed9a2
software/common.mak: fix LTO refactoring issue.
2020-03-05 23:42:36 +01:00
Karol Gugala
da580e31fd
Fix copyrights
...
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
2020-03-05 17:44:10 +01:00
Gabriel Somlo
020bef4197
targets/nexys4ddr: fix sdcard clocker initialization
2020-03-05 09:02:29 -05:00
enjoy-digital
9249fc90cf
Merge pull request #410 from antmicro/netv2-edid
...
platform/netv2: add proper I2C pins for HDMI IN0
2020-03-05 11:43:02 +01:00
Piotr Binkowski
72f63243cd
platform/netv2: add proper I2C pins for HDMI IN0
2020-03-05 11:27:47 +01:00
Florent Kermarrec
ad11ff39ad
targets/ecp5: make sure all BaseSoC/EthernetSoc default to trellis.
2020-03-05 11:19:29 +01:00
Florent Kermarrec
3770195048
bios/sdcard: update sdclk_mmcm_write with LiteSDCard clocker changes.
2020-03-04 18:33:08 +01:00
Florent Kermarrec
4c83c975b1
doc: align to improve readability.
2020-03-04 16:46:56 +01:00
Florent Kermarrec
4f935714de
soc/doc: remove soc.get_csr_regions support.
...
Now that SoC documentation is integrated in LiteX, this is no longer needed.
2020-03-04 16:27:11 +01:00
Florent Kermarrec
6893222cf1
bios/main: rename flushl2 command to flush_l2_cache, add flush_cpu_dcache command and expose them in help.
2020-03-04 15:53:18 +01:00
Florent Kermarrec
0b923aa497
build: assume vendor tools are in the PATH and remove automatic sourcing, source and toolchain_path parameters.
...
Automatic sourcing was not consistent between build backends (and only really supported by ISE/Vivado)
and had no real additional value vs the complexity needed to support it. Now just assume required vendor
tools are in the PATH.
This also removes distutils dependency.
2020-03-04 09:13:26 +01:00
Florent Kermarrec
1d7c6943af
software/common: add LTO enable flag and cleanup.
2020-03-04 08:11:21 +01:00
Florent Kermarrec
b29f443fe5
litex_sim: fix with_uart parameter.
2020-03-03 19:04:18 +01:00
Florent Kermarrec
98e41e2e0d
targets/nexys4ddr: add default kwargs parameters.
2020-03-02 09:44:20 +01:00
Florent Kermarrec
598ad692a0
Merge branch 'master' of https://github.com/enjoy-digital/litex
2020-03-02 09:31:45 +01:00
Florent Kermarrec
a67e19c660
integration/soc_core: change disable parameters to no-xxyy.
2020-03-02 09:31:32 +01:00
enjoy-digital
ddb264f3fd
Merge pull request #405 from sajattack/sifive-triple
...
add riscv-sifive-elf triple
2020-03-02 09:30:05 +01:00
Florent Kermarrec
156a85b15b
integration/soc: add auto_int type and use it on all int parameters.
...
Allow passing parameters as int or hex values.
2020-03-02 09:08:30 +01:00
Florent Kermarrec
7e96c911b9
targets/nexys4ddr: use SoCCore and add_sdram to avoid use of specific SoCSDRAM.
2020-03-02 09:01:05 +01:00
Florent Kermarrec
cb0371b330
integration/soc: add ethphy CSR in target.
2020-03-02 08:42:59 +01:00
Florent Kermarrec
f27225c2de
targets/nexys4ddr: use soc.add_ethernet method.
2020-03-01 21:21:01 +01:00
Florent Kermarrec
9735bd5bf2
integration/soc: add add_ethernet method.
2020-03-01 20:50:13 +01:00
Florent Kermarrec
1c74143a39
integration/soc: mode litedram imports to add_sdram, remove some separators.
2020-03-01 18:58:55 +01:00
Paul Sajna
68c013d13f
add riscv-sifive-elf triple
2020-03-01 01:39:03 -08:00
Florent Kermarrec
59e99bfbcd
soc/uart: add configurable UART FIFO depth.
2020-02-28 22:34:11 +01:00
Florent Kermarrec
9199306a65
cores/uart: cleanup
2020-02-28 22:12:05 +01:00
Florent Kermarrec
ea8563339f
soc/cores/uart/UARTCrossover: reduce fifo_depth to 1.
2020-02-28 22:03:40 +01:00
Florent Kermarrec
12a7528667
interconnect/stream/SyncFIFO: allow depth down to 0.
2020-02-28 21:54:02 +01:00
Florent Kermarrec
9e31bf357e
interconnect/axi: remove Record inheritance on AXIInterface/AXILiteInterface.
2020-02-28 16:33:18 +01:00
Florent Kermarrec
1e0e96f9a0
interconnect/axi: add AXI Stream definition and get_ios/connect_to_pads methods.
2020-02-28 16:25:09 +01:00
Florent Kermarrec
6be7e9c33d
interconnect/axi: set default data_width/address_width to 32-bit.
2020-02-28 13:20:01 +01:00
Florent Kermarrec
8e1d528663
targets: default to trellis toolchain on all ECP5 targets (now able to build all supported targets).
2020-02-28 09:48:48 +01:00
Florent Kermarrec
a7c5dd5d3e
cores/gpio: use separate TSTriple for each bit.
...
This fixes per bit OE control.
2020-02-28 09:10:28 +01:00
Florent Kermarrec
400492e234
lattice/yosys: don't use quiet operation since logs are useful and for consistency with others build backends.
2020-02-28 08:32:29 +01:00
Florent Kermarrec
c4fd6a7f2f
targets/kc705: use DDRPHY_CMD_DELAY to center write leveling.
2020-02-27 13:00:35 +01:00
Florent Kermarrec
78a3223573
software/bios/sdram: allow setting CLK/CMD delay from user design and configure it before write/read leveling.
...
Setting a manual delay on CLK/CMD vs DQ/DQS is required on some configuration to center the write leveling window:
Before (delay = 0 taps):
Write leveling:
m0: |11000000000000011111111111| delay: 15
m1: |00000000000000111111111111| delay: 14
m2: |11110000000000000111111111| delay: 17
m3: |11110000000000000011111111| delay: 18
m4: |11111111110000000000000111| delay: 00
m5: |11111111110000000000000111| delay: 00
m6: |11111111111000000000000001| delay: 00
m7: |11111111111000000000000011| delay: 00
After (delay = 12 taps):
Write leveling:
m0: |11111111111111000000000000| delay: 00
m1: |11111111111100000000000001| delay: 00
m2: |00011111111111110000000000| delay: 03
m3: |00011111111111110000000000| delay: 03
m4: |00000000111111111111110000| delay: 08
m5: |00000000111111111111110000| delay: 08
m6: |00000000001111111111111000| delay: 10
m7: |00000000001111111111111000| delay: 10
2020-02-27 12:26:27 +01:00
Florent Kermarrec
eab5161d47
boards: keep in sync with LiteX-boards
2020-02-27 11:18:14 +01:00
Florent Kermarrec
935e4effd2
interconnect/axi: remove mode on AXIInterface (not used and breaking LiteDRAM tests)
2020-02-26 15:13:29 +01:00
Florent Kermarrec
d324c54eee
integration/soc: -x on soc.py
2020-02-26 14:43:01 +01:00
Florent Kermarrec
ee27a9e534
soc/cores/bitbang: fix missing self.comb on miso.
2020-02-25 15:57:14 +01:00
enjoy-digital
a2d6986910
Merge pull request #402 from antmicro/litex-gen-fix-uart-pins
...
tools: litex_gen: fix missing UART pins
2020-02-25 15:53:13 +01:00
Florent Kermarrec
e2aebb427e
software: disable LTO with LM32 (not supported by old GCC versions easily available).
2020-02-25 15:32:36 +01:00
Jan Kowalewski
75b000a32f
tools: litex_gen: fix missing UART pins
2020-02-25 14:24:29 +01:00
Tim 'mithro' Ansell
718a65c3c9
software: enable link time optimization (LTO)
...
Co-authored-by: Pawel Czarnecki <pczarnecki@internships.antmicro.com>
2020-02-24 16:12:21 +01:00
Xiretza
7a87d4e262
Fix ECP5PLL VCO frequency range
...
See https://www.latticesemi.com/view_document?document_id=50461 ("ECP5
and ECP5-5G Family Data Sheet"), section 3.19 "sysCLOCK PLL Timing".
2020-02-24 14:39:59 +01:00
Florent Kermarrec
0c7e0bf025
integration/soc: improve presentation of SoCLocHandler's locations.
2020-02-24 13:37:38 +01:00
Florent Kermarrec
0042a02807
interconnect/axi: remove bus_name on connect_to_pads
2020-02-24 13:24:32 +01:00
Florent Kermarrec
5aba1fe824
tools/litex_gen: add bus parameter and AXI (Lite) support.
2020-02-24 12:49:42 +01:00
Florent Kermarrec
a3584147a5
litex_gen/axi: simplify the way the bus is exposed as ios and connected to pads.
2020-02-24 12:48:52 +01:00
Florent Kermarrec
d86db6f12b
litex_gen/wishbone: simplify the way the bus is exposed as ios and connected to pads.
2020-02-24 12:48:20 +01:00
Florent Kermarrec
18c57a64a3
tools: rename litex_extract to litex_gen (use similar name than litedram/liteeth generators) and cleanup/simplify.
2020-02-24 10:25:18 +01:00
enjoy-digital
0083e0978b
Merge pull request #396 from antmicro/external-wb
...
Add a script that allows to generate standalone cores
2020-02-24 10:01:16 +01:00
Gabriel Somlo
173117ad4b
Add 'volatile' qualifier to new CSR accessors
...
Through their use of the MMPTR() macro, the "classic"
csr_[read|write]simple() accsessors identify the MMIO
subregister with the 'volatile' qualifier.
Adjust the new, csr_[rd|wr]_uint[8|16|32|64]() accessors
to also utilize the 'volatile' qualifier. Since accesses
are implicit (a[i], where a is an 'unsigned long *'),
change 'a' to be a 'volatile unsigned long *' instead.
No difference was noticed in opcodes generated using the
gcc9 risc-v cross-compiler on x86_64 with standard LiteX
cflags (vexriscv and rocket were tested), but since
reports exist that 'volatile' matters on some combinations
of compilers and targets, add the 'volatile' qualifier just
to be on the safe side.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com
2020-02-21 14:10:13 -05:00
Piotr Binkowski
9e2aede8a8
tools: add script for extracting wishbone cores
2020-02-21 16:33:26 +01:00
Karol Gugala
79a14001b0
axi: add to_pads method
...
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2020-02-21 12:22:18 +01:00
Jan Kowalewski
e0bcb57d3d
wishbone: add extracting module signals to the top
2020-02-21 11:20:32 +01:00
Florent Kermarrec
53ee9a5e05
cpu/blackparrot: first cleanup pass
2020-02-20 18:50:13 +01:00
Florent Kermarrec
f3829cf081
integration/soc: set base_address on LiteDRAMWishbone2Native, fix addressing with >= 1GB SDRAMs.
2020-02-20 16:16:36 +01:00
Florent Kermarrec
3a6f97fff3
build/sim: add Verilator FST tracing support.
2020-02-20 13:53:31 +01:00
Gabriel Somlo
516cf40506
targets/nexys4ddr: add optional sdcard support
...
Add the option to select LiteSDCard support in BaseSoC, via the
'--with-sdcard' command line argument.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-02-19 20:16:13 -05:00
Gabriel Somlo
d4d2b7f7c6
bios: add litesdcard test routines to boot menu
...
This is a straightforward import of the sdcard initialization and
testing routines from the LiteSDCard demo example, made available
as mainline LiteX bios boot-prompt commands.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-02-19 20:16:13 -05:00
Gabriel Somlo
7a2e33b817
targets/nexys4ddr: add ethernet via method instead of inheritance
...
Switch adding LiteETH support to BaseSoc via a method instead of
inheritance. This allows further optional peripherals to be added
in the future, via additional methods.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-02-19 20:16:13 -05:00
Florent Kermarrec
774a55a2aa
soc_core: fix missing init on main_ram
2020-02-19 14:59:58 +01:00
enjoy-digital
5d580ca4e1
Merge pull request #389 from antmicro/linux_flash_offsets
...
bios/boot: allow to customize flash offsets of Linux images
2020-02-18 17:54:13 +01:00
Florent Kermarrec
00895518e5
cores/cpu: use standard+debug variant when only debug is specified.
2020-02-18 16:59:55 +01:00
Mateusz Holenko
659c244a0b
bios/boot: allow to customize flash offsets of Linux images
2020-02-18 13:38:09 +01:00
Florent Kermarrec
ae45be4773
soc/cores/clock: add reset_cycles parameter to S7IDELAYCTRL/USIDELAYCTRL
2020-02-18 10:15:01 +01:00
Florent Kermarrec
9baa3ad5bb
soc/csr_bus: fix aligned_paging computation (should be done with SoC's Bus data width not bus.alignment)
2020-02-18 09:13:32 +01:00
Florent Kermarrec
854e7cc908
integration/soc: improve Region logger
2020-02-18 08:27:59 +01:00
Florent Kermarrec
9cb8f68e82
bios/boot: update and fix flashboot, improve verbosity
2020-02-17 19:21:54 +01:00
Florent Kermarrec
6ed0f445b6
soc: increase supporteds address_width/paging
2020-02-17 08:36:40 +01:00
Florent Kermarrec
5b3808cb81
soc_core: expose CSR paging
2020-02-17 08:34:10 +01:00
Florent Kermarrec
0497f3ca71
soc/csr_bus: improve CSR paging genericity
2020-02-17 08:28:56 +01:00
Florent Kermarrec
351896bf57
tools/litex_sim: use new sdram verbosity parameter
2020-02-16 16:09:06 +01:00
Florent Kermarrec
67e8a042f8
integration/soc: add configurable CSR Paging
2020-02-16 12:32:05 +01:00
Florent Kermarrec
6576470179
soc_core: add back identifier
2020-02-15 19:04:47 +01:00
enjoy-digital
8f6114d0cd
Merge pull request #387 from BracketMaster/master
...
litex_sim now working on MacOS and Linux
2020-02-15 17:05:50 +01:00
Yehowshua Immanuel
3da204edd6
update to work with mac
2020-02-15 10:37:39 -05:00
Florent Kermarrec
3574b90924
tools/litex_sim: specify default local/remote-ip addresses.
2020-02-15 14:04:44 +01:00
Florent Kermarrec
aebaea7764
tools/litex_sim: add ethernet local/remote-ip arguments.
2020-02-15 14:01:56 +01:00
Florent Kermarrec
18a9d4ff2f
interconnect/stream: cleanup imports/idents
2020-02-14 08:08:19 +01:00
Piotr Binkowski
eff85a99bb
tools/litex_sim: add cli options to control SDRAM timing checker
2020-02-13 14:45:15 +01:00
Florent Kermarrec
e4712ff7f3
soc_core: fix cpu_variant renaming regression
2020-02-13 08:34:39 +01:00
Sean Cross
baa29f1b03
doc: fix regression with new irq manager
...
Previously, we were accessing the `soc.soc_interrupt_map` property in
order to be able to enumerate the interrupts. This has been subsumed
into a more general `irq` object that manages the interrupts.
Use `soc.irq.locs` instead of `soc.soc_interrupt_map` as the authority
on interrupts for both doc and export.
This fixes #385 .
Signed-off-by: Sean Cross <sean@xobs.io>
2020-02-13 08:32:44 +08:00
Florent Kermarrec
1620f9c5b0
soc/CSR: show alignment in report and add info when updating.
2020-02-12 21:55:30 +01:00
Florent Kermarrec
5b34f4cd34
soc/add_cpu: use cpu.data_width as CSR alignment, fix regression on Rocket
2020-02-12 21:25:52 +01:00
Florent Kermarrec
2f69f607e3
integration/soc: fix refactoring issues
2020-02-12 18:16:38 +01:00
Florent Kermarrec
1d6ce66bf7
soc/integration/builder: update copyright, align arguments
2020-02-12 16:43:11 +01:00
Xiretza
b56545791c
Unify output directory handling in builder
2020-02-12 15:47:16 +01:00
Florent Kermarrec
e9c665a539
soc_core/soc_sdram: add disclaimer
2020-02-11 18:28:05 +01:00
Florent Kermarrec
5558865cbf
soc_core: provide full retro-compatibily when add_wb_slave is called before add_memory_region
2020-02-11 18:21:41 +01:00
Florent Kermarrec
1b5caf56fb
soc: fix busword typo
2020-02-11 17:57:05 +01:00
Florent Kermarrec
8b5cc34553
targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC)
2020-02-11 17:44:24 +01:00
enjoy-digital
240a55bace
Merge branch 'master' into new_soc
2020-02-11 17:22:06 +01:00
Florent Kermarrec
d5ad1d56f2
soc/integration: move mem_decoder to soc_core
2020-02-11 17:19:22 +01:00
Florent Kermarrec
0a737cb624
soc/integration/common: simplify get_version
2020-02-11 17:16:24 +01:00
Florent Kermarrec
399b65fa17
soc/add_uart: fix bridge
2020-02-11 16:55:37 +01:00
Florent Kermarrec
160c55d1d4
soc_core/soc_sdram: remove disclaimer (we'll add it later when designs will be adapted)
2020-02-11 16:44:25 +01:00
Florent Kermarrec
b2c66b1efd
soc: avoid double definition of main_ram
2020-02-11 16:39:37 +01:00
Florent Kermarrec
5f9946085b
soc: improve log colors on error reporting
2020-02-11 16:24:57 +01:00
Florent Kermarrec
b22d2ca02b
soc: add linker regions management
2020-02-11 15:28:02 +01:00
Florent Kermarrec
abc31a92c6
soc: improve log presentation/colors
2020-02-11 14:50:16 +01:00
Florent Kermarrec
91e2797bb4
soc: fix cpu_reset_address
2020-02-11 14:17:32 +01:00
Florent Kermarrec
0d7430fc69
tools/litex_sim_new: remove
2020-02-11 14:05:01 +01:00
Florent Kermarrec
21d38701df
soc: fix build_time format
2020-02-11 13:23:53 +01:00
Florent Kermarrec
4d761e1afd
cores/cpu: remove separators on io_regions (requires python 3.6)
2020-02-11 13:12:54 +01:00
Florent Kermarrec
b43d830fda
soc/add_sdram: simplify L2 Cache, use FullMemoryWE on L2 Cache by default (seems better on all devices)
2020-02-11 09:30:45 +01:00
Florent Kermarrec
ea8e745ac2
soc_core/common: move old mem_decoder to soc_core, simplify get_version
2020-02-11 08:44:23 +01:00
Xiretza
e301df7f56
Allow all memory regions to be used as IO with CPUNone
2020-02-10 19:56:36 +01:00
Florent Kermarrec
16d1972bf8
integration/common: fix mem_decoder (shadow base has been deprecated)
2020-02-10 19:40:56 +01:00
Florent Kermarrec
5e11e8391f
tools/litex_sim_new: switch to dynamically allocated ethmac origin
2020-02-10 19:37:53 +01:00
Florent Kermarrec
dd0c71d7a1
soc/SoCRegion/Decoder: pass bus to decoder and remove mask on origin
2020-02-10 19:34:18 +01:00
Florent Kermarrec
e8e4537e14
soc/add_sdram: avoid L2 cache when l2_cache_size == 0.
2020-02-10 19:02:44 +01:00
Florent Kermarrec
dcbdb73231
soc: remove unneeded \n
2020-02-10 18:38:59 +01:00
Florent Kermarrec
0f1811fb51
tools/litex_sim_new: use new bus/csr/irq methods
2020-02-10 18:21:41 +01:00
Florent Kermarrec
d320be8ecb
soc: use io_regions for alloc_region
2020-02-10 18:19:35 +01:00
Florent Kermarrec
9ac09ddde5
tools: add litex_sim_new based on SoCCore and using add_sdram method
2020-02-10 18:00:46 +01:00
Florent Kermarrec
cbcd953dd7
soc_core: use add_rom
2020-02-10 17:43:29 +01:00
Florent Kermarrec
487ac3da9a
soc/add_cpu: simplify CPUNone integration
2020-02-10 17:40:46 +01:00
Florent Kermarrec
f7d4648ca1
soc/SoCBusHandler: add add_adapter method and use it to convert Master/Slave before connecting to the Bus
2020-02-10 17:17:31 +01:00
Florent Kermarrec
379d47a843
soc/add_sdram: add sdram csr
2020-02-10 17:02:20 +01:00
Florent Kermarrec
3921b6345c
soc/add_sdram: fix rocket, shorten comments
2020-02-10 16:55:15 +01:00
Florent Kermarrec
14b627b466
soc/add_sdram: improve API
2020-02-10 16:38:20 +01:00
Florent Kermarrec
1faefdc0fa
soc: add LiteXSoC class and mode add_identifier/uart/sdram to it
2020-02-10 16:28:11 +01:00
Florent Kermarrec
11dbe19084
soc_core/sdram: cleanup, add disclaimer
2020-02-10 16:21:21 +01:00
Florent Kermarrec
5eb88cd904
soc: add add_sdram
2020-02-10 16:01:19 +01:00
Florent Kermarrec
39011593ac
soc: add csr_regions, update copyright
2020-02-10 15:11:37 +01:00
Florent Kermarrec
d2b069516a
soc: add cpu rom/sram check
2020-02-10 14:48:46 +01:00
Florent Kermarrec
de100fddf5
soc: add SOCIORegion and manage it
2020-02-10 14:36:53 +01:00
Florent Kermarrec
6b8c425f9b
soc: reorder main components/peripherals
2020-02-10 13:07:09 +01:00
Florent Kermarrec
84b5df7871
soc: add add_cpu method
2020-02-09 21:56:32 +01:00
Florent Kermarrec
7ee9ce38a7
.gitmodules/black-parrot: switch to https://github.com/enjoy-digital/black-parrot (without the submodules)
2020-02-09 19:53:04 +01:00
Florent Kermarrec
b676a559fd
soc: fix unit-tests
2020-02-09 19:01:03 +01:00
Florent Kermarrec
0a5883901a
soc: integrate constants/build
2020-02-08 22:08:37 +01:00
Florent Kermarrec
014d5a56a8
soc: show sorted regions (by origin) / locs
2020-02-08 21:34:26 +01:00
Florent Kermarrec
c69b6b7c12
soc: simplify color theme
2020-02-08 21:30:34 +01:00
enjoy-digital
1dced8183e
Merge pull request #278 from scanakci/blackparrot_litex
...
Blackparrot litex
2020-02-08 10:30:55 +01:00
Florent Kermarrec
3cb90297ac
soc: add add_uart method
2020-02-08 10:19:18 +01:00
Florent Kermarrec
e5cacb8bbd
soc_core: cleanup imports
2020-02-07 23:16:29 +01:00
Florent Kermarrec
33d498b826
soc_core: get_csr_address no longer used
2020-02-07 23:11:08 +01:00
Florent Kermarrec
1feff1d7d5
soc: integrate CSR master/interconnect/collection and IRQ collection
2020-02-07 19:50:35 +01:00
Florent Kermarrec
3ba7c29ed9
soc: add add_constant/add_config methods
2020-02-07 19:09:54 +01:00
Florent Kermarrec
29bbe4c02a
soc: add add_csr_bridge method
2020-02-07 18:49:20 +01:00
Florent Kermarrec
b84c291c34
soc: add add_controller/add_identifier/add_timer methods
2020-02-07 18:31:50 +01:00
Florent Kermarrec
9445c33e9d
soc: add add_ram/add_rom methods
2020-02-07 16:06:32 +01:00
Florent Kermarrec
e5a8ac1dab
soc: add automatic bus data width convertion to add_master/add_slave
2020-02-07 15:31:59 +01:00
Florent Kermarrec
8f67f1157d
soc/soc_core: cleanup, remove some unused attributes
2020-02-07 15:19:02 +01:00
Florent Kermarrec
2c6e5066a7
soc: move SoCController from soc_core to soc
2020-02-07 14:52:53 +01:00
Florent Kermarrec
848fa20d1e
soc: create SoCLocHandler and use it to simplify SoCCSRHandler and SoCIRQHandler
2020-02-07 13:25:54 +01:00
Florent Kermarrec
39458c92eb
soc: add use_loc_if_exists on SoCIRQ.add to use current location is already defined
2020-02-06 19:50:44 +01:00
Florent Kermarrec
1eff0799a4
soc: add use_loc_if_exists on SoCCSR.add to use current location is already defined
2020-02-06 18:50:17 +01:00
Florent Kermarrec
8bc420679a
soc/integration: initial adaptation to new SoC class
2020-02-06 18:21:13 +01:00
Florent Kermarrec
1d70ef6958
soc/cores/spi_opi: cleanup, rename to S7SPIOPI (since 7-Series specific for now)
2020-02-06 17:58:01 +01:00
Florent Kermarrec
62f3537db0
soc/cores: rename spiopi to spi_opi
2020-02-06 17:08:00 +01:00
Florent Kermarrec
f58e8188b7
soc/cores/i2s: cleanup pass, rename to S7I2SSlave (since 7-Series specific for now), rename fifodepth to fifo_depth for consistency with others cores.
2020-02-06 17:00:04 +01:00
enjoy-digital
c2c80b5d0a
Merge pull request #378 from betrusted-io/merge_ip
...
Request to merge I2S and SPIOPI cores
2020-02-06 16:29:33 +01:00
bunnie
98e46c2708
reduce indents
2020-02-06 21:55:44 +08:00
Florent Kermarrec
6baa07a69b
soc/integration: add new soc class prorotype with SoCRegion/SoCBus/SoCCSR/SoCIRQ/SoC
2020-02-06 11:06:41 +01:00
bunnie
d2b394a9be
update doc comments on events for i2s
2020-02-06 17:58:02 +08:00
bunnie
416afd3109
add doc comment for event
2020-02-06 17:56:21 +08:00
bunnie
33d9e45a8b
fix formatting on spiopi
...
Pycharm really butchered the code when I did a copy-and-paste...
it has questionable default formatting preferences.
2020-02-06 17:54:26 +08:00
Florent Kermarrec
9b11e9192d
cpu/vexriscv: update submodule
2020-02-06 10:50:35 +01:00
bunnie
cc6ed667df
Request to merge I2S and SPIOPI cores
2020-02-06 17:25:00 +08:00
enjoy-digital
5ff02e23a0
Merge pull request #375 from xobs/add-lxsocdoc
...
Add lxsocdoc
2020-02-05 10:15:21 +01:00
Florent Kermarrec
1944d8d9d0
bios/main: add LiteX tagline
2020-02-04 19:14:23 +01:00
Mariusz Glebocki
90fe585003
build/sim: allow to use environment's {C,LD}FLAGS
...
There are use cases where additional flags should be added to CFLAGS or
LDFLAGS, e.g. when using Conda environment.
2020-02-04 17:31:31 +01:00
Sean Cross
58598d4fda
integration: svd: move svd generation to export
...
It was suggested that we should move svd generation into `export`,
alongside the rest of the generators such as csv, json, and h. This
performs this move, while keeping a compatible `generate_svd()` function
inside `soc/doc/`.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-02-04 23:49:08 +08:00
Sean Cross
73ed7e564c
soc: doc: use sphinx toctree as it was intended
...
The sphinx toctree was behaving oddly, and so previously we were
ignoring it completely. This patch causes it to be used correctly,
which removes the need for double-including various sections.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-02-04 20:34:10 +08:00
Sean Cross
7c3bc0b09f
litex-doc: initial merge of lxsocdoc
...
lxsocdoc enables automatic documentation of litex projects, including
automatic generation of SVD files.
This merges the existing lxsocdoc distribution into the `soc/doc` directory.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-02-04 20:14:41 +08:00
Piotr Binkowski
f3b068e2ee
tools/litex_sim: use l2_reverse flag
2020-02-03 12:03:57 +01:00
Florent Kermarrec
3350d33f9c
wishbone/Cache: add reverse parameter
2020-01-31 19:31:33 +01:00
Florent Kermarrec
eff9caee6a
soc_sdram: add l2_reverse parameter
2020-01-31 19:18:07 +01:00
Vadim Kaushan
de88ed282a
Fix argument descriptions
2020-01-31 18:54:25 +03:00
Vadim Kaushan
eb49ec217e
Pass --csr-json to the Builder
2020-01-31 18:53:50 +03:00
Florent Kermarrec
b69f2993e4
soc_core: add UART bridge support (simplify having to do it externally)
2020-01-31 15:12:18 +01:00
Florent Kermarrec
7a6c04db9e
build/altera/quartus: fix fmt_r typo
2020-01-30 13:55:13 +01:00
Florent Kermarrec
c6b9676db8
cpu/minerva: update (use new nMigen API)
2020-01-30 13:42:02 +01:00
Florent Kermarrec
9d2894727e
inteconnect/stream: use PipeValid implementation for Buffer
2020-01-30 09:36:04 +01:00
Florent Kermarrec
1c88c0f896
inteconnect/stream: cleanup
2020-01-30 09:32:04 +01:00
enjoy-digital
cafd9c358a
Merge pull request #366 from gsomlo/gls-csr-followup
...
software, integration/export: (re-)expose CSR subregister accessors
2020-01-30 08:18:12 +01:00
Gabriel Somlo
ff2775c264
software, integration/export: (re-)expose CSR subregister accessors
...
Expose a pair of `csr_[read|write]_simple()` subregister accessors, and
restore the way dedicated accessors are generated in "generated/csr.h"
to use hard-coded combinations of shifts and subregister accessor calls.
This restores downstream ability to override CSR handling at the
subregister accessor level.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-01-29 14:29:24 -05:00
Florent Kermarrec
f3f9808d1f
interconnect/stream: add PipeValid and PipeWait to cut timing paths.
2020-01-29 18:27:29 +01:00
Florent Kermarrec
b22ad1acfb
build/xilinx/vivado: improve readability of generated tcl/xdc files
2020-01-29 16:27:18 +01:00
Florent Kermarrec
7bc34a9bc7
integration/soc_core: revert integrate_sram_size default value (cause issues when using External SPRAM).
...
When using SoCCore, integrated SRAM can be disabled with integrated_sram_size=0 if not wanted.
2020-01-29 08:31:41 +01:00
Piotr Binkowski
c02dd5e8f9
tools/litex_sim: add ddr4 PhySettings
2020-01-28 14:28:24 +01:00
Florent Kermarrec
0820adbda1
tools/litex_sim: add --sdram-init parameter
2020-01-27 21:30:13 +01:00
Florent Kermarrec
01ae10b803
software/bios: revert M-Labs MiSoC copyright.
2020-01-27 13:12:37 +01:00
Florent Kermarrec
ea5ef8c1be
README: update copyright year and make sure LICENSE/README both mention MiSoC
2020-01-27 12:15:11 +01:00
Florent Kermarrec
95cfa6a82c
platforms/netv2: add pcie pins
2020-01-27 08:25:57 +01:00
Greg Davill
1f43906236
soc/software/bios/sdram: ECP5 move strobe dly_sel
2020-01-26 09:55:38 +10:30
Greg Davill
f84f57d651
soc/software/bios/sdram: On ECP5 strobe dly_sel after read leveling
2020-01-25 13:11:39 +10:30
Florent Kermarrec
52765488b5
tools/litex_sim: update copyrights and cosmetic changes
2020-01-24 13:58:49 +01:00
enjoy-digital
b280bb2ff2
Merge pull request #358 from antmicro/litex_sim_ddr
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tools/litex_sim: add support for other sdram types
2020-01-24 13:33:03 +01:00
Piotr Binkowski
9aa97c2e0c
tools/litex_sim: add support for other sdram types (DDR, LPDDR, DDR2, DDR3)
...
Right now litex_sim supports only SDR memories because it uses hardcoded
PhySettings. With this change PhySettings will be generated based on
selected sdram type which will allow us to use all the different types
of sdram chips in simulation.
2020-01-24 12:30:35 +01:00
Florent Kermarrec
19ef19ce0d
cores/clock/create_clkout: rename clk_ce to ce, improve error reporting
2020-01-24 09:10:31 +01:00
enjoy-digital
7e08836062
Merge pull request #357 from betrusted-io/add_clk_ce
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Add clk ce
2020-01-24 09:01:57 +01:00
bunnie
1f7549b4c0
add BUFIO to clockgen buffer options
2020-01-24 15:01:13 +08:00
bunnie
b3f9aa11be
add option for BUFGCE to the clock generator buffer types
2020-01-24 14:58:51 +08:00
Florent Kermarrec
cbc081c43d
tools/litex_sim: review/cleanup sdram-module/sdram-data-width features.
2020-01-23 15:42:47 +01:00
enjoy-digital
b35ea459e7
Merge pull request #354 from antmicro/litex_sim_ddr
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tools/litex_sim: specify dram chip and data width via commandline
2020-01-23 15:34:53 +01:00
Piotr Binkowski
674cfcde7d
tools/litex_sim: specify dram chip and data width via commandline
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litex_sim used a single predefined DRAM chip, with this it is now
possible to specify which one to use with --sdram-module and also
its data bus width can be set using --sdram-data-width
2020-01-23 14:41:37 +01:00
enjoy-digital
b23f13d960
Merge pull request #351 from antmicro/fix_sram_size_argument
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Fix sram size argument
2020-01-23 14:16:02 +01:00
Mateusz Holenko
7a05353aa7
soc_core: rename integrated_sram_size argument
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To keep a consistent naming scheme across all arguments.
2020-01-23 13:46:09 +01:00
Mateusz Holenko
c4bb4169f1
soc_core: fix integrated_sram_size argument type
...
Right now it's kept as a string and crashes
when trying to do math operations on it.
2020-01-23 13:45:16 +01:00
Florent Kermarrec
5845df76cc
build/xilinx/vivado: add pre_placement/pre_routing commands
2020-01-21 19:00:58 +01:00
Florent Kermarrec
1388088240
cores/icap: add add_timing_constraints method
2020-01-21 14:08:36 +01:00
Florent Kermarrec
2074a86ee3
cores/dna: cleanup and add add_timing_constraints method
2020-01-21 14:08:17 +01:00
Florent Kermarrec
d39dc8cf5d
tools/litex_sim: cleanup/simplify
2020-01-20 21:22:41 +01:00
Florent Kermarrec
a0d95766ac
build/sim: add -Wl,--no-as-needed to LDFLAGS for Ubuntu 16.04 support (thanks kamejoko80)
2020-01-20 12:55:38 +01:00
Florent Kermarrec
80c3dc41d3
targets: use mem_region.origin instead of mem_map definition (prepare for automatic mem_region allocation)
2020-01-20 12:10:00 +01:00
Florent Kermarrec
53bc18cc3f
soc_core: add new alloc_mem/add_mem_region to allow automatic allocation of memory regions
...
With add_memory_region, user needs to provide the memory origin, which should not be needed since
could be retrieved from mem_map and prevent automatic allocation which is already possible for csr
and interrupts.
New add_mem_region method now allows both: defining the memory origin in mem_map (which will then
be used) or let the SoC builder automatically find and allocate a memory region.
2020-01-20 12:05:08 +01:00
bunnie
eae0e00496
cores/clock/xadc: ease DRP timings
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Hard IP blocks are fixed in location, so long/deep combinational paths routing to multiple hard IP blocks can lead to timing closure problems.
XADC and MMCM DRPs currently have their DEN pins triggered by the ".re" output of a CSR. This is asynchronously derived from a fairly complicated set of logic that involves a logic path that goes all the way back through the cache and arbitration mechanisms of the wishbone bus. On more complex designs, this is leading to a failure of timing closure for these paths, because the hard IP blocks can be located in disparate portions of the chip which "pulls" the logic cluster in opposite directions in an attempt to absorb the routing delays to these IP blocks, leading to non-optimal placement for everything else and thus timing closure problems.
This pull request proposes that we add a pipeline delay on these critical paths. This delays the commit of the data to the DRP by one cycle, but greatly relieves timing because the pipeline register can be placed close to the cluster of logic that computes addresses, caching, and arbitration, allowing for the routing slack to the hard IP blocks to be absorbed by the path between the pipe register and the hard IP block.
In general, this shouldn't be a problem because the algorithm to program the DRP is to hit the write or read CSR, and then poll the drdy bit until it is asserted (so the process is already pretty slow). The MMCM in particular should have almost no impact, because MMCM updates are infrequent and the subsequent lock time of the MMCM is pretty long. The XADC is potentially more problematic because it can produce data at up to 1MSPS; but if sysclk is around 100MHz, adding 10ns to the read latency is relatively small compared to the theoretical maximum data rate of one every 1,000ns.
Note that the xadc patch requires introducing a bit of logic into the non-DRP path. This is because without explicitly putting an "if" statement around the logic, you fall back to the non-blocking semantics of the verilog operator, which ultimately leads to a pretty hefty combinational path. By having a default "if" that should get optimized out when DRP is not enabled, when the DRP path /is/ enabled the synthesizer knows it can safely push the async signal into a simple mux as opposed to worrying about enforcing the non-blocking operator semantics to get the desired result.
2020-01-19 20:57:14 +01:00
Florent Kermarrec
008a089471
targets/nexys4ddr: fix typo
2020-01-17 13:17:08 +01:00
Florent Kermarrec
36e5274a2b
SoCSDRAM: set default max_sdram_size to 1GB (maximum we can map with current mem_map)
2020-01-17 12:45:23 +01:00
Florent Kermarrec
46c1c5c16f
targets/kcu105: remove main_ram_size_limit
2020-01-17 12:27:21 +01:00
Florent Kermarrec
5913c91caa
SoCSDRAM: rename main_ram_size_limit to max_sdram_size and make it a parameter of SoCSDRAM, expose SoCSDRAM parameters to user
2020-01-17 12:16:08 +01:00
Florent Kermarrec
1c465f89b6
build/lattice: add add_false_path_constraint method for API compatibility but false paths are not yet used/translated to .lpf file
2020-01-17 10:17:19 +01:00
Florent Kermarrec
b4ba2a47ef
soc/cores/uart: set rx_fifo_rx_we to True on UARTCrossover
2020-01-17 06:32:00 +01:00
sadullah
d15c911cac
BlackParrot initial commit
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w/ Litex BIOS simulation including LiteDRAM
w/ Litex BIOS working on FPGA excluding LiteDRAM
2020-01-16 19:13:02 -05:00
Florent Kermarrec
5aa516cb8d
soc/cores/uart: add rx_fifo_rx_we parameter to pulse rx_fifo.source.ready on rxtx register read.
...
When UARTCrossover is used over Etherbone, acking data directly with the read avoid the write/read round-trip
and speed up communication a lot (>10x).
2020-01-16 19:45:41 +01:00
Florent Kermarrec
862e784eae
cpu/vexriscv: use 32-bit signal for externalResetVector
2020-01-16 16:20:25 +01:00
Florent Kermarrec
f2a1673f46
targets/arty/genesys2: fix EthernetSoC/EtherboneSoC selection
2020-01-16 13:17:33 +01:00
Florent Kermarrec
990870d061
targets/genesys2: add EtherboneSoC
2020-01-16 12:32:59 +01:00
Florent Kermarrec
820e79bf9c
platforms/de0nano: specify gpio for serial
2020-01-16 12:32:25 +01:00
Florent Kermarrec
ba366d42d0
targets: cleanup EthernetSoC
2020-01-16 10:14:42 +01:00
Florent Kermarrec
a26853702c
soc/interconnect/packet/Depacketizer: use both sink.valid and sink.ready to update sink_d, fix Etherbone regression on Arty.
2020-01-16 09:46:54 +01:00
Florent Kermarrec
a168ecbabd
targets/arty: add EtherboneSoC
2020-01-16 09:11:44 +01:00
Florent Kermarrec
7a4ecfa59d
targets/kcu105: update
2020-01-15 13:17:59 +01:00
Florent Kermarrec
42efa99826
SoCCore: set default integrated_rom/ram_size to 0. For targets, defaults values are provided by soc_core_args.
2020-01-15 10:59:01 +01:00
Florent Kermarrec
4050e60834
SoCCore: use hex for integrated_rom/sram_size
2020-01-13 20:01:45 +01:00
enjoy-digital
f818755c9c
Merge pull request #339 from gsomlo/gls-csr-cleanup
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CSR Improvements and Cleanup
2020-01-13 19:57:59 +01:00
Florent Kermarrec
f1606dbc72
tools/litex_sim: use default integrated_rom_size
2020-01-13 17:39:23 +01:00
Florent Kermarrec
4648db0c2a
cores/uart/UARTInterface: remove connect method
2020-01-13 16:58:00 +01:00
Florent Kermarrec
6c9f418d26
soc_core: fix uart stub
2020-01-13 16:56:31 +01:00
Gabriel Somlo
b073ebadf6
bios/sdram: switch to updated CSR accessors, and misc. cleanup
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Revert to treating SDRAM_DFII_PIX_[RD|WR]DATA CSRs as arrays
of bytes, but use the new uintX_t array accessors for improved
legibility, and to avoid unnecessary byteswapping.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-01-13 10:09:02 -05:00
Gabriel Somlo
2c39304110
software, integration/export: rename and reimplement CSR accessors
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Implement CSR accessors for all standard integer types and
combinations of subregister alignments (32 or 64 bit) and
sizes (i.e., csr_data_width 8, 16, or 32).
Rename accessors to better reflect the size of the register
being accessed, and correspondingly update the generation
of "csr.h" in "export.py".
Additionally, provide read/write accessors that superimpose arrays
of standard unsigned C types over a CSR register (which may itself
be spread across multiple subregisters).
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-01-13 10:09:02 -05:00
Florent Kermarrec
63cd23c9c3
cpu/vexriscv: revert mem_map_linux/main_ram
2020-01-13 16:02:32 +01:00
Florent Kermarrec
83a7225ccc
SoCCore: set integrated rom/sram size default values in soc_core_args and use it in targets
2020-01-13 15:03:36 +01:00
Florent Kermarrec
6e3f25a7e0
cpu/vexriscv/mem_map_linux: update main_ram to 0x40000000
2020-01-13 14:40:26 +01:00
Florent Kermarrec
fe14b9cf86
targets/genesys2: update self.register_sdram
2020-01-13 14:39:45 +01:00
Florent Kermarrec
39ce39a298
soc_sdram: add l2_data_width parameter to set minimal l2_data_width to improve DRAM accesses efficiency.
2020-01-13 13:00:17 +01:00
Florent Kermarrec
23175190d8
cores/uart: add UARTCrossover
2020-01-13 10:14:38 +01:00
Florent Kermarrec
2f03d3234e
cores/uart/UART: add stream interface (phy=None), add connect method and use this for UART Stub/Crossover.
...
A bridged/crossover UART can now just be created by:
- passing uart_name="stream" to SoCCore/SoCSDRAM.
- adding a crossover UART core to the design:
# UART Crossover (over Wishbone Bridge
from litex.soc.cores.uart import UART
self.submodules.uart_xover = UART(tx_fifo_depth=2, rx_fifo_depth=2)
self.add_csr("uart_xover")
self.comb += self.uart.connect(self.uart_xover)
2020-01-13 09:20:40 +01:00
Florent Kermarrec
d92bd8ffaa
gen/fhdl/verilog: fix signed init values
2020-01-12 22:06:35 +01:00
enjoy-digital
ff066a5e09
Merge pull request #338 from DurandA/master
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Add optional 'ignore-loops' flag to nextpnr
2020-01-12 21:18:23 +01:00
Florent Kermarrec
26fe45fce1
cores/uart: rename BridgedUART to UARTEmulator and rework/simplify it. Also integrated it in SoCCore with uart_name="emulator"
2020-01-12 21:13:02 +01:00
Sean Cross
5079a3c32e
uart: add BridgedUart
...
This version of the UART adds a second, compatible UART after
the first. This maintians software compatibility, and allows a
program running on the other side of the litex bridge to act as
a terminal emulator by manually reading and writing the second
UART.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-01-12 19:52:42 +10:00
Arnaud Durand
d24a4b5428
Add optional 'ignore-loops' flag to nextpnr
2020-01-10 16:07:56 +01:00
Florent Kermarrec
f70dd48279
bios/sdram: add memspeed
2020-01-10 14:25:46 +01:00
Florent Kermarrec
fa22d6aa82
wishbone/Cache: avoid REFILL_WRTAG state to improve speed.
2020-01-10 14:25:07 +01:00
Florent Kermarrec
f408527dd4
soc/cores/cpu: add riscv64-linux toolchain support for risc-v cpus.
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Toolchain can be downloaded from https://toolchains.bootlin.com/
2020-01-10 08:49:34 +01:00
Florent Kermarrec
8889821c54
targets: sync with litex-boards
2020-01-09 21:12:00 +01:00
Florent Kermarrec
aba8fc5c94
build/altera/quartus: allow multiple call of add_period_constraint if constraint is similar.
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Similar to the changes already applied to Xilinx backend.
2020-01-09 19:45:51 +01:00
enjoy-digital
e318287ec2
Merge pull request #337 from gregdavill/spi-flash
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soc/cores/spi_flash: Don't tristate DQ2/DQ3 when bitbanging
2020-01-09 13:24:17 +01:00
Greg Davill
49781467d7
soc/cores/spi_flash: Don't tristate DQ2/DQ3 when bitbanging
2020-01-09 21:53:00 +10:30
Florent Kermarrec
2cf95e9f93
platforms/minispartan6: rename sd to sdcard and regroup data lines
2020-01-09 11:12:37 +01:00
Florent Kermarrec
e99740e814
platforms/nexys4ddr: add sdcard pins
2020-01-09 11:00:54 +01:00
Florent Kermarrec
83ad674feb
build/lattice/trellis: use a single fonction to parse device
2020-01-08 19:38:27 +01:00
Konrad Beckmann
426ab676e8
trellis: Pass speed grade argument to nextpnr
2020-01-08 08:42:29 +01:00
enjoy-digital
fd4cbd8053
Merge pull request #331 from betrusted-io/xadc_mods
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WIP: add support for DRP on XADC
2020-01-06 18:09:12 +01:00
Florent Kermarrec
378722a7ef
soc/cores/xadc: define analog_layout and simplify analog_pads connections
2020-01-06 16:28:48 +01:00
bunnie
87d456cae2
bring back analog_pads specifier, remove reset conditions on VP
...
For the "P" side of the analog channels, actually, connecting
a digital line to them has "no meaning". The docs say that
either you connect an analog pin to a pad, or vivado "ties it off
appropriately". I wish it were the case that tying a pin to 0 or 1
would actually connect it to a power or ground, because it means
that even in unipolar mode you have to burn two pins to break out
the signal of interest *and* the ground reference analog pad
(I thought I could just connect it to "0" and the pin would be
grounded, but that doesn't happen -- it's just ignored if it's
not wired to a pad).
For the pad specifier, is it OK to leave it with an optional
argument of analog_pads=None? I tried assigning to the
self.analog property after instantiation, but this doesn't
seem to work, the default values are preferred. It looks like
if you don't want to do the analog_pads= optional argument
the other way to do it would be to add code on the instiating
module that tampers with the properties of the instance directly,
but I think that's sort of ugly.
Also, I noticed you stripped out the layout specifier for
the analog_pads. I thought it would be nice to provide that
in the file, so the caller doesn't have to infer what the
pad layout is by reading the code...what's the motivation for
removing that?
2020-01-06 21:47:58 +08:00
Florent Kermarrec
642d073700
cpu/minerva: fix variant syntax warning
2020-01-05 21:04:27 +01:00
Florent Kermarrec
4dc0a61428
soc/core/xadc: cleanup, simplify and add expose_drp method - keep CSR ordering with older version, requested for software compatibility. - always enable analog capability (user will just not use it if not needed). - add expose_drp method (similar to clock.py) for cases where DRP is needed.
2020-01-05 09:13:14 +08:00
Gabriel Somlo
d087e2e0af
interconnect/csr_bus/SRAM: allow 64-bit alignment (on 64-bit CPUs)
...
Similarly to how CSRBank subregisters are aligned to the CPU word
width (see commit f4770219f
2020-01-03 16:36:42 -05:00
bunnie
5eec7432b8
fix a couple bugs in the DRP readout path
...
I'm now getting data out via DRP. Still some TODOs, but
progress.
2020-01-04 03:03:59 +08:00
bunnie
56ccaeebf0
add support for DRP on XADC
...
The design is backward-compatible in functionality for users
who don't want to use DRP. That is, on power on, the XADC will
scan the supply and temperature and store them in CSRs.
If drp_enable is set, the scanning stops, and the XADC is now
controlled by the DRP bus.
Wher drp_enable is reset, the XADC may return to an auto-sample
mode, but only if the internal registers are configured to do this.
If you return to drp_enable without, for example, turning on
the continuous sequence and setting which channels to check,
the results will be unpredictable (mostly either it'll scan just
once and stop, or it'll not scan all the channels, depending on
the register settings).
At this point, the backward compatibility was confirmed in testing,
the DRP API is still a work in progress as the application this
is being developed for needs to support fun stuff like real time
sampling of signals to a buffer.
Down the road, this block may have to be modified again to support an
output FIFO, so we're not railing the CPU trying to do real time
sampling of ADC data. This will probably be added as a True/False flag
of some sort in the parameter list, because the FIFO will be expensive
as far as BRAM goes to implement and applications that don't need the
FIFO buffer can probably use that BRAM for better things.
2020-01-04 00:25:09 +08:00
Florent Kermarrec
690de79d8b
cpu/microwatt: reorder sources, add comments
2020-01-03 15:29:10 +01:00
Florent Kermarrec
e36df2a6fb
build/lattice/icestorm: increase similarities with trellis.
2020-01-02 10:26:33 +01:00
Florent Kermarrec
197edad34e
soc/integration/soc_core/SoCController: specify initial reset value of scratch register in description
2020-01-02 09:41:47 +01:00
Florent Kermarrec
b65a36e7e8
soc/integration/soc_core/SoCController: rephrase CSR descriptions a bit
2020-01-02 09:38:23 +01:00
Sean Cross
c5aa929d4c
cores: timer: clean up wording for timer documentation
...
This fixes some formatting errors with the timer documentation, such as
the lack of a space between the first and second sentences. It also
fixes some grammar for documentation of various fields.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-01-02 16:24:12 +08:00
Sean Cross
2d75aee7e0
soc_core: ctrl: document registers
...
This adds a small amount of documentation to the three registers present
inside the `CTRL` module.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-01-02 15:37:45 +08:00
Sean Cross
a251d71211
cores: timer: fix documentation formatting
...
The ReStructured Text used was not properly formatted, resulting in
confusing and broken output. This corrects the output and lets it
format correctly when using sphinx.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-01-02 15:36:35 +08:00
Florent Kermarrec
db7a48c05d
soc/cores/clock: also allow margin=0 on iCE40PLL and ECP5PLL
2020-01-01 13:24:06 +01:00
bunnie
219bb7f294
add the possibility for a "precise" clock solution
...
If clocks and multipliers are planned well, we can have
a zero-error solution for clocks. Suggest to change < to <= in
margin comparison loop, so that a "perfect" solution is allowed
to converge.
2020-01-01 18:49:35 +08:00
Florent Kermarrec
9336fe1139
build/microsemi/libero_soc: update add_period_constraint behavior when clock is already constrainted.
2019-12-31 10:33:12 +01:00
Florent Kermarrec
3022f02b3f
build/xilinx/vivado: update add_period_constraint behavior when clock is already constrainted.
2019-12-31 10:32:09 +01:00
Florent Kermarrec
fe4eaf5860
build/lattice/icestorm/add_period_constraint: improve
...
- store period in ns.
- pass clocks to_build_pre_pack and do the convertion to MHz there.
- improve error message.
2019-12-31 10:30:09 +01:00
Florent Kermarrec
6b91e8827c
soc/integration/builder: avoid try/except on LiteDRAM import, just check if SoC has an sdram and do the import if so
2019-12-31 09:58:26 +01:00
enjoy-digital
2157d0f332
Merge pull request #327 from zakgi/master
...
moving RAM offsets outside of CSR_ETHMAC define
2019-12-31 09:49:53 +01:00
Tim 'mithro' Ansell
f0b5c67216
Allow specifying the same clock constraint multiple times.
...
(As long as the clock values actually match.)
2019-12-30 19:25:14 +01:00
Tim 'mithro' Ansell
8b955e6f69
Allow LiteX builder to be used without LiteDRAM.
2019-12-30 19:24:26 +01:00
Tim 'mithro' Ansell
a738739acd
Improve the invalid CPU type error message.
2019-12-30 16:10:57 +01:00
Florent Kermarrec
85ade2b3b3
build/xilinx/programmer: fix vivado_cmd when settings are sourced manually.
2019-12-30 10:07:08 +01:00
Giammarco Zacheo
39ae230b83
moving RAM offsets outside of CSR_ETHMAC define
2019-12-29 22:56:42 -08:00
enjoy-digital
ffa7ca8f0b
Merge pull request #321 from gsomlo/gls-rocket-aximem-wide
...
cpu/rocket: variants with double (128b) and quad (256b) wide mem_axi
2019-12-21 21:31:04 +01:00
enjoy-digital
e754c0555a
Merge pull request #319 from DurandA/feature-integer-attributes
...
Add integer attributes
2019-12-21 21:30:09 +01:00
Gabriel Somlo
cd8feca574
cpu/rocket: variants with double (128b) and quad (256b) wide mem_axi
...
Various development boards' LiteDRAM ports may have native data
widths of either 64 (nexys4ddr), 128 (versa5g), or 256 (trellis)
bits. Add Rocket variants configured with mem_axi ports of matching
data widths, so that a point to point connection between the CPU's
memory port and LiteDRAM can be accomplished without any additional
data width conversion gateware.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-12-21 14:11:48 -05:00
Gabriel Somlo
585b50b292
soc_core: csr_alignment assertions
...
Enforce the condition that csr_alignment be either 32 or 64 when
requested explicitly when initializing SoCCore().
Additionally, if a CPU is specified, enforce that csr_alignment be
equal to the native CPU word size (currently either 32 or 64), and
warn the caller if an alignment value *higher* than the CPU native
word size was explicitly requested.
In conclusion, if a CPU is specified, then csr_alignment should be
assumed to equal 8*sizeof(unsigned long).
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-12-21 13:00:40 -05:00
Gabriel Somlo
b6818c205e
cpu/rocket: access PLIC registers via pointer dereference
...
Since the PLIC is internal to Rocket, access its registers
directly via pointer dereference, rather than through the
LiteX CSR Bus accessors (which assume subregister slicing,
and are therefore inappropriate for registers NOT accessed
over the LiteX CSR Bus).
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-12-21 12:59:19 -05:00
Florent Kermarrec
0e46913d52
cpu/microwatt: add initial software support
2019-12-20 23:32:21 +01:00
Arnaud Durand
94e239ff13
Add integer attributes
2019-12-19 09:03:12 +01:00
Arnaud Durand
f8c5821658
Revert "gen/fhdl/verilog: allow single element verilog inline attribute"
...
This reverts commit b845755995
2019-12-19 08:53:44 +01:00
Florent Kermarrec
f883f0c703
cpu/microwatt: add submodule
2019-12-18 19:07:08 +01:00
Florent Kermarrec
5da0bcbd7a
cpu/microwatt: set csr to 0xc0000000 (IO region)
2019-12-18 08:59:35 +01:00
Florent Kermarrec
39a8ebe70c
cpu/microwatt: fix add_source/add_sources
2019-12-18 08:56:36 +01:00
Florent Kermarrec
d74a7463e0
soc/cores/pwm: remove debug print(n)
2019-12-18 08:47:56 +01:00
Florent Kermarrec
bd15f07cf7
platforms/netv2: add xc7a100t support
2019-12-17 09:47:31 +01:00
Florent Kermarrec
76e57414c3
platforms/minispartan6: add assert on available devices
2019-12-17 09:47:12 +01:00
Florent Kermarrec
bfe0bf6402
cpu/microwatt: simplify add_sources
2019-12-17 09:41:46 +01:00
Florent Kermarrec
b9edde20de
cpu/microwatt: add io_regions and gcc_flags
2019-12-17 09:33:46 +01:00
Florent Kermarrec
16e7c6b634
cpu/microwatt: update copyright
2019-12-17 09:27:19 +01:00
Florent Kermarrec
3d79324fce
cpu/microwatt: drive stall signal (no burst support)
2019-12-16 12:37:27 +01:00
Florent Kermarrec
da3a178bc6
soc/cores/pwm: add clock_domain support
2019-12-16 11:13:10 +01:00
Florent Kermarrec
9da28c4ea5
build/xilinx/XilinxMultiRegImpl: fix n=0 case
2019-12-16 11:12:38 +01:00
Florent Kermarrec
ec7dc2d8f4
build/xilinx/ise: cleanup/simplify pass, remove mist support (not aware of anyone using it)
2019-12-14 22:47:07 +01:00
Florent Kermarrec
1b963bb2d5
soc/cores/cpu: add initial Microwatt gateware support
...
Implementation tested on arty:
cd litex/soc/cores/cpu/microwatt
git clone https://github.com/antonblanchard/microwatt
mv microwatt sources
cd litex/boards/targets
./arty --cpu-type=microwatt --no-compile-gateware
2019-12-14 00:00:13 +01:00
Florent Kermarrec
c34255d2ab
soc/cores/cpu/minerva: add self.reset to i_rst
2019-12-14 00:00:07 +01:00
Gabriel Somlo
a0dad1b071
soc_core: additional CSR safety assertions
...
Since csr_data_width=64 has probably never worked properly, remove
it as one of the possible options (to be fixed and re-added later).
Add csr_data_width=16, which has been tested and does work.
Additionally, ensure csr_data_width <= csr_alignment (we should not
attempt to create (sub)registers larger than the CPU's native word
size or XLen).
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-12-12 13:14:16 -05:00
Florent Kermarrec
fb6b0786b6
soc_core: remove static 16MB csr region allocation (use csr_address_width to allocate the correct size)
2019-12-12 12:41:47 +01:00
Florent Kermarrec
b1a1e5e227
soc_core: add sort of CSR regions by origin (allow csr.h/csr.csv to be ordered by origin)
2019-12-12 11:27:56 +01:00
Florent Kermarrec
061d593de3
cores/8b10b: use real Memory for 6b5b table (to improve timings on ECP5)
2019-12-09 19:25:38 +01:00
Florent Kermarrec
a0122f9863
build/xilinx/vivado: move build_script generation
2019-12-08 12:19:38 +01:00
Florent Kermarrec
18ff8f38d1
build/xilinx/vivado: cleanup/simplify
2019-12-08 12:08:17 +01:00
Florent Kermarrec
0931ccc919
build/lattice/icestorm: cleanup/simplify (and remove arachne-pnr support)
2019-12-07 22:11:17 +01:00
Florent Kermarrec
b1b920531a
build/xilinx/common/platform/programmer: cleanup pass
2019-12-06 22:23:04 +01:00
Florent Kermarrec
edaa66bbed
boards: add Lambdaconcept's PCIe Screamer (R02)
2019-12-06 18:20:59 +01:00
Florent Kermarrec
a8635c48a4
targets/versa_ecp5: fix compilation with diamond
2019-12-06 16:15:08 +01:00
Florent Kermarrec
30a18808ad
boards/targets: keep attributes are no longer needed since automatically added when applying constraints to signals.
2019-12-06 15:58:06 +01:00
Florent Kermarrec
23c33cfa99
build: automatically add keep attribute to signals with timing constraints.
...
Avoid having to specify it manually or eventually forget to do it and have a constraints that is not applied correctly.
2019-12-06 15:41:15 +01:00
Florent Kermarrec
4c9af635d2
build/altera/quartus: allow adding period constraints on nets and add optional additional sdc/qsf commands
...
Additional sdc/qsf commands can be added from the design like:
platform.sdc_additional_commands.append("create_clock ...")
platform.sdc_additional_commands.append("set_false_path ...")
2019-12-06 15:19:07 +01:00
Florent Kermarrec
22e6f5ac1d
build/lattice/trellis: nextpnr now handle LPF timing constraints and multiple clock domains, freq_constraint is no longer needed.
2019-12-06 12:57:59 +01:00
Florent Kermarrec
8fb3f9a90d
build/lattice: cleanup/simplify (no functional changes)
...
icestorm still need to be cleaned up
2019-12-06 12:54:52 +01:00
Florent Kermarrec
946478a71e
build/lattice: cleanup/simplify
2019-12-06 12:13:20 +01:00
Florent Kermarrec
60edca2345
build/microsemi: cleanup/simplify (no functional change)
2019-12-06 12:12:43 +01:00
Florent Kermarrec
50fdc5ce41
build/altera: cleanup/simplify (no functional change)
...
Altera build backend was a bit messy and needed some cleanup to ease future maintenance and new features.
2019-12-06 11:08:46 +01:00
Tim Ansell
b17dfafa55
Merge pull request #313 from mmicko/yosys_ise_flow_fix
...
Yosys - ISE flow fix
2019-12-05 19:05:44 -08:00
Florent Kermarrec
8d90f4e97b
build/xilinx/vivado: use VHDL 2008 as default
2019-12-03 15:27:20 +01:00
Florent Kermarrec
cfd17321e2
targets/nexys4ddr: remove MEMTEST_ADDR_SIZE limitation (no longer needed)
2019-12-03 10:11:15 +01:00
Florent Kermarrec
201d60f37a
targets/netv2: switch to MVP DDR3 (K4B2G1646F instead of MT41J128M16)
2019-12-03 09:05:52 +01:00
Florent Kermarrec
6b82064723
targets: uniformize, improve presentation
2019-12-03 08:58:01 +01:00
Florent Kermarrec
6de20f185a
soc/interconnect/csr: add fields support for CSRStorage's write simulation method
2019-12-02 09:44:44 +01:00
Florent Kermarrec
2567a0ae1d
soc/cores/gpio: add GPIO Tristate
2019-12-01 21:26:37 +01:00
Konrad Beckmann
f411d6d362
trellis: Support the CABGA256 package
2019-11-30 02:50:41 +01:00
Miodrag Milanovic
783dfa508c
Properly select family for those currently supported
2019-11-29 19:11:22 +01:00
Miodrag Milanovic
6560911df2
Integrate with latest yosys changes
2019-11-29 17:12:08 +01:00
Sean Cross
581c23725e
spi_flash: correct documentation on SPI mode
...
The SPI mode is actually mode3, since the output value is updated on the
falling edge of CLK and the input value is updated on the rising edge.
This also clarifies some of the documentation based on experience with
the core.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-11-25 12:35:13 +08:00
Florent Kermarrec
de205d4a84
tools/remote/comm_udp: only use one socket
2019-11-22 15:28:35 +01:00
Florent Kermarrec
bdaca40fe4
build/generic_platform: avoid duplicate in GenericPlatform.sources
2019-11-22 15:28:07 +01:00
Florent Kermarrec
6883a43680
soc/cores/clock: change drp_locked to CSRStatus and connect it :)
2019-11-20 19:37:16 +01:00
Florent Kermarrec
36107cdfd7
soc/cores/clock: reset PLL/MMCM on all 7-series/Ultrascale with self.reset signal
2019-11-20 19:24:40 +01:00
enjoy-digital
e8e70b164a
Merge pull request #309 from antmicro/mmcm-fix
...
soc/cores/clock: add lock reg and assign reset
2019-11-20 19:20:15 +01:00
Pawel Czarnecki
fd14b76594
soc/cores/clock: add lock reg and assign reset
...
It was necessary to add drp_locked CSR for reading LOCK signal from
MMCM. Additionally, input signal RESET from MMCM was not driven by
any signal to do a proper reset of MMCM module thus it was impossible
to perform entirely correct dynamic clock reconfiguration.
2019-11-20 16:22:49 +01:00
Florent Kermarrec
04017519c8
soc/interconnect/axi: add Wishbone2AXILite
2019-11-20 12:32:22 +01:00
Florent Kermarrec
d905521185
build/tools/get_migen/litex_git_revision: avoid git fatal error message is not installed as a git repository
2019-11-19 09:11:11 +01:00
enjoy-digital
02bfda5e38
Merge pull request #308 from gsomlo/gls-sdram-init
...
soc_sdram, bios/sdram: support sdram init for csr_data_width <= 32
2019-11-18 18:24:35 +01:00
Gabriel Somlo
3ef13fd27a
soc_sdram, bios/sdram: support sdram init for csr_data_width <= 32
...
Enable SDRAM to be initialized when csr_data_width > 8 bits.
Currently, csr_data_width up to 32 bits is supported.
Read leveling tested with csr_data_width [8, 16, 32] on the
ecp5-versa5g and trellisboard (using yosys/trellis/nextpnr),
and on the nexys4ddr (using Vivado).
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-11-18 09:00:19 -05:00
Florent Kermarrec
1efb18f1ea
soc/interconnect/packet/Depacketizer: another simplifcation pass
2019-11-18 09:06:56 +01:00
Florent Kermarrec
af52203c00
soc/interconnect/packet/Depacketizer: cleanup "ALIGNED-DATA-COPY" state
2019-11-17 11:57:14 +01:00
Florent Kermarrec
8272a00d6e
soc/interconnect/packet/Depacketizer: replace no_payload with sink_d.last
2019-11-17 11:50:09 +01:00
Florent Kermarrec
6059712794
test/test_packet: add randomness on ready output, fix corner-cases on Packetizer/Depacketizer
2019-11-16 14:39:18 +01:00
Florent Kermarrec
9642893371
test/test_packet: add randomness on valid input, fix corner-cases on Packetizer
2019-11-16 08:49:04 +01:00
enjoy-digital
888fd55bd8
Merge pull request #307 from sergachev/master
...
change >512 B CSR memory exception to a warning
2019-11-15 18:17:35 +01:00
Florent Kermarrec
2f2cfc9951
soc/interconnect/packet: fix synthesis (synthesis tools can do all sort of optimizations, but we still need to provide valid verilog :))
2019-11-15 16:19:05 +01:00
Ilia Sergachev
444ae951e9
change >512 B CSR memory exception to a warning
2019-11-15 15:34:12 +01:00
Florent Kermarrec
31661e9e2d
soc/interconnect/packet: connect error/last_be only present on both sink and source
2019-11-15 14:57:31 +01:00
Florent Kermarrec
2946581e50
soc/interconnect/packet: simplify/refactor Packetizer/Depacketizer to keep it simple
...
To avoid complex FSMs, let the synthesis tool do the simplifications when the FSM states are not reachable.
2019-11-15 14:39:55 +01:00
Florent Kermarrec
86662b54d0
soc/interconnect/packet: update copyright
2019-11-15 11:25:38 +01:00
Vamsi K Vytla
5c19b133ac
soc/interconnect/packet: add > 8-bit support to Packetizer/Depacketizer
...
With high speed link (10gbps XGMII ethernet for example), stream data_width is generally
> 8-bit which make header/data un-aligned on bytes boundaries. The change allows the
Packetizer/Depacketizer to work on stream with a data_width > 8-bit.
2019-11-15 11:24:17 +01:00
Florent Kermarrec
5f151152ca
build/sim: cleanup run_as_root
2019-11-15 10:57:31 +01:00
Vamsi K Vytla
446ae57b75
build/sim/modules: add XGMII 10Gbps ethernet module
...
Used to simulate SoCs with XGMII 10Gbps ethernet and to do LiteEth verification
2019-11-15 10:51:55 +01:00
Florent Kermarrec
56fbd2f250
sim/ethernet: remove trailing whitespaces
2019-11-15 10:39:49 +01:00
Florent Kermarrec
eb3888f68e
tools/litex_sim: cleanup/update (no functional change)
2019-11-14 11:19:23 +01:00
Florent Kermarrec
4798d6b750
tools/litex_term: remove automatic reboot when flashing and clear mem_regions to avoid re-flashing on next reboot(s)
2019-11-11 18:38:10 +01:00
Florent Kermarrec
a17e307acf
bios/flash: minor cleanup on serialboot flashing, add flash address support
2019-11-09 00:05:36 +01:00
enjoy-digital
2d6100bdbe
Merge pull request #305 from FrankBuss/master
...
adding support to flash an FBI image
2019-11-08 23:51:49 +01:00
Florent Kermarrec
05e8abfee3
soc_core: add integrated-rom-file parameter to allow initializing rom from command line
2019-11-08 23:32:10 +01:00
Florent Kermarrec
0a030fe17d
cores/code_8b10b/Decoder: add basic invalid symbols detection
...
Check that we have 4,5 or 6 ones in the symbol. This does not report all
invalid symbols but still allow detecting issues with the link.
2019-11-08 19:43:01 +01:00
fb@frank-buss.de
9857d9d9d2
adding support to flash an FBI image
2019-11-08 17:16:28 +01:00
Florent Kermarrec
c96f31a9ad
software/bios: rename ef command to fe (for consistency)
2019-11-08 13:14:21 +01:00
Florent Kermarrec
4a12a92d62
software/libbase/spiflash: rename CHIP_ERASE_CMD to CE_CMD (for consistency)
2019-11-08 13:13:54 +01:00
enjoy-digital
7fb9cfeb64
Merge pull request #302 from FrankBuss/master
...
erase flash command added
2019-11-08 13:04:33 +01:00
Florent Kermarrec
db4739df81
soc_core: remove add_cpu method (when no real CPU but only wishbone masters, self.cpu is declared as CPUNone)
2019-11-08 12:55:29 +01:00
fb@frank-buss.de
468df3c857
erase flash command added
2019-11-07 19:19:54 +01:00
Florent Kermarrec
f1714405c3
integration/export: do not include soc.h in csr.h when with_access_functions=False
...
Idealy we should have another parameter for that.
2019-11-07 09:02:31 +01:00
Florent Kermarrec
b52dcde9ba
soc_sdram/kcu105: add optional main_ram_size_limit and use it on KCU105 to limit to 1GB instead of 2GB.
...
CSR map will need to be updated to support the 2GB.
2019-11-07 09:00:54 +01:00
Florent Kermarrec
9053d0803a
soc_sdram: remove use_full_memory_we parameter (always used as True)
2019-11-07 08:56:52 +01:00
Florent Kermarrec
1b94699d12
soc_sdram: update copyrights
2019-11-07 08:44:34 +01:00
Gabriel Somlo
28708f4208
cpu/rocket: parameterize axi interface data width
...
Rocket variants can be configured with axi port data widths that
are multiples of the native word size (64 bits in our case). In
the future, we will add variants with mem_axi data width > 64 bit,
to match the native data width of the LiteDRAM controller on
various development boards (e.g., 128 bits on the ecp5versa, and
256 bits on the trellisboard).
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-11-01 08:55:27 -04:00
Gabriel Somlo
014db66444
soc_sdram: remove upper limit on usable main RAM
...
Revert commit #68a503174.
2019-11-01 08:55:15 -04:00
Gabriel Somlo
ec831f5b63
cpu/rocket, soc_sdram: Connect mem_axi to LiteDRAM, bypass WB bus
...
Connect Rocket's dedicated port for cached RAM accesses (mem_axi)
directly to the LiteDRAM data port, bypassing the shared LiteX
(Wishbone) bus.
When both Rocket's mem_axi and LiteDRAM's port have the same data
width, use a native point-to-point AXI connection.
Otherwise, convert both ends to Wishbone, and use the Wishbone
data width converter to bridge the gap.
FIXME: In the future, this part should be replaced with a native
AXI data width converter!
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-11-01 08:52:39 -04:00
Florent Kermarrec
9c3c43c94a
interconnect/csr_bus/SRAM: add mem_size check
...
Memory size is limited to 512 bytes:
- CSR region size is 0x800 (4096)
- default csr_data_width is 8
maximum size = 4096/8 = 512 bytes.
2019-11-01 11:33:50 +01:00
Florent Kermarrec
edb1731ef9
soc_core/soc_core_args: specify default cpu (vexriscv)
2019-11-01 11:30:50 +01:00
Florent Kermarrec
cc607f022a
lattice/diamond/tcl: always use / separators, even on windows
2019-11-01 10:11:12 +01:00
Florent Kermarrec
59acf0ea1c
cpu/minerva: elaborate minerva verilog to build directory
2019-11-01 09:59:13 +01:00
Florent Kermarrec
a762d29b19
soc/integration/builder: pass output_dir to platform, make sure gateware/software directory are created before finalizing
2019-11-01 09:59:06 +01:00
Florent Kermarrec
855d0e925d
cpu/minerva: generate minerva.v near core.py not in submodule
2019-10-31 21:16:27 +01:00
Florent Kermarrec
85d6607257
cpu/minverva: give more explicit error message when not able to elaborate cpu
2019-10-31 08:52:04 +01:00
Tim 'mithro' Ansell
4408dad9d2
Improve the error message on memory region conflict.
...
Before;
```
ValueError: Memory region conflict between rom and main_ram
```
After;
```
ValueError: Memory region conflict between rom (<SoCMemRegion 0x10000000 0x10000 cached>) and main_ram (<SoCMemRegion 0x0 0x20000000 cached>)
```
Fixes #296 .
2019-10-30 19:32:20 -07:00
Tim 'mithro' Ansell
607e1cc4f6
Fix file names for the mor1kx processor.
...
Fixes #292 .
2019-10-30 13:50:01 -07:00
Florent Kermarrec
a54b80b9b4
targets: use type="io" instead of io_region=True
2019-10-30 16:42:31 +01:00
Florent Kermarrec
a0c0a6fd05
integration/SoCMemRegion: use type instead of io_region/linker_region and export type to csv/json
...
Supported types: "cached", "io", "cached+linker", "io+linker", default="cached"
2019-10-30 16:42:26 +01:00
Florent Kermarrec
9fcf297387
soc_core: add check_regions_overlap method, add linker_region support (overlap is not checked on linker_regions)
2019-10-28 18:34:03 +01:00
Florent Kermarrec
4014fbffe1
soc_core/add_memory_region: fix memory overlap detection
2019-10-28 17:07:37 +01:00
Florent Kermarrec
ab8af28213
cpu/minerva: elaborate from nmigen sources during build, enable hardware multiplier
2019-10-28 10:23:08 +01:00
Gabriel Somlo
49372852da
build/lattice/trellis: optionally allow failure if p&r timing not met
...
When timing requirements are strict, allow the build process to fail upon
failure to meet timing. This facilitates running the build process from a
loop, repeatedly, until a "lucky" p&r solution is found, e.g.:
while true; do
litex/boards/targets/versa_ecp5.py --gateware-toolchain trellis \
--sys-clk-freq=60e06 --cpu-type rocket --cpu-variant linux \
--with-ethernet --yosys-nowidelut \
--nextpnr-timingstrict
if [ "$?" == "0" ]; then
echo "Success" | mail -s "Build Succeeded" your@email.here
break
fi
done
This augments commit #683e0668, which unconditionally forced p&r to
succeed, regardless of whether timing was met, via '--timing-allow-fail'.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-10-24 13:56:20 -04:00
enjoy-digital
b6d35c92ae
Merge pull request #283 from kbeckmann/kbeckmann/bios_increment_address
...
bios: Increment address when writing to flash
2019-10-20 15:30:22 +02:00
Konrad Beckmann
ef78ae951f
bios: Increment address when writing to flash
2019-10-19 22:58:24 +02:00
Florent Kermarrec
683e066812
build/lattice/trellis: use --timing-allow-fail to allow generating bistream when timings are not met
...
This is the default behaviour of the others tools and allow testing designs on hardware with small violations.
2019-10-18 14:12:01 +02:00
Florent Kermarrec
4cf346a1d4
soc/cores/icap/ICAPBitstream: always keep fifo.source.ready to 1
2019-10-18 10:27:37 +02:00
Jan Kowalewski
8b5da9c623
cores/icap/ICAPBitstream: add source ready signal.
2019-10-18 09:33:31 +02:00
Florent Kermarrec
626533ce9d
soc/integration/__init__: remove imports (not used and causing issues
2019-10-17 12:44:37 +02:00
Florent Kermarrec
675b455259
build: always use platform.add_source and avoid manipulate platform.sources directly
2019-10-17 12:17:36 +02:00
Florent Kermarrec
43f5d1ef13
build/generic_platform: replace set with list for sources/verilog_include_paths
...
Python does not have native OrderedSet and we need to be able to preserve the order of the sources
for some backends (Verilator for instance), so use list instead of set.
2019-10-17 09:52:49 +02:00
Florent Kermarrec
97a77b950c
cores/icap/ICAPBitstream: simplify, add icap_clk_div parameter, describe how to use it.
2019-10-16 15:00:58 +02:00
